Method for wear leveling of memory cells based on tunneling effect compensation

By constructing a stress interference matrix and dynamically adjusting the address mapping logic, the problems of storage cell loss and interference propagation under tunneling effect compensation are solved, thereby extending the storage cell lifespan and stabilizing global data, and improving the operational stability and data retention capability of high-density storage systems.

CN122337282APending Publication Date: 2026-07-03DAIMA (ZHUHAI) INTEGRATED CIRCUIT CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-14
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

In high-density stacking storage architectures, the storage cell loss and global interference propagation caused by tunneling effect compensation are problems that existing technologies cannot effectively avoid. The interference superposition generated by high voltage pulses at specific geometric nodes leads to a non-linear increase in bit error rate, and conflicts between local cell performance and global array reliability.

Method used

By constructing a stress interference matrix that characterizes the spatial distribution of storage cells, and combining the logical update frequency of the data to be written with the retention sensitivity of adjacent physical pages, the address mapping logic is dynamically adjusted to redirect high-energy compensation operations to the region of minimum stress interference, thereby suppressing the loss of induced charge caused by tunnel oxide layer damage and achieving global bit error rate control of the storage medium at the end of its lifespan.

Benefits of technology

Without altering the underlying characteristics of the storage medium, it achieves extended storage cell lifespan and stable global data distribution, improves the data retention characteristics and system operational stability of high-density storage systems, and prevents the risk of global bit error rate propagation.

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Abstract

This invention relates to the field of computer storage technology and discloses a storage cell wear equalization method based on tunneling effect compensation. The method includes: monitoring the characteristic offset of the write and erase durations of the physical address cells to be equalized with the number of operation cycles to determine the tunnel oxide aging factor; constructing a topological interference model by combining the spatial spacing between physical address cells and the data update frequency, and performing interference boundary calculations to determine the physical stress divergence profile generated by the compensation voltage pulse; selecting idle physical address cells with stress values ​​below a safety threshold as cold zone nodes, and then correcting the address mapping conversion logic and implementing write redirection. This invention utilizes address mapping conversion logic to resolve physical stress conflicts in the logical dimension, suppresses the loss of induced charge caused by tunnel oxide damage, and effectively improves the data retention characteristics and system stability of the storage medium at the end of its lifespan.
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Citation Information

Patent Citations

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