Power failure detection method and device of NAND flash memory, embedded device and medium

Abstract

This application provides a method, apparatus, embedded device, and medium for power failure detection of NAND flash memory. The method is applied to an embedded device, which includes NAND flash memory. The method includes: during the operation of the NAND flash memory, monitoring whether a voltage jitter flag is triggered. The voltage jitter flag is set to be triggered when a voltage detection circuit detects that the power supply voltage is lower than a preset voltage threshold and the duration is less than a preset time threshold; if the voltage jitter flag is triggered, monitoring the operating state of the NAND flash memory within a preset monitoring period; if the operating state is abnormal, performing a reset operation on the NAND flash memory. This technical solution can solve the problem that NAND flash memory operation failures caused by brief voltage jitter cannot be diagnosed and recovered in a timely manner, improving the data reliability and system availability of embedded devices in unstable power environments.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a method, apparatus, embedded device, and medium for detecting power loss of NAND flash memory. Background Technology

[0002] NAND flash memory is the primary storage medium in embedded devices. To prevent data corruption due to power failures, systems typically integrate a voltage detection circuit (VDT) for power-down protection. When the voltage detection circuit detects that the power supply voltage is lower than a preset threshold, it triggers an interrupt, notifying the firmware to perform power-down protection on the NAND flash memory to avoid data loss.

[0003] However, in practical applications, when a voltage drop of extremely short duration occurs (e.g., tens of microseconds), a special scenario may arise where the VDT event recovery time is shorter than the firmware interrupt response time. In this case, although the voltage detection circuit can quickly detect the anomaly, due to the extremely short drop time, the power supply voltage may have already returned to normal by the time the firmware interrupt service routine begins execution. This causes the firmware to misjudge the event as a "false trigger" or "negligible interference," thus filtering it out and failing to perform any protective operations.

[0004] Although these brief voltage fluctuations are filtered by the firmware, they are still sufficient to cause substantial interference to NAND flash memory that is undergoing delicate operations. This interference may lead to malfunctions in the NAND internal state machine, abnormal operation of the charge pump, and other issues, resulting in operational failures of the NAND flash memory. However, because the initial VDT event has been filtered, the device cannot associate this failure with the power event, making it impossible to diagnose and recover from the abnormal state of the NAND flash memory in a timely manner. Summary of the Invention

[0005] This application provides a method, apparatus, embedded device, and medium for detecting power loss in NAND flash memory, in order to solve the technical problem that NAND flash memory operation failures caused by voltage jitter cannot be diagnosed and recovered in a timely manner.

[0006] In a first aspect, a power-down detection method for NAND flash memory is provided, applied to an embedded device, the embedded device including NAND flash memory. The method includes: during the operation of the NAND flash memory, monitoring whether a voltage jitter flag is triggered, the voltage jitter flag being set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold; if the voltage jitter flag is triggered, monitoring the operating state of the NAND flash memory within a preset monitoring period; if the operating state is an abnormal state, performing a reset operation on the NAND flash memory.

[0007] The first approach involves actively detecting whether the NAND flash memory has malfunctioned as a result of triggering a voltage jitter flag within a preset monitoring period. When the NAND flash memory is confirmed to be in an abnormal state, a reset operation is performed on that NAND. This method achieves refined fault diagnosis and targeted recovery, avoids unnecessary global resets, and ensures the healthy state of the NAND flash memory.

[0008] In conjunction with the first aspect, in one possible implementation, an abnormal operating state includes at least one of the following situations: the preset register identifier of the NAND flash memory indicates an abnormal state, an instruction indicating a failure of the operation on the NAND flash memory is detected, or the execution time of the operation command on the NAND flash memory exceeds a preset timeout threshold.

[0009] By defining multiple parallel detection anomaly judgment conditions, this method constructs a multi-level, highly reliable anomaly state judgment system. For example, the preset register identifier typically refers to the NAND flash memory's status register, which is specifically set in cases of programming / erase failure, ECC errors, etc., representing a direct anomaly report from within the NAND flash memory chip. Operation failure instructions may originate from upper-layer drivers or the file system, such as the ECC uncorrectable state returned when reading data. Command execution timeout is an active detection mechanism; if the NAND flash memory does not respond within a specified time after a command is sent, it is judged as an anomaly. These three methods cross-validate from different dimensions (chip self-reporting, upper-layer feedback, and active detection), greatly reducing the probability of false positives and false negatives, and ensuring the accuracy and necessity of the reset operation.

[0010] In conjunction with the first aspect, in one possible implementation, if the operating state is abnormal, a reset operation is performed on the NAND flash memory, including: if the operating state is abnormal, a power-down and power-on operation is performed on the NAND flash memory chip via a hardware reset signal line or a power management unit.

[0011] This implementation method uses a fast and standard hardware reset signal line (such as the #RESET pin) to directly place the NAND flash memory into a known initial state. A more thorough reset method involves cutting off and then restoring power to the NAND flash memory via the power management unit (PMU), which is particularly suitable for chips where the reset pin may fail or which are more sensitive to power cycling. Both methods can physically eliminate internal logic lock-up or state disorder caused by voltage jitter, providing effective ways to restore functionality.

[0012] In conjunction with the first aspect, in one possible implementation, the method further includes: clearing the voltage jitter indicator if the operating state is normal.

[0013] Even if voltage fluctuations are detected, as long as the NAND flash memory function is confirmed to be normal within the subsequent preset monitoring period, the fluctuation is considered not to have caused substantial damage to the NAND. At this point, the embedded device only needs to clear the flag and continue the normal process without performing any reset operation, thereby avoiding any unnecessary interference with normal operation and ensuring the continuity and efficiency of the system.

[0014] In conjunction with the first aspect, in one possible implementation, the method further includes: if the operating state is abnormal, sending a reset command to the NAND flash controller to reset the internal state machine of the NAND flash controller.

[0015] In some embedded devices, the NAND flash memory controller (which may be a separate chip) is responsible for managing the low-level access and control of the NAND flash memory. Voltage jitter can affect not only the NAND flash memory itself but also cause errors in the internal state machine of the NAND flash memory controller. This step ensures that the NAND flash memory controller and the NAND flash memory are synchronized and restored to the correct initial state by sending a reset command (such as a software reset or configuration register reset) to the NAND flash memory controller, clearing obstacles for subsequent reinitialization and access.

[0016] In conjunction with the first aspect, in one possible implementation, the method further includes: clearing the voltage jitter flag and initializing the NAND flash memory after performing a reset operation on the NAND flash memory.

[0017] After completing the targeted reset operation, the jitter event handling process is terminated by clearing the voltage jitter flag. Subsequently, standard initialization operations are performed on the NAND flash memory to ensure the integrity and closed-loop nature of the entire recovery process.

[0018] In conjunction with the first aspect, in one possible implementation, the method further includes: if the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is greater than or equal to a preset time threshold, then suspending the current operation of the NAND flash memory; and if the voltage detection circuit detects that the power supply voltage is greater than or equal to the preset voltage threshold, initializing the NAND flash memory and resuming the execution of the suspended current operation.

[0019] Secondly, a power-down detection device for NAND flash memory is provided, applied to an embedded device. The embedded device includes NAND flash memory. The device includes: a monitoring module, used to monitor whether a voltage jitter flag is triggered during the operation of the NAND flash memory. The voltage jitter flag is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold; the monitoring module is also used to monitor the operating state of the NAND flash memory within a preset monitoring period if the voltage jitter flag is triggered; and an operation module, used to perform a reset operation on the NAND flash memory if the operating state is abnormal.

[0020] In a third aspect, an embedded device is provided, including a processor, a memory, and a computer program or instructions stored on the memory, the memory including NAND flash memory, wherein the processor executes the computer program or instructions to implement the steps of any of the methods in the first aspect.

[0021] Fourthly, a computer-readable storage medium is provided, on which a computer program or instructions are stored, which, when executed by a processor, implement the steps of any of the methods in the first aspect.

[0022] The technical solution provided in this application has the following beneficial effects: During the operation of NAND flash memory, the embedded device monitors whether the voltage jitter flag is triggered. If the voltage jitter flag is triggered, the operating status of the NAND flash memory is monitored within a preset monitoring period. If the operating status is abnormal, a reset operation is performed on the NAND flash memory, which realizes accurate fault identification and intelligent recovery. This effectively solves the technical problem that NAND operation faults caused by brief voltage jitter cannot be diagnosed and recovered in a timely manner, and significantly improves the data reliability and system availability of embedded devices in unstable power environments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of an embedded device provided in an embodiment of this application; Figure 2 A schematic diagram of power supply voltage protection provided in an embodiment of this application; Figure 3 A flowchart illustrating a power-down detection method for NAND flash memory provided in an embodiment of this application; Figure 4 A flowchart illustrating another power-loss detection method for NAND flash memory provided in an embodiment of this application; Figure 5 A schematic diagram of the structure of a power-down detection device for NAND flash memory provided in an embodiment of this application; Figure 6 This is a schematic diagram of another embedded device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0025] The technical solution of this application is applicable to storage medium management scenarios, especially to the control and management of NAND flash memory. To understand this application in more detail, an embedded device related to this application is first introduced below. Please refer to... Figure 1 This is a schematic diagram of an embedded device provided in an embodiment of this application. The embedded device 10 includes: a main control processor, memory, NAND flash memory, and a NAND flash memory controller serving the NAND flash memory. Power can be supplied externally, with the required voltage provided to each component via a power management unit (PMU). A voltage detection circuit (VDT) continuously monitors the core power supply voltage (VCC). The NAND flash memory can be connected to the NAND flash memory controller via signal lines such as data bus, command latch enable, address latch enable, read / write enable, ready / busy, write protection, and reset.

[0026] In one embodiment, see Figure 2 Assume the NAND flash memory in this embedded device has a supply voltage (VCC) of 3.3V and a preset voltage detection threshold of 2.6V. When the embedded device detects that the VCC voltage is below 2.6V, the voltage detection circuit can generate an interrupt signal. The firmware will immediately enter the terminal service routine, terminating the current operation on the NAND flash memory (such as programming or erasing) and attempting to save critical states. Subsequently, when the VCC voltage recovers to above 2.7V, the firmware can reinitialize the NAND flash memory and continue executing any suspended unfinished work.

[0027] However, in actual operation, the following situation may occur: the VCC voltage experiences a brief drop below the 2.6V threshold, but due to the extremely short duration of the drop (e.g., only a few microseconds), the voltage returns to normal before the firmware has a chance to respond to the voltage detection interrupt. In this case, the firmware's interrupt service routine, upon detecting that the voltage is now normal, will classify this event as a voltage jitter (VCC filter) and ignore it. The problem is that although the firmware filters this event, this brief voltage jitter may have already caused substantial interference to the internal circuitry of the NAND flash memory performing delicate operations, such as abnormal erase, write, and read operations, causing the NAND to enter an abnormal state. Subsequent access to this NAND flash memory may result in timeouts, return error states, or complete unresponsiveness, and the embedded device cannot correlate these anomalies with the previously filtered voltage event, forming a difficult-to-diagnose soft fault.

[0028] To address the aforementioned issues, this application proposes a method, apparatus, embedded device, and medium for detecting power failures in NAND flash memory, which can effectively solve the technical problem that NAND flash memory operational failures caused by voltage fluctuations cannot be diagnosed and recovered in a timely manner.

[0029] The inventive concept of this application is as follows: when the power supply experiences a momentary voltage fluctuation and triggers the generation of a voltage fluctuation flag, the embedded device actively monitors and judges whether the NAND flash memory has entered an abnormal state within a preset monitoring period, and performs a targeted reset and recovery when the abnormality is confirmed, thereby ensuring system reliability while avoiding unnecessary operation interruptions, and realizing accurate detection and intelligent recovery of NAND flash memory soft faults caused by momentary voltage fluctuations.

[0030] The power-loss detection method for the NAND flash memory shown in this application will be described in detail below. Please refer to [link / reference]. Figure 3 This is a flowchart illustrating a power-down detection method for NAND flash memory according to an embodiment of this application. Figure 3 The method shown can be applied to, for example Figure 1 The embedded device shown may include the following steps: S301. During the operation of NAND flash memory, monitor whether the voltage jitter indicator is triggered.

[0031] It should be noted that the voltage jitter indicator is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold.

[0032] It should also be noted that this voltage detection circuit can be a hardware circuit capable of sampling the power supply voltage in real time and comparing it with a preset voltage threshold. When the detected power supply voltage is lower than the preset voltage threshold, the voltage detection circuit can set a voltage jitter flag or generate an interrupt.

[0033] As one feasible implementation, during normal operation of the embedded device, the NAND flash memory may be in any state, such as idle, read, programmed, or erased. The embedded device (e.g., its firmware) continuously monitors whether a voltage jitter flag is triggered. The triggering condition for this voltage jitter flag is defined as follows: the voltage detection circuit must simultaneously detect the following two conditions: first, the power supply voltage is less than a preset voltage threshold; second, the duration of the low-voltage state (power supply voltage less than the preset voltage threshold) is less than a preset time threshold.

[0034] As a feasible implementation, the preset time threshold can be the interrupt power-down response time of the power supply voltage detection circuit, for example, ranging from 10 microseconds to several milliseconds. The specific value can be optimized and adjusted according to the interrupt response performance of the embedded device, the timing requirements of NAND flash memory operation, and power supply noise characteristics. For example, for embedded devices with fast interrupt response, the preset time threshold can be set to 15-50 microseconds; while for embedded devices with slow interrupt response or requiring more stringent filtering, the preset time threshold can be set to 100 microseconds to 2 milliseconds to ensure that voltage jitter events that are shorter than the complete firmware response process but are sufficient to interfere with the internal operation of NAND flash memory can be effectively captured.

[0035] S302. If the voltage jitter indicator is triggered, the operating status of the NAND flash memory will be monitored within a preset monitoring period.

[0036] It should be noted that the preset monitoring period refers to the time window from the start of the trigger voltage jitter indicator to the completion of the NAND flash memory status judgment.

[0037] As a feasible implementation method, the preset monitoring period can be set based on the operation command timeout threshold, and the preset monitoring period can be set to be slightly longer than the maximum allowed execution time of a typical NAND flash memory operation command. For example, if the timeout threshold for a NAND flash memory read status register command is usually 100 microseconds, the monitoring period can be set to 150-200 microseconds to ensure that there is enough time to complete a complete command interaction and status check.

[0038] The preset monitoring period can also be set based on the firmware task scheduling period. In embedded devices using a real-time operating system, the monitoring period can be set to one or more task scheduling periods. For example, if the minimum scheduling period of the real-time operating system is 1 millisecond, the monitoring period can be set to 1-5 scheduling periods (i.e., 1-5 milliseconds), so that status monitoring can be completed within one or more complete task cycles.

[0039] This preset monitoring period can also be set based on the internal operation timing of the NAND flash memory. For example, for NAND chips that need to complete internal charge balancing or state updates, this preset monitoring period can be set to be longer than its longest internal operation time (typically hundreds of microseconds to milliseconds).

[0040] The embedded device can also dynamically adjust the preset monitoring cycle based on historical fault records. For example, if NAND flash memory anomalies caused by voltage fluctuations are frequently detected recently, the monitoring cycle can be appropriately extended to improve detection reliability; conversely, if no anomalies are detected for a long time, the preset monitoring cycle can be shortened to reduce performance impact. It is understood that the above method is only an example, and in practical applications, the preset monitoring cycle can be set in other ways, and this application does not impose any restrictions on it.

[0041] In one embodiment, an abnormal operation state includes at least one of the following situations: the preset register identifier of the NAND flash memory indicates an abnormal state, an instruction indicating an operation failure for the NAND flash memory is detected, or the execution time of the operation command for the NAND flash memory exceeds a preset timeout threshold.

[0042] It should be noted that this preset register identifier refers to a specific error flag bit in the Status Register inside the NAND flash memory. After the NAND flash memory performs a programming, erasing, or reading operation, the controller can obtain the value of this register by sending a Read Status command.

[0043] For example, within a preset monitoring period that triggers the voltage jitter flag, the embedded device can proactively send a read status command to the NAND flash memory. Assume the returned status byte is 0x41 (binary 0100 0001), where bit 0 (programming failure bit) is 1 and bit 6 (write protection bit) is 1. This indicates that the NAND flash memory has simultaneously reported a programming failure and a write protection exception, allowing the embedded device to determine that the NAND flash memory is in an abnormal state.

[0044] It should also be noted that instructions indicating a failure in NAND flash memory operations refer to explicit error codes or failure signals returned from the NAND flash memory controller driver layer, file system layer, or application layer. These instructions can be derived from the system software stack's assessment of the NAND operation result, and may include ECC (Error-Correcting Code) failure, read verification failure, interface communication errors, etc.

[0045] For example, within a preset monitoring period, the embedded device's file system attempts to read a previously programmed data page. After the NAND flash controller drives the NAND flash memory to perform the read operation, its hardware ECC engine reports an "ECC uncorrectable error," and the driver layer immediately returns error code 0xFF02 (indicating a multi-bit ECC error) to the upper layer. If the embedded device detects this error code, it can determine that a failed operation has been detected.

[0046] It should also be noted that this timeout threshold is an independent timing threshold set for various NAND flash memory operation commands, used to prevent the system from waiting indefinitely due to NAND flash memory not responding. Monitoring whether the execution time of operation commands for NAND flash memory exceeds the preset timeout threshold can be achieved through hardware timers or software timing within the embedded device.

[0047] For example, at the start of the preset monitoring period, the embedded device can send a read ID command to the NAND flash memory and simultaneously start a 100-microsecond timeout timer. If the NAND flash memory fails to return a valid manufacturer ID and device ID via the data bus within 100 microseconds, the timeout timer will trigger. Based on this, it is determined that the command execution has timed out, and the NAND flash memory may be in a faulty state of being unresponsive or responding abnormally.

[0048] As a feasible implementation method, the embedded device can execute the above three anomaly detection mechanisms in parallel, forming a multi-layered anomaly state determination network. If any one of the three detection results meets the condition, the operation state can be determined to be an anomaly.

[0049] S303. If the operation status is abnormal, a reset operation is performed on the NAND flash memory.

[0050] In one embodiment, if the operating state is abnormal, a reset operation is performed on the NAND flash memory, including: if the operating state is abnormal, a power-down and power-on operation is performed on the NAND flash memory chip through a hardware reset signal line or a power management unit.

[0051] It should be noted that this hardware reset signal line can refer to a dedicated reset pin on the NAND flash memory (usually marked as #RESET, RST#, or / RESET). This reset pin is active low, and when it is pulled low and held for a certain period of time (meeting the minimum pulse width specified in the chip datasheet, typically hundreds of nanoseconds to several microseconds), it will force all internal logic circuits of the chip to reset to the power-on initial state.

[0052] For example, the processor or dedicated reset control logic of an embedded device controls the signal line connected to the #RESET pin of the NAND flash memory via a general purpose input / output interface (GPIO). The GPIO output is set low and maintained for a period of time (e.g., for a certain NAND chip model, the datasheet requires a minimum reset pulse width of 500 nanoseconds, but in practice, it can be set to 2-10 microseconds to ensure reliability). Then, the GPIO is returned to high, at which point the NAND chip completes a hardware reset, clearing its internal state machine, registers, and interface logic.

[0053] As a possible implementation, after performing a reset, the embedded device may also need to insert the necessary delay (tRST, typically a few microseconds to tens of microseconds) according to the datasheet requirements to ensure that the internal reset operation of the NAND flash memory is fully completed before proceeding with subsequent initialization operations.

[0054] It should also be noted that the Power Management Unit (PMU) refers to a power circuit module that provides independent power supply control for NAND flash memory. This PMU performs a power-down and power-on operation on the NAND flash memory chip, achieving a more thorough physical reset by cutting off and restoring the core power supply voltage (VCC) of the NAND flash memory. It is especially suitable for chips where the reset pin may fail or are more sensitive to power cycling.

[0055] For example, first, the embedded device can ensure that all access to the NAND flash memory is suspended. Then, by configuring the PMU register, the power output to the NAND flash memory is turned off. At this point, the NAND flash memory is completely powered off, and all internal states are naturally lost. Then, the power-off state can be maintained for a period of time (typically on the order of milliseconds, such as 10-100 milliseconds) to ensure that the internal capacitors of the chip are fully discharged. Next, the PMU output to the NAND flash memory is re-enabled, and after power-on, the initialization operation can be initiated after meeting the power-on reset time (tPU, typically several hundred microseconds to several milliseconds) specified in the NAND flash memory datasheet.

[0056] As a feasible implementation method, the embedded device can also use two methods in combination, for example, first try a hardware reset, and if the NAND still behaves abnormally after the reset, then perform a power reset.

[0057] As a feasible implementation, after the reset operation is completed, the embedded device can clear the voltage jitter flag and reconfigure the NAND flash memory according to the power-on initialization process, including reading the ID, setting timing parameters, scanning for bad blocks, etc., and finally restore the NAND flash memory to a fully usable working state.

[0058] As can be seen, by implementing the NAND flash memory power-down detection method shown in the embodiments of this application, during the operation of the NAND flash memory, the embedded device monitors whether the voltage jitter flag is triggered. If the voltage jitter flag is triggered, the operating status of the NAND flash memory is monitored within a preset monitoring period. If the operating status is abnormal, a reset operation is performed on the NAND flash memory. This achieves accurate fault identification and intelligent recovery, effectively solving the problem that NAND operation faults caused by brief voltage jitter cannot be diagnosed and recovered in a timely manner, and significantly improving the data reliability and system availability of the embedded device in an unstable power environment.

[0059] Please see Figure 4 This is a flowchart illustrating another power-loss detection method for NAND flash memory provided in an embodiment of this application. Figure 4 The method shown can be applied to embedded devices, including NAND flash memory, such as... Figure 4 The methods shown include: S401. During the operation of NAND flash memory, monitor whether the voltage jitter flag is triggered.

[0060] The voltage jitter flag is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold.

[0061] S402. If the voltage jitter indicator is triggered, monitor the operating status of the NAND flash memory within the preset monitoring period.

[0062] S403. If the operation status is abnormal, a reset operation is performed on the NAND flash memory.

[0063] It should be noted that the specific implementation methods of steps S401-S403 above can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0064] S404. After performing a reset operation on the NAND flash memory, clear the voltage jitter flag and initialize the NAND flash memory.

[0065] As a feasible implementation, after successfully resetting the NAND flash memory, the embedded device can first write a clear command to the control register of the voltage detection circuit to clear the voltage jitter flag. Then, after waiting for the NAND flash memory reset recovery time requirement to be met, a reset command is sent, followed by a read ID command to obtain device information. Finally, the optimal timing parameters are configured based on the device ID to ensure that the NAND flash memory can be initialized in an orderly manner.

[0066] For example, after an embedded device detects a NAND flash memory malfunction and performs a reset (pulling the #RESET pin low for 10 microseconds), it can send a read ID command to the NAND flash memory to obtain a device code such as 0xEC 0xDC. The firmware can then use this device code to query an internally pre-set parameter table to obtain the optimal timing configuration for the chip: for example, the write cycle time should be set to 25 nanoseconds, the read access time to 20 nanoseconds, and the maximum page programming timeout to 800 microseconds. These parameters can then be used to configure the optimal timing parameters to ensure that the NAND flash memory can be initialized in an orderly manner.

[0067] After completing the targeted reset operation, this step concludes the jitter event handling process by clearing the voltage jitter flag. Subsequently, standard initialization operations are performed on the NAND flash memory to ensure the integrity and closed-loop nature of the entire recovery process.

[0068] S405. If the operation state is abnormal, a reset command is sent to the NAND flash memory controller to reset the internal state machine of the NAND flash memory controller.

[0069] As a feasible implementation, upon detecting a NAND flash memory anomaly, in addition to resetting the NAND flash memory itself, the embedded device can also write a reset command (such as 0x0000_0001) to the configuration register of the NAND flash memory controller, triggering a soft reset of the NAND flash memory controller. This operation can reset the controller's internal state machine, and in some embodiments, it can also reset the FIFO (First In First Out) buffer and ECC calculation unit.

[0070] As a feasible implementation, the NAND flash controller can be reset after all suspend operations of the NAND flash controller and the NAND chip have been completed; otherwise, bus conflicts may occur.

[0071] This step ensures that the control logic and physical chip are restored synchronously, avoiding subsequent problems caused by inconsistent NAND flash controller states.

[0072] S406. If the operation status is normal, clear the voltage jitter indicator.

[0073] As a feasible implementation, if the NAND flash memory operates normally within the preset monitoring period (e.g., all test commands are successfully responded to, the status register returns a normal value, and no operation failure reports are received, the embedded device can determine that the NAND flash memory is operating normally), the embedded device can determine that the event triggering the voltage jitter flag is a harmless event. At this time, the embedded device can clear the voltage jitter flag and allow the NAND flash memory to perform tasks, such as continuing to write user data.

[0074] In one embodiment, the method further includes: if the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is greater than or equal to a preset time threshold, then suspending the current operation of the NAND flash memory; and if the voltage detection circuit detects that the power supply voltage is greater than or equal to the preset voltage threshold, initializing the NAND flash memory and resuming the execution of the suspended current operation.

[0075] For example, if the voltage detection circuit detects that the power supply voltage is lower than a preset voltage threshold and the duration is greater than or equal to a preset time threshold, and the NAND flash memory is in a programming or erasing cycle, the embedded device can immediately send an abort command (typically a 70h-FFh sequence) to the NAND flash memory via the NAND flash memory controller to pause the operation. Simultaneously, key information such as the type of operation being performed (read / write / erase), the target address, the data buffer pointer, and the operation progress can be saved to non-volatile storage media. Then, a global flag can be set to prevent any new NAND flash memory operation requests until the system completes the recovery process.

[0076] As a feasible implementation, during a sustained power outage, the embedded device can enter a deep low-power state to extend the backup power supply duration. When the voltage detection circuit detects that the power supply voltage is greater than or equal to a preset voltage threshold, the voltage detection circuit can generate a rising-edge interrupt to wake up the embedded device in the low-power state. After exiting the low-power state, the embedded device can initialize the NAND flash memory and resume the execution of any suspended current operations.

[0077] As can be seen, the NAND flash memory power-down detection method shown in this application further provides a complete closed-loop recovery process and a collaborative reset mechanism for the controller state. By clearing the flag and initializing, and resetting the NAND flash memory controller, it ensures complete cleanup and logical synchronization of the system state after anomaly handling, avoiding secondary faults caused by residual states. Simultaneously, by clearing the voltage jitter flag when the NAND flash memory state is confirmed to be normal, it minimizes the handling of harmless voltage jitter events, minimizing performance loss while ensuring reliability. Furthermore, it provides a complete protection scheme for continuous power-down events. Together, these two aspects constitute a multi-layered, complete power anomaly handling system, significantly improving the data security and system reliability of the embedded storage system under various power anomaly conditions.

[0078] The method of this application has been described above; the apparatus of this application will be described below.

[0079] See Figure 5 , Figure 5 This application provides a power-loss detection device for NAND flash memory, applied to embedded devices, such as NAND flash memory. Figure 5 The device includes: The monitoring module 501 is used to monitor whether the voltage jitter flag is triggered during the operation of the NAND flash memory.

[0080] The voltage jitter flag is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold.

[0081] The monitoring module 501 is also used to monitor the operating status of the NAND flash memory within a preset monitoring period if a voltage jitter indicator is triggered.

[0082] The operation module 502 is used to perform a reset operation on the NAND flash memory if the operation status is abnormal.

[0083] In one possible design, an abnormal operating state includes at least one of the following situations: the preset register identifier of the NAND flash memory indicates an abnormal state, an instruction indicating a failure of the operation on the NAND flash memory is detected, or the execution time of the operation command on the NAND flash memory exceeds a preset timeout threshold.

[0084] In one possible design, the operation module 502 is specifically used to perform a power-down and power-on operation on the NAND flash memory chip via a hardware reset signal line or a power management unit if the operation state is abnormal.

[0085] In one possible design, the operation module 502 is also used to clear the voltage jitter flag if the operation state is normal.

[0086] In one possible design, the operation module 502 is also configured to send a reset command to the NAND flash controller to reset the internal state machine of the NAND flash controller if the operation state is abnormal.

[0087] In one possible design, the operation module 502 is also used to clear the voltage jitter flag and initialize the NAND flash memory after performing a reset operation on the NAND flash memory.

[0088] In one possible design, the operation module 502 is further configured to: suspend the current operation of the NAND flash memory if the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is greater than or equal to a preset time threshold; and initialize the NAND flash memory and resume the suspended current operation when the voltage detection circuit detects that the power supply voltage is greater than or equal to the preset voltage threshold.

[0089] The aforementioned device can monitor whether a voltage jitter flag is triggered during NAND flash memory operation. If the voltage jitter flag is triggered, the device monitors the operating status of the NAND flash memory within a preset monitoring period. If the operating status is abnormal, the device performs a reset operation on the NAND flash memory. This achieves accurate fault identification and intelligent recovery, effectively solving the problem that NAND operation faults caused by brief voltage jitters cannot be diagnosed and recovered in a timely manner. It significantly improves the data reliability and system availability of embedded devices in environments with unstable power supplies.

[0090] See Figure 6 , Figure 6 This is a schematic diagram of another embedded device provided in an embodiment of this application. The embedded device includes a processor 601 and a memory 602. The memory 602 is connected to the processor 601, for example, via a bus.

[0091] Processor 601 is configured to support the smart terminal 60 in performing the corresponding functions in the methods described in the above method embodiments. Processor 601 may be a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0092] Memory 602 is used to store program code, etc. Memory 602 may include NAND flash memory. In some embodiments, it may also include volatile memory (VM), such as random access memory (RAM), and non-volatile memory (NVM) such as read-only memory (ROM), hard disk drive (HDD), or solid-state drive (SSD). Memory 602 may also include combinations of the above types of memory.

[0093] As a feasible implementation method, Figure 6 The embedded device shown only illustrates the necessary components for performing the methods of this application. In some embodiments, the embedded device may include... Figure 1 All the structures shown will not be described in detail here.

[0094] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method as described in the foregoing embodiments.

[0095] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0096] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A method for detecting power loss in NAND flash memory, characterized in that, Applied to an embedded device, the embedded device including NAND flash memory, the method includes: During the operation of the NAND flash memory, it is monitored whether a voltage jitter flag is triggered. The voltage jitter flag is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold. If the voltage jitter flag is triggered, the operating status of the NAND flash memory is monitored within a preset monitoring period; If the operation status is abnormal, a reset operation is performed on the NAND flash memory.

2. The method as described in claim 1, characterized in that, The abnormal operation status includes at least one of the following situations: the preset register identifier of the NAND flash memory is in an abnormal state, an instruction indicating that the operation on the NAND flash memory has failed is detected, or the execution time of the operation command on the NAND flash memory exceeds a preset timeout threshold.

3. The method as described in claim 1, characterized in that, If the operation state is abnormal, then a reset operation is performed on the NAND flash memory, including: If the operation state is abnormal, the NAND flash memory chip is powered down and then powered on again via a hardware reset signal line or a power management unit.

4. The method as described in claim 1, characterized in that, The method further includes: If the operating state is normal, then the voltage jitter indicator is cleared.

5. The method as described in claim 1, characterized in that, The method further includes: If the operation state is abnormal, a reset command is sent to the NAND flash memory controller to reset the internal state machine of the NAND flash memory controller.

6. The method as described in claim 1 or 5, characterized in that, The method further includes: After performing a reset operation on the NAND flash memory, the voltage jitter flag is cleared and the NAND flash memory is initialized.

7. The method as described in claim 1, characterized in that, The method further includes: If the voltage detection circuit detects that the power supply voltage is less than the preset voltage threshold and the duration is greater than or equal to the preset time threshold, then the current operation of the NAND flash memory is paused. When the voltage detection circuit detects that the power supply voltage is greater than or equal to the preset voltage threshold, the NAND flash memory is initialized and the suspended current operation is resumed.

8. A power-loss detection device for NAND flash memory, characterized in that, Applied to embedded devices, the embedded devices including NAND flash memory, the device includes: The monitoring module is used to monitor whether a voltage jitter flag is triggered during the operation of the NAND flash memory. The voltage jitter flag is set to be triggered when the voltage detection circuit detects that the power supply voltage is less than a preset voltage threshold and the duration is less than a preset time threshold. The monitoring module is also used to monitor the operating status of the NAND flash memory within a preset monitoring period if the voltage jitter indicator is triggered. An operation module is used to perform a reset operation on the NAND flash memory if the operation state is an abnormal state.

9. An embedded device, comprising a processor, a memory, and a computer program or instructions stored in the memory, characterized in that, The memory includes NAND flash memory, and the processor executes the computer program or instructions to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1 to 7.

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