Method of manufacturing a semi-floating gate transistor
By forming a vertical direct contact window using self-aligned etching technology, the problem of photolithographic pattern alignment deterioration in the fabrication of semi-floating gate transistors is solved, thereby improving device uniformity and charging speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2025-01-02
- Publication Date
- 2026-07-03
AI Technical Summary
In existing semi-floating gate transistor manufacturing methods, the alignment of the photolithographic pattern of the contact window is prone to deterioration, leading to device asymmetry and affecting tunneling efficiency and charging speed.
By employing self-aligned etching technology, the photolithographic etching of the lateral contact window is omitted. The vertical direct contact window is formed by using the SIN hard mask and sidewall protection of the control gate structure, which simplifies the process and improves tunneling efficiency.
It improves the uniformity and process window size of semi-floating gate transistors, increases charging speed and tunneling efficiency, and avoids the formation of asymmetric devices.
Smart Images
Figure CN122340872A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor manufacturing technology, and more specifically to a method for manufacturing a semi-floating gate transistor (SFGT). Background Technology
[0002] Capacitors are a bottleneck in the development of traditional DRAM (Dynamic Random Access Memory). Semi-floating gate transistors (SFGTs), as a promising capacitor-free DRAM, are compatible with standard logic processes and are easier to miniaturize. For example... Figure 1 As shown, the semi-floating gate transistor (SFGT) is a novel device with a "semi-floating gate" structure, combining a tunneling field-effect device (TFET) and a floating gate device. The TFET is used to charge and discharge the floating gate and perform the "data erase and write" operation, while the floating gate realizes the "data storage and read" function. The "data" erase and write of the semi-floating gate transistor (SFGT) is easier and faster.
[0003] The U-trench of a floating gate device isolates the semi-floating gate N-well, forming a U-shaped channel at its bottom. Compared to traditional profile channels, this is beneficial for miniaturizing the device area. Furthermore, the gate polysilicon within the U-trench is used to store charge, utilizing the tunneling effect to accelerate charge writing.
[0004] P-type doped semi-floating gate polysilicon forms a PN junction by directly contacting the N-type doped semi-floating gate N-well on the silicon substrate through the semi-floating gate dielectric contact window (C-window) on the U-trench gate oxide. The charging and discharging process of the semi-floating gate polysilicon is the process of charge entering and exiting the semi-floating gate dielectric contact window (C-window), thereby realizing the transition between the logic 1 and 0 states of the device.
[0005] In logic / memory compatible embedded semi-floating gate technology, after the U-shaped trench is formed, a semi-floating gate dielectric layer is grown. Then, a first semi-floating gate polysilicon deposition is performed to fill the U-shaped trench. Next, the semi-floating gate dielectric is etched onto the upper surface of the semi-floating gate N-well on one side of the U-shaped trench to form a semi-floating gate dielectric contact window (C-window), exposing the upper surface of the silicon substrate's semi-floating gate N-well. A second semi-floating gate polysilicon deposition is then performed, and P-type doping is applied to achieve contact between the semi-floating gate polysilicon and the silicon substrate's semi-floating gate N-well. Finally, etching is used to reduce the thickness of the semi-floating gate polysilicon above the silicon substrate (to approximately...). Subsequently, a control gate dielectric layer is grown and control gate polysilicon is deposited. Based on this, a control gate / semi-floating gate self-aligned pattern is formed through a control gate photolithography etching process.
[0006] In the aforementioned logic / memory compatible embedded semi-floating gate process, the PN junction formed by the contact between the semi-floating gate polysilicon and the active region of the substrate at the semi-floating gate dielectric contact window (C-window) is the core of the semi-floating gate operation. Since photolithography is used to define the contact window (C-window) region, forming a horizontal contact window (C-window), the overlay along the AA (active region) direction has a significant impact on the device. Under ideal photolithographic pattern overlay conditions at the contact window (C-window), a symmetrical semi-floating gate device will be formed; however, if the photolithographic pattern overlay at the contact window (C-window) deteriorates, an asymmetrical semi-floating gate device will be formed.
[0007] Ideally, the photolithographic pattern of the contact window (C-window) should be aligned (PH overlay) as follows: Figure 2 As shown, a symmetrical semi-floating gate device is formed.
[0008] Deterioration of lithographic pattern alignment (PH overlay) in the contact window (C-window) is as follows: Figure 3 As shown, an asymmetric semi-floating gate device is formed: On the left side of the semi-floating gate dielectric contact window (C-window), the opening of the contact window (C-window) is small, and the contact window (C-window) is far from the gate of the tunnel field-effect transistor (TFET), resulting in low tunneling efficiency and slow charge loading into the semi-floating gate polysilicon; On the right side of the semi-floating gate device, the opening of the contact window (C-window) is too large, and when the control gate photolithography pattern alignment (control gate PH OVL) is also poor, the exposed silicon substrate will be damaged during the etching process to form the control gate pattern, forming void defects. Summary of the Invention
[0009] The technical problem to be solved by the present invention is to provide a method for manufacturing a semi-floating gate transistor (SFGT) that can avoid the formation of asymmetrical semi-floating gate devices, improve uniformity and process window size, and increase charging speed.
[0010] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a semi-floating gate transistor, which includes the following steps:
[0011] S1. Provides a semiconductor silicon substrate 100;
[0012] In the first region 103 of the semiconductor silicon substrate 100, multiple X-direction field oxygen 101 isolates multiple X-direction first active regions 105, and the multiple X-direction field oxygen 101 and the multiple X-direction first active regions 105 are arranged in parallel.
[0013] The X direction is parallel to the length direction of the first active region, and the Y direction is perpendicular to the X direction.
[0014] Open the first region 103 to expose the upper surface of the X-direction field oxygen 101 and the upper surface of the first active region 105 of the first region 103;
[0015] Photolithography, etching, and U-shaped trenches 109 are formed in each first active region 105 by opening multiple pairs of Y-directions;
[0016] Each pair of Y-direction openings consists of two adjacent Y-direction openings in the X-direction.
[0017] A trench oxide layer 110 is formed on the upper surface of the first active region 105 and the surface of the U-shaped trench 109;
[0018] S2. Deposit semi-floating gate polysilicon 120, the semi-floating gate polysilicon 120 filling the U-shaped trench 109;
[0019] S3. Photolithography, etching, and removal of the semi-floating gate polysilicon 120 on the X-direction field oxygen 101;
[0020] S4. Deposited gate oxide layer 121
[0021] S5. Deposited control gate polysilicon 122;
[0022] S6. Deposit SIN hard mask 123;
[0023] S7. Photolithography, etching, remove the SIN hard mask 123 and control gate polysilicon outside the set width of each pair of Y-direction openings in the X-direction, stop at the gate oxide layer 121, and retain the SIN hard mask 123 and control gate polysilicon 122 between each pair of Y-direction openings and within the set width of their X-direction openings.
[0024] S8. Deposited SIN sidewall medium layer 124;
[0025] S9. Etch the SIN sidewall dielectric layer 124, remove the SIN sidewall dielectric layer 124 above the control gate polysilicon 122 corresponding to each pair of Y-direction openings, and remove the SIN sidewall dielectric layer 124 above the gate oxide layer 121 on the X-direction outer side of the control gate polysilicon 122 corresponding to each pair of Y-direction openings to form a control gate sidewall.
[0026] S10. Using the SIN hard mask 123 and the control gate sidewall as a mask, the trench oxide layer 110 is self-aligned and etched to remove the gate oxide layer 121, the semi-floating gate polysilicon 120 and the trench oxide layer 110 on the outer side of the control gate polysilicon 122 in the X direction corresponding to each pair of Y-direction openings, so that the outer side of the semi-floating gate polysilicon 120 in the X direction corresponding to each pair of Y-direction openings is exposed as a contact window 111.
[0027] S11. A silicon epitaxial layer 125 is grown on the upper surface of the exposed first active region 105 and at the contact window 111 of the semi-floating gate polysilicon 120;
[0028] S12. Proceed with subsequent processes.
[0029] Preferably, in step S12, subsequent processes include removing the SIN hard mask 123 and the SIN sidewall dielectric layer 124.
[0030] Preferably, the semiconductor silicon substrate 100 further includes a second region 104;
[0031] The first region 103 and the second region 104 are separated by shallow trench isolation 102;
[0032] The first region 103 is used to form a memory cell array;
[0033] The second region 104 is used to form logic circuits.
[0034] Preferably, in step S2, a semi-floating gate polysilicon 120 is first deposited, and then patternless etching is performed to thin the semi-floating gate polysilicon 120 to the height required for the top surface of the semi-floating gate polysilicon gate.
[0035] Preferably, in step S11, the residual oxides on the surface of the first active region 105 on the outer side of the semi-floating gate polysilicon 120 corresponding to each pair of Y-direction openings are first removed, and then silicon epitaxy 125 is grown on the upper surface of the exposed first active region 105 and at the contact window 111 of the semi-floating gate polysilicon 120.
[0036] Preferably, in step S11, the upper surface of the grown silicon epitaxial layer 125 is flush with the upper surface of the semi-floating gate polysilicon 120.
[0037] Preferably, the set width is 1 to 3 times the thickness of the trench oxide layer 110.
[0038] Preferably, the set width is 10nm to 80nm.
[0039] Preferably, in step S1, the upper part of the first active region 105 is doped with a first type and the lower part is doped with a second type.
[0040] The bottom of the U-shaped trench 109 enters the lower part of the first active region 105;
[0041] In step S2, the semi-floating gate polysilicon 120 is subjected to a second type of doping;
[0042] The first type of doping is N-type doping, and the second type of doping is P-type doping; or, the first type of doping is P-type doping, and the second type of doping is N-type doping.
[0043] The manufacturing method of the semi-floating gate transistor (SFGT) of the present invention directly omits the photolithography etching of the lateral contact window (C-window), simplifying the existing two-stage semi-floating gate polysilicon deposition process into one. A SIN hard mask 123 is deposited on the control gate polysilicon 122, and then the control gate structure pattern is defined by photolithography. The control gate polysilicon 122 and the SIN hard mask 123 are etched and stopped on the gate oxide layer 121 on the upper surface of the semi-floating gate polysilicon 120 to form the control gate structure. Then, the SIN sidewalls of the control gate structure are formed. Since the top of the formed control gate structure is protected by the SIN hard mask 123 and the sides are protected by the SIN sidewalls, the control gate structure is completely protected by SIN. Therefore, the SIN hard mask can be used to self-align the etching of the semi-floating gate polysilicon 120. Two semi-floating gate polysilicon side notches are formed on the X-direction outer side of the semi-floating gate polysilicon 120 corresponding to a pair of Y-direction openings, which are the self-aligned vertical direct contact window (C-window) 111. The fabrication method of this semi-floating gate transistor (SFGT) utilizes the illumination of the control gate structure photolithography to form a vertical direct contact window (C-window) 111 through self-aligned etching using the SIN protective layer of the control gate structure, replacing the conventional lateral contact window (C-window) photolithography etching. This eliminates one contact window (C-window) photolithography process and avoids the formation of asymmetrical semi-floating gate devices due to deterioration of the photolithographic pattern alignment (PH overlay) of the lateral contact window (C-window). This significantly improves the uniformity and process window size of the semi-floating gate transistor (SFGT). In addition, since the physical distance between the vertical direct contact window (C-window) 111 and the tunneling field-effect device (TFET) gate of the semi-floating gate transistor (SFGT) is greatly shortened, the tunneling efficiency is high, which can improve the charging speed of the semi-floating gate polysilicon. Attached Figure Description
[0044] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a schematic diagram of a typical semi-floating gate transistor structure;
[0046] Figure 2 This is a schematic diagram of a symmetrical semi-floating gate device formed by aligning the photolithographic pattern of the contact window with an ideal configuration in the existing semi-floating gate transistor manufacturing method.
[0047] Figure 3 This is a schematic diagram of an asymmetric semi-floating gate device formed by the deterioration of the photolithographic pattern alignment of the contact window in existing semi-floating gate transistor manufacturing methods:
[0048] Figures 4 to 15 This is a three-dimensional structural diagram of each process step in the manufacturing method of the semi-floating gate transistor of the present invention.
[0049] Explanation of the reference numerals in the figure:
[0050] 100. Semiconductor silicon substrate; 101. Field oxide; 102. Shallow trench isolation; 103. First region; 104. Second region; 105. First active region; 109. U-shaped trench; 110. Trench oxide layer; 120. Semi-floating gate polysilicon; 121. Gate oxide layer; 122. Control gate polysilicon; 123. SIN hard mask; 124. SIN sidewall dielectric layer; 111. Contact window; 125. Silicon epitaxy. Detailed Implementation
[0051] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0052] Example 1
[0053] A method for manufacturing a semi-floating gate transistor (SFGT) includes the following steps:
[0054] S1. Provides a semiconductor silicon substrate 100;
[0055] In the first region 103 of the semiconductor silicon substrate 100, multiple X-direction field oxygen 101 isolates multiple X-direction first active regions 105, and the multiple X-direction field oxygen 101 and the multiple X-direction first active regions 105 are arranged in parallel.
[0056] The X direction is parallel to the length direction of the first active region, and the Y direction is perpendicular to the X direction.
[0057] Open the first region 103 to expose the upper surface of the X-direction field oxygen 101 and the upper surface of the first active region 105 of the first region 103;
[0058] Photolithography, etching, and U-shaped trenches 109 are formed in each first active region 105 along multiple pairs of Y-direction openings;
[0059] Each pair of Y-direction openings consists of two adjacent Y-direction openings in the X-direction.
[0060] A trench oxide layer 110 is formed on the upper surface of the first active region 105 and the surface of the U-shaped trench 109, such as Figure 4 As shown;
[0061] S2. Deposit semi-floating gate polysilicon 120, the semi-floating gate polysilicon 120 filling the U-shaped trench 109, such as Figure 6 As shown;
[0062] S3. Photolithography, etching, removal of the semi-floating gate polysilicon 120 on the X-direction field oxygen 101, such as... Figure 7 As shown;
[0063] S4. Deposited gate oxide layer 121
[0064] S5. Deposited control gate polysilicon 122, such as Figure 8 As shown;
[0065] S6. Deposit SIN hard mask 123, as shown Figure 9 As shown;
[0066] S7. Photolithography, etching, removing the SIN hard mask 123 and control gate polysilicon beyond the set width outside the X direction of each pair of Y-direction openings, stopping at the gate oxide layer 121, retaining the SIN hard mask 123 and control gate polysilicon 122 between each pair of Y-direction openings and within the set width outside the X direction, as shown. Figure 10 As shown;
[0067] S8. Deposited SIN sidewall medium layer 124, such as Figure 11 As shown;
[0068] S9. Etch the SIN sidewall dielectric layer 124, remove the SIN sidewall dielectric layer 124 above the control gate polysilicon 122 corresponding to each pair of Y-direction openings, and remove the SIN sidewall dielectric layer 124 above the gate oxide layer 121 on the outer side of the X-direction of the control gate polysilicon 122 corresponding to each pair of Y-direction openings, to form the control gate sidewall, as shown. Figure 12 As shown;
[0069] S10. Using the SIN hard mask 123 and the control gate sidewall as a mask, self-align the etching trench oxide layer 110 to remove the gate oxide layer 121, the semi-floating gate polysilicon 120, and the trench oxide layer 110 on the outer side of the control gate polysilicon 122 in the X direction corresponding to each pair of Y-direction openings, exposing the outer side of the semi-floating gate polysilicon 120 in the X direction as a contact window (C-window) 111, which is the self-aligned vertical direct contact window (C-window). Figure 13 As shown;
[0070] S11. A silicon epitaxial layer 125 is grown on the upper surface of the exposed first active region 105 and at the contact window (C-window) 111 of the semi-floating gate polysilicon 120, as shown. Figure 14 As shown, the grown silicon epitaxial layer 125 will contact the side of the semi-floating gate polysilicon 120 to form a PN junction, realizing the function of the contact window (C-window);
[0071] S12. Proceed with subsequent processes.
[0072] The manufacturing method of the semi-floating gate transistor (SFGT) in Embodiment 1 directly omits the photolithography etching of the lateral contact window (C-window), simplifying the existing two-stage semi-floating gate polysilicon deposition process into one. A SIN hard mask 123 is deposited on the control gate polysilicon 122, and then the control gate structure pattern is defined by photolithography. The control gate polysilicon 122 and the SIN hard mask 123 are etched and stopped on the gate oxide layer 121 on the upper surface of the semi-floating gate polysilicon 120 to form the control gate structure. Then, the SIN sidewalls of the control gate structure are formed. Since the top of the formed control gate structure is protected by the SIN hard mask 123 and the sides are protected by the SIN sidewalls, the control gate structure is completely protected by SIN. Therefore, the SIN can be used as a hard mask for self-aligned etching of the semi-floating gate polysilicon 120. Two semi-floating gate polysilicon side notches are formed on the outer side of the semi-floating gate polysilicon 120 in the X direction corresponding to a pair of Y-direction openings, which are the self-aligned vertical direct contact window (C-window) 111.
[0073] The fabrication method of the semi-floating gate transistor (SFGT) in Embodiment 1 utilizes the illumination of the control gate structure photolithography to form a vertical direct contact window (C-window) 111 through self-aligned etching using the SIN protective layer of the control gate structure, replacing the conventional lateral contact window (C-window) photolithography etching. This eliminates one contact window (C-window) photolithography process and avoids the formation of asymmetrical semi-floating gate devices due to deterioration of the photolithographic pattern alignment (PH overlay) of the lateral contact window (C-window). This significantly improves the uniformity and process window size of the semi-floating gate transistor (SFGT). In addition, since the physical distance between the vertical direct contact window (C-window) 111 and the tunneling field-effect device (TFET) gate of the semi-floating gate transistor (SFGT) is greatly shortened, the tunneling efficiency is high, which can improve the charging speed of the semi-floating gate polysilicon.
[0074] Example 2
[0075] In the manufacturing method of the semi-floating gate transistor (SFGT) based on Embodiment 1, in step S1, the upper part of the first active region 105 is doped with a first type and the lower part is doped with a second type.
[0076] The bottom of the U-trench 109 enters the lower part of the first active region 105;
[0077] In step S2, the semi-floating gate polysilicon (120) is subjected to a second type of doping;
[0078] The first type of doping is N-type doping, and the second type of doping is P-type doping; or, the first type of doping is P-type doping, and the second type of doping is N-type doping.
[0079] Preferably, the semiconductor silicon substrate 100 further includes a second region 104; the first region 103 and the second region 104 are separated by shallow trench isolation (STI) 102; the first region 103 is used to form a memory cell array; and the second region 104 is used to form logic circuits.
[0080] Example 3
[0081] Based on the fabrication method of the semi-floating gate transistor (SFGT) in Embodiment 1, in step S2, a semi-floating gate polysilicon 120 is first deposited, such as... Figure 5 As shown; then, blank etching (blanket ET) is performed to thin the semi-floating gate polysilicon 120 to the height required for the top surface of the semi-floating gate polysilicon, as shown. Figure 6 As shown.
[0082] Example 4
[0083] In the manufacturing method of the semi-floating gate transistor (SFGT) based on Embodiment 1, in step S7, the set width is 1 to 3 times the thickness of the trench oxide layer 110.
[0084] Preferably, the specified width is 10nm to 80nm.
[0085] Example 5
[0086] In the manufacturing method of the semi-floating gate transistor (SFGT) based on Embodiment 1, in step S11, the residual oxide on the surface of the first active region 105 on the outer side of the semi-floating gate polysilicon 120 in the X direction corresponding to each pair of Y-direction openings is first removed, and then silicon epitaxy 125 is grown on the exposed upper surface of the first active region 105 and at the contact window 111 of the semi-floating gate polysilicon 120.
[0087] Preferably, in step S11, the upper surface of the grown silicon epitaxial layer 125 is flush with the upper surface of the semi-floating gate polysilicon 120.
[0088] Example 6
[0089] Based on the manufacturing method of the semi-floating gate transistor (SFGT) in Embodiment 1, step S12 includes subsequent processes such as removing the SIN hard mask 123 and the SIN sidewall dielectric layer 124. Figure 15 As shown.
[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method of fabricating a semi-floating gate transistor, characterized by, Includes the following steps: S1. Provides a semiconductor silicon substrate (100); In the first region (103) of the semiconductor silicon substrate (100), multiple X-direction field oxygen (101) isolates multiple X-direction first active regions (105), and the multiple X-direction field oxygen (101) and the multiple X-direction first active regions (105) are arranged in parallel. The X direction is parallel to the length direction of the first active region, and the Y direction is perpendicular to the X direction. Open the first region (103) to expose the upper surface of the X-direction field oxygen (101) and the upper surface of the first active region (105) of the first region (103); Photolithography, etching, and U-shaped trenches (109) are formed in each first active region (105) by opening along multiple pairs of Y directions; Each pair of Y-direction openings consists of two adjacent Y-direction openings in the X-direction. A trench oxide layer (110) is formed on the upper surface of the first active region (105) and the surface of the U-shaped trench (109); S2. Deposit semi-floating gate polysilicon (120), the semi-floating gate polysilicon (120) fills the U-shaped trench (109); S3. Photolithography, etching, removal of the semi-floating gate polysilicon (120) on the X-direction field oxygen (101); S4. Deposited gate oxide layer (121) S5. Deposit control gate polysilicon (122); S6. Deposit SIN hard mask (123); S7. Photolithography, etching, removing the SIN hard mask (123) and control gate polysilicon outside the set width of each pair of Y-direction openings in the X direction, stopping at the gate oxide layer (121), retaining the SIN hard mask (123) and control gate polysilicon (122) between each pair of Y-direction openings and within the set width of their X-direction outer side. S8. Deposit SIN sidewall medium layer (124); S9. Etch the SIN sidewall dielectric layer (124), remove the SIN sidewall dielectric layer (124) above the control gate polysilicon (122) corresponding to each pair of Y-direction openings, remove the SIN sidewall dielectric layer (124) above the gate oxide layer (121) on the outer side of the X-direction of the control gate polysilicon (122) corresponding to each pair of Y-direction openings, and form the control gate sidewall. S10. Using the SIN hard mask (123) and the control gate sidewall as a mask, the trench oxide layer (110) is self-aligned and etched to remove the gate oxide layer (121), the semi-floating gate polysilicon (120) and the trench oxide layer (110) on the outer side of the control gate polysilicon (122) corresponding to each pair of Y-direction openings, so that the outer side of the semi-floating gate polysilicon (120) corresponding to each pair of Y-direction openings is exposed as a contact window (111). S11. A silicon epitaxial layer (125) is grown on the upper surface of the exposed first active region (105) and at the contact window (111) of the semi-floating gate polysilicon (120); S12. Proceed with subsequent processes.
2. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, In step S12, subsequent processes include removing the SIN hard mask (123) and the SIN sidewall dielectric layer (124).
3. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, The semiconductor silicon substrate (100) also includes a second region (104); The first region (103) and the second region (104) are separated by shallow trench isolation (102); The first region (103) is used to form a memory cell array; The second region (104) is used to form logic circuits.
4. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, In step S2, a semi-floating gate polysilicon (120) is first deposited, and then patternless etching is performed to thin the semi-floating gate polysilicon (120) to the height required for the top surface of the semi-floating gate polysilicon gate.
5. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, In step S11, the residual oxide on the surface of the first active region (105) on the outer side of the X direction of each pair of Y-direction openings of the semi-floating gate polysilicon (120) is first removed, and then silicon epitaxy (125) is grown on the upper surface of the exposed first active region (105) and at the contact window (111) of the semi-floating gate polysilicon (120).
6. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, In step S11, the upper surface of the grown silicon epitaxial layer (125) is flush with the upper surface of the semi-floating gate polysilicon (120).
7. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, The set width is 1 to 3 times the thickness of the trench oxide layer (110).
8. The method for manufacturing a semi-floating gate transistor according to claim 7, characterized in that, The set width is 10nm to 80nm.
9. The method for manufacturing a semi-floating gate transistor according to claim 1, characterized in that, In step S1, the upper part of the first active region (105) is doped with the first type, and the lower part is doped with the second type; The bottom of the U-shaped trench (109) enters the lower part of the first active region (105); In step S2, the semi-floating gate polysilicon (120) is subjected to a second type of doping; The first type of doping is N-type doping, and the second type of doping is P-type doping; or, the first type of doping is P-type doping, and the second type of doping is N-type doping.