A manufacturing method of a back SE structure TOPCon cell

Abstract

This invention provides a method for fabricating a TOPCon battery with a back-side SE structure. By forming high surface concentration + thick poly and low surface concentration + thin poly regions on the back side, this structure solves the problem of slurry sintering in the metal region, while reducing the poly thickness in the non-metal region, reducing parasitic absorption, and increasing the short-circuit current of the battery, thereby improving the battery conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, specifically to a method for manufacturing a back-side SE structure TOPCon cell. Background Technology

[0002] Currently, the TOPCon structure adopts a tunneling oxide structure on the back side, which involves depositing an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer on the back side. By utilizing the chemical passivation and majority carrier tunneling effect of silicon oxide, as well as the field passivation of the doped polycrystalline silicon layer, the surface recombination on the back side is greatly reduced, thereby improving the conversion efficiency of the battery.

[0003] While the TOPCon structure offers excellent passivation, the introduced doped polysilicon exhibits severe parasitic absorption of light. According to experimental data, the doped polysilicon on the back side can cause an absorption of approximately 0.004 mA / cm² / nm. A 30nm doped polysilicon layer already meets the current passivation requirements. However, due to limitations in the current back-side paste, when the thickness is less than 80nm, the back-side polysilicon layer will experience paste burn-through, thus affecting electrical performance. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a TOPCon solar cell with a back-side SE structure, in order to solve the problem of severe parasitic absorption of light by doped polycrystalline silicon introduced by the back-side TOPCon structure.

[0005] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a method for manufacturing a back-side SE structure TOPCon battery, comprising: S1. First alkaline etching: Select an N-type silicon wafer and texturize it through alkaline etching; S2, Boron diffusion: Boron diffusion is performed on the texturized silicon wafer in a back-to-back manner; S3, Secondary Alkaline Etching: Removing the BSG and PN junction on the back and edges of the silicon wafer using alkaline etching; S4. Backside deposition: A tunneling oxide layer, a first poly layer, an intermediate oxide layer, and a second poly layer are sequentially deposited on the backside of the silicon wafer. After phosphorus diffusion, a first doped poly layer and a second doped poly layer are formed. S5. Mask Formation: A mask material is coated on the back of a silicon wafer, and the mask material is patterned and modified. The modified areas form a mask layer, while the unmodified areas retain the mask material. The modified mask layer is resistant to acids and alkalis, while the unmodified mask material is not resistant to acids and alkalis. S6, Acid Etching: HF is used to etch the mask material and PSG in the unmodified area on the back side. In the modified area, the PSG under the mask layer is preserved due to the presence of the mask layer. S7. Three-stage alkaline etching: The second doped poly layer in the unmodified area on the back side is removed by alkaline etching. In the modified area, the PSG under the mask layer is retained due to the presence of the mask layer, and in the unmodified area, the first doped poly layer is retained due to the presence of the intermediate oxide layer. S8, RCA cleaning: RCA cleaning removes the mask layer from the modified area on the back of the silicon wafer; S9. Functional layer deposition: Deposit a functional layer on the surface of the silicon wafer; S10, Electrode Formation: An electrode is formed in the modified region to form the back SE structure.

[0006] Preferably, in step S3, the BSG and PN junction on the back and edge of the silicon wafer are removed while the front BSG is retained.

[0007] Preferably, in step S4, the thickness of the second doped poly layer is greater than the thickness of the first doped poly layer.

[0008] Preferably, in step S4, the doping concentration of the second doped ply layer is higher than that of the first doped ply layer.

[0009] Preferably, in step S5, the patterning modification method used is laser scanning heating, wherein the mask material reacts under heating to generate a mask layer.

[0010] More preferably, in step S5, the coated mask material is tetraethyl orthosilicate, silane, etc.

[0011] More preferably, the laser is one of ultraviolet, green light, and infrared light, with a power of 5-100W, a repetition frequency of 100-1000KHZ, and a speed of 10000-70000mm / min.

[0012] Preferably, before acid etching in step S6, the poly layer coated on the front side is removed by alkaline etching.

[0013] Preferably, in step S8, the RCA cleaning removes the front-side BSG simultaneously.

[0014] Preferably, in step S9, the functional layer can be a passivation layer, an antireflection layer, or a passivation and antireflection layer, and the material of the functional layer can be alumina, silicon nitride, silicon oxynitride, silicon oxide, etc.

[0015] Preferably, in step S10, the electrode is formed by printing silver paste on the electrode area using screen printing and sintering to form a metallized structure.

[0016] In a second aspect, the present invention also provides a TOPCon battery with a back-side SE structure, the battery comprising a back-side SE structure formed using the method described above.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: The manufacturing method of the present invention involves depositing an intermediate oxide layer and two poly layers of different thicknesses on the back side of a silicon wafer. The intermediate oxide layer blocks phosphorus atoms. After phosphorus diffusion, the phosphorus doping concentration of the first doped poly layer is lower than that of the second doped poly layer. Then, a mask material coated on the back side of the silicon wafer is modified. The mask material in the modified region (metal region) is modified to form an oxide and / or nitride and / or carbide mask layer with acid and alkali resistance. This mask layer provides protection, and the silicon wafer is etched after... The unmodified region (non-metallic region) on the back side forms a tunneling oxide layer and a first doped poly layer, serving as a lightly doped region. The modified region (metallic region) on the back side forms a tunneling oxide layer, a first doped poly layer, an intermediate oxide layer, and a second doped poly layer, serving as a heavily doped region. This satisfies the thickness and concentration differences between the metallic and non-metallic regions on the back side of the silicon wafer. The metallic region with high doping concentration and thick doped poly layer ensures the contact performance of the paste, while the non-metallic region with low doping concentration and thin doped poly layer can reduce the parasitic absorption of light by the poly layer, thereby improving the short-circuit current. Attached Figure Description

[0018] Figure 1 This is a structural diagram of a back-side SE structure TOPCon battery prepared according to the method of the present invention; Figure 2 This is a topographic image of the metal and non-metal regions of a silicon wafer prepared according to the method of Example 1 after reverse etching. Figure 3 This is an ECV image of the metal and non-metal regions of a silicon wafer prepared according to the method of Example 1 after reverse etching; Figure 4 These are images of the metal and non-metal regions of a silicon wafer prepared according to the method of Example 2 after reverse etching. Figure 5 The image shows the ECV pattern of the metal and non-metal regions of the silicon wafer prepared according to the method of Example 2 after reverse etching.

[0019] In the diagram: 1. Front silicon nitride; 2. Aluminum oxide; 3. P-type emitter; 4. N-type silicon substrate; 5. Tunneling oxide layer; 6. First doped poly layer; 7. Intermediate oxide layer; 8. Second doped poly layer; 9. Back silicon nitride; 10. Back electrode; 11. Front electrode. Detailed Implementation

[0020] To reduce parasitic light absorption caused by the doped poly structure introduced by the TOPCon battery structure on the back side, a method for fabricating a TOPCon battery with a back-side SE structure is provided. In this method, an "SE" structure is used on the back side of the TOPCon battery, i.e., a double-layer poly structure is deposited on the back side. Both poly layers are doped using high-temperature phosphorus diffusion. Due to the presence of the intermediate oxide layer, phosphorus diffusion is hindered, resulting in a lower poly concentration in the first layer compared to the second. A patterned region is then formed using mask coating and laser heating. The laser-coated mask possesses acid and alkali resistance. The SE structure is then formed by reverse etching. The heavily doped region (metal region) has a structure of tunneling oxide layer + first doped poly layer + intermediate oxide layer + second doped poly layer, while the lightly doped region (non-metal region) has a structure of tunneling oxide layer + first doped poly layer. The thickness of the first doped poly layer is less than the thickness of the second doped poly layer.

[0021] In an exemplary embodiment, the back-side SE structure is prepared as follows: 1. Select N-type silicon wafers with a thickness of 100-150um and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a grooved process to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g. 2. The silicon wafers obtained in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-400 ohms / sq. 3. Remove the BSG and PN junction on the back and edges of the silicon wafer obtained in step 2 using a tank alkaline polishing method, while retaining the BSG on the front. 4. The silicon wafer obtained in step 3 is deposited sequentially with a first poly layer, an intermediate oxide layer, and a second poly layer using LPCVD. After high-temperature phosphorus diffusion, two doped poly layers are formed. Due to the presence of the intermediate oxide layer, it will have a blocking effect on phosphorus atoms. Therefore, the poly doping concentration of the first layer will be lower than that of the second layer. That is, a tunneling oxide layer + a thinner low-doped poly layer with thicknesses of 1-2 nm and 10-50 nm, respectively; and an oxide layer + a thicker high-doped poly layer with thicknesses of 0.5-1 nm and 50-100 nm, respectively. 5. Coat the surface of the silicon wafer obtained in step 4 with a mask material solution such as tetraethyl orthosilicate and silane nitride. After drying, a mask material is formed. The surface of the mask material is heated by a laser. The mask material in the heated area will react under the high temperature of laser irradiation to generate a mask layer with acid and alkali resistance, such as silicon oxide / silicon nitride / silicon oxynitride / silicon carbide and other types of oxides, nitrides and carbides. The laser is one of ultraviolet / green light / infrared light, with a power of 5-100W, a repetition frequency of 100-1000KHZ, and a speed of 10000-70000mm / min. 6. Remove the PSG on the front side of the silicon wafer obtained in step 5, and then etch it using a tank-type alkaline polishing machine. The etching process is as follows: first, remove the poly layer around the front side with alkali and additives, and then clean the PSG and mask material in the non-laser area on the back side with HF solution at a concentration-volume ratio of 1%-10% for 30-200s. Since the mask in the laser area has a certain acid resistance, it will not be completely cleaned away, so the PSG under the mask can be completely retained. Then, etch the second layer of poly with alkali at a concentration-volume ratio of 0.1-5% for 100-200s. Since there is a mask and PSG in the laser area, the alkali will not corrode the poly. In the non-laser area, since the PSG has been cleaned away, the alkali can corrode the second layer of poly, but due to the presence of the intermediate oxide layer, it has a blocking effect on the alkali. Therefore, the poly underneath will not be etched, thus forming the SE structure mentioned above. The mask and the front side BSG will be completely removed in the subsequent RCA cleaning. 7. The silicon wafer obtained in step 6 is coated with silicon nitride + aluminum oxide on the front side with thicknesses of 70-90nm and 3-10nm respectively; and silicon nitride on the back side with a thickness of 80-90nm. 8. The silicon wafer obtained in step 7 is screen printed with silver-aluminum paste on the front and silver paste on the back.

[0022] The back-side SE structure TOPCon battery fabrication method proposed above solves the slurry sintering problem in the metal region and reduces the thickness of the poly layer in the non-metal region, thereby reducing parasitic absorption, increasing the short-circuit current of the battery, and thus improving the battery conversion efficiency.

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicating orientation or positional relationships, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Example 1

[0026] 1. Select an N-type 182*91 rectangular silicon wafer with a thickness of 100-150um and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a groove to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g. 2. The silicon wafers obtained in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-400 ohms / sq. 3. Remove the BSG and PN junction on the back and edges of the silicon wafer obtained in step 2 using a tank alkaline polishing method, while retaining the BSG on the front. 4. The silicon wafer obtained in step 3 is deposited sequentially with a first poly layer, an intermediate oxide layer, and a second poly layer using LPCVD. After high-temperature phosphorus diffusion, two doped poly layers are formed. Due to the presence of the intermediate oxide layer, it will have a blocking effect on phosphorus atoms. Therefore, the poly doping concentration of the first layer will be lower than that of the second layer. That is, a tunneling oxide layer + a thinner low-doped poly layer with thicknesses of 1.5 nm and 30 nm, respectively; and an oxide layer + a thicker high-doped poly layer with thicknesses of 1 nm and 80 nm, respectively. 5. Coat the surface of the silicon wafer obtained in step 4 with a mask material solution of tetraethyl orthosilicate, and dry it at high temperature to form a mask material. Heat the surface of the mask material with a laser. The mask material in the heated area will react to generate silicon oxide and other types of oxides, which have acid and alkali resistance. The laser is ultraviolet green with a power of 30W, a repetition frequency of 300KHZ, and a speed of 30000mm / min. 6. Remove the PSG on the front side of the silicon wafer obtained in step 5, and then etch it using a tank-type alkaline polishing machine. The etching process is as follows: first, remove the poly layer around the front side using alkali and additives; then, clean the PSG and mask material in the non-laser area on the back side with HF solution at a concentration-to-volume ratio of 3% for 150 seconds. Since the mask in the laser area has a certain acid resistance, it will not be completely cleaned away, so the PSG under the mask can be completely retained. Then, etch the second layer of poly using alkali at a concentration-to-volume ratio of 1% for 120 seconds. Because the laser area has the mask and PSG, the alkali will not corrode the poly. In the non-laser area, since the PSG has been cleaned away, the alkali can corrode the second layer of poly, but due to the presence of the intermediate oxide layer, it has a blocking effect on the alkali, so the lower poly layer will not be etched, thus forming the SE structure described above. The mask and the front side BSG will be completely removed in the subsequent RCA cleaning. See Appendix for details. Figure 2 morphology and appendages Figure 3 ECV results; 7. The silicon wafer obtained in step 6 is coated with silicon nitride and aluminum oxide on the front side with thicknesses of 80nm and 3.5nm respectively; and with silicon nitride on the back side with a thickness of 80-90nm. 8. The silicon wafer obtained in step 7 is screen printed with silver-aluminum paste on the front and silver paste on the back. Example 2

[0027] 1. Select an N-type 182*91 rectangular silicon wafer with a thickness of 100-150um and a resistivity of 0.2-2.1mΩ*cm. Then, perform alkaline texturing in a groove to achieve a reflectivity of 9-11% and a weight reduction of 0.3-0.5g. 2. The silicon wafers obtained in step 1 are subjected to boron diffusion in a back-to-back manner for 3 hours and 30 minutes, with a sheet resistance of 200-400 ohms / sq. 3. Remove the BSG and PN junction on the back and edges of the silicon wafer obtained in step 2 using a tank alkaline polishing method, while retaining the BSG on the front. 4. The silicon wafer obtained in step 3 is deposited sequentially with a first poly layer, an intermediate oxide layer, and a second poly layer using LPCVD. After high-temperature phosphorus diffusion, two doped poly layers are formed. Due to the presence of the intermediate oxide layer, it will have a blocking effect on phosphorus atoms. Therefore, the poly doping concentration of the first layer will be lower than that of the second layer. That is, a tunneling oxide layer + a thinner low-doped poly layer with thicknesses of 1.5 nm and 30 nm, respectively; and an oxide layer + a thicker high-doped poly layer with thicknesses of 1 nm and 100 nm, respectively. 5. Coat the surface of the silicon wafer obtained in step 4 with a mask material solution of silazane, dry it at high temperature to form a mask material, and use a laser to heat the surface of the mask material. The mask material in the heated area will react to generate silicon oxide and other types of oxides, which are mask layers with acid and alkali resistance. The laser is an infrared laser with a power of 50W, a repetition frequency of 500KHZ, and a speed of 50000mm / min. 6. Remove the PSG on the front side of the silicon wafer obtained in step 5, and then etch it using a tank-type alkaline polishing machine. The etching process is as follows: first, remove the poly layer around the front side using alkali and additives; then, clean the PSG and mask material in the non-laser area on the back side with HF solution at a concentration-to-volume ratio of 3% for 150 seconds. Since the mask in the laser area has a certain acid resistance, it will not be completely cleaned away, so the PSG under the mask can be completely retained. Then, etch the second layer of poly using alkali at a concentration-to-volume ratio of 1% for 120 seconds. Since the laser area has the mask and PSG, the alkali will not corrode the poly. In the non-laser area, since the PSG has been cleaned away, the alkali can corrode the second layer of poly, but due to the presence of the intermediate oxide layer, it has a blocking effect on the alkali, so the poly underneath will not be etched, thus forming the SE structure described above. The mask and the front side BSG will be completely removed in the subsequent RCA cleaning. See Appendix for details. Figure 4 morphology and appendages Figure 5 ECV results; 7. The silicon wafer obtained in step 6 is coated with silicon nitride and aluminum oxide on the front side with thicknesses of 80nm and 3.5nm respectively; and with silicon nitride on the back side with a thickness of 80-90nm. 8. The silicon wafer obtained in step 7 is screen printed with silver-aluminum paste on the front and silver paste on the back.

[0028] The electrical performance data for Examples 1 and 2 are detailed in Table 1.

[0029] Table 1 Compared to the control group GAP Uoc(V) Isc(A) Rser Rshunt FF (%) Eta (%) Example 1 0.0015 0.0459 -0.00004 152 -0.034 0.211 Example 2 0.0012 0.0421 -0.0001 108 -0.012 0.193 Any aspects of this invention not described in detail are well-known to those skilled in the art.

[0030] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications and equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for manufacturing a back-side SE structure TOPCon cell, characterized in that, The method includes the following steps: S1. First alkaline etching: Select an N-type rectangular silicon wafer and texturize the wafer through alkaline etching; S2, Boron diffusion: Boron diffusion is performed on the texturized silicon wafer in a back-to-back manner; S3, Secondary Alkaline Etching: Removing the BSG and PN junction on the back and edges of the silicon wafer using alkaline etching; S4. Backside deposition: A tunneling oxide layer, a first poly layer, an intermediate oxide layer, and a second poly layer are sequentially deposited on the backside of the silicon wafer. After phosphorus diffusion, a first doped poly layer and a second doped poly layer are formed. S5. Mask Formation: A mask material is coated on the back of a silicon wafer, and the mask material is patterned and modified. The modified areas form a mask layer, while the unmodified areas retain the mask material. The modified mask layer is resistant to acids and alkalis, while the unmodified mask material is not resistant to acids and alkalis. S6, Acid Etching: HF is used to etch the mask material and PSG in the unmodified area on the back side. In the modified area, the PSG under the mask layer is preserved due to the presence of the mask layer. S7. Three-stage alkaline etching: The second doped poly layer in the unmodified area on the back side is removed by alkaline etching. In the modified area, the PSG under the mask layer is retained due to the presence of the mask layer, and in the unmodified area, the first doped poly layer is retained due to the presence of the intermediate oxide layer. S8, RCA cleaning: RCA cleaning removes the mask layer from the modified area on the back of the silicon wafer; S9. Functional layer deposition: Deposit a functional layer on the surface of the silicon wafer; S10, Electrode Formation: An electrode is formed in the modified region to form the back SE structure.

2. The method for manufacturing the back surface SE structure TOPCon cell according to claim 1, wherein In step S3, the BSG and PN junction on the back and edges of the silicon wafer are removed while the front BSG is retained.

3. The method for manufacturing the back surface SE structure TOPCon cell according to claim 1, wherein In step S4, the thickness of the second doped poly layer is greater than the thickness of the first doped poly layer.

4. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 1, characterized in that, In step S4, the doping concentration of the second doped poly layer is higher than that of the first doped poly layer.

5. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 1, characterized in that, In step S5, the patterning modification method used is laser scanning heating, wherein the mask material reacts under heating to generate a mask layer.

6. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 5, characterized in that, In step S5, the coated mask material is tetraethyl orthosilicate or silane.

7. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 5, characterized in that, The laser is one of ultraviolet, green, or infrared light, with a power of 5-100W, a repetition frequency of 100-1000kHz, and a speed of 10000-70000mm / min.

8. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 1, characterized in that, Before acid etching in step S6, the poly layer on the front side is removed by alkaline etching.

9. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 2, characterized in that, In step S8, RCA cleaning removes the front-side BSG simultaneously.

10. The method for manufacturing a TOPCon battery with a rear SE structure as described in claim 1, characterized in that, In step S10, the electrode is formed by printing silver paste on the electrode area using screen printing and sintering it to form a metallized structure.

11. A TOPCon battery with a rear SE structure, characterized in that, It includes a back-side SE structure manufactured using the method described in any one of claims 1 to 10.

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