An enhanced turn-off active gate drive device for a three-level T-type converter

Abstract

The application relates to an enhanced turn-off active gate drive device for a three-level T-type converter, and belongs to the technical field of power electronics. In view of the problems of voltage overshoot, voltage stress and electromagnetic interference (EMI) caused by the parasitic inductance effect of SiC power devices in a high-speed switching process, an active gate drive (AGD) with a programmable intermediate voltage level is provided. The drive generates an enhanced turn-off waveform containing an intermediate voltage platform in the turn-off stage, and by adjusting the intermediate voltage, active control of the turn-off di / dt is realized, so that voltage overshoot and oscillation are effectively inhibited, and the influence of EMI is reduced. In addition, the application proposes an optimization method based on a weighted cost function, which realizes a trade-off between voltage stress suppression and switching loss. The scheme improves the reliability and safety of the converter without significantly reducing the system efficiency.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to an enhanced turn-off active gate driver (AGD) device and method for silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs), applicable to three-level T-type AC / DC converters, high-frequency high-efficiency power conversion systems, and fields related to voltage overshoot and electromagnetic interference (EMI) suppression. Background Technology

[0002] Wide-bandgap semiconductor devices, especially silicon carbide (SiC) MOSFETs, are widely used in high-power-density, high-efficiency power converters due to their excellent material properties. However, their inherent high-speed switching capability, while improving system performance, also brings serious challenges: the extremely high current change rate during switching transients (…). di / dt ) Interacting with the unavoidable parasitic inductance in the power circuit, a significant turn-off voltage overshoot will occur across the device. ∆V p This overshoot voltage may jeopardize device safety, limit its performance, and exacerbate electromagnetic interference (EMI).

[0003] Three-level T-type converters have advantages in medium-voltage, high-power applications (such as electric vehicle traction and energy storage systems), but their topology results in a non-negligible commutation loop inductance, which further amplifies the risk of voltage overshoot when using SiC MOSFETs.

[0004] To address this problem, existing technologies mainly rely on two solutions: one is to add a passive buffer circuit, which increases system complexity and cost and may introduce resonance; the other is to use a conventional gate driver (CGD) with a fixed gate resistor. R g The latter increases... R g To slow down the switching speed, thereby suppressing di / dt While it avoids overshoot, the trade-off is a significant increase in switching losses, resulting in a rigid, suboptimal trade-off between device safety and system efficiency.

[0005] To more clearly reveal the contradiction between voltage overshoot and switching losses in existing technologies, the turn-off process under a conventional gate driver is quantitatively analyzed below. A waveform diagram of this process can be found in [reference needed]. Figure 2 The process can be divided into the following five stages: Sub-stage I (t0-t1): Shutdown delay stage.

[0006] Drive voltage V dr from V dr_ON Switch to V dr_OFF Then, the gate capacitance passes through the total gate resistance. R g Discharge, gate-source voltage V gs from V dr_ON Drop to Miller plateau voltage V Miller This stage is delayed. t delay It can be approximated as: ,in, C gs and C gd These are the gate-source capacitance and gate-drain (Miller) capacitance of the device, respectively.

[0007] Sub-stage II (t1-t2): Miller plateau stage.

[0008] V gs The clamp is located V Miller Drain-source voltage V ds It begins to rise from the on-state voltage drop. Miller plateau voltage. ,in I o To cut off the load current, g fs It is the transconductance of the MOSFET and the plateau duration. t II Related to the charging process of Miller capacitors: .

[0009] Sub-stages IV (t3-t4) and V (t4-t5): current drop and ringing stages.

[0010] V gs from V Miller Descending to V th Below, drain current I d The load current drops to zero. Current drop slope. di / dt This is a key parameter, and its expression is: ;inC iss It is the input capacitor. L s This is the source parasitic inductance. This stage generates another part of the turn-off loss. E CF Total shutdown loss After the circuit is turned off, the parasitic inductance and capacitance in the circuit will cause high-frequency ringing.

[0011] The above analysis reveals a key contradiction in existing technologies. The formula shows that in the CGD scheme, di / dt Both switching losses and gate resistance strongly depend on a fixed parameter: gate resistance. R g Increase R g Although it can reduce di / dt Thus suppressing overshoot ∆V p (Based on the analysis of the equivalent circuit model of the turn-off process, their relationship) ∆V p ∝ L loop *( di / dt However, this will inevitably prolong the switching time and quadratically increase the switching losses. E off .once R g This trade-off is locked in by the hardware and cannot be optimized based on real-time operating conditions.

[0012] Although active gate drivers (AGDs) capable of actively shaping gate waveforms have been studied, existing solutions mostly focus on device-level characteristics or specific problems (such as parallel current sharing). There is a lack of an AGD solution that can systematically and quantitatively address the aforementioned core contradiction—that is, to achieve a dynamic optimal trade-off between voltage overshoot and switching losses in continuously operating power converters. This constitutes the technical problem that this invention aims to solve. Summary of the Invention

[0013] 1. Technical problem to be solved: To address the problems existing in the prior art, the main objective of this invention is to provide a system and method that overcomes the limitations of the aforementioned prior art. This invention aims to effectively suppress [the problem] in a flexible and controllable manner. SiC-MOSFET of T Voltage overshoot in the converter is addressed, while simultaneously optimizing the tradeoff between device voltage stress and converter switching losses.

[0014] To achieve this objective, the present invention proposes a method equipped with a specially designed active gate driver ( AGD (three-level) TType-fed converter system. The core of this technical solution lies in... AGD This invention can generate an "enhanced turn-off" gate voltage waveform. Unlike traditional drivers that switch directly from the on-state voltage to the off-state voltage, the proposed method... AGD A controllable intermediate voltage level is introduced during the turn-off transient. V int By precisely controlling the amplitude and duration of this intermediate voltage, it is possible to actively manage and mitigate its effects. SiC-MOSFET The switching slope during the transient critical phase ( di / dt This directly suppresses the root cause of voltage overshoot.

[0015] 2. Technical Solution: To solve the above problems, the present invention adopts the following technical solution.

[0016] In a first aspect, the present invention provides an enhanced turn-off active gate drive device for a three-level T-type converter.

[0017] The core of this device lies in its ability to output an innovative, segmented gate voltage trajectory during the turn-off period of power devices (such as SiC MOSFETs), rather than the traditional drive signal that jumps directly from a high level to a low level. This trajectory includes at least one enhanced turn-off phase, during which the gate voltage transitions from the on-state voltage... V dr_ON First, switch to a voltage higher than the shutdown voltage. V dr_OFF intermediate voltage V int And maintain this for a period of time before finally switching to V dr_OFF By introducing and controlling this V int The platform can proactively mitigate the impact of critical phases during the shutdown process (especially the current change phase). di / dt This effectively suppresses voltage overshoot caused by parasitic inductance in the circuit at its source. ∆V p .

[0018] Specifically, the device includes the following functional units: Drive control unit: Used to generate the control timing and logic of the segmented drive signals, and can output parameter adjustment instructions according to preset algorithms or feedback signals.

[0019] Gate power stage: Electrically connected to the drive control unit, used to receive control signals and provide sufficient pull-up and pull-down currents to quickly establish and change the gate voltage of the power device.

[0020] Intermediate voltage generation and selection unit: controlled by the drive control unit, used to generate a programmable intermediate level voltage. V int It outputs its output to the gate of the power device during a designated phase of the turn-off process.

[0021] Programmable gate resistor network: used to provide switchable gate loop resistance values ​​to adjust the edge rate and damping characteristics of the drive signal.

[0022] Detection and protection unit: used to acquire the drain current of power devices in real time. I d Bus voltage V bus It records key parameters such as temperature T and provides feedback to the drive control unit, while also providing overcurrent, overvoltage and overheat protection functions.

[0023] As a preferred embodiment of the present invention, the segmented gate voltage trajectory is specifically as follows: V gs ：V dr_ON → V int → V dr_OFF The process consists of three stages. Among them, the Miller plateau stage is related to the drain-source voltage. V ds During the rapid rise phase, the gate voltage is clamped at V int At this time, the power device operates in the linear region, and its current change rate is... di / dt Received V int The direct limitation of the value effectively controls the main factors that cause voltage overshoot.

[0024] As a further improvement of the present invention, the drive control unit may integrate an optimization unit. This optimization unit operates based on a cost function J that balances voltage overshoot and switching losses. The cost function is defined as: J=α* ∆V' p / ∆V p +β* E' off / E off ; Where α+β=1, ∆V' p , E' off These are the voltage overshoot and turn-off loss when using this device. ∆Vp , E off To find the corresponding values ​​when using traditional fixed gate resistor driving, the optimal overall performance can be found dynamically or statically by adjusting the weighting coefficients α and β (e.g., setting α > β for overshoot-sensitive positions and α ≈ β for positions with high efficiency requirements) and combining them with optimization algorithms (such as online search or offline table lookup). V int , t int And combinations of parameters such as gate resistance.

[0025] As another preferred embodiment of the present invention, the intermediate voltage V int It is not a fixed value. The intermediate voltage generation and selection unit can generate and select based on real-time operating parameters provided by the detection and protection unit (such as...). I d , V bus (T) Dynamic adjustment V int The amplitude. For example, when the load current... I d When increasing the size, it can be appropriately increased. V int To provide stronger di / dt Suppression capability; when the bus voltage V bus When raised, it can be adjusted. V int and gate resistor to coordinate dv / dt stress.

[0026] As another preferred embodiment of the present invention, the gate power stage can operate in both voltage source mode and current source mode. During the voltage rise phase of the turn-off process, the current source mode allows for precise control of the Miller capacitance. C gd The discharge current, thus directly limiting dv / dt During the subsequent current drop phase, switching back to voltage source mode can quickly pull the gate voltage down to... V dr_OFF This ensures that the device is completely shut down, avoiding trailing losses.

[0027] Secondly, the present invention provides a voltage overshoot suppression method for a three-level T-type converter.

[0028] This method is implemented based on the aforementioned device, and its core steps include: after receiving a power device turn-off command, controlling its gate voltage to change according to a predetermined segmented trajectory; firstly from... V dr_ON Switch to preset Vint And maintain a set duration t int During this period, utilize V int It partially shuts off the channel conductivity of power devices, actively limiting the rate of decrease in drain current. di / dt After the holding phase ends, the gate voltage is quickly pulled down to V dr_OFF This completes the shutdown process. In this way, the mechanism of voltage overshoot is directly suppressed at the control level.

[0029] In a preferred embodiment of the method, the method further includes an adaptive adjustment step: real-time monitoring of the converter's operating conditions; and dynamic adjustment of the intermediate voltage based on the monitored current, voltage, and other information, through table lookup or interpolation calculations. V int Amplitude and / or holding time t int This allows for near-optimal overshoot suppression and loss balance under various operating conditions.

[0030] As an extended application of this method, the segmented voltage control approach can be used not only during the turn-off process to suppress overshoot, but also during the turn-on process. By introducing a similar intermediate voltage plateau in the turn-on trajectory, turn-on can be controlled. di / dt This effectively reduces the peak reverse recovery current of the freewheeling diode and the resulting oscillations and losses.

[0031] 3. Beneficial effects: Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) Active inhibition, with significant effects: By directly controlling the shutdown of key stages di / dt It suppresses voltage overshoot at its source, and its effect is more direct and effective than passive absorption or simply increasing resistance.

[0032] (2) Dynamic optimization and balanced performance: The introduction of cost function and parameter adaptive mechanism breaks the rigid trade-off between overshoot suppression and switching loss in the traditional method, and can maintain the system efficiency to the greatest extent while ensuring safe voltage margin.

[0033] (3) Wide adaptability and high flexibility: driving parameters ( V int , R g It is programmable and dynamically adjustable, and can adapt to different bus voltages, load currents, device batches, and even different application scenarios (such as traction inverters and energy storage converters), making it highly versatile.

[0034] (4) Simplify the system and improve reliability: The scheme itself can effectively suppress oscillation and overshoot, reduce or eliminate the dependence on external passive absorption circuits, simplify the design of the main power circuit, improve power density and system reliability, and at the same time help reduce electromagnetic interference (EMI).

[0035] It should be noted that the structures not described in this invention are not related to the design points and improvement directions of this invention, and are the same as or can be implemented using existing technologies, so they will not be elaborated here. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a three-level T-type converter topology; Figure 2 Waveform diagram of the conventional turn-off process implemented by a conventional gate driver (CGD); Figure 3 The equivalent circuit models for voltage overshoot analysis during the turn-off process are shown, where (a) is the equivalent circuit for turn-off at S2 and (b) is the equivalent circuit for turn-off at S3. Figure 4 The waveform diagram shows the enhanced turn-off process implemented by the active gate driver (AGD) of the present invention. Figure 5 This is a schematic diagram of a continuous inductive load (CIL) test. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0038] Example 1: Detailed Explanation of Enhanced Shutdown Waveform Timing and Principles This embodiment combines Figure 4 The waveform diagram shown illustrates the timing and control mechanism of the enhanced off-type active gate drive (AGD) of the present invention.

[0039] Upon receiving the shutdown command, the drive control unit executes the following segmented voltage control sequence: 1. First stage (t0-t1): Turn-off delay and initial gate voltage decrease stage.

[0040] The drive control unit commands the gate power stage to operate, causing the gate-source voltage of the power device to... V gs Self-on level V dr_ON (Typical values ​​are +15V or +20V) The gate capacitance begins to decrease. During this stage, the total resistance set by the programmable gate resistor network... R g Discharge, , V gs Drop to Miller plateau voltage V Miller The shutdown delay time t delay Primarily determined by the gate circuit parameters, it can be expressed as: , in, C gs and C gd These are the gate-source capacitance and gate-drain capacitance of the device, respectively.

[0041] 2. Second stage (t1-t2): Miller plateau and intermediate voltage V int Intervention phase.

[0042] when V gs Down to V Miller At this time, it enters the Miller plateau period, and the drain-source voltage... V ds It begins to rise. The Miller plateau voltage... ,in I o To cut off the load current, g fs It is the transconductance of the MOSFET. V th It is the threshold voltage. Plateau duration. t II With Miller capacitor C gd Related to charging: , At this stage, the AGD of the present invention performs the core operation: controlling the intermediate voltage generation and selection unit to output a preset intermediate voltage. V int and will V gs The clamp is positioned at this voltage. This allows for proactive intervention in the subsequent shutdown process. V int satisfy V dr_OFF < V int < V th Its typical value range is 2V to 5V.

[0043] 3. Third stage (t2-t3): Based on intermediate voltage V int The active control stage of current change rate.

[0044] This is the core innovation stage. V ds During the ascent, V gs Actively maintained V int ( V dr_OFF < V int < V th At this time, the drain current... I d It begins to descend, and its descent slope is... di / dt Depend on V int Direct regulation, the quantitative relationship is: ;in C iss It is the input capacitor. L s It is the source parasitic inductance. This formula shows that by setting... V int It can be precisely controlled di / dt And the overshoot voltage is turned off. ∆V p The root cause lies in the parasitic inductance of the circuit. L loop and di / dt The product of and is given by formula (3): ∆V p ∝ L loop *( di / dt Therefore, the present invention controls... V int To reduce di / dt It can linearly inhibit from the root cause. ∆V p This enables proactive management of voltage stress.

[0045] Its rate of change of current di / dt Directly by V int Amplitude control: V int The higher the value, the lower the channel resistance. di / dt The lower; conversely di / dt Increase.

[0046] Formula (3):

[0047] 4. Fourth stage (t3-t4): Final shutdown stage.

[0048] when Vds Rise completion or intermediate voltage hold time t int At the end, the drive control unit commands the gate voltage to... V int Quickly switch to final shutdown level V dr_OFF This quick dropdown makes V gs Rapidly dropped V th Next, the MOSFET is completely turned off, and the residual current rapidly decays to zero. This phase is short in duration, and its switching losses are minimal. E CF Total shutdown loss Part of it. Through optimization t int The final pull-down speed can achieve a balance between suppressing ringing and controlling losses.

[0049] 5. Fifth stage (after t4): Ringing suppression and steady-state maintenance stage.

[0050] After shutdown, the drive control unit controls the programmable gate resistor network to switch to a high resistance state (e.g., from...). R g1 Switch to R g2 ,and R g2 > R g1 This significantly increases the gate circuit damping, effectively absorbing residual oscillation energy caused by gate parasitic parameters, preventing false triggering, and assisting in attenuating the main power circuit. L loop and device output capacitor C oos The resulting voltage and current ringing ensures that the system stably enters the shutdown steady state.

[0051] In summary, this embodiment, through the sequential control of the above five stages and combined with key quantitative relationships, fully reveals the present invention's principle of "introducing and programming control of intermediate voltage." V int Actively regulate and shut down di / dt This outlines the specific implementation path and design basis for the technical solution of "suppressing voltage overshoot and optimizing switching losses".

[0052] Example 2: Specific hardware implementation plan of the drive device This embodiment provides a feasible hardware implementation of the driving device.

[0053] Drive control unit: This can be implemented using a microcontroller (MCU) or field-programmable gate array (FPGA) with high-speed PWM generation and digital signal processing capabilities. It is responsible for generating accurate segmented drive timing and executing parameter optimization algorithms.

[0054] Intermediate voltage generation and selection unit: Voltage generation: A voltage source consisting of a high-precision digital-to-analog converter (DAC) is preferred. The drive control unit sets the DAC output value via a digital bus (such as SPI) for precise programming. V int An alternative solution could be to use a precision resistor divider network in conjunction with a multi-channel analog switch to provide several discrete voltage levels. V int Level.

[0055] Voltage selection and switching: Employs low on-resistance, high-speed analog switches or MOSFET arrays. In the turn-off sequence, controlled by logic signals from the drive control unit, this unit first connects the drive output to... V int Source, and switch to after the scheduled time. V dr_OFF power supply.

[0056] Gate power stage: Designed as a push-pull amplifier circuit with independent pull-up and pull-down paths. To achieve current source operation mode, a voltage-controlled constant current source circuit consisting of an operational amplifier and a power transistor can be integrated into the push-pull path. The drive control unit controls its switching between conventional voltage source mode and constant current source mode via a mode selection signal.

[0057] Programmable gate resistor network: Multiple gate resistor branches are connected in parallel between the drive output and the gate of the power device (e.g., R g1 =2Ω, R g2 =10Ω), each branch is connected in series with an electronic switch composed of MOSFETs. The drive control unit controls the on / off state of these switches to achieve programmable switching of the equivalent gate resistance.

[0058] Detection and Protection Unit: Employing high-bandwidth, high-isolation current sensing schemes (such as those based on Rokowski coils or isolated Hall effect sensors) to acquire drain current in real time. I d .

[0059] A high-precision resistor divider network is used in conjunction with an isolation operational amplifier or linear optocoupler to control the bus voltage. V bus Perform sampling.

[0060] Place temperature sensors (such as surface mount NTC or digital temperature sensor IC) in critical locations.

[0061] The acquired analog signals are conditioned and then connected to the high-precision ADC pin of the drive control unit to achieve closed-loop control and protection functions.

[0062] Example 3: Implementation of Parameter Optimization and Adaptive Control Strategy This embodiment details the cost function-based optimization method and the specific implementation process of the dynamic adaptive strategy.

[0063] 1. Offline parameter optimization and lookup table construction: On a given experimental platform, different methods are systematically traversed for the target power module. V int and R g Parameter combinations.

[0064] Accurately measure the turn-off voltage overshoot under each set of parameters. ∆V' p and shutting off energy loss E' off .

[0065] A set of typical parameters for traditional fixed resistor drive (CGD) was selected as a benchmark to obtain the corresponding... ∆V p and E off .

[0066] The weighting coefficients (α, β) are defined according to the application focus. For example, for the clamping arm (CS) module which is sensitive to overpressure stress, α=0.7 and β=0.3 can be set to suppress overshoot first; for the outer arm (HB) module with higher efficiency requirements, α=0.5 and β=0.5 can be set to achieve balanced optimization.

[0067] Calculate the cost function value for each set of parameters. Combine the optimal parameters ( V int , R g ) and their corresponding operating conditions ( I d , V bus The data is constructed into a multidimensional lookup table (LUT) and stored in non-volatile memory.

[0068] 2. Online adaptive parameter adjustment: During system operation, the detection and protection unit continuously monitors real-time operating parameters. I d and Vbus .

[0069] The drive control unit uses the current monitored value as an index to query a pre-stored lookup table. If the current operating point matches a data point in the table, the corresponding optimal parameters are directly retrieved. If the data points are between the current points, a set of suitable parameters is calculated using a linear interpolation algorithm. V int and R g value.

[0070] This mechanism enables parameter adaptation: for example, when I d Automatically adjust height when increasing. V int To enhance di / dt Inhibition ability; when V bus When it rises, it may be adjusted accordingly. R g To manage dv / dt stress.

[0071] 3. Differentiated configuration of multiple converter loops: For different commutation circuit inductors (CCL1 and CCL2) corresponding to different switching transistors (such as S2 and S3) in a three-level T-type topology when they are turned off, independent optimization parameter lookup tables can be pre-established for each. The drive control unit automatically selects and loads the corresponding parameter table based on the identity of the target driven device.

[0072] Example 4: Application in electric vehicle traction inverter system This embodiment illustrates the system-level implementation scheme and effects of integrating the present invention into the specific application scenario of an electric vehicle traction inverter.

[0073] 1. System Integration: The four-channel AGD (corresponding to the four main switching transistors of a T-type three-level full-bridge) described in this invention is integrated into the inverter controller driver board. Each AGD channel receives PWM commands from the main controller through a high-immunity digital isolation interface (such as fiber optic or magnetic coupling).

[0074] 2. Initialization configuration: Based on the device parameters of the selected automotive-grade 650V SiC MOSFET power module and the measured system parasitic inductance, an initial optimization parameter lookup table is generated for each switching position through the aforementioned offline optimization process, and then stored in the memory of each AGD.

[0075] 3. Operational Performance: Under dynamic conditions such as rapid vehicle acceleration (high load current) or high-intensity braking feedback (high bus voltage), the AGD of this invention dynamically optimizes the turn-off trajectory based on real-time operating conditions. Compared to traditional fixed resistor drive schemes, under equally severe conditions, it can reduce the overshoot of the turn-off voltage across the power device.∆V p Reducing voltage stress by 30% to 50% ensures sufficient margin for operating voltage stress, significantly improving system reliability. Simultaneously, thanks to the optimized trade-off of the cost function, its turn-off losses are also reduced. E' off Compared to traditional low-resistance drive solutions that pursue maximum efficiency, the increase is only about 10% to 20%, far lower than the loss increase (often exceeding 100%) caused by simply increasing the gate resistance. In addition, the controlled switching transients effectively suppress high-frequency oscillations, significantly converging the system's conducted and radiated electromagnetic interference (EMI) spectrum, making it easier to meet stringent automotive electromagnetic compatibility (EMC) standards.

[0076] The above-described embodiments are merely illustrative of certain implementations of the present invention, and are described in a relatively specific and detailed manner. However, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements are all within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An enhanced turn-off active gate drive device for a three-level T-type converter, characterized in that, include: The drive control unit is used to output segmented drive signals during the power device turn-off period; The gate power stage, electrically connected to the drive control unit, is used to provide drive current; An intermediate voltage generation and selection unit is used to generate and output a preset intermediate voltage during the turn-off process. V int ; Programmable gate resistor network; The detection and protection unit is used to detect the operating parameters of power devices; The drive control unit controls the device to output a segmented gate voltage trajectory during the turn-off period, the trajectory comprising at least the turn-on voltage. V dr_ON Switch to the intermediate voltage V int Then switch to the shutdown voltage V dr_OFF The enhanced shutdown phase, and V int > V dr_OFF This is used to reduce the rate of change of current during the turn-off process.

2. The enhanced turn-off active gate drive device for a three-level T-type converter according to claim 1, characterized in that, The segmented gate voltage trajectory is specifically as follows: V gs ：V dr_ON → V int → V dr_OFF 。 3. The enhanced turn-off active gate drive device for a three-level T-type converter according to claim 2, characterized in that, The enhanced turn-off phase is configured to maintain the intermediate voltage during the Miller plateau phase and the drain-source voltage rise phase. V int To limit the rate of change of current di / dt .

4. An enhanced turn-off active gate drive device for a three-level T-type converter according to any one of claims 1 to 3, characterized in that, The drive control unit includes an optimization unit, which performs parameter optimization based on a cost function, J, defined as: J=α（ ∆V' p / ∆V p ）+β（ E' off / E off ）， Where α+β=1, ∆V' p , E' off These are the voltage overshoot and turn-off loss when using this device. ∆V p , E off These are the corresponding values ​​when using a traditional fixed gate resistor drive, and α and β are adjustable weighting coefficients.

5. An enhanced turn-off active gate drive device for a three-level T-type converter according to any one of claims 1 to 3, characterized in that, The intermediate voltage generation and selection unit is configured to generate and select voltage based on the drain current detected by the detection and protection unit. I d Bus voltage V bus and / or dynamic adjustment of the intermediate voltage based on temperature T V int The value of .

6. The enhanced turn-off active gate drive device for a three-level T-type converter according to claim 5, characterized in that, The intermediate voltage generation and selection unit includes a digital-to-analog converter or a resistor divider network for generating the intermediate voltage. V int .

7. An enhanced turn-off active gate drive device for a three-level T-type converter according to any one of claims 1 to 3, characterized in that, The gate power stage supports dual operating modes of voltage source mode and current source mode, and is configured to use current source mode during the drain-source voltage rise phase of the turn-off process, and switch to voltage source mode during the drain current fall phase.

8. A voltage overshoot suppression method applied to a three-level T-type converter, characterized in that, Includes the following steps: Obtain the power device's shutdown command; In response to the shutdown command, the gate voltage of the power device is controlled to change in a segmented trajectory, the trajectory including: from the on-voltage... V dr_ON Switch to an intermediate voltage V int and maintain the preset duration. t int Then switch to the shutdown voltage. V dr_OFF ,in V int > V dr_OFF ; During the holding phase, the intermediate voltage is utilized. V int Limiting the rate of change of current in power devices di / dt To suppress overshoot of the turn-off voltage.

9. A voltage overshoot suppression method for a three-level T-type converter according to claim 8, characterized in that, Further steps include: Detect the operating parameters of power devices; The intermediate voltage is dynamically adjusted according to the operating parameters. V int The amplitude and / or the duration of the hold t int .

10. A voltage overshoot suppression method for a three-level T-type converter according to claim 9, characterized in that, The method is used to suppress voltage overshoot during the turn-off phase and to reduce the peak reverse recovery current during the turn-on phase through similar voltage trajectory control.

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