Method and circuit for reducing collector-emitter voltage overshoot in a bipolar transistor with an insulated gate

Abstract

Circuit (100) comprising the following: - a bipolar insulated gate transistor (102) - IGBT-, which can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT (102), with an overshoot in the collector-emitter voltage (V CE ) of the IGBT (102) occurs in the second phase of the switching cycle; and - Circuits (104), operable to: - to generate a pulse that has a rising edge synchronized with the moment when current through the IGBT (102) begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of V CE -Overshoot is; and - to combine the pulse with the control signal applied to a gate of the IGBT (102) in order to temporarily increase the gate voltage of the IGBT (102) in the second phase of the switching cycle above a threshold voltage of the IGBT (102) during the duration of the pulse.

Description

[0001] The present application relates to insulated-gate bipolar transistors (IGBTs), in particular the reduction of collector-emitter voltage overshoot in IGBTs.

[0002] During the shutdown of an IGBT, the voltage (V) overshoots. CE The voltage at the terminals of the collector (C) and emitter (E) of the IGBT often reaches its nominal value. Such a voltage CE Turn-off overshoot often reduces the safety margin of IGBT operation and can lead to immediate IGBT destruction as soon as the maximum breakdown voltage rating is exceeded. A key factor in reducing V CE -Shutdown overshoot is the reduction of the rate of rise (di C / dt) of the collector current I C during shutdown. CHowever, the voltage drop (Vdt) during turn-off is difficult to control. This is especially true for trench-gate IGBTs, where the insulated gate is located in a trench formed in a semiconductor material, such as silicon. Trench-gate IGBTs have significantly higher internal capacitance compared to planar-gate IGBTs. This internal capacitance stores charges during IGBT turn-on, and these charges must be removed during IGBT turn-off. The high internal capacitance of the IGBT makes it more difficult to control the IGBT turn-off process and therefore more difficult to control the voltage drop. CE -To reduce overshoot without significantly reducing efficiency.

[0003] There are five main approaches to reducing V CE -Shutdown overshoot for trench-gate IGBTs. In a first approach, the shutdown gate resistance R is used. GOFFThis approach uses a higher gate resistance during the IGBT turn-off process. A disadvantage of this approach is that the entire turn-off process is slowed down, leading to a significant increase in turn-off loss E. OFF leads.

[0004] A second approach involves adjusting the gate turn-off voltage. This approach uses a variable gate voltage below the threshold voltage to reduce the gate discharge rate during turn-off. A disadvantage of this approach is that it slows down the entire turn-off process, resulting in a significantly increased turn-off loss E. OFF leads.

[0005] A third approach uses active voltage limiting. This approach uses collector voltage feedback to temporarily turn on the gate when Vc is exceeded. CEexceeds a predefined level during the turn-off process. A disadvantage of this approach is that voltage feedback from the IGBT collector is required, which leads to reliability issues for high-voltage IGBT applications. Additionally, this approach controls or reduces turn-off dI. C / dt not.

[0006] A fourth approach uses dynamic voltage rise control (DVRC). DVRC uses one or more capacitors to detect the collector voltage and uses the detected signal to temporarily turn on the gate when dV exceeds a certain threshold. CE / dt exceeds a predefined level during the turn-off process. A disadvantage of this approach is that voltage feedback from the IGBT collector is required, which leads to reliability problems for high-voltage IGBT applications.

[0007] In a fifth approach, di / dt control is implemented via emitter inductance voltage feedback. This approach uses the emitter leakage inductance to control the di E to generate a / dt voltage signal that is added to the gate voltage and acts as negative feedback to the gate voltage when I E decreases. A Zener diode and / or a resistor network can be added to limit or adjust the feedback voltage. This approach is useful when reducing V CE -Overvoltage after a short circuit is useful when very high current with high di E / dt is to be switched off by the shutdown di E / dt, which is implemented with high gain in the feedback loop, at the cost of increasing the turn-off time and therefore the turn-off loss E OFF is significantly reduced. When using this technique to reduce shutdown voltage CEOvershoot increases this during normal operation, as the feedback action occurs during the current drop-out time t. F (voltage overshoot period) is active, the decay time t F and E OFF quite significant, which is often unacceptable for normal operation.

[0008] US 2015 / 0028923A1 discloses a gate driver circuit for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source used to control the switching transient when the power transistor is turned off; and a second secondary current source used to control the switching transient when the power transistor is turned on. In operation, the current control circuit ensures that when the power transistor is turned on, a gate driver current flows into a control node of the power transistor, and when the power transistor is turned off, a gate driver current is drawn from the control node of the power transistor. The first and second secondary current sources adjust the gate driver current to control the rate of change of the voltage or current and thus the overshoot during the switching transition.

[0009] WO 02 / 007 315 ​​A1 discloses a control method for switching on and off power semiconductor switches. In switching phase A, the collector current transient is controlled to ensure controlled clearing of the edge regions of a series freewheeling diode. In switching phase B, the collector voltage gradient is controlled to switch the power semiconductor switch in a controlled manner. A closed control loop is achieved by feeding back primary and, if necessary, secondary state variables of the power semiconductor switch.

[0010] US 9,007,102 B2 discloses an exemplary gate drive circuit and a method for controlling a gate-controlled device. The gate drive circuit includes a PI controller that can receive an input reference signal and control a gate voltage of the gate-controlled device. The gate drive circuit may include a first feedback loop for the PI controller, which has a first gain, a second feedback loop for the PI controller, which has a second gain, and a limiting circuit that can modify a feedback signal in the second feedback loop during the turn-on of the gate-controlled device when the time derivative of the collector current is negative. The first feedback loop may include a first blanking circuit that breaks the feedback loop when the gate-controlled device is in a cut-off state.

[0011] One task, therefore, is to improve existing approaches and provide an efficient and cost-effective solution.

[0012] This problem is solved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

[0013] To solve the problem, a circuit is specified which includes the following: - a bipolar insulated gate transistor (IGBT) that can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT, with an overshoot in the collector-emitter voltage (VCE). CE ) of the IGBT in the second phase of the switching cycle; and - Circuits, operable to: - to generate a pulse that has a rising edge synchronized with the moment when current through the IGBT begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of V CE -Overshoot is; and - to combine the pulse with the control signal applied to a gate of the IGBT in order to temporarily increase the gate voltage of the IGBT in the second phase of the switching cycle above a threshold voltage of the IGBT during the duration of the pulse.

[0014] It should be noted that these circuits are also referred to as circuits.

[0015] It is further information that the IGBT is a Trench-Gate IGBT.

[0016] It is a further development that the impulse has a fixed amplitude.

[0017] It is a further development step that the breadth of the impulse is fixed.

[0018] It is a further development that the width of the impulse is a function of the intrinsic turn-off decay time of the IGBT.

[0019] It is a further development that the width of the impulse is between ½ and ¼ of the duration of the V CE -Overshoot is.

[0020] It is further education that the circuits include the following: - a first circuit that is operational to detect the collector or emitter current of the IGBT; - a second circuit that can be operated to output a signal representing the time differentiation of the detected collector or emitter current; - a third circuit that is operable to generate the pulse in response to the signal output by the second circuit; and - a fourth circuit that can be operated to combine the pulse and the control signal.

[0021] It is a further development that the third circuit has a user-controllable amplitude gain and time constant variable for setting the amplitude and duration of the pulse.

[0022] It is a further development that the third circuit can be operated to adjust the width of the pulse in response to a user input signal.

[0023] It is a further development that the fourth circuit is operable to pass the control signal to the IGBT without combining it with the pulse in response to a deactivation of a pulse enable signal.

[0024] It is a further development that the first circuit is operable to detect the collector or emitter current of the IGBT by detecting current through an emitter leakage inductor at an emitter terminal of the IGBT or a shunt resistor connected to the emitter terminal, and in which the second circuit is operable to output the signal representing the time differentiation of the detected output collector or emitter current based on the voltage across the emitter leakage inductor, the voltage across the shunt resistor, a voltage generated across a Rogowski coil magnetically coupled to the emitter terminal, or a voltage induced across a current transformer coil magnetically coupled to the emitter terminal.

[0025] It is a further development that the third circuit is operable to generate the impulse at the moment when the voltage measured by the second circuit begins to rise in the second phase of the switching cycle.

[0026] It is further information that the third circuit includes the following: - a protective circuit that can be operated to limit the output of the second circuit against excessively high voltage during short-circuit shutdown; - a signal amplifier that can be operated to amplify the protection circuit output; and - a first pulse generator that can be operated to trigger in response to a falling and / or rising edge of the signal amplifier output.

[0027] It is a further development that the third circuit also includes a second pulse generator, which is triggered by the same signal amplifier as the first pulse generator and is operable to generate an additional pulse that has a longer width than the pulse generated by the first pulse generator, and in which the second pulse generator is activated during short-circuit protection of the IGBT and deactivated during normal operation of the IGBT.

[0028] It is a further development that the fourth circuit is operational in order to combine the pulses output by the first and second pulse generators and the control signal.

[0029] It is a further development that the first and second pulse generators each comprise a monostable multivibrator.

[0030] It is a further development that the third circuit has an input signal range that is from 0.1 to 2.0 times the collector rated current of the IGBT during normal operation of the IGBT, and from 0.1 to 6.0 times the collector rated current during short-circuit protection of the IGBT.

[0031] It is a further development that the circuits are set up to disable the generation of the pulse in response to a control signal indicating that the pulse should be deactivated.

[0032] It is a further development that the circuits are set up to increase the pulse width in response to a signal indicating a short-circuit fault condition, so that the pulse width is narrower for normal operation and wider for short-circuit operation.

[0033] Furthermore, a method is proposed for reducing overshoot for an insulated-gate bipolar transistor (IGBT) that can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT, whereby collector-emitter voltage (V) overshoot is reduced. CE ) of the IGBT in the second phase of the switching cycle, the method comprising the following: - Generating a pulse that has a rising edge synchronized with the moment when current through the IGBT begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of the V CE -Overshoot is; and - Combining the pulse with the control signal applied to a gate of the IGBT to temporarily increase the gate voltage of the IGBT in the second phase of the switching cycle above a threshold voltage of the IGBT during the duration of the pulse.

[0034] Furthermore, a circuit is proposed for reducing collector-emitter voltage (V). CE )-Overshoot in an insulated-gate bipolar transistor (IGBT), wherein the circuit comprises circuits that can be operated to: - to generate a pulse that has a rising edge synchronized with the instant when the collector or emitter current of the IGBT begins to fall during IGBT turn-off, and has a width that is a fraction of the duration of the V CE -Overshoot is; and - to combine the pulse with the control signal applied to a gate of the IGBT in order to temporarily increase the gate voltage of the IGBT during the IGBT's turn-off above a threshold voltage of the IGBT for the duration of the pulse.

[0035] According to one embodiment of a circuit, the circuit comprises an insulated-gate bipolar transistor (IGBT) that can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT, with overshoot in the collector-emitter voltage (VCE). CE) of the IGBT in the second phase of the switching cycle. The circuit further includes circuits that can be operated to generate a pulse having a rising edge synchronized with the instant the current through the IGBT begins to fall in the second phase of the switching cycle, and a width that is a fraction of the duration of the V CE -overshoot. The circuits are further operable to combine the pulse with the control signal applied to a gate of the IGBT in order to temporarily increase the gate voltage of the IGBT in the second phase of the switching cycle above a threshold voltage of the IGBT during the duration of the pulse.

[0036] According to an embodiment of a method for reducing overshoot for an IGBT that is operable to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT, wherein the overshoot of the collector-emitter voltage (V) CE ) of the IGBT in the second phase of the switching cycle, the method comprises the following: generating a pulse that has a rising edge synchronized with the moment the current through the IGBT begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of the V CE-Overshoot is, and combining the pulse with the control signal applied to a gate of the IGBT to temporarily increase the gate voltage of the IGBT in the second phase of the switching cycle above a threshold voltage of the IGBT during the duration of the pulse.

[0037] According to one embodiment of a circuit for reducing collector-emitter voltage (V) CE )-Overshoot in an IGBT, the circuit comprises circuits that are operable to generate a pulse having a rising edge synchronized with the instant the collector or emitter current of the IGBT begins to fall during IGBT turn-off, and having a width that is a fraction of the duration of the V CE-Overshoot is, and to combine the pulse with a control signal applied to a gate of the IGBT to temporarily increase the gate voltage of the IGBT above a threshold voltage of the IGBT during the duration of the pulse.

[0038] The expert will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings.

[0039] The elements in the drawings are not necessarily to scale with each other. Identical reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined, unless they are mutually exclusive. Embodiments are shown in the drawings and described in detail in the following description. Fig. Figure 1 illustrates a block diagram of an embodiment of a circuit that incorporates an IGBT and circuits for reducing V CE -Exhibits IGBT overshoot. Fig. Figure 2 illustrates a timing diagram that leads to the operation of the circuit described in Fig. 1 is shown, belongs. Fig. Figure 3 illustrates a sketch of an analogous embodiment of current sensing and time differentiation circuits that, when reducing V CE -Overshoot of an IGBT can be used. Fig. Figures 4(a) to 4(d) illustrate sketches of different analogous embodiments of the current sensing and time differentiation circuits that are used when reducing V CE -Overshoot of an IGBT can be used. Fig. Figures 5(a) to 5(c) illustrate sketches of different analog embodiments of the pulse signal processing circuit that are used when reducing V CE-Overshoot of an IGBT can be used. Fig. Figure 6 illustrates a sketch of an embodiment of a circuit for combining a control pulse with a gate drive signal of an IGBT to reduce V CE - IGBT overshoot. Fig. Figure 7 illustrates a sketch of a digital embodiment of signal processing and signal combination circuits that, when reducing V CE -Overshoot of an IGBT can be used. Fig. Figure 8 illustrates a timing diagram that leads to the operation of the digital circuits that are in Fig. 7 are shown, heard. Fig. Figures 9(a) to 9(c) illustrate sketches of different analog embodiments of a pulse signal processing circuit, modified with short-circuit shutdown overvoltage protection. Fig. Figure 10 illustrates a sketch of a digital embodiment of pulse signal processing and signal combination circuits for providing short-circuit shutdown overvoltage protection. Fig. Figure 11 illustrates a timing diagram that leads to the operation of the digital circuits that are in Fig. 10 are shown, heard.

[0040] The embodiments described here reduce the IGBT collector-emitter voltage (V). CE )-Shutdown overshoot by controlling and reducing shutdown di C / dt or -di E / dt for normal operation and short-circuit operation, implemented by using a short V GE -control impulse, also known here as "di" E / dt-control impulse" or "di E This pulse, called the " / dt control," is applied to the IGBT gate during turn-off. The gate voltage of the IGBT is driven above the gate threshold voltage V by this pulse. THlifted, so that the IGBT temporarily switches on during the shutdown period, thereby di E / dt and therefore the V CE -Overshoot voltage peak is reduced.

[0041] Fig. Figure 1 illustrates an embodiment of a circuit 100 which includes an IGBT 102 and circuits 104 for reducing V CE -exhibits overshoot of the IGBT 102, and Fig. Figure 2 illustrates a timing diagram belonging to the operation of circuit 100. In one embodiment, the IGBT 102 is a trench-gate IGBT, in which the insulated gate of the IGBT 102 is arranged in a trench formed in a semiconductor material, such as silicon. Alternatively, the IGBT 102 can be a planar-gate IGBT, in which the insulated gate is arranged on the surface of the semiconductor material. Both types of IGBTs are well known in semiconductor technology, which is why no further description of the IGBT structure is given here.

[0042] The IGBT 102 conducts current (i C / i E ) in a first (switch-on) phase of a switching cycle and blocks current in a second (switch-off) phase of the switching cycle in response to a control signal (V GE ), which is applied to the gate (G) of the IGBT 102. During the turn-off of the IGBT 102, the voltage (V) overshoots. CE The voltage at the terminals of the collector (C) and emitter (E) of the IGBT often reaches its nominal value. If it is not moderated, the voltage can... CE -Shutdown overshoot reduces the safety margin of the IGBT operation or even leads to the immediate destruction of the IGBT 102 if the overshoot exceeds the maximum V CE -The breakdown voltage rating of the IGBT 102 is exceeded.

[0043] The circuits 104 provide optimal control of the shutdown di E / dt / -di C / dt and reduction of V CE-Overshoot in order to moderate the negative effects associated with the overshoot. Circuits 104 force the IGBT 102 to immediately and temporarily switch back on when i E / i C to begin to fall. This means that the V GE -Control pulse is generated by circuits 104 when the emitter current i E or the collector current i C just beginning to fall, that is, when the E / dt / di C / dt is increased from zero, which changes by time t2 in Fig. 2 occurs. For this, circuits 104 generate a di E / dt control pulse, which has a rising edge that is synchronized with the moment when current (i C or i E , both of which can be detected) begins to fall by the IGBT 102 in the second (switch-off) phase of the switching cycle. The width (w) of the di E The / dt control pulse is a fraction of the duration of the VCE -Overshoot. In one embodiment, the width of the di E / dt control pulse between ½ and ¼ of the duration of the V CE -Overshoot.

[0044] The circuits 104 combine the di E / dt control pulse with the control signal ("Gate control signal input" in the Fig. 1 and Fig. 2), which is applied to the gate of the IGBT 102, so that the gate voltage V GE of the IGBT 102 in the second (switch-off) phase of the switching cycle via a voltage threshold (V TH ) of the IGBT 102 during the duration of the pulse, as in Fig. 2 is shown, it is increased.

[0045] In particular, the circuits 104 detect the emitter current i E or collector current i C and process the detected voltage signal i E / i C , to generate a signal V(di E / dt) to give that the time differentiation of the streams i E / i Crepresents the time differentiation signal V(di). E / dt) has synchronized the shape of a voltage pulse with its rising edge to the moment when i E / i C just beginning to fall, as in Fig. Figure 2 shows that to achieve the optimal control result, the synchronization delay time is minimized. The delay time can be minimized by increasing the gain of the pulse signal processing circuit 110. The time differentiation signal V(di) E / dt) causes the circuits 104, the di E / dt control pulse with short pulse to switch on the IGBT 102 for a short duration, to generate a switch-off di E / dt to control and reduce and V CE -To reduce overshoot.

[0046] A compromise exists in connection with the selection of the pulse width (duration) of the di E / dt control pulse. A longer pulse width (w) increases the shutdown energy loss E. OFF and can even lead to oscillations, while a shorter pulse width leads to insufficient reduction of shutdown di E / dt and V CE -can lead to overshoot. The optimal pulse width depends on the intrinsic IGBT turn-off decay time and is therefore longer for high-voltage IGBTs or IGBTs with soft-turn-off characteristics. The optimal pulse width also depends on the leakage inductance of the switching path. The width of the di E The / dt control pulse can be fixed or programmable to optimize according to specific application requirements and is limited to a fraction, for example ½ to ¼ etc., of the duration of the V. CE -Overshoot limited. The amplitude of the di E The / dt control pulse can also be fixed or programmable. The amplitude of the di EThe / dt control pulse can be controlled, for example, by adjusting the amplitude gain and time constant settings of circuits 104. These parameters can be set by the user.

[0047] To achieve optimal performance, the circuits have 104 fast response times and minimal latency compared to the duration of the E / dt control pulse. Since the IGBT shutdown energy loss E OFF in the presence of the di E As the / dt control pulse increases, an enable function (EN) can be provided to allow the user to selectively disable the shutdown function. E To activate / deactivate the / dt control pulse function. For example, if the DC intermediate circuit voltage of the IGBT 102 reaches a defined value beyond which the normal shutdown of the IGBT would result in a dangerously high voltage. CE -Voltage overshoot results, the shutdown di E / dt control pulse function activated.

[0048] In one embodiment, the circuits 104 comprise a current sensing circuit 106 for sensing the current through the IGBT 102. Either the emitter current i can be measured. E or the collector current i C The circuits 104 also include a time differentiation circuit 108 for processing the detected current signal i. E / i C , to generate a signal V(di E / dt) proportional to the time differentiation of the recorded current i E / i C to generate. The circuits 104 also include a pulse signal processing circuit 110 for processing the V(di). E / dt) time differentiation signal, which provides input protection and signal amplification with frequency compensation and the di E / dt control pulse generated. The di E The / dt control pulse is synchronized with the moment i E / i CThe voltage will begin to drop during the IGBT 102 shutdown, with a minimal time delay. When the control pulse function is activated, the voltage will decrease. E The / dt control pulse is used to temporarily switch on the IGBT 102 when i E / i C during IGBT shutdown. The width of the di E The / dt control pulse can be fixed or user-controllable to strike a balance between reducing shutdown di E / dt and V CE -Overshoot compared to increased shutdown energy loss E OFF to allow and is limited to a fraction, for example half, a quarter, etc. of the duration of the V CE -Voltage overshoot is limited.

[0049] The circuits 104 also include a signal combination circuit 112 for combining the di EThe / dt control pulse is combined with the gate drive signal. The combined signal is sent to an output buffer stage 114 to drive the gate of the IGBT 102 such that the di E / dt control pulse the IGBT gate voltage V GE temporarily exceeding the IGBT gate threshold voltage V TH lifts, and IGBT shutdown di E / dt and V CE Overshoot is determined by the voltage level and the pulse duration (width) of the di E / dt control pulses controlled. The circuits 104 also have an enable function (EN) for selectively activating or deactivating the di E / dt control pulse function. In one embodiment, only the gate control signal is sent directly to the output buffer memory 114 without the di E / dt control pulse sent if the control signal EN indicates that the E The / dt control pulse function should be deactivated. EThe / dt control pulse is combined with the gate drive signal before being sent to the output buffer 114 if the control signal EN indicates that the di E The / dt control pulse function is to be activated. The enable function can be implemented in the pulse signal processing circuit 110 to enable the generation of the di E / dt control pulse, or in the signal combination circuit 112 to control the combination of the di E The / dt control pulse is controlled with the gate drive signal. The EN signal should be activated to control the di E / dt control pulse to be generated and combined with the gate drive signal if the DC intermediate circuit voltage applied to the IGBT 102 exceeds a predetermined value.

[0050] Fig. Figure 3 shows an implementation form for the current sensing circuit 106 and the time differentiation circuit 108. The emitter leakage inductance L eThe main emitter terminal E of the IGBT 102 is used to control the combined functions of the emitter current. E -Capture and generation of the signal V(di) E / dt) , which is the time differentiation of the emitter current i E to execute. The voltage V Le (=L e di E / dt) at the emitter stray inductance L e is to di E / dt is proportional and therefore functions as the desired time differentiation signal V(di). E / dt).

[0051] The Fig. Figures 4(a) to 4(d) show four different embodiments of the current sensing and time differentiation circuits 106, 108 for generating the V(di). E / dt) signal. The V(di E The / dt) signal can be determined by measuring the voltage across the emitter shunt resistor (R S ) and differentiating the voltage by an operational amplifier differentiation circuit 120, as in Fig. 4(a) shown. Alternatively, the V(di E The / dt) signal can be obtained by measuring the induced voltage output of a Rogowski coil 122, as shown in Fig. 4(b) shown. In another embodiment, the V(di E / dt) signal by using a current transformer (CT) 124 to couple the emitter current i E and differentiation of the CT output voltage by an operational amplifier differentiation circuit 126, as in Fig. 4(c) shown. In yet another embodiment, the V(di E / dt) signal by measuring the voltage across the current sensing IGBT sensing emitter shunt resistor (R S ) and differentiation of the voltage by an operational amplifier differentiation circuit 128, as shown in Fig. 4(d) shown.

[0052] When using the emitter leakage inductance L e to the E / dt-capture to capture the V(di Eto give a / dt) time differentiation signal, as in the Fig. As shown in 3 and 4(a) to 4(d), a wide area of ​​V Le -Signal voltage levels can vary due to several factors, such as the wide range of the IGBT current rating I CNOM , the packet-collector-emitter stray inductance L SCE and shutdown current drop time t F of the IGBT 102. The sum parameter L SCE I CNOM / (2t F ), which is a close approximation of the voltage V Le The voltage can range from 0.3 V to 55 V. Le The signal voltage level also varies because of the emitter stray inductance L. e no controlled parameter and uncontrolled deviation, for example ±30%, and the large operating current range of the IGBT 102 from low load, full load, overload to short circuit, for example 0.1×, 1.0×, 2.0× and 6.0× I each CNOM (Collector rated current), is subject to.

[0053] Such a wide range of possible V Le -Signal voltage level means that when the emitter leakage inductance L e to the E When / dt-acquisition is used, different pulse signal processing circuits should be used to achieve the L SCE I CNOM / (2t F )-characteristics of the IGBT 102, and each pulse signal processing circuit should be designed to handle an input signal with a dynamic range of [0.07 ... 2.6] and [0.07 ... 7.8] of its nominal value for operation and short circuit respectively, and with respect to L S -to be insensitive to parameter fluctuations.

[0054] The Fig. Figures 5(a) to 5(c) illustrate analogous embodiments of the pulse signal processing circuit 110. The pulse processing circuit 110 immediately generates a pulse (di E / dt control pulse) with optional, user-selectable pulse width programmability, when the V(di EThe / dt) signal begins to rise. To achieve such synchronization, the pulse signal processing circuit 110 includes an input protection circuit 130 to limit excessively high V(di). E / dt) voltage during short-circuit shutdown, before the V(di E The / dt) signal is sent to a subsequent signal amplifier 132. The signal amplifier 132 has sufficient gain to cover the desired IGBT operating current range, for example (0.1 to 2.0) × I CNOM, to produce an output voltage with a wide amplitude, possibly by operating in saturation, and with a fast falling / rising edge, when the V(di E The voltage output by signal amplifier 132 triggers the subsequent pulse generator 134. Triggered by the falling / rising edge of the preceding signal amplifier output, pulse generator 134 generates a positive pull-up resistor.E / dt control pulse. The width of the positive pull-up di E The / dt control pulse can be set by an RC circuit formed by the capacitor C2 and the resistor R2.

[0055] The di E The / dt control pulse is combined with the IGBT gate drive signal and superimposed on it by the signal combination circuit 112. The combined signal is sent to an output buffer 114 to drive the IGBT gate by means of a V GE -Impulse (di E / dt-control) is applied to the IGBT gate, which switches on the IGBT 102 for a short duration when I E / I C fall. Depending on the output impedance characteristics of the gate drive signal, the di EThe / dt control pulse can be combined with the gate drive signal by direct connection, by a resistor network, or by a logic gate. The pulse signal processing circuit 110 also includes an enable circuit 136 to enable the generation of the di E / dt control pulses in response to an enable signal (EN).

[0056] Fig. Figure 6 illustrates an embodiment of the pulse signal processing circuit 110, the signal combination circuit 112, and the output buffer stage 114. According to this embodiment, the di E The / dt control pulse from the pulse signal processing circuit 110 is combined with the gate drive signal by a resistor network 140, which implements the signal combination function. The combined signal is then temporarily stored by the output buffer stage 114 and sent to drive the IGBT gate.

[0057] Fig. Figure 7 illustrates a digital embodiment of the pulse signal processing circuit 110 and the signal combination circuit 112. Fig. Figure 8 shows the corresponding timing diagram. According to this embodiment, the pulse signal control circuit 110 comprises an input protection circuit 150, a signal amplifier 152, and a pulse generator 154. The signal amplifier 152 has an adjustable gain A(f), and its frequency response is used for signal conditioning of the V(di). E / dt) signal input is used. With a suitable input signal dynamic range, a logic gate buffer can be used instead of the signal amplifier 152. The output of the amplifier or gate buffer 152 is used as the trigger signal to a monostable multivibrator 154 to activate the di E To generate a / dt control signal output with a fixed logic level amplitude and user-controllable pulse width (duration). Since the pulse duration (width) of the di EThe / dt control pulse is shorter than the V CE -Overshoot period, the monostable multivibrator 154 is edge-triggered instead of level-triggered. The reset function (RESET) of the monostable multivibrator 154 can be used to implement the enable function, so that generating the di E / The dt control pulse is selectively activated or deactivated in response to the enable control signal (EN). Alternatively, a digital counter can be used to generate a pulse when triggered. In yet another embodiment, an embedded microcontroller (MCU) within a digital gate driver board can be triggered by the output of the signal amplifier 152. The MCU executes program code to generate a short gate drive output pulse to turn on the output buffer 114. In such a setup, the MCU performs the function of the monostable multivibrator 154 and the signal combination circuit 156 by software, without requiring any additional hardware.

[0058] The di E / The dt control pulse is combined with the gate drive signal by a logic gate 156, which implements the signal combination function. Such a logic gate 156 can be implemented as an OR gate for positive logic signals or an AND gate for negative logic signals.

[0059] Due to the circuit simplicity, the combined functions of the pulse signal processing circuit 110 and the signal combination circuit 112, which are described in Fig. 7 shown, can also be implemented in a driver IC (integrated circuit) or by a microcontroller as an additional feature alongside its existing functionality, for example in a digital IGBT gate driver board that has such a microcontroller.

[0060] During the IGBT short circuit to low impedance (short circuit type I), i E / i C quickly to a very high value, typically six times the collector rated current I CNOMNormally, the IGBT short-circuit protection function in the gate driver board monitors the voltage. CE -Voltage to check for desaturation, and confirms the state of a short-circuit fault condition when V CE The IGBT gate voltage rises to a defined value, for example, a few tens of volts, into the desaturation range. The IGBT gate voltage can then be slowly reduced once the short-circuit fault is confirmed, using a soft turn-off or two-stage shutdown techniques, and after a brief moment, for example, 5 µs, the IGBT is switched off. Due to the high short-circuit current I C before switching off, V CE Voltage overshoot can reach dangerous levels after a shutdown if it is not moderated. Active limiting techniques are often used for overvoltage protection to reduce the voltage. CE to limit it to a defined maximum value. With some changes, the V CE-Overshoot control techniques described above are extended to provide overvoltage protection during short-circuit shutdown.

[0061] The operating concept for short-circuit shutdown overvoltage protection is the same as for the overshoot control described above, with the pulse signal processing circuit 110 providing a di E / A dt control pulse is generated immediately after the short-circuit shutdown. Due to the much higher current during the short-circuit shutdown, the width of the di E / The dt control pulse for short-circuit and overvoltage protection is longer than required for normal operation. Using such a long di E / The dt control pulse leads to an unnecessarily high shutdown loss E OFF during normal operation. The pulse signal processing circuit 110 therefore generates a short circuit (SC) di E / dt control pulse with a longer pulse width when activated by a signal SC confirming the state of a short-circuit fault condition, for example from a short-circuit detection function in the gate driver board.

[0062] With this SC-di E / The SC-di switches the dt-control pulse approach. E / dt control pulse the IGBT 102 earlier at a lower V CE -Overvoltage during the V CE -overshoot, and is therefore safer than conventional active limiting approaches that implement the IGBT's turn-on at a later stage and at a higher overvoltage. Additionally, conventional active limiting approaches prevent V CE - Overshoot beyond the intended limiting voltage level by immediately switching on the IGBT when the V CEOvershooting of the Zener limit voltage occurs when a high pulse current is passed through to turn on the IGBT gate via the active limiting scener diodes. This current pulse results in high instantaneous power dissipation in the active limiting scener diodes and high continuous power dissipation in situations such as DC link overvoltage and repeated overload or short circuit. The Zener diodes in the active limiting circuit are at risk of overpower failure if they are not carefully dimensioned. On the other hand, the di E The / dt control pulse approach described here is a signal control approach that involves no power loss of its own. There is also no feedback from the high-voltage collector (C) to the low-voltage gate (G) for the di E / dt control impulse approach required.

[0063] The Fig. Figures 9(a) to 9(c) illustrate the respective pulse signal processing circuit implementations found in the Fig. Figures 5(a) to 5(c) are shown, modified to create a synchronized di E / dt control pulse from the V(di E To generate a / dt) signal with additional short-circuit shutdown and overvoltage protection. Compared to the respective functions that are in the Fig. As shown in Figures 5(a) to 5(c), a short-circuit (SC) pulse generator 160 is provided to create an SC-di E / to generate a dt control pulse that has a width longer than the di E / dt control pulse, generated by the main pulse generator 134 for overshoot reduction during normal operation. The SC pulse generator 160 is controlled by an SC overvoltage protection (OVP) enable circuit 162. The SC pulse generator 160 is triggered by the same signal amplifier 132 as the main di E / dt control pulse generator 134, generates the SC-di E / The dt control pulse is only generated when activated by the SC overvoltage protection enable circuit 162, for example, when a short circuit is detected by the short-circuit detection function in the gate driver board. The SC pulse generator 160 is deactivated by the SC overvoltage protection enable circuit 162 during normal operation of the IGBT 102. The outputs of both pulse generators 134 and 160 are combined to produce a single di E / to generate a dt control pulse, which is combined with the IGBT gate drive signal as described above. The width of the combined pulse signal is therefore increased in response to a signal (SC) indicating a short-circuit fault condition, so that the resulting pulse width is narrower for normal operation and wider for short-circuit operation.

[0064] Fig. Figure 10 illustrates a digital embodiment of the pulse signal processing circuit 110, the signal combination circuit 112 and the output buffer stage 114, implemented with short-circuit shutdown overvoltage protection function. Fig. Figure 11 shows the corresponding timing diagram. Compared to Fig. 7 an additional monostable multivibrator (U4) 170 is present, which acts as an SC pulse generator for generating the SC-di E The / dt control pulse operates. The SC pulse generator 170 is triggered by the same signal amplifier 152 as the main pulse generator 154 and is activated by the SC signal, for example, from the gate driver board short-circuit detection function. When a short-circuit condition is detected, the SC signal is set to a logic high, and the SC pulse generator 170 is activated. When the IGBT 102 is switched off after a short circuit, a falling I E a V(dI E / dt) signal to trigger the monostable SC multivibrator 170, which in turn triggers an SC-di E / dt generates a control pulse that has a pulse width longer than the normal di E / dt control pulse generated by the main pulse generator 154. The output of the monostable SC multivibrator 170 is sent to the signal combination circuit 156 to be logically combined with the gate drive signal and the di E The / dt control pulse generated by the main pulse generator 154 is added and sent to the output buffer stage 114 to drive the gate of the IGBT 102.

[0065] Terms such as "first," "second," and the like are used to describe various elements, regions, sections, etc., but they are not intended to be restrictive. Throughout the description, similar terms refer to similar elements.

[0066] As used here, the terms "have," "contain," "exhibit," "comprise," and the like are unrestricted terms that indicate the presence of the elements or features mentioned, but do not exclude additional elements or features. The articles "a / an" and "the" are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0067] It is clear that the features of the various embodiments described here can be combined with one another, unless expressly stated otherwise.

[0068] Although specific embodiments have been described here for illustrative purposes, the person skilled in the art understands that a variety of alternative and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover all adaptations and variations of the specific embodiments discussed herein. This invention is therefore intended to be limited only by the claims and their equivalents.

Claims

[1] Circuit (100) comprising the following: - a bipolar insulated gate transistor (102) - IGBT-, which can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT (102), with an overshoot in the collector-emitter voltage (V CE ) of the IGBT (102) occurs in the second phase of the switching cycle; and - Circuits (104), operable to: - to generate a pulse that has a rising edge synchronized with the moment when current through the IGBT (102) begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of V CE -Overshoot is; and - to combine the pulse with the control signal applied to a gate of the IGBT (102) in order to temporarily increase the gate voltage of the IGBT (102) in the second phase of the switching cycle above a threshold voltage of the IGBT (102) during the duration of the pulse. [2] Circuit according to claim 1, wherein the IGBT (102) is a trench gate IGBT. [3] Circuit according to one of the preceding claims, wherein the pulse has a fixed amplitude. [4] Circuit according to one of the preceding claims, wherein the width of the pulse is fixed. [5] Circuit according to one of the preceding claims, wherein the pulse width is a function of an intrinsic turn-off decay time of the IGBT (102). [6] Circuit according to one of the preceding claims, wherein the width of the pulse is between ½ and ¼ of the duration of the V CE -Overshoot is. [7] Circuit according to any of the preceding claims, wherein the circuits (104) comprise: - a first circuit (106) that is operable to detect collector or emitter current of the IGBT (102); - a second circuit (108) that can be operated to output a signal representing the time differentiation of the detected collector or emitter current; - a third circuit (110) that is operable to generate the pulse in response to the signal output by the second circuit; and - a fourth circuit (112) that can be operated to combine the pulse and the control signal. [8] Circuit according to claim 7, wherein the third circuit (110) has a user-controllable amplitude gain and time constant variable for adjusting the amplitude and duration of the pulse. [9] Circuit according to one of claims 7 or 8, wherein the third circuit (110) is operable to adjust the width of the pulse in response to a user input signal. [10] Circuit according to one of claims 7 to 9, wherein the fourth circuit (112) is operable to transmit the control signal without combining it with the pulse to the IGBT (102) in response to a deactivation of a pulse enable signal. [11] Circuit according to any one of claims 7 to 10, wherein the first circuit (106) is operable to detect the collector or emitter current of the IGBT by detecting current through an emitter leakage inductance at an emitter terminal of the IGBT (102) or a shunt resistor connected to the emitter terminal, and wherein the second circuit (108) is operable to output the signal representing the time differentiation of the detected output collector or emitter current based on the voltage across the emitter leakage inductance, the voltage across the shunt resistor, a voltage generated across a Rogowski coil magnetically coupled to the emitter terminal, or a voltage induced across a current transformer coil magnetically coupled to the emitter terminal. [12] Circuit according to claim 11, wherein the third circuit (110) is operable to generate the pulse at the moment when the voltage measured by the second circuit (108) begins to rise in the second phase of the switching cycle. [13] Circuit according to one of claims 11 or 12, wherein the third circuit (110) comprises: - a protective circuit that can be operated to limit the output of the second circuit (108) against excessively high voltage during short-circuit shutdown; - a signal amplifier that can be operated to amplify the protection circuit output; and - a first pulse generator that can be operated to trigger in response to a falling and / or rising edge of the signal amplifier output. [14] Circuit according to claim 13, wherein the third circuit (110) further comprises a second pulse generator which is triggered by the same signal amplifier as the first pulse generator and is operable to generate an additional pulse which has a longer width than the pulse generated by the first pulse generator, and wherein the second pulse generator is activated during short-circuit protection of the IGBT (102) and deactivated during normal operation of the IGBT (102). [15] Circuit according to claim 14, wherein the fourth circuit (112) is operable to combine the pulses output by the first and second pulse generators and the control signal. [16] Circuit according to one of claims 14 or 15, wherein the first and the second pulse generator each comprise a monostable multivibrator. [17] Circuit according to any one of claims 7 to 16, wherein the third circuit has an input signal range which is from 0.1 to 2.0 times the collector rated current of the IGBT (102) during normal operation of the IGBT (102), and from 0.1 to 6.0 times the collector rated current during short-circuit protection of the IGBT (102). [18] Circuit according to one of the preceding claims, wherein the circuits (104) are configured to disable the generation of the pulse in response to a control signal indicating that the pulse should be disabled. [19] Circuit according to one of the preceding claims, wherein the circuits (104) are configured to increase the pulse width in response to a signal indicating a short-circuit fault condition, such that the pulse width is narrower for normal operation and wider for short-circuit operation. [20] Method for reducing overshoot for a bipolar insulated gate transistor (102) -IGBT- which can be operated to conduct current in a first phase of a switching cycle and to block current in a second phase of the switching cycle in response to a control signal applied to the gate of the IGBT (102), wherein collector-emitter voltage (V) overshoot is reduced. CE ) of the IGBT (102) occurs in the second phase of the switching cycle, the method comprising the following: - Generating a pulse that has a rising edge synchronized with the moment when current through the IGBT (102) begins to fall in the second phase of the switching cycle, and has a width that is a fraction of the duration of the V CE -Overshoot is; and - Combining the pulse with the control signal applied to a gate of the IGBT (102) to temporarily increase the gate voltage of the IGBT (102) in the second phase of the switching cycle above a threshold voltage of the IGBT (102) during the duration of the pulse. [21] Circuit (100) for reducing collector-emitter voltage (V) CE )-Overshoot in an insulated gate bipolar transistor (102) -IGBT-, wherein the circuit (100) comprises circuits (104) that are operable to: - to generate a pulse that has a rising edge synchronized with the instant when the collector or emitter current of the IGBT (102) begins to fall during the turn-off of the IGBT (102), and has a width that is a fraction of the duration of the V CE -Overshoot is; and - to combine the pulse with the control signal applied to a gate of the IGBT (102) to temporarily increase the gate voltage of the IGBT (102) during the turn-off of the IGBT (102) above a threshold voltage of the IGBT (102) during the duration of the pulse.

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