LDO circuit and method for preventing output overshoot caused by hot plugging under residual voltage during no load

Abstract

Disclosed in the present invention are an LDO circuit and method for preventing output overshoot caused by hot plugging under a residual voltage during no load. The LDO circuit comprises a comparator and a pulse signal generation module; the pulse signal generation module is connected to the comparator and is connected to a low static power consumption circuit by means of a PMOS transistor; a first amplifier outputs a voltage signal on the basis of an external reference voltage and a feedback voltage, and outputs a driving voltage (I) by means of an NMOS transistor and the low static power consumption circuit; a second PMOS transistor generates and controls an output voltage on the basis of an external input voltage and the driving voltage; the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generation module; the pulse signal generation module generates a second voltage signal on the basis of the third voltage signal; a pulse signal is generated by means of the comparator and the pulse signal generation module so as to modulate a gate of the second PMOS transistor, thereby preventing output voltage overshoot caused by hot plugging under residual voltage from an external input during no load.

Description

An LDO circuit and method for preventing overcharging of output during hot-plugging under no-load conditions Technical Field

[0001] This invention relates to the field of power management chip technology, and in particular to an LDO circuit and method for preventing overcharging of output by hot-plugging residual power under no-load conditions. Background Technology

[0002] Please refer to Figure 2, which shows a static power LDO circuit in the prior art. As shown in Figure 2, the circuit may include a circuit input terminal, a circuit output terminal and a ground terminal, a first amplifier, a second amplifier, a third amplifier, a PMOS transistor M3 and an output sampling module.

[0003] When the external input voltage is lower than the preset output voltage, the output voltage of the circuit will decrease as the input voltage decreases. At this time, the first sampling signal decreases, the gate voltage of M1 increases, and the gate voltage of M3 decreases, placing PMOS transistor M3 in the linear region. The third amplifier, based on the drain voltage of M2 and the output voltage, outputs the gate voltage of M4, ensuring that the source voltage of M4 changes with the output voltage and has the same value. At this time, PMOS transistor M2 is in the linear region, and the gate, drain, and source voltages of PMOS transistor M2 are equal to those of PMOS transistor M3. The current IM2 of PMOS transistor M2 and the current IM3 of PMOS transistor M3 are mirror images of each other.

[0004]

[0005] Wherein, the preset voltage at the output terminal is greater than or equal to the first reference signal, IM2 is the current of PMOS transistor M2, IM3 is the current of PMOS transistor M3, (W / L)M2 is the width-to-length ratio of PMOS transistor M2, and (W / L)M3 is the width-to-length ratio of PMOS transistor M3; so that when the input terminal voltage is lower than the preset voltage at the output terminal, the current of PMOS transistor M2 is:

[0006]

[0007] This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0008] Those skilled in the art will understand that the above has very high application value in the fields of low power consumption and lithium batteries, manifested in the following way: when VIN is low, M2 is limited by M4, preventing the increase in static power consumption caused by current mirror mismatch. Currently, to improve response speed and load capacity, the second-stage amplifier of low-power LDOs on the market typically uses a P-tube current mirror to replicate the power transistor's current. However, the aforementioned prior art has the following drawbacks: under no-load conditions, when VIN is low, the overall current is small, meaning the op-amp's response speed is slow, leading to VOUT overcharging issues, including:

[0009] During a slow start-up of VIN, VOUT may become overcharged.

[0010] When VIN is hot-swapped with residual charge, VOUT may become overcharged. Summary of the Invention

[0011] In view of the above-mentioned shortcomings in the current power management chip technology field, the present invention provides an LDO circuit and method to prevent overcharging of the output voltage when hot-plugging with residual power under no-load conditions, thereby preventing the problem of overcharging of the output voltage when hot-plugging with residual external input voltage under no-load conditions.

[0012] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0013] An LDO circuit for preventing overcharging of the output during hot-plugging with residual charge under no-load conditions includes: a first amplifier, a first NMOS transistor, a second PMOS transistor, a low quiescent power circuit, a fourth PMOS transistor, a first voltage divider sampling resistor, a second voltage divider sampling resistor, and an external input voltage. External reference voltage and output voltage The first amplifier is connected to a low static power circuit via an NMOS transistor. The first and second voltage-dividing sampling resistors are connected to the low static power circuit and generate a feedback voltage. The amplifier further includes a comparator and a pulse signal generation module. The comparator is connected to the low static power circuit via a second PMOS transistor. The pulse signal generation module is connected to the comparator and to the low static power circuit via a fourth PMOS transistor. The first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through the first NMOS transistor and the low static power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal. The second voltage signal is input to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage during hot-plugging when the external input voltage is still charged under no-load conditions.

[0014] According to one aspect of the present invention, the first NMOS transistor is a common-source amplifier with its source grounded, its drain connected to the drain of the fourth PMOS transistor and the low static power circuit, and its gate connected to the output terminal of the first amplifier. Based on the first voltage signal and the bias current provided by the low static power, it outputs a drive voltage. The source of the second PMOS transistor is connected to an external input voltage, its gate is connected to the drain of the fourth PMOS transistor, and its drain is connected to the first voltage divider sampling resistor and the comparator.

[0015] According to one aspect of the present invention, the low static power consumption circuit includes a first PMOS transistor, a third PMOS transistor, and a second amplifier. The source of the first PMOS transistor is connected to an external input voltage, the gate is connected to the gate of the second PMOS transistor, and the drain is connected to the source of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the input terminal of the second amplifier, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the drain of the fourth PMOS transistor and the drain of the first PMOS transistor.

[0016] According to one aspect of the invention, the LDO circuit further includes a current-limiting resistor located between the source of the first PMOS transistor and the external input voltage.

[0017] According to one aspect of the present invention, the second amplifier and the third PMOS transistor constitute a follower, and the drain voltage of the first PMOS transistor is controlled to follow the output voltage based on the output voltage, so as to avoid the increase of circuit static power consumption due to current mirror mismatch.

[0018] According to one aspect of the present invention, a negative feedback loop is formed by the first amplifier, the first NMOS transistor, the bias current provided by the low quiescent power circuit, the second PMOS transistor, the first sampling voltage divider resistor, and the second sampling voltage divider resistor. One end of the first voltage divider sampling resistor is connected to the drain of the low quiescent power circuit and the second PMOS transistor, and the other end of the first voltage divider sampling resistor is connected to one end of the second voltage divider sampling resistor and outputs a feedback voltage signal. The other end of the second voltage divider sampling resistor is grounded. The negative feedback loop makes the reference voltage and the feedback voltage consistent, and the output voltage is set by the first sampling voltage divider resistor and the second sampling voltage divider resistor. The output voltage is:

[0019] .

[0020] According to one aspect of the present invention, the gate of the fourth PMOS transistor is connected to the pulse signal generation module, the drain is connected to the drain of the first NMOS transistor and the low static power consumption circuit, and the source is connected to an external input voltage as a control drive voltage for the switch controller.

[0021] A method for preventing overcharging of hot-swapped output with residual charge under no-load conditions, the method comprising the following steps: a first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and a low static power consumption circuit; a second PMOS transistor generates and controls an output voltage based on an external input voltage and a drive voltage; a comparator compares the external input voltage and the output voltage and outputs a third voltage signal to a pulse signal generation module; the pulse signal generation module generates a second voltage signal based on the third voltage signal; and the second voltage signal is input to the gate of the second PMOS transistor through a fourth PMOS transistor.

[0022] According to one aspect of the invention, the comparator is internally a comparator with an offset voltage, that is, the comparator output switching voltage point is: Under no-load hot-swap conditions, when the external input voltage is removed, the third voltage signal output by the comparator is a high-level signal before the external input voltage is higher than the comparator's flip-off voltage point; when the external input voltage is lower than the comparator's flip-off voltage point, the third voltage signal output by the comparator flips to a low level.

[0023] According to one aspect of the invention, when the external input voltage is hot-swapped and powered on, the comparator, based on the external input voltage being greater than the comparator's flip-flop voltage point, reverses the output third voltage signal to a high level. The pulse signal generation module generates a pulse second voltage signal with an effective low level based on the rising edge of the third voltage signal. The fourth PMOS transistor is turned on based on the low-level pulse second voltage signal and pulls up its gate drive voltage, while simultaneously turning off the power transistor, thereby preventing overcharging of the output voltage. After the pulse second voltage signal recovers from a low level to a high level, it no longer controls the fourth PMOS transistor to turn on, and only adjusts the output voltage through a negative feedback operational amplifier.

[0024] According to one aspect of the invention, the no-load hot-swap condition includes a case where no load is connected, and a case where the load is connected to the output voltage but the switch turns the load off.

[0025] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 is a circuit diagram of an LDO circuit for preventing overcharging of residual hot-plug output under no-load conditions, as described in this invention.

[0028] Figure 2 is a circuit structure diagram of the prior art of an LDO circuit for preventing overcharging of residual hot-plug output under no-load conditions, as described in this invention.

[0029] Figure 3 is a simulation diagram of the no-load hot-plug effect of an LDO circuit for preventing overcharging of residual charge output during hot-plugging under no-load conditions, as described in this invention.

[0030] Figure 4 is a diagram showing the effect of the static current of an LDO circuit for preventing overcharging of residual hot-plug output under no-load conditions as described in this invention varies with the external input voltage.

[0031] Figure 5 is a simulation diagram of the no-load hot-plugging effect of the LDO circuit for preventing overcharging of residual hot-plugging output under no-load conditions, without the comparison circuit and pulse signal generation module, as described in this invention.

[0032] Figure 6 is a second embodiment of the LDO circuit for preventing overcharging of residual power during hot-plugging under no-load conditions, as described in this invention.

[0033] Figure 7 is a third embodiment of the LDO circuit for preventing overcharging of residual power during hot-plugging under no-load conditions, as described in this invention.

[0034] Figure 8 is a fourth embodiment of the LDO circuit for preventing overcharging of residual power during hot-plugging under no-load conditions, as described in this invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] Example 1:

[0037] As shown in Figure 1, an LDO circuit for preventing overcharging of the output during hot-plugging under no-load residual charge includes: a first amplifier, , Low static power consumption circuits , ,switch Comparator, pulse signal generation module, external power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on an external reference voltage. and feedback voltage Output voltage control signal . This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to... The drain of the circuit and the low static power circuit, with the source connected to an external input voltage. As a switch controller, it controls the drive voltage. . The source is connected to an external input voltage, and the gate is connected to... The drain, the drain is connected to the and comparator, Based on external input voltage and internal signals Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator internally carries an offset voltage. The comparator, i.e., the point at which the comparator output flips voltage, is: + The comparator is based on an external input voltage. The output is compared with the comparator's flip-point voltage. The pulse signal generation module is based on This generates a switch control signal. The pass Input to The gate. The low static power circuit includes... , Second amplifier, The source is connected to an external input voltage. Gate access The gate and drain are connected The source pole; Source access The drain of the second amplifier is connected to the input terminal of the second amplifier, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the input terminal of the second amplifier. Drain and The drain of the amplifier. The second amplifier and... Construct a follower buffer based on the output voltage control The drain voltage follows the output voltage. This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0038] Under the condition of unloaded hot-swappable external input voltage removal, if the external input voltage is removed... When the power supply is activated, the external input voltage at this time... The power supply is provided by the charge stored in the external input capacitor, and the voltage gradually decreases over time. When the external input voltage is higher than the comparator's flip-flop voltage point, the comparator output at this time... It is a high-level signal; if the external input voltage Lower than the preset output voltage Then the negative feedback loop pulls down the gate drive voltage. This causes the power transistor to be fully turned on, and at this time the output voltage... Follow external input voltage The comparator output decreases when the external input voltage is less than the comparator's inverting voltage point. Invert to low level. If the external input voltage... When hot-plugging is performed and powered on, the negative feedback loop starts to pull up the drive voltage. The comparator is based on an external input voltage. If the voltage is greater than the comparator's flip-point voltage, then the output... The pulse signal generation module is based on the inversion to a high level. The rising edge generates a pulse signal with an effective low level. The switch Based on the low-level pulse Turn on and pull up the gate drive voltage At the same time, the power transistor is turned off to avoid output voltage. Overcharging occurs. When the pulse signal... After returning to a high level from a low level, the fourth PMOS transistor is no longer turned on; the output voltage is adjusted only through the negative feedback operational amplifier. The no-load hot-swap conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns the load off.

[0039] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The symptoms include uniform power loss, and the aforementioned hot-swapped overcharging. When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease, as shown in the simulation diagram above. Power on at 3µs speed There was no overcharging.

[0040] As shown in Figure 5, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparator circuit and pulse signal generation module, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0041] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0042] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions.

[0043] Example 2:

[0044] As shown in Figure 6, an LDO circuit for preventing overcharging of the output during hot-plugging under no-load residual charge includes: a first amplifier, , Low static power consumption circuits , ,switch Comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage In this embodiment, a clamping circuit is also included. The first amplifier is based on an external reference voltage. and feedback voltage Output voltage control signal . It is a common-source amplifier, with the source grounded, the drain connected to the drain of the low quiescent power circuit, and the gate connected to the output of the first amplifier, and based on... The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to... The drain of the circuit and the low static power circuit, with the source connected to an external input voltage. As a switch controller, it controls the drive voltage. . The source is connected to an external input voltage, and the gate is connected to... The drain, the drain is connected to the and comparator, Based on external input voltage and internal signals Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator internally carries an offset voltage. The comparator, i.e., the point at which the comparator output flips voltage, is: + The comparator is based on an external input voltage. The output is compared with the comparator's flip-point voltage. The pulse signal generation module is based on This generates a switch control signal. and The pass Input to The gate of the pulse signal generation module is connected to the clamping circuit, based on the pulse signal generation module. To control Whether it is clamped. The low static power circuit includes a current-limiting resistor. , , Second amplifier, The source is connected to the current limiting resistor. Gate access The gate and drain are connected The source pole; Source access The drain and the second amplifier, the gate is connected to the second amplifier, and the drain is connected to... Drain and The drain of the amplifier. The second amplifier and... Construct a follower buffer based on the output voltage control The drain voltage follows the output voltage. This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0045] Under no-load hot-swap conditions, if the external input voltage is removed... When the power supply is activated, the external input voltage at this time... The power supply is provided by the charge stored in the external input capacitor, and the voltage gradually decreases over time. When the external input voltage is higher than the comparator's flip-flop voltage point, the comparator output at this time... It is a high-level signal; if the external input voltage Lower than the preset output voltage Then the negative feedback loop pulls down the gate drive voltage. This causes the power transistor to be fully turned on, and at this time the output voltage... Follow external input voltage The comparator output decreases when the external input voltage is less than the comparator's switching voltage point. Invert to low level. If the external input voltage... During hot-plugging and power-on, the negative feedback loop begins to pull up the gate drive voltage. The comparator is based on an external input voltage. If the voltage is greater than the comparator's flip-point voltage, then the output... The pulse signal generation module is based on the inversion to a high level. The rising edge generates a pulse signal with an effective high level. ,exist During the high-level period, the clamping circuit is activated. It was pulled down and shut down. This is beneficial to the upper level. pipe pull-up The pulse signal generation module is based on The rising edge generates a pulse signal with an effective low level. The switch Based on the low-level pulse Turn on and pull up the gate drive voltage At the same time, the power transistor is turned off to avoid output voltage. Overcharging occurs. When the pulse signal... After returning to a high level from a low level, the fourth PMOS transistor is no longer turned on; the output voltage is adjusted only through the negative feedback operational amplifier. The no-load hot-swap conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns the load off.

[0046] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The symptoms include uniform power loss, and the aforementioned hot-swapped overcharging. When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease, as shown in the simulation diagram above. Power on at 3µs speed There was no overcharging.

[0047] As shown in Figure 5, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparator circuit and pulse signal generation module, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0048] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0049] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions.

[0050] Example 3:

[0051] As shown in Figure 7, an LDO circuit for preventing overcharging of the output during hot-plugging under no-load residual current includes: a first amplifier, , Low static power consumption circuits , ,switch Comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage In this embodiment, a clamping circuit is added, and the pulse signal generation module description is expanded. The first amplifier is based on an external reference voltage. and feedback voltage Output voltage control signal . This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to... The drain of the circuit and the low static power circuit, with the source connected to an external input voltage. As a switch controller, it controls the drive voltage. . The source is connected to an external input voltage, and the gate is connected to... The drain, the drain is connected to the and comparator, Based on external input voltage and internal signals Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator internally carries an offset voltage. The comparator, i.e., the point at which the comparator output flips voltage, is: + The comparator is based on an external input voltage. The output is compared with the comparator's flip-point voltage. The pulse signal generation module is based on This generates a switch control signal. The pass Input to The gate. The low static power circuit includes... , Second amplifier, The source is connected to an external input voltage. Gate access The gate and drain are connected The source pole; Source access The drain of the second amplifier is connected to the input terminal of the second amplifier, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the input terminal of the second amplifier. Drain and The drain electrode. In and A current-limiting resistor can be connected between the two to limit the current flow when the external input power is low. The current. Among them, the second amplifier and Construct a follower buffer based on the output voltage control The drain voltage follows the output voltage. This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0052] The clamping circuit includes: , and , Gate access voltage signal Drain connection The source, the source access , Voltage signal is output from drain Gate access voltage signal , The other side is grounded. When When it is high level, Conductive, and It was dragged down.

[0053] The pulse signal generation module specifically includes: , , , , , , , The comparator's output signal Do , The gate input signal; based on , , Output Voltage; Capacitance Access The drain is grounded. connect This has a delaying effect; gate access The drain and source are connected Drain connection The source pole, The other end is grounded, voltage signal Do The gate input voltage signal; when When it is high level, If it is conducting, then It was dragged down.

[0054] Under no-load hot-swap conditions, if the external input voltage is removed... When the power supply is activated, the external input voltage at this time... The power supply is provided by the charge stored in the external input capacitor, and the voltage gradually decreases over time. When the external input voltage is higher than the comparator's flip-flop voltage point, the comparator output at this time... It is a high-level signal; if the external input voltage Lower than the preset output voltage Then the negative feedback loop pulls down the gate drive voltage. This causes the power transistor to be fully turned on, and at this time the output voltage... Follow external input voltage The comparator output decreases when the external input voltage is less than the comparator's inverting voltage point. The value is reversed to low. At this time... , , All because It is in the off state due to being low level, and , High level Controlled by the first amplifier. If the external input voltage... During hot-plugging and power-on, the negative feedback loop begins to pull up the gate drive voltage. , and in the During the initial rise, the external input voltage If the voltage is greater than the comparator's flip-flop voltage, then the output... Invert to high level; when When a high-level input is sent to the pulse signal generation module, then... , , Conductive, and When conducting, based on , , A falling edge is generated. Conductive, and If it is still during the falling edge of the high level, then , Conduction; Voltage based , and The switch flips to a low level. Open, will Raise to . Conductive, and It is still in the falling edge of the high level. If it is conducting, then The voltage is pulled low, as mentioned above The common-source amplifier is cut off, and the accelerating op-amp is pulled high. ;switch , The three components—the positive feedback op-amp, the negative feedback op-amp, and the negative feedback op-amp—work together to raise the gate drive voltage. At the same time, the power transistor is turned off to avoid output voltage. Overcharging occurred. The voltage at the falling edge makes Stop after the deadline. pull down ;when Continue to decrease to of + * back, Deadline, then The voltage returns to a high level. The switch is off. When the... Lower to low level and make , After being turned off, if no additional circuitry affects the normal operation of the negative feedback op-amp, then... based on , , During the falling edge, It appears as a pulse signal consisting of a high-low-high pattern; It manifests as a low-pulse turn-on-off cycle. The state.

[0055] As shown in Figure 3, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The symptoms include uniform power loss, and the aforementioned hot-swapped overcharging. When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease, as shown in the simulation diagram above. Power on at 3µs speed There was no overcharging.

[0056] As shown in Figure 4, the horizontal axis is... The vertical axis represents the quiescent current of the entire LDO circuit. At 3.25V, Maximum, the maximum is 0.955uA; normal. At 4.3V, =656nA.

[0057] As shown in Figure 5, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparator circuit and pulse signal generation module, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0058] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0059] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions.

[0060] Example 4:

[0061] As shown in Figure 8, an LDO circuit for preventing overcharging of the output during hot-plugging under no-load residual current includes: a first amplifier, , Low static power consumption circuits , ,switch Comparator, pulse signal generation module, and external power supply Power supply, ground voltage GND, reference voltage and external output voltage The first amplifier is based on an external reference voltage. and feedback voltage Output voltage control signal In this embodiment, the description of the pulse signal generation module is expanded. This is a common-source amplifier, with the source grounded and the drain connected to ground. The drain and the low static power circuit, the gate is connected to the output of the first amplifier, and based on The bias current provided by low quiescent power consumption, and the output gate drive voltage . The gate is connected to the pulse signal generating module, and the drain is connected to... The drain of the circuit and the low static power circuit, with the source connected to an external input voltage. As a switch controller, it controls the drive voltage. . The source is connected to an external input voltage, and the gate is connected to... The drain, the drain is connected to the and comparator, Based on external input voltage and internal signals Control output voltage Size. One end is connected to the low static power consumption circuit and The drain electrode, The other end connects One end is connected to a feedback voltage signal ; The other end is grounded. First amplifier, The bias current provided by the low static power circuit , and The resulting loop forms a negative feedback loop, which causes the reference voltage to... and feedback voltage Consistency, then approval and Set output voltage The output voltage is: The comparator internally carries an offset voltage. The comparator, i.e., the point at which the comparator output flips voltage, is: + The comparator is based on an external input voltage. The output is compared with the comparator's flip-point voltage. The pulse signal generation module is based on This generates a switch control signal. The pass Input to The gate. The low static power circuit includes... , Second amplifier, The source is connected to an external input voltage. Gate access The gate and drain are connected The source pole; Source access The drain of the second amplifier is connected to the input terminal of the second amplifier, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the input terminal of the second amplifier. Drain and The drain electrode. In and A current-limiting resistor can be connected between the two to limit the current flow when the external input power is low. The current. Among them, the second amplifier and Construct a follower buffer based on the output voltage control The drain voltage follows the output voltage. This avoids increased static power consumption in the circuit due to current mirror mismatch.

[0062] The pulse signal generation module specifically includes: Inverter , , NOR gate , and The inverter The output terminal is connected to , The other end connects NOR gate, The other end is grounded, and the output of the NOR gate is connected to an inverter. inverter The output terminal is connected to The comparator's output signal Do Gate input voltage, based on and Output voltage signal . As an inverter The input of the inverter and one of the inputs of the NOR gate, the inverter. based on and The output voltage passes through Later obtained , As another input to NOR, and Obtained via NOR , go through Later obtained ,Depend on Control the switching transistor .

[0063] Under no-load hot-swap conditions, if the external input voltage is removed... When the power supply is activated, the external input voltage at this time... The power supply is provided by the charge stored in the external input capacitor, and the voltage gradually decreases over time. When the external input voltage is higher than the comparator's flip-flop voltage point, the comparator output at this time... It is a high-level signal; if the external input voltage Lower than the preset output voltage Then the negative feedback loop pulls down the gate drive voltage. This causes the power transistor to be fully turned on, and at this time the output voltage... Follow external input voltage The comparator output decreases when the external input voltage is less than the comparator's inverting voltage point. Invert to low level, at this time If enabled, It was pulled up, and Low level, High level It is in the off state. If the external input voltage... During hot-plugging and power-on, the negative feedback loop begins to pull up the gate drive voltage. , and During the initial rise, the If the voltage is greater than the comparator's flip-flop voltage, then the comparator output... Invert to high level.

[0064] when When a high-level input is sent to the pulse charge signal generation module, then... Deadline It was dragged down. based on , Rate limiting and used as input, then passed through and Rate limiting and timeout, and Compared to This is manifested as a slow rise from a low level to a high level; at this time It is low level, and When the rising edge is still at a low level, The signal flips to a high level. based on High level output low level , then the switch Open, will Voltage pulled up to Turn off the power transistor to avoid Overcharging occurred. After the rising edge is high, NOR makes When the signal transitions from high to low, then After passing through the inverter, the signal is high, and the switch... Cut off, no additional circuitry affects the normal operation of the negative feedback op-amp. Based on After being pulled down, During the rising edge, It is represented by a low-level active pulse signal consisting of a high-low-high sequence.

[0065] As shown in Figure 4, Under the condition of inconsistent residual hot-plug speed, The change. When removed Then, it is powered by the input capacitor. Since the LDO has low and constant static power consumption under no-load conditions, The symptoms include uniform power loss, and the aforementioned hot-swapped overcharging. When the residual voltage is higher than 3.24V, the negative feedback op-amp is still in normal regulation state, so Unchanged; when Below 3.24V, Followers began to appear The decrease, as shown in the simulation diagram above. Power on at 3µs speed There was no overcharging.

[0066] As shown in Figure 5, The residual current hot-plugging conditions are the same as in Figure 3, but due to the lack of a comparator circuit and pulse signal generation module, the circuit response speed is slow. After overcharging, the power transistor remains off until... Falling to the preset Later, the power transistor is released only after the negative feedback, so in the simulation diagram, After overcharging, it will last for 3-4 seconds.

[0067] By changing some of the structures in this embodiment, the new embodiment can achieve the same function and effect.

[0068] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions.

[0069] Example 5:

[0070] As shown in Figure 1, a method for preventing overcharging of the output during hot-plugging with residual charge under no-load conditions is described in this embodiment, which is based on the LDO circuit of Embodiment 1. The specific steps of this embodiment are as follows:

[0071] S1: Under no-load hot-swap conditions, remove the external input voltage. When the power supply is activated, the external input voltage at this time... The power supply is provided by the charge stored in the external input capacitor, and the voltage gradually decreases over time. When the external input voltage is higher than the comparator's flip-flop voltage point, the comparator output at this time... This is a high-level signal.

[0072] S2: The external input voltage Lower than the preset output voltage Then the negative feedback loop pulls down the gate drive voltage. This causes the power transistor to be fully turned on, and at this time the output voltage... Follow external input voltage The comparator output decreases when the external input voltage is less than the comparator's inverting voltage point. Invert to low level.

[0073] S3: External input voltage During hot-plugging and power-on, the negative feedback loop begins to pull up the gate drive voltage. The comparator is based on an external input voltage. If the voltage is greater than the comparator's flip-point voltage, then the output... The pulse signal generation module is based on the inversion to a high level. The rising edge generates a pulse signal with an effective low level. The switch Based on the low-level pulse Turn on and pull up the gate drive voltage At the same time, the power transistor is turned off to avoid output voltage. Overcharging occurred.

[0074] S4: When the pulse signal After returning to a high level from a low level, the fourth PMOS transistor is no longer turned on; the output voltage is adjusted only through the negative feedback operational amplifier. The no-load hot-swap conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns the load off.

[0075] By replacing or modifying parts of the LDO circuit structure in this embodiment, new LDO circuit structures can be obtained, with the new embodiments having the same function and effect. For example, a clamping circuit was added in embodiment two, based on the newly added... To control the judgment Whether it is clamped. For example, in embodiment three, a clamping circuit is added, and the description of the pulse signal generation module is expanded. For example, in embodiment four, the description of the pulse signal generation module is expanded.

[0076] Advantages of this invention: The invention connects the pulse signal generation module to the comparator and a PMOS transistor to a low quiescent power circuit. The first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through an NMOS transistor and the low quiescent power circuit. The second PMOS transistor generates and controls the output voltage based on the external input voltage and the driving voltage. The comparator compares the external input voltage and the output voltage and outputs a third voltage signal to the pulse signal generation module. The pulse signal generation module generates a second voltage signal based on the third voltage signal and inputs it to the gate of the second PMOS transistor through the fourth PMOS transistor. The comparator and the pulse signal generation module generate a pulse signal to modulate the gate of the second PMOS transistor to prevent overcharging of the output voltage when the external input voltage is hot-plugged under no-load conditions.

[0077] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An LDO circuit for preventing overcharging of output during hot-plugging with residual charge under no-load conditions, comprising: a first amplifier, a first NMOS transistor, a second PMOS transistor, a low quiescent power circuit, a fourth PMOS transistor, and a first voltage divider sampling resistor. Second voltage divider sampling resistor and external input voltage External reference voltage and output voltage The first amplifier is connected to a low quiescent power circuit via an NMOS transistor, and the first and second voltage-dividing sampling resistors are connected to the low quiescent power circuit to generate a feedback voltage. The characteristic of this circuit is that... It also includes a comparator and a pulse signal generation module; wherein, the comparator is connected to a low quiescent power circuit via a second PMOS transistor, the pulse signal generation module is connected to the comparator and to the low quiescent power circuit via a fourth PMOS transistor, the first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and the low quiescent power circuit, the second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage, the comparator compares the external input voltage and the output voltage, and outputs a third voltage signal to the pulse signal generation module, the pulse signal generation module based on... The third voltage signal generates a second voltage signal, which is input to the gate of the second PMOS transistor through the fourth PMOS transistor. A pulse signal is generated by a comparator and a pulse signal generation module to modulate the gate of the second PMOS transistor, preventing overcharging of the output voltage during hot-plugging under no-load conditions. The gate of the fourth PMOS transistor is connected to the pulse signal generation module, its drain is connected to the drain of the first NMOS transistor and the low static power circuit, and its source is connected to the external input voltage, serving as the control voltage for the switch controller. The comparator internally has an offset voltage, meaning the comparator output switching voltage point is: Under no-load hot-swap conditions, when the external input voltage is disconnected, the third voltage signal output by the comparator is a high-level signal before the external input voltage is higher than the comparator's flip-off voltage point; when the external input voltage is lower than the comparator's flip-off voltage point, the third voltage signal output by the comparator flips to a low level; the no-load hot-swap conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns off the load.

2. The LDO circuit for preventing overcharging of output during hot-plugging under no-load conditions as described in claim 1, characterized in that, The first NMOS transistor is a common-source amplifier with its source grounded and its drain connected to the drain of the fourth PMOS transistor and the low static power circuit. Its gate is connected to the output of the first amplifier and outputs a drive voltage based on the first voltage signal and the bias current provided by the low static power. The source of the second PMOS transistor is connected to the external input voltage, and its gate is connected to the drain of the fourth PMOS transistor. Its drain is connected to the first voltage divider sampling resistor and the comparator.

3. The LDO circuit for preventing overcharging of output during hot-plugging under no-load conditions, as described in claim 1, is characterized in that... The low static power consumption circuit includes a first PMOS transistor, a third PMOS transistor, and a second amplifier. The source of the first PMOS transistor is connected to an external input voltage, the gate is connected to the gate of the second PMOS transistor, and the drain is connected to the source of the third PMOS transistor. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the input terminal of the second amplifier, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the drain of the fourth PMOS transistor and the drain of the first NMOS transistor.

4. The LDO circuit for preventing overcharging of output during hot-plugging under no-load conditions as described in claim 3, characterized in that, The LDO circuit also includes a current-limiting resistor located between the source of the first PMOS transistor and the external input voltage.

5. The LDO circuit for preventing overcharging of output during hot-plugging under no-load conditions as described in claim 3, characterized in that, The second amplifier and the third PMOS transistor form a follower, and the drain voltage of the first PMOS transistor is controlled to follow the output voltage based on the output voltage, so as to avoid the increase of static power consumption of the circuit due to current mirror mismatch.

6. The LDO circuit for preventing overcharging of output during hot-plugging under no-load conditions, as described in claim 1, is characterized in that... The loop formed by the first amplifier, the first NMOS transistor, the bias current provided by the low quiescent power circuit, the second PMOS transistor, the first sampling voltage divider resistor, and the second sampling voltage divider resistor constitutes a negative feedback loop. One end of the first voltage divider sampling resistor is connected to the drain of the low quiescent power circuit and the second PMOS transistor, and the other end of the first voltage divider sampling resistor is connected to one end of the second voltage divider sampling resistor and outputs a feedback voltage signal; the other end of the second voltage divider sampling resistor is grounded. The negative feedback loop makes the reference voltage and the feedback voltage consistent, and then sets the output voltage through the first and second sampling voltage divider resistors. The output voltage is: 。 7. A method for preventing overcharging of hot-swapped output with residual charge under no-load conditions, implemented based on the LDO circuit described in any one of claims 1 to 6, characterized in that, The method includes the following steps: A first amplifier outputs a first voltage signal based on an external reference voltage and a feedback voltage, and outputs a drive voltage through a first NMOS transistor and a low quiescent power circuit; a second PMOS transistor generates and controls the output voltage based on the external input voltage and the drive voltage; a comparator compares the external input voltage and the output voltage and outputs a third voltage signal to a pulse signal generation module; the pulse signal generation module generates a second voltage signal based on the third voltage signal; the second voltage signal is input to the gate of the second PMOS transistor through a fourth PMOS transistor; the comparator internally has an offset voltage, i.e., the comparator output switching voltage point is: Under no-load hot-swap conditions, when the external input voltage is disconnected, the third voltage signal output by the comparator is a high-level signal before the external input voltage is higher than the comparator's flip-off voltage point; when the external input voltage is lower than the comparator's flip-off voltage point, the third voltage signal output by the comparator flips to a low level; the no-load hot-swap conditions include the case where no load is connected, and the case where the load is connected to the output voltage but the switch turns off the load.

8. A method for preventing overcharging of hot-swapped output with residual charge under no-load conditions, as described in claim 7, characterized in that... When the external input voltage is hot-swapped and powered on, the comparator, based on the fact that the external input voltage is greater than the comparator's flip-flop voltage point, reverses the output third voltage signal to a high level. The pulse signal generation module generates a pulse second voltage signal with an effective low level based on the rising edge of the third voltage signal. The fourth PMOS transistor turns on based on the low-level pulse second voltage signal and pulls up the gate drive voltage, while turning off the power transistor, thereby preventing the output voltage from overcharging. After the pulse second voltage signal recovers from a low level to a high level, it no longer controls the fourth PMOS transistor to turn on, and only adjusts the output voltage through the negative feedback operational amplifier.

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