Light detection device

Abstract

A light detecting device according to the present disclosure includes a first substrate having a photoelectric conversion element for photoelectrically converting light, and a readout circuit capable of outputting a signal based on electric charges generated by conversion of the photoelectric conversion element; a second substrate having a signal processing unit capable of performing signal processing on a signal output from the readout circuit, and laminated on the first substrate; and at least one transistor provided between the readout circuit and the signal processing unit. The first substrate has a first semiconductor layer and a first wiring layer, and the second substrate has a second semiconductor layer and a second wiring layer. The transistor is provided in the first wiring layer and / or the second wiring layer.

Description

Technical Field

[0001] This disclosure relates to a light detection device. Background Technology

[0002] For imaging devices, there are techniques that divide the signal lines that read out pixel signals into multiple segments to reduce the load on the signal lines (see Patent Document 1). Furthermore, as an imaging device configuration, some imaging devices include a pixel substrate on which pixels are disposed and a circuit board on which signal processing circuitry for processing pixel signals is disposed.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: International Patent Application Publication WO 2021 / 085025 A1 Summary of the Invention

[0006] The technology described in Patent Document 1 provides a configuration in which signals output to segmented signal lines are synthesized by a synthesis circuit disposed on the side where the circuit board is located. This results in redundancy in the wiring between the pixel substrate and the circuit board, as well as within the circuit board. Furthermore, the circuit board ultimately has an area in which the synthesis circuit is disposed. This becomes an obstacle to miniaturization and accelerated signal readout.

[0007] Therefore, it is desirable to provide an optical detection device that enables the reduction of wiring redundancy, thereby facilitating miniaturization and accelerated signal readout.

[0008] A light detection device according to one embodiment of the present disclosure includes: a first substrate including a photoelectric conversion element and a readout circuit, the photoelectric conversion element performing photoelectric conversion of light, and the readout circuit being configured to output a signal based on the charge photoelectricly converted in the photoelectric conversion element; a second substrate stacked on the first substrate and including a signal processor configured to perform signal processing on the signal output from the readout circuit; and at least one transistor disposed between the readout circuit and the signal processor. The first substrate includes a first semiconductor layer and a first wiring layer, and the second substrate includes a second semiconductor layer and a second wiring layer. The transistor is disposed in at least one of the first wiring layer and the second wiring layer.

[0009] In a photodetector according to one embodiment of the present disclosure, the at least one transistor is disposed between the readout circuit in the first substrate and the signal processor in the second substrate. The transistor is disposed in at least one of the first wiring layer of the first substrate and the second wiring layer of the second substrate. Attached Figure Description

[0010] Figure 1 This is a block diagram showing an outline of an imaging apparatus as a light detection device according to a comparative example.

[0011] Figure 2 This is a configuration diagram showing an example of a pixel unit in an imaging apparatus of a light detection device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a configuration diagram showing an example of a pixel unit in an imaging apparatus according to an embodiment.

[0013] Figure 4 This is a configuration diagram showing an outline of an imaging apparatus according to an embodiment.

[0014] Figure 5 This is a schematic diagram illustrating the configuration example 1 of the imaging apparatus according to an embodiment.

[0015] Figure 6 This is a schematic diagram illustrating the configuration example 1 of the imaging apparatus according to an embodiment.

[0016] Figure 7 This is a schematic diagram illustrating the configuration example 2 of the imaging apparatus according to the embodiment.

[0017] Figure 8 This is a schematic diagram illustrating the configuration example 3 of the imaging apparatus according to the embodiment.

[0018] Figure 9 This is a schematic diagram illustrating the configuration example 3 of the imaging apparatus according to the embodiment.

[0019] Figure 10 This is a schematic diagram illustrating the configuration example 4 of the imaging apparatus according to the embodiment.

[0020] Figure 11 This is a schematic diagram illustrating the configuration example 5 of the imaging apparatus according to an embodiment.

[0021] Figure 12 This is a schematic cross-sectional view illustrating an example 5 of the configuration of the imaging apparatus according to an embodiment.

[0022] Figure 13 This is a schematic diagram illustrating the configuration example 6 of the imaging apparatus according to an embodiment.

[0023] Figure 14 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0024] Figure 15 This is an illustration of an example of the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0025] In the following, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Note that the description proceeds in the following order.

[0026] 0. Comparative Example

[0027] 1. Implementation Method

[0028] 1.1. Overview

[0029] 1.2. Configuration Example

[0030] 1.3. Effects

[0031] 2. Examples of applications for moving bodies

[0032] 3. Other implementation methods

[0033] <0. Comparative Example>

[0034] Figure 1 This is a block diagram showing an outline of an imaging device 300, which is a light detection device according to a comparative example.

[0035] Before describing the light detection apparatus according to the embodiment, a configuration example of the imaging apparatus 300, which is a light detection apparatus according to a comparative example, will be described. The light detection apparatus is a device configured to detect incident light. The imaging apparatus 300 according to the comparative example includes a plurality of pixels P, each pixel P including a photoelectric conversion unit (photoelectric conversion element), and is configured to perform photoelectric conversion on the incident light to generate a signal. The imaging apparatus 300 can receive light that has passed through an optical system (not shown) including an optical lens to generate a signal.

[0036] Imaging device 300 includes, for example, a semiconductor substrate (e.g., a silicon substrate) having a plurality of pixels P disposed thereon. Each pixel P of imaging device 300 has a photoelectric conversion unit, for example, a photodiode (PD), configured to perform photoelectric conversion of light. Imaging device 300 includes a region (pixel unit 100) in which the plurality of pixels P are arranged in a matrix in a two-dimensional manner, serving as an imaging region. Pixel unit 100 is a pixel array having a plurality of pixels P disposed therein, and may be referred to as a light receiving region.

[0037] Imaging device 300 receives incident light (image light) from a subject through an optical system including optical lenses. Imaging device 300 images the subject using an image formed by the optical lenses. Imaging device 300 can perform photoelectric conversion on the received light to generate pixel signals. Imaging device 300 is, for example, a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor. Imaging device 300 can be used in electronic devices such as digital still cameras, camcorders, and mobile phones.

[0038] The imaging device 300 includes, for example, a pixel driver 111, a signal processor 112, a controller 113, and a processor 114 in the peripheral area of ​​the pixel unit 100 (pixel array). Furthermore, the imaging device 300 is provided with multiple control lines Lread and multiple signal lines VSL.

[0039] The control line Lread is a signal line configured to transmit signals controlling pixel P, and is coupled to pixel P of pixel driver 111 and pixel unit 100. Figure 1 In the example shown, in pixel unit 100, multiple control lines Lread are wired for each pixel row, each pixel row including multiple pixels P arranged side by side in the horizontal direction (row direction). The control lines Lread are configured to transmit control signals for reading signals from pixels P.

[0040] The imaging device 300 has multiple control lines Lread for each pixel row, including, for example, lines for transmitting signals to control transmission transistors, lines for transmitting signals to control selection transistors, and lines for transmitting signals to control reset transistors. The control lines Lread can be referred to as drive lines (pixel drive lines) that transmit signals to drive pixels P.

[0041] A signal line VSL is a signal line configured to transmit signals from a pixel P and coupled to the pixel P of the pixel unit 100 and the signal processor 112. For example, one or more signal lines VSL are wired to the pixel unit 100 for each pixel column (including multiple pixels P arranged side by side in the vertical direction (column direction)).

[0042] The signal line VSL is a vertical signal line and is configured to transmit the signal output from pixel P. In the imaging apparatus 300, multiple signal lines VSL can be provided for a single pixel column. The imaging apparatus 300 can include multiple signal lines VSL for each pixel column.

[0043] Pixel driver 111 is configured to drive each pixel P of pixel unit 100. Pixel driver 111 is a driving circuit and includes multiple circuits, such as buffers, shift registers, address decoders, etc. Pixel driver 111 (pixel driving circuit) generates signals for driving pixel P and outputs the signals to each pixel P of pixel unit 100 via control line Lread. Pixel driver 111 is controlled by controller 113 and controls the pixels P of pixel unit 100.

[0044] For example, pixel driver 111 generates signals for controlling pixel P, such as signals controlling the transfer transistor of pixel P, signals controlling the select transistor, signals controlling the reset transistor, etc., and provides the generated signals to each pixel P via the control line Lread. Pixel driver 111 can be controlled to read pixel signals from each pixel P. Pixel driver 111 can be referred to as a pixel controller configured to control each pixel P. Note that pixel driver 111 and controller 113 can also be collectively referred to as a pixel controller.

[0045] Signal processor 112 is configured to perform signal processing on the signal from the input pixel P. Signal processor 112 is a signal processing circuit and includes, for example, a load circuit unit, an AD converter 40, a level selection switch, etc. The load circuit unit includes, for example, a current source configured to supply current to the amplifying transistor of pixel P. The load circuit unit, together with the amplifying transistor of pixel P, forms, for example, a source follower circuit. Note that signal processor 112 may include an amplifier circuit unit configured to amplify the signal read from pixel P via signal line VSL.

[0046] Signal processor 112 may include multiple AD converters 40 (AD conversion circuits) and output pixel signals converted into digital signals by the AD converters 40. The AD converters 40 are ADCs (analog-to-digital converters). For example, an AD converter 40 may be configured for each of multiple signal lines VSL. An AD converter 40 may be configured for each pixel column of pixel unit 100. The AD converters 40 are not limited to SS (single-slope) ADCs and may be other configured ADCs.

[0047] Each of the AD converters 40 is configured to convert an input analog signal into a digital signal. Each AD converter 40 performs AD conversion processing on the signal of pixel P, which is an analog signal input from each pixel P through the signal line VSL. Each AD converter 40 (AD conversion circuit) includes, for example, a comparator circuit and a counter, and can convert the signal of the input pixel P into a digital signal of a predetermined number of bits.

[0048] The signal output by each pixel P selected and scanned by pixel driver 111 is input to signal processor 112 via signal line VSL. Signal processor 112 can perform signal processing such as AD conversion and CDS (correlated double sampling) of the signal of pixel P. The signal of each pixel P transmitted through each signal line VSL is processed by signal processor 112 and output to processor 114.

[0049] Processor 114 is configured to perform signal processing on the input signal. Processor 114 is a processing circuit and includes circuitry for performing various signal processing operations on pixel signals, for example. Processor 114 may include a processor and a memory. Processor 114 performs signal processing on the signal of pixel P input from signal processor 112 and outputs the processed signal of pixel P. Processor 114 can perform various signal processing operations, such as noise reduction processing and grayscale correction processing.

[0050] The controller 113 is configured to control each unit of the imaging device 300. The controller 113 can receive data such as clock signals and command operation modes provided from an external source, and can output data such as internal information about the imaging device 300. The controller 113 is a control circuit and includes, for example, a timing generator configured to generate various timing signals.

[0051] The controller 113 performs drive control on the pixel driver 111, signal processor 112, etc., based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. Note that some or all of the signal processor 112, controller 113, and processor 114 may be integrated.

[0052] <1. Implementation Method>

[0053] Next, a detection apparatus according to an embodiment of the present disclosure will be described. Note that in the following text, parts that are substantially the same as the components of the imaging apparatus 300, which is a detection apparatus according to a comparative example, are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0054] <1.1. Summary>

[0055] Figure 2 This is a configuration diagram showing an example of a pixel unit 100 in an imaging apparatus 1 of a detection apparatus according to an embodiment of the present disclosure. Figure 3 This is a configuration diagram showing an example of a pixel unit 100 in an imaging apparatus 1 according to an embodiment. Figure 4 This is a configuration diagram showing an outline of the imaging apparatus 1 according to an embodiment.

[0056] In the following text, such as Figure 2 As shown, assume the incident direction of light from the subject is the Z-axis. Assume the horizontal direction orthogonal to the Z-axis along the plane of the paper is the X-axis. Assume the perpendicular direction orthogonal to both the Z-axis and X-axis along the plane of the paper is the Y-axis.

[0057] like Figure 3 and Figure 4As shown, the imaging apparatus 1 according to this embodiment includes, for example, a first segmented signal line VSL1N and a second segmented signal line VSL1S, which are segmented at the central portion 100C of the pixel unit 100, as signal lines VSL. A readout circuit 20 from at least one first pixel among a plurality of pixels P (see description below) Figure 5 The signal from the readout circuit 20 in at least one of the multiple pixels P is output to the first segmentation signal line VSL1N.

[0058] like Figure 4 As shown, the imaging apparatus 1 according to this embodiment includes a first substrate 101 and a second substrate 102 stacked with the first substrate 101. The first substrate 101 includes a first semiconductor layer 110 and a first wiring layer 210. The second substrate 102 includes a second semiconductor layer 120 and a second wiring layer 220.

[0059] The first semiconductor layer 110 of the first substrate 101 includes a photodiode PD as a photoelectric conversion element and a readout circuit 20 configured to output a signal based on the charge converted by the photodiode PD. The first semiconductor layer 110 includes a plurality of pixels P, each pixel P including a photodiode PD and a readout circuit 20.

[0060] The second semiconductor layer 120 of the second substrate 102 includes a signal processor 112 configured to perform signal processing on signals output from the readout circuit 20.

[0061] The imaging apparatus 1 according to this embodiment includes at least one transistor disposed between the readout circuit 20 and the signal processor 112. The at least one transistor is disposed in at least one of the first wiring layer 210 and the second wiring layer 220.

[0062] The at least one transistor is, for example, a switching transistor configured to switch the electrical coupling state between the readout circuit 20 and the signal processor 112. The transistor is, for example, a switching transistor configured to switch the electrical coupling state between the signal line VSL and the signal processor 112.

[0063] As a switching transistor, the imaging device 1 according to this embodiment is, for example, Figure 4 The diagram may include a first switching transistor (first switching switch SW1N) and a second switching transistor (second switching switch SW1S).

[0064] The first switching transistor (first switching switch SW1N) includes a first coupling terminal and a second coupling terminal. In the first switching switch SW1N, the first coupling terminal is coupled to the first split signal line VSL1N, while the second coupling terminal is coupled to the signal processor 112. The first switching switch SW1N can be configured to switch the electrical coupling state between the first split signal line VSL1N and the signal processor 112.

[0065] The second switching transistor (second switching switch SW1S) includes a first coupling terminal and a second coupling terminal. In the second switching switch SW1S, the first coupling terminal is coupled to the second split signal line VSL1S, while the second coupling terminal is coupled to the signal processor 112. The second switching switch SW1S can be configured to switch the electrical coupling state between the second split signal line VSL1S and the signal processor 112.

[0066] <2. Configuration Example>

[0067] In the following text, a more detailed configuration example of the imaging apparatus 1 according to this embodiment is described.

[0068] <Configuration Example 1>

[0069] Figure 5 This is a schematic diagram showing a configuration example 1 of the imaging apparatus 1 according to this embodiment. Figure 6 This is a schematic cross-sectional view showing an example of the configuration of the imaging apparatus 1 according to this embodiment.

[0070] For example, such as Figure 6 As shown, the imaging device 1 includes a light guide 80, a first substrate 101, and a second substrate 102. The first substrate 101 includes a first semiconductor layer 110 and a first wiring layer 210. The second substrate 102 includes a second semiconductor layer 120 and a second wiring layer 220.

[0071] Imaging device 1 has a configuration in which a light guide 80, a first semiconductor layer 110, a first wiring layer 210, a second wiring layer 220, and a second semiconductor layer 120 are stacked in the Z-axis direction. The light guide 80, the first semiconductor layer 110, the first wiring layer 210, the second wiring layer 220, and the second semiconductor layer 120 are provided from the light incident side. The first semiconductor layer 110 and the second semiconductor layer 120 each include a semiconductor substrate (e.g., a silicon substrate, an SOI substrate, etc.).

[0072] The light guide 80 includes a lens 81 and a filter 82, and guides the incident light toward the first semiconductor layer 110. The photodiode PD performs photoelectric conversion on the light incident through the lens 81 and the filter 82.

[0073] Lens 81 is provided, for example, for each pixel P or in units of multiple pixels P. Lens 81 is an optical component also known as an on-chip lens. Light from the subject is incident on lens 81 through an optical system such as an imaging lens.

[0074] The filter 82 is configured to selectively transmit light within a specific wavelength range from the incident light. The filter 82 is an RGB color filter, a complementary color filter, an infrared light-transmitting filter, etc., and is disposed between the lens 81 and the first semiconductor layer 110. Note that the filter 82 can be omitted as needed. Furthermore, some or all of the pixels P in the imaging device 1 may be without the filter 82. For example, a pixel P that receives white light (W) and performs photoelectric conversion may be without the filter 82.

[0075] The first wiring layer 210 includes a plurality of electrodes 91, and the second wiring layer 220 includes a plurality of electrodes 92. Electrodes 91 and 92 are each, for example, electrodes comprising copper (Cu). Electrodes 91 and 92 are electrodes used for bonding between metal electrodes and may be referred to as bonding electrodes. For example, the first substrate 101 and the second substrate 102 are bonded together by bonding between the Cu-containing metal electrodes (electrodes 91 and 92), i.e., Cu-Cu bonding.

[0076] The circuits of the first substrate 101 and the second substrate 102 are electrically coupled through electrodes 91 and 92. A signal processor 112, including an AD converter 40, is disposed in the second semiconductor layer 120, for example. Furthermore, a pixel driver 111, a controller 113, a processor 114, etc., may be disposed in the second semiconductor layer 120. Other circuits, such as memory, processor, power supply circuits, and interface circuits, may be disposed in the second semiconductor layer 120.

[0077] Note that electrodes 91 and 92 may comprise metallic materials other than copper, such as nickel (Ni), cobalt (Co), gold (Au), etc. Alternatively, bumps may be used to stack the first substrate 101 and the second substrate 102.

[0078] like Figure 5 As shown, the pixel P of the imaging device 1 includes a photodiode PD, a transmission transistor TG, a floating diffuser FD, and a readout circuit 20. The photodiode PD is configured to receive light and generate a signal. The photodiode PD is configured to generate charge through photoelectric conversion.

[0079] The readout circuit 20 is configured to output a signal based on the charge after photoelectric conversion.

[0080] The transfer transistor TG is configured to transfer the charge converted by the photodiode PD to the floating diffuser FD. The transfer transistor TG electrically connects or disconnects the photodiode PD from the floating diffuser FD. The transfer transistor TG can transfer the charge converted and accumulated by the photodiode PD to the floating diffuser FD.

[0081] A floating diffuser FD is an accumulator configured to accumulate transferred charge. The floating diffuser FD can accumulate charge converted by a photodiode (PD). The floating diffuser FD can also be referred to as a holding section configured to hold the transferred charge. The floating diffuser FD accumulates the transferred charge and converts it into a voltage corresponding to the capacitance of the floating diffuser FD.

[0082] For example, such as Figure 5 As shown, the readout circuit 20 includes an amplifier transistor AMP, a selector transistor SEL, and a reset transistor RST. The amplifier transistor AMP is configured to generate and output a signal based on the charge accumulated in the floating diffuser FD. The gate of the amplifier transistor AMP is electrically coupled to the floating diffuser FD and is supplied with a voltage converted by the floating diffuser FD.

[0083] The drain of the amplifier transistor AMP is coupled to the power supply line VDD. The source of the amplifier transistor AMP is coupled to the signal line VSL via the selector transistor SEL. The amplifier transistor AMP can generate a signal based on the charge accumulated in the floating diffuser FD, i.e., a signal based on the voltage of the floating diffuser FD, and output this signal to the signal line VSL. The amplifier transistor AMP is configured to generate a signal based on the charge converted by the photodiode PD.

[0084] The selector transistor SEL is configured to control the signal output of pixel P. The selector transistor SEL is configured to output the signal from amplifier transistor AMP to signal line VSL. The selector transistor SEL can control the timing of the signal output of pixel P. The selector transistor SEL is configured to output a signal based on the charge converted by photodiode PD. Note that the selector transistor SEL can be positioned between the power supply line to which the power supply voltage VDD is applied and the amplifier transistor AMP. Alternatively, the selector transistor SEL can be omitted if necessary.

[0085] The reset transistor RST is configured to reset the voltage of the floating diffusion FD. The reset transistor RST is electrically coupled to the power supply line supplying the power supply voltage VDD and is configured to reset the charge in pixel P. The reset transistor RST can reset the charge accumulated in the floating diffusion FD and reset the voltage of the floating diffusion FD.

[0086] The transfer transistor TG, amplifier transistor AMP, selector transistor SEL, and reset transistor RST can each be a MOSFET, comprising a gate terminal, a source terminal, and a drain terminal. Figure 5 In the configuration example, the transfer transistor TG, amplifier transistor AMP, selector transistor SEL, and reset transistor RST each include an NMOS transistor. Note that the transfer transistor TG, amplifier transistor AMP, selector transistor SEL, and reset transistor RST may include PMOS transistors.

[0087] The first semiconductor layer 110 and the second semiconductor layer 120 include a semiconductor substrate, such as a Si (silicon) substrate. Note that the first semiconductor layer 110 and the second semiconductor layer 120 may include an SOI (silicon-on-insulator) substrate, a SiGe (silicon-germanium) substrate, or other compound semiconductor materials, etc.

[0088] The insulating films (interlayer insulating films) of the first wiring layer 210 and the second wiring layer 220 include, for example, TEOS, silicon nitride (SiN), silicon oxide (SiO), etc. Furthermore, the insulating film of the first wiring layer 210 may include, for example, SiCN, SiCON, HfO2, Al2O3, or ZrO2. Note that the insulating films of the first wiring layer 210 and the second wiring layer 220 may include other insulating materials. The insulating films of the first wiring layer 210 and the second wiring layer 220 are also passivation films (protective films) of the thin-film transistors and are formed to cover the periphery of each thin-film transistor.

[0089] The first wiring layer 210 and the second wiring layer 220 can be wiring layers formed, for example, by BEOL (back-end process).

[0090] The first wiring layer 210 and the second wiring layer 220 include, for example, a conductive film and an insulating film, and include multiple wirings and vias (VIAs), interlayer insulating films, etc. The wirings of the first wiring layer 210 and the second wiring layer 220 include metallic materials such as aluminum (Al), copper (Cu), and tungsten (W). The wirings of the first wiring layer 210 may include other conductive materials. The interlayer insulating film includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc.

[0091] In the imaging apparatus 1 according to configuration example 1, a first switching transistor (first switching switch SW1N) and a second switching transistor (second switching switch SW1S) are provided in the first wiring layer 210. The first switching switch SW1N and the second switching switch SW1S may be thin-film transistors (TFTs).

[0092] like Figure 5As shown, the imaging apparatus 1 according to configuration example 1 further includes a coupling unit 200. The coupling unit 200 is disposed in the first wiring layer 210. The coupling unit 200 is coupled to the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S. Thus, the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S are jointly coupled to the AD converter 40 of the signal processor 112 through the coupling unit 200.

[0093] like Figure 6 As shown, the first switching switch SW1N includes an electrode (drain or source) 71a, an electrode (source or drain) 71b, a semiconductor region 71c, a gate electrode 71g, and a gate insulating film 71i.

[0094] like Figure 6 As shown, the second switching switch SW1S includes an electrode (drain or source) 72a, an electrode (source or drain) 72b, a semiconductor region 72c, a gate electrode 72g, and a gate insulating film 72i.

[0095] Semiconductor region 71c and semiconductor region 72c are each regions that form a channel (channel region). Semiconductor region 71c and semiconductor region 72c each include, for example, two-dimensional materials (MoS2, WS2, MoSe2, WSe2, HfS2, etc.) or oxide semiconductors (InGaZnO, InZnO, ZnO, SnO, TiO2, etc.).

[0096] Note that semiconductor region 71c and semiconductor region 72c can each include organic semiconductors (fullerene, pentacene, ruberene, etc.), carbon nanotubes, hydrogenated amorphous silicon, low-temperature polycrystalline silicon, etc. as channel materials.

[0097] Electrodes 71a, 71b, 72a, and 72b each comprise a metallic material such as copper (Cu), tungsten (W), ruthenium (Ru), or cobalt (Co). Note that electrodes 71a, 71b, 72a, and 72b may comprise other conductive materials. Electrodes 71a, 71b, 72a, and 72b may comprise low-resistance conductive materials.

[0098] Gate insulating films 71i and 72i each comprise, for example, silicon oxide (SiO) and silicon nitride (SiN). Furthermore, gate insulating films 71i and 72i each comprise insulating materials such as Al₂O₃, HfO₂, ZrO₂, LaO₂, HfSiO, Y₂O₃, or SiON. Note that gate insulating films 71i and 72i may include other insulating materials.

[0099] Gate electrode 71g and gate electrode 72g each comprise, for example, metallic materials such as Au, Pt, Cu, Ti, W, Pd, TiN, TaN, TiAl, Bi, In, Al, Sc, Co, Mo, etc. Gate electrode 71g and gate electrode 72g may also comprise other conductive materials.

[0100] Notice, Figure 6 The configurations shown, such as the positions of the first switching transistor (first switching switch SW1N) and the second switching transistor (second switching switch SW1S), are examples, and other configurations may be used.

[0101] <Configuration Example 2>

[0102] Figure 7 This is a schematic diagram illustrating a configuration example 2 of the imaging apparatus 1 according to this embodiment.

[0103] The imaging apparatus 1 according to configuration example 2 differs from configuration example 1 in the location of the coupling unit 200. In the imaging apparatus 1 according to configuration example 2, the coupling unit 200 is disposed in the second wiring layer 220. That is, in the imaging apparatus 1 according to configuration example 2, the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S are connected to each other in the second wiring layer 220. Thus, the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S are coupled together to the AD converter 40 of the signal processor 112 through the coupling unit 200.

[0104] Other configurations can be basically similar to those in Configuration Example 1.

[0105] <Configuration Example 3>

[0106] Figure 8 This is a schematic diagram illustrating a configuration example 3 of the imaging apparatus 1 according to this embodiment. Figure 9 This is a schematic cross-sectional view showing a configuration example 3 of the imaging apparatus 1 according to this embodiment.

[0107] In addition to Configuration Example 1, the imaging apparatus 1 according to Configuration Example 3 also includes a third segmented signal line VSL2N and a fourth segmented signal line VSL2S as signal lines VSL. The third segmented signal line VSL2N is configured in parallel with the first segmented signal line VSL1N. The fourth segmented signal line VSL2S is configured in parallel with the second segmented signal line VSL1S.

[0108] Signals from readout circuits 20 in at least one first pixel of the plurality of pixels P are output to the third segmentation signal line VSL2N. Signals from readout circuits 20 in at least one second pixel of the plurality of pixels P are output to the fourth segmentation signal line VSL2S.

[0109] In addition to configuration example 1, the imaging device 1 according to configuration example 3 also includes a third switching transistor (third switching switch SW2N) and a fourth switching transistor (fourth switching switch SW2S) as switching transistors.

[0110] The third switching switch SW2N includes a first coupling terminal and a second coupling terminal. The first coupling terminal of the third switching switch SW2N is coupled to the third segmented signal line VSL2N. The second coupling terminal of the third switching switch SW2N is coupled to the signal processor 112. The electrical coupling state between the third segmented signal line VSL2N and the signal processor 112 can be switched by the third switching switch SW2N.

[0111] The fourth switching switch SW2S includes a first coupling terminal and a second coupling terminal. The first coupling terminal of the fourth switching switch SW2S is coupled to the fourth segmented signal line VSL2S. The second coupling terminal of the fourth switching switch SW2S is coupled to the signal processor 112. The electrical coupling state between the fourth segmented signal line VSL2S and the signal processor 112 can be switched using the fourth switching switch SW2S.

[0112] Furthermore, the imaging device 1 according to configuration example 3 also includes a first adder transistor (first adder switch SWaN) and a second adder transistor (second adder switch SWaS).

[0113] The first adder switch SWaN is configured to switch the electrical coupling state between the first segmentation signal line VSL1N and the third segmentation signal line VSL2N, and to add multiple signals from multiple readout circuits 20 in multiple first pixels.

[0114] The second adder switch SWAS is configured to switch the electrical coupling state between the second segmentation signal line VSL1S and the fourth segmentation signal line VSL2S, and to add multiple signals from multiple readout circuits 20 in multiple second pixels.

[0115] Furthermore, the imaging apparatus 1 according to configuration example 3 includes a first coupling unit 201 and a second coupling unit 202 to replace the coupling unit 200 in configuration example 1.

[0116] The first coupling unit 201 is disposed in the first wiring layer 210. The first coupling unit 201 is coupled to the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S.

[0117] The second coupling unit 202 is disposed in the first wiring layer 210. The second coupling unit 202 is coupled to the second coupling terminal of the third switching switch SW2N and the second coupling terminal of the fourth switching switch SW2S.

[0118] In the imaging apparatus 1 according to configuration example 3, the second coupling terminal of the first switching switch SW1N and the second coupling terminal of the second switching switch SW1S are coupled together to the AD converter 40-1 of the signal processor 112 through the first coupling unit 201.

[0119] In addition, the second coupling terminal of the third switching switch SW2N and the second coupling terminal of the fourth switching switch SW2S are coupled together to the AD converter 40-2 of the signal processor 112 through the second coupling unit 202.

[0120] Notice, Figure 8 An example of a configuration is shown in which the first switching switch SW1N, the third switching switch SW2N, the first adder switch SWAN, the second switching switch SW1S, the fourth switching switch SW2S, the second adder switch SWAS, the first coupling unit 201 and the second coupling unit 202 are all located in the first wiring layer 210, but some or all of them may be located in the second wiring layer 220.

[0121] like Figure 9 As shown, similar to the first switching switch SW1N, the third switching switch SW2N may include an electrode (drain electrode or source electrode) 71a, an electrode (source electrode or drain electrode) 71b, a semiconductor region 71c, a gate electrode 71g, and a gate insulating film 71i.

[0122] Similar to the second switching switch SW1S, the fourth switching switch SW2S may include an electrode (drain electrode or source electrode) 72a, an electrode (source electrode or drain electrode) 72b, a semiconductor region 72c, a gate electrode 72g, and a gate insulating film 72i.

[0123] like Figure 9 As shown, the first adder switch SWaN and the second adder switch SWaS may include an electrode (drain electrode or source electrode) 73a, an electrode (source electrode or drain electrode) 73b, a semiconductor region 73c, a gate electrode 73g, and a gate insulating film 73i.

[0124] In the imaging apparatus 1 according to configuration example 3, the operation of adding the signal from the first segmentation signal line VSL1N to the signal from the third segmentation signal line VSL2N can be provided by the first adder switch SWaN.

[0125] Furthermore, the second adder switch SWaS can provide the operation of adding the signal from the second segment signal line VSL1S to the signal from the fourth segment signal line VSL2S.

[0126] Other configurations can be basically similar to those in Example 1 above.

[0127] <Configuration Example 4>

[0128] Figure 10 This is a schematic diagram illustrating a configuration example 4 of the imaging apparatus 1 according to this embodiment.

[0129] The imaging apparatus 1 according to configuration example 4 has a configuration in which the first coupling unit 201 and the second coupling unit 202 are omitted from configuration example 3.

[0130] In the imaging apparatus 1 according to configuration example 4, the second coupling terminal of the first switching switch SW1N is coupled to the AD converter 40-1N of the signal processor 112.

[0131] In addition, the second coupling terminal of the second switching switch SW1S is coupled to the AD converter 40-1S of the signal processor 112.

[0132] In addition, the second coupling terminal of the third switching switch SW2N is coupled to the AD converter 40-2N ​​of the signal processor 112.

[0133] In addition, the second coupling terminal of the fourth switching switch SW2S is coupled to the AD converter 40-2S of the signal processor 112.

[0134] Other configurations can be basically similar to those in Example 3 above.

[0135] <Configuration Example 5>

[0136] Figure 11 This is a schematic diagram illustrating a configuration example 5 of the imaging apparatus 1 according to this embodiment. Figure 12 This is a schematic cross-sectional view showing a configuration example 5 of the imaging apparatus 1 according to this embodiment.

[0137] The imaging device 1 according to configuration example 5 has a different configuration from configuration example 1 described above, wherein the first switching switch SW1N, the second switching switch SW1S and the coupling unit 200 are all disposed in the second wiring layer 220.

[0138] Other configurations can be basically similar to those in Example 1 above.

[0139] <Configuration Example 6>

[0140] Figure 13 This is a schematic diagram illustrating a configuration example 6 of the imaging apparatus 1 according to this embodiment.

[0141] The imaging device 1 according to configuration example 6 has a different configuration from configuration example 4 above, wherein the first switching switch SW1N, the third switching switch SW2N, the first adder switch SWAN, the second switching switch SW1S, the fourth switching switch SW2S, and the second adder switch SWAS are all disposed in the second wiring layer 220.

[0142] Other configurations can be basically similar to those in Example 4 above.

[0143] <Variation Example>

[0144] In the above configuration examples, the first substrate 101 may have a configuration including two substrates. For example, the photodiode PD, the transmission transistor TG, and the floating diffuser FD in each pixel P may be formed on one of the two substrates, and other components of the readout circuit 20 may be formed on the other of the two substrates.

[0145] <1.3 Effects>

[0146] As described above, according to the imaging apparatus 1, which is a detection device according to this embodiment, at least one transistor is disposed between the readout circuit 20 in the first substrate 101 and the signal processor 112 in the second substrate 102. This transistor is disposed in at least one of the first wiring layer 210 of the first substrate 101 and the second wiring layer 220 of the second substrate 102. This reduces wiring redundancy, thereby facilitating miniaturization and accelerating signal readout.

[0147] According to the imaging apparatus 1, which is a detection device according to this embodiment, a configuration is provided in which switching transistors can be disposed in at least one of the first wiring layer 210 and the second wiring layer 220. This allows signals output from different signal lines to be synthesized without providing a synthesis circuit on the circuit board (second board 102). This facilitates miniaturization of the circuit board and increases the freedom of floor planning. Furthermore, the reduction of wiring redundancy leads to a reduction in wiring load and an acceleration of signal processing. As a result, the effect of reducing power consumption is also achieved.

[0148] Note that the effects described herein are illustrative rather than limiting. Other effects may exist. This also applies to the effects of other embodiments described below.

[0149] <2. Examples of applications for moving bodies>

[0150] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented in the form of a device mounted on any kind of mobile body. Examples of mobile bodies include automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, and robots.

[0151] Figure 14 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0152] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 14 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0153] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 acts as a control device to control: drive force generating equipment for generating the vehicle's driving force, such as an internal combustion engine or drive motor; drive force transmission mechanism for transmitting the driving force to the wheels; steering mechanism for adjusting the vehicle's steering angle; and braking equipment for generating the vehicle's braking force.

[0154] The body system control unit 12020 controls the operation of various types of equipment installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device to control the following: keyless entry system, smart key system, power window devices, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from mobile devices that replace the key as input. The body system control unit 12020 receives these input radio waves or signals to control the vehicle's door locking devices, power window devices, lights, etc.

[0155] The exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to an imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing for detecting objects (such as people, vehicles, obstacles, signs, symbols, etc. on the road) or processing for the distance of the detected objects.

[0156] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0157] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 can be connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 may include, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or the driver's level of concentration, or it can determine whether the driver is dozing off.

[0158] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation for the vehicle, distance-based following, speed-maintaining driving, vehicle collision warning, lane departure warning, etc.

[0159] Furthermore, the microcomputer 12051 can control the drive force generation device, steering mechanism, and braking device based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing coordinated control intended for automatic driving that does not depend on the driver's operation.

[0160] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights from high beam to low beam based on the position of the vehicle ahead or oncoming vehicle detected by the external information detection unit 12030, thereby performing coordinated control aimed at preventing glare by controlling the headlights.

[0161] The sound / image output unit 12052 transmits at least one of sound and image output signals to an output device capable of visually or audibly notifying passengers of the vehicle or the outside of the vehicle. Figure 14 In this example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0162] Figure 15 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0163] exist Figure 15 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0164] Imaging units 12101, 12102, 12103, 12104, and 12105 can be arranged at the front nose, side mirrors, rear bumper, rear door, and upper part of the windshield inside the vehicle 12100. Imaging unit 12101 at the front nose and imaging unit 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 at the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0165] Incidentally, Figure 15 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above can be obtained.

[0166] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0167] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111-12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101-12104, and thereby extract the nearest three-dimensional object as the vehicle ahead, which specifically exists on the driving path of the vehicle 12100 and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset the following distance to be maintained from the vehicle ahead and execute automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform cooperative control intended for automatic driving and the like, independent of driver operation.

[0168] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101-12104, and extract the classified three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 can distinguish whether obstacles around vehicle 12100 are obstacles that the driver of vehicle 12100 can visually recognize, or obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collision.

[0169] At least one of the imaging units 12101-12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101-12104. This pedestrian identification is performed, for example, by a program that extracts characteristic points from the image captured by the imaging units 12101-12104, which are infrared cameras, and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of characteristic points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101-12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian to emphasize the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0170] The foregoing describes examples of vehicle control systems to which the technology of this disclosure is applicable. Based on the configuration described above, the technology of this disclosure can be applied to imaging unit 12031, driver state detection unit 12041, and imaging units 12101, 12102, 12103, 12104, and 12105.

[0171] <3. Other Implementation Methods>

[0172] The technology described herein is not limited to the embodiments described above, and various modifications can be made.

[0173] For example, this technology can have the following configuration.

[0174] According to the present technology, at least one transistor is disposed between a readout circuit in a first substrate and a signal processor in a second substrate. The transistor is disposed in at least one of a first wiring layer of the first substrate and a second wiring layer of the second substrate. Therefore, a photodetector that enables reduced wiring redundancy can be provided, thereby facilitating miniaturization and accelerated signal readout.

[0175] <1>

[0176] A light detection device, comprising: A first substrate includes a photoelectric conversion element and a readout circuit, wherein the photoelectric conversion element performs photoelectric conversion on light, and the readout circuit is configured to output a signal based on the charge photoelectrically converted in the photoelectric conversion element; A second substrate, stacked on the first substrate and including a signal processor configured to perform signal processing on a signal output from the readout circuit; and At least one transistor is disposed between the readout circuit and the signal processor. The first substrate includes a first semiconductor layer and a first wiring layer. The second substrate includes a second semiconductor layer and a second wiring layer, and The transistor is disposed in at least one of the first wiring layer and the second wiring layer.

[0177] <2>

[0178] According to the above <1> The optical detection device, wherein, The transistor includes a switching transistor configured to switch the electrical coupling state between the readout circuit and the signal processor.

[0179] <3>

[0180] According to the above <1> or <2> The optical detection device, wherein, The first substrate includes a plurality of pixels, and each pixel includes the photoelectric conversion element and the readout circuit. The first substrate further includes signal lines, to which signals from the readout circuit of each of the plurality of pixels are output, and The transistor includes a switching transistor configured to switch the electrical coupling state between the signal line and the signal processor.

[0181] <4>

[0182] According to the above <3> The optical detection device, wherein, The signal line includes: A first segmentation signal line, wherein a signal from the readout circuit of at least one of the plurality of pixels is output to the first segmentation signal line, and The second segmentation signal line receives a signal from the readout circuit in at least one of the plurality of pixels. The switching transistor includes: A first switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the first segmented signal line, and the second coupling terminal being coupled to the signal processor. The first switching transistor is configured to switch the electrical coupling state between the first segmented signal line and the signal processor. The second switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the second segmented signal line and the second coupling terminal being coupled to the signal processor, and the second switching transistor is configured to switch the electrical coupling state between the second segmented signal line and the signal processor.

[0183] <5>

[0184] According to the above <4> The optical detection device further includes: a coupling unit, wherein the coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to a second coupling terminal of the first switching transistor and a second coupling terminal of the second switching transistor, wherein... The second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor are coupled to the signal processor through the coupling unit.

[0185] <6>

[0186] According to the above <4> The optical detection device, wherein, The signal line also includes: The third segmentation signal line, from the readout circuit of at least one of the plurality of pixels in the first pixel, is output to the third segmentation signal line, and The fourth segmentation signal line receives signals from the readout circuit in at least one of the second pixels among the plurality of pixels. The switching transistor further includes: A third switching transistor, comprising a first coupling terminal and a second coupling terminal, wherein the first coupling terminal is coupled to the third segmented signal line and the second coupling terminal is coupled to the signal processor, the third switching transistor being configured to switch the electrical coupling state between the third segmented signal line and the signal processor, and A fourth switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the fourth segmented signal line and the second coupling terminal being coupled to the signal processor, the fourth switching transistor being configured to switch the electrical coupling state between the fourth segmented signal line and the signal processor.

[0187] <7>

[0188] According to the above <6> The optical detection device also includes: A first adder transistor is configured to switch the electrical coupling state between the first segmentation signal line and the third segmentation signal line, and is configured to add multiple signals from multiple readout circuits of multiple first pixels; and The second adder transistor is configured to switch the electrical coupling state between the second segmentation signal line and the fourth segmentation signal line, and is configured to add multiple signals from multiple readout circuits of multiple second pixels.

[0189] <8>

[0190] According to the above <6> or <7> The optical detection device also includes: A first coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to the second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor; and The second coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to the second coupling terminal of the third switching transistor and the second coupling terminal of the fourth switching transistor, wherein... The second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor are jointly coupled to the signal processor through the first coupling unit, and The second coupling terminal of the third switching transistor and the second coupling terminal of the fourth switching transistor are coupled to the signal processor through the second coupling unit.

[0191] <9>

[0192] According to the above <1> to <8> The light detection device of any one of the following, wherein, The signal processor includes at least one AD conversion circuit configured to convert a signal output from the readout circuit into a digital signal.

[0193] This application claims the benefit of Japanese priority patent application No. 2023-212393, filed with the Japan Patent Office on December 15, 2023, the entire contents of which are incorporated herein by reference.

[0194] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations can be made according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A light detection device, comprising: A first substrate includes a photoelectric conversion element and a readout circuit, wherein the photoelectric conversion element performs photoelectric conversion on light, and the readout circuit is configured to output a signal based on the charge photoelectrically converted in the photoelectric conversion element; A second substrate, stacked with the first substrate and including a signal processor, the signal processor being configured to perform signal processing on a signal output from the readout circuit; as well as At least one transistor is disposed between the readout circuit and the signal processor. The first substrate includes a first semiconductor layer and a first wiring layer. The second substrate includes a second semiconductor layer and a second wiring layer, and The transistor is disposed in at least one of the first wiring layer and the second wiring layer.

2. The optical detection device according to claim 1, wherein, The transistor includes a switching transistor configured to switch the electrical coupling state between the readout circuit and the signal processor.

3. The optical detection device according to claim 1, wherein, The first substrate includes a plurality of pixels, and each pixel includes the photoelectric conversion element and the readout circuit. The first substrate further includes signal lines, to which signals from the readout circuit of each of the plurality of pixels are output, and The transistor includes a switching transistor configured to switch the electrical coupling state between the signal line and the signal processor.

4. The optical detection device according to claim 3, wherein, The signal line includes: A first segmentation signal line, wherein a signal from the readout circuit of at least one of the plurality of pixels is output to the first segmentation signal line, and The second segmentation signal line receives a signal from the readout circuit in at least one of the plurality of pixels. The switching transistor includes: A first switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the first segmented signal line, and the second coupling terminal being coupled to the signal processor. The first switching transistor is configured to switch the electrical coupling state between the first segmented signal line and the signal processor. The second switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the second segmented signal line and the second coupling terminal being coupled to the signal processor, and the second switching transistor is configured to switch the electrical coupling state between the second segmented signal line and the signal processor.

5. The optical detection device according to claim 4, further comprising: A coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to the second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor, wherein... The second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor are coupled to the signal processor through the coupling unit.

6. The optical detection device according to claim 4, wherein, The signal line also includes: The third segmentation signal line, from the readout circuit of at least one of the plurality of pixels in the first pixel, is output to the third segmentation signal line, and The fourth segmentation signal line receives signals from the readout circuit in at least one of the second pixels among the plurality of pixels. The switching transistor further includes: A third switching transistor, comprising a first coupling terminal and a second coupling terminal, wherein the first coupling terminal is coupled to the third segmented signal line and the second coupling terminal is coupled to the signal processor, the third switching transistor being configured to switch the electrical coupling state between the third segmented signal line and the signal processor, and A fourth switching transistor includes a first coupling terminal and a second coupling terminal, the first coupling terminal being coupled to the fourth segmented signal line and the second coupling terminal being coupled to the signal processor, the fourth switching transistor being configured to switch the electrical coupling state between the fourth segmented signal line and the signal processor.

7. The optical detection device according to claim 6, further comprising: A first adder transistor is configured to switch the electrical coupling state between the first segmentation signal line and the third segmentation signal line, and is configured to add multiple signals from multiple readout circuits of multiple first pixels. as well as The second adder transistor is configured to switch the electrical coupling state between the second segmentation signal line and the fourth segmentation signal line, and is configured to add multiple signals from multiple readout circuits of multiple second pixels.

8. The optical detection device according to claim 6, further comprising: A first coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to the second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor; as well as The second coupling unit is disposed in either the first wiring layer or the second wiring layer, and is coupled to the second coupling terminal of the third switching transistor and the second coupling terminal of the fourth switching transistor, wherein... The second coupling terminal of the first switching transistor and the second coupling terminal of the second switching transistor are jointly coupled to the signal processor through the first coupling unit, and The second coupling terminal of the third switching transistor and the second coupling terminal of the fourth switching transistor are coupled to the signal processor through the second coupling unit.

9. The optical detection device according to claim 1, wherein, The signal processor includes at least one AD conversion circuit configured to convert a signal output from the readout circuit into a digital signal.

Images