A method for preparing high sheet resistance shallow pn junction monocrystalline silicon based on rapid boron diffusion

Abstract

This invention discloses a method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion, comprising the following steps: S1: depositing a boron-containing precursor on the textured silicon wafer surface; S2: depositing a low-temperature oxide layer on the surface of the boron-containing precursor; S3: placing the silicon wafer with the deposited low-temperature oxide layer in a rapid thermal processing device, rapidly heating it to 1050-1350℃ at a heating rate of 5-200℃ / s, holding it at this temperature for 20-600s, and then rapidly cooling it to complete the diffusion and activation of boron atoms in the silicon wafer. This invention employs a combination of low-temperature deposition and rapid boron diffusion, which can significantly shorten the boron diffusion time, reduce energy consumption, and shorten the high-temperature processing time. It also suppresses the formation of oxygen precipitate defects at the source, eliminating problems such as black cores and black rings in batteries, and significantly improving carrier lifetime and material electrical performance.

Description

Technical Field

[0001] This invention belongs to the field of monocrystalline silicon solar cell fabrication technology, and specifically relates to a method for preparing high sheet resistance shallow pn junction monocrystalline silicon wafers based on rapid boron diffusion. Background Technology

[0002] Czochralski-grown silicon single crystals are the core substrate material for current crystalline silicon photovoltaic cells. During crystal growth, the melting of the quartz crucible due to heat continuously introduces a large number of oxygen atoms into the silicon interior. These oxygen atoms gradually accumulate inside the crystal, forming tiny oxygen precipitate nuclei or interstitial oxygen atoms. Under the high-temperature, long-term heat treatment conditions of 1000-1100℃ commonly used in traditional boron diffusion processes, these oxygen precipitate nuclei grow rapidly, forming bulk defects with strong carrier recombination capabilities. This directly reduces the minority carrier lifetime of the silicon wafer, becoming a significant factor limiting the photoelectric conversion efficiency of the cell. For n-type high-efficiency cells, especially TOPCon cells, boron diffusion is a key step in the preparation of surface pn junctions. Traditional processes rely on high-temperature, long-term diffusion to fully propagate and activate boron atoms, which not only has the problem of high energy consumption but also further promotes the growth of oxygen precipitate-like bulk defects and deteriorates the electrical performance of the silicon wafer. Although the industry generally adopts hydrogen passivation technology to reduce the recombination of minority carriers by bulk defects, this method has limited effect on repairing oxygen precipitation-type bulk defects and cannot fundamentally solve the performance degradation problem of high oxygen silicon wafers during high-temperature diffusion. Therefore, suppressing the generation of bulk defects has become the core breakthrough for improving battery efficiency.

[0003] Boron atoms exist in the silicon lattice in two forms: interstitial sites and substitutional sites. Only boron atoms occupying lattice sites are electrically active, effectively providing charge carriers and exhibiting ideal pn junction characteristics. Interstitial boron is an electroactive impurity and does not contribute to conductivity. Traditional tubular boron diffusion is limited by diffusion kinetics, resulting in a low lattice occupancy rate of boron atoms. To achieve the target sheet resistance and junction depth, it is often necessary to significantly increase the total amount of boron incorporated. Excess boron atoms exacerbate silicon lattice distortion, increase the probability of crystal defects such as dislocations and stacking faults, further increase carrier recombination channels, and reduce the open-circuit voltage and short-circuit current of the battery. At the same time, the traditional boron diffusion process is accompanied by high-temperature oxidation, which significantly oxidizes and consumes the pyramid light-trapping structure formed on the silicon wafer surface through texturing. The textured surface morphology is destroyed, reflectivity increases, and light-trapping performance decreases, directly affecting the battery's absorption and utilization efficiency of incident light, further restricting the overall performance improvement of the battery.

[0004] Rapid thermal processing technology, with its ultra-fast heating rate, can instantly inject a large number of vacancies into silicon, providing a kinetic advantage for boron atom migration and lattice occupancy. This significantly shortens diffusion time and improves boron activation efficiency, offering a feasible path to overcome the shortcomings of traditional processes. However, existing rapid diffusion technologies have not yet formed a complete industrial-scale process system. They lack a synergistic design of low-temperature boron source deposition, low-temperature oxide layer protection, and rapid advancement, making it difficult to simultaneously achieve the comprehensive requirements of high sheet resistance, shallow junction depth, low bulk defect density, and high texture retention rate. As the photovoltaic industry continues to upgrade towards higher efficiency and lower cost, the shortcomings of traditional boron diffusion in bulk defect control, boron activation rate, texture protection, and energy consumption cost are becoming increasingly prominent. It can no longer meet the stringent material and process requirements of n-type high-efficiency cells. The industry urgently needs a new technology that can rapidly complete boron diffusion, inhibit oxygen precipitation from the source, protect the texture structure, and increase the proportion of boron activity, in order to break through existing process bottlenecks and promote the continuous optimization of the performance and cost of high-efficiency crystalline silicon cells.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion, thereby overcoming the defects in the prior art.

[0007] To achieve the above objectives, the present invention provides a method for preparing a high sheet resistance shallow pn junction single crystal silicon wafer based on rapid boron diffusion, comprising the following steps: S1: Deposit a boron-containing precursor on the textured silicon wafer surface; S2: Deposit a low-temperature oxide layer on the surface of the boron-containing precursor; S3: The silicon wafer with the low-temperature oxide layer deposited is placed in a rapid thermal processing device and rapidly heated to 1050~1350℃ at a heating rate of 5~200℃ / s, and held at this temperature for 20~600s, and then cooled down to complete the diffusion and activation of boron atoms in the silicon wafer.

[0008] Preferably, the silicon wafer is an n-type Czochralski single-crystal silicon wafer.

[0009] Preferably, in step S1, the precursor deposition is performed using atmospheric pressure chemical vapor deposition (APCVD) at a deposition temperature of 200-500℃ and a deposition time of 30-120s.

[0010] Preferably, in step S1, the precursor deposition is performed using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature of 800-900℃ and a deposition time of 600-800s.

[0011] Preferably, in step S1, the thickness of the boron-containing layer deposited by the precursor is 50-200 nm, and the boron atomic surface density concentration is 10. 19 ~10 22 atoms / cm 3 .

[0012] Preferably, in step S2, the low-temperature oxide layer is deposited at 200~500℃ using atmospheric pressure chemical vapor deposition (APCVD) with a deposition thickness of 100~200nm.

[0013] Preferably, the rapid heating process in step S3 is carried out under a protective atmosphere, which is oxygen, nitrogen, or argon, or a mixture thereof.

[0014] Preferably, step S3 employs a multi-cycle process, which involves repeatedly performing rapid heating, heat preservation, and cooling, with the number of cycles being 1 to 10.

[0015] Preferably, in step S3, the temperature is reduced to below 800°C before the product is removed from the furnace.

[0016] Compared with the prior art, one aspect of the present invention has the following beneficial effects: (1) The present invention adopts a low temperature deposition combined with a rapid boron diffusion process, which can significantly shorten the boron diffusion time and reduce energy consumption. The silicon wafer has a short high temperature residence time, which inhibits the generation of oxygen precipitate defects from the root, eliminates the black core and black ring problems of the battery, and greatly improves the carrier lifetime and material electrical performance. (2) The present invention deposits a low-temperature oxide layer on the surface of the boron-containing precursor to protect the textured structure, which greatly reduces the oxidation consumption of the pyramid textured surface and maintains excellent light trapping performance; at the same time, the rapid diffusion process improves the activation rate of boron atoms, reduces the total boron doping amount, reduces silicon lattice distortion and defects, and improves the quality of pn junction and photoelectric conversion efficiency. (3) This invention can relax the tolerance of oxygen content in silicon wafers, reduce the production cost of silicon wafers, and has strong process compatibility and is compatible with existing production lines; it can stably prepare high sheet resistance shallow pn junctions, comprehensively improve the efficiency and yield of n-type TOPCon cells, and has excellent industrialization value. Attached Figure Description

[0017] Figure 1 This is a PL image of a silicon wafer obtained in Embodiment 1 of the present invention; Figure 2 This is a PL image of the silicon wafer obtained in Comparative Example 1 of the present invention. Detailed Implementation

[0018] The specific embodiments of the present invention will be described in detail below, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0019] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components. Example 1

[0020] A method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion includes the following steps: S1: Take an n-type single crystal silicon wafer with a resistivity of 1~5Ω·cm and an oxygen content of 13.5ppma, and perform alkaline texturing to form a pyramid textured surface; The texturized silicon wafer is placed in an APCVD apparatus, and borane (B₂H₆), silane (SiH₄), and oxygen are introduced. Deposition is carried out at 400°C for 90 seconds to form a borosilicate glass (BSG) layer with a thickness of approximately 150 nm and a boron atom concentration of approximately 10⁻⁶. 21 atoms / cm 3 ; S2: An n-type silicon wafer with deposited BSG is subjected to APCVD at 450°C, with TEOS (tetraethoxysilane) and ozone introduced to deposit a low-temperature silicon oxide layer with a thickness of 120nm. S3: Transfer the silicon wafer to a rapid thermal processing furnace (RTP), introduce a nitrogen / oxygen mixture as a protective atmosphere, set the heating rate to 150℃ / s, heat to 1200℃, hold for 120s, and then cool down to 750℃ before removing from the furnace. The silicon wafer prepared in this embodiment has a sheet resistance of approximately 400 ohm / sq and a junction depth of 0.5 μm. Due to the use of rapid thermal treatment, the diffusion time is only 2 minutes, and the low-temperature oxide layer effectively protects the pyramid textured surface without obvious oxide rounding at the pyramid tips. The vacancies injected by rapid heating improve the boron activation rate and inhibit the growth of oxygen precipitation. Example 2

[0021] A method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion includes the following steps: S1: Take an n-type single crystal silicon wafer with a resistivity of 1~5Ω·cm and an oxygen content of 13.5ppma, and perform alkaline texturing to form a pyramid textured surface; The texturized silicon wafer is placed in an LPCVD apparatus, and boron trichloride (BCl3) and oxygen are introduced. Deposition is carried out at 800°C for 700 seconds to form a borosilicate glass (BSG) layer with a thickness of approximately 80 nm and a boron atom concentration of approximately 10. 21 atoms / cm 3 ; S2: Transfer the silicon wafer to APCVD, adjust the temperature to 450°C, introduce TEOS (tetraethoxysilane) and ozone, and deposit a low-temperature silicon oxide layer with a thickness of 100nm; S3: Transfer the silicon wafer to a rapid thermal processing furnace (RTP), introduce a nitrogen / oxygen mixture as a protective atmosphere, set the heating rate to 120℃ / s, heat to 1250℃, hold for 30s, and then cool down to 750℃ before removing from the furnace. Due to the extremely short time and high temperature, the boron atoms diffuse to a shallow depth, resulting in a silicon wafer with a sheet resistance of up to 500 ohms / sq and a junction depth of 0.4 μm. No obvious textured pyramid tip oxidation rounding phenomenon was observed. This structure effectively reduces surface recombination and is suitable for high-efficiency TOPCon cell structures. Example 3

[0022] Unlike Example 1, the S3 rapid boron expansion process uses a dual-cycle process. The silicon wafer is transferred to a rapid thermal processing furnace (RTP), nitrogen is introduced as a protective atmosphere, the heating rate is set to 150°C / s, the temperature is raised to 1200°C, held for 30s, and then cooled to 800°C; the temperature is then raised again to 1200°C (at a rate of 150°C / s), held for 60s, and then cooled to 750°C before being removed from the furnace.

[0023] Through a multi-cycle process, superior doping distribution control was achieved. Compared to a single high-temperature, short-time process, this method maintains a high activation rate while providing more precise junction depth control and a more uniform internal stress distribution in the silicon wafer. No obvious textured pyramid tip oxidation or rounding phenomenon was observed. The resulting silicon wafer has a sheet resistance of 450 ohms / sq and a junction depth of 0.35 μm. Example 4

[0024] A method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion includes the following steps: S1: Take an n-type single crystal silicon wafer with a resistivity of 1~5Ω·cm and an oxygen content of 13.5ppma, and perform alkaline texturing to form a pyramid textured surface; The texturized silicon wafer is placed in an LPCVD apparatus, and boron trichloride (BCl3) and oxygen are introduced. Deposition is carried out at 800°C for 800 seconds to form a borosilicate glass (BSG) layer with a thickness of approximately 120 nm and a boron atom concentration of approximately 10. 21 atoms / cm 3 ; S2: Transfer the silicon wafer to a rapid thermal processing furnace (RTP), introduce a nitrogen / oxygen mixture as a protective atmosphere, set the heating rate to 160℃ / s, heat to 1250℃, hold for 30s, and then cool down to 750℃ before removing from the furnace. This embodiment omits the step of depositing a low-temperature oxide layer for protection, resulting in slight oxidation of the textured surface. However, thanks to the high-quality precursor deposited by LPCVD and the long advance time, good sheet resistance uniformity is still achieved. The resulting silicon wafer has a sheet resistance of 500 ohm / sq and a junction depth of 0.4 μm. No obvious oxidation and rounding phenomenon is observed at the tip of the textured pyramid, indicating that the core "rapid advance" of this invention has a certain degree of adaptability under different deposition source conditions.

[0025] Comparative Example 1: S1: Take an n-type single crystal silicon sample with an oxygen content of 13.5 ppma, perform alkaline texturing to form a pyramid textured surface; The texturized silicon wafer is placed in an LPCVD apparatus, and boron trichloride (BCl3) and oxygen are introduced. Deposition is carried out at 850°C for 700 seconds to form a borosilicate glass (BSG) layer with a thickness of approximately 120 nm and a boron atom concentration of approximately 10. 21 atoms / cm 3 ; S2: The silicon wafer was slowly heated to 1050℃ in an LPCVD equipment and boron propagation was performed in a nitrogen / oxygen mixed atmosphere for 4500s. The resulting silicon wafer had a sheet resistance of 400 ohm / sq and a junction depth of 0.5μm. PL detection revealed defects such as "black rings" and "black cores" on the silicon wafer. At the same time, the absolute value of the textured surface reflectance of this group of samples was found to be about 1.5% higher than that of the RTP fast boron propagation group, indicating a decrease in light trapping performance.

[0026] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion, characterized in that, Includes the following steps: S1: Deposit a boron-containing precursor on the textured silicon wafer surface; S2: Deposit a low-temperature oxide layer on the surface of the boron-containing precursor; S3: The silicon wafer with the low-temperature oxide layer deposited is placed in a rapid thermal processing device and rapidly heated to 1050~1350℃ at a heating rate of 5~200℃ / s, and held at this temperature for 20~600s, and then cooled down to complete the diffusion and activation of boron atoms in the silicon wafer.

2. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, The silicon wafer is an n-type Czochralski single-crystal silicon wafer.

3. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, In step S1, the precursor deposition is performed using atmospheric pressure chemical vapor deposition (APCVD) at a deposition temperature of 200-500℃ and a deposition time of 30-120s.

4. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, In step S1, the precursor deposition adopts the low-pressure chemical vapor deposition (LPCVD) method, with a deposition temperature of 800~900℃ and a deposition time of 600~800s.

5. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, In step S1, the boron-containing layer deposited by the precursor has a thickness of 50-200 nm and a boron atom concentration of 10. 19 ~10 22 atoms / cm 3 .

6. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, In step S2, the low-temperature oxide layer is deposited at 200-500℃ using atmospheric pressure chemical vapor deposition (APCVD) with a thickness of 100-200 nm.

7. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, The rapid heating process in step S3 is carried out under a protective atmosphere, which is oxygen, nitrogen, or argon.

8. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, Step S3 employs a multi-cycle process, which involves repeatedly performing rapid heating, heat preservation, and cooling, with the number of cycles ranging from 1 to 10.

9. The method for preparing high sheet resistance shallow pn junction single crystal silicon wafers based on rapid boron diffusion according to claim 1, characterized in that, In step S3, the temperature is lowered to below 800°C before the product is removed from the furnace.

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