A data processing method and related apparatus

Abstract

This application discloses a data processing method and related apparatus. The method includes: obtaining a first request for requesting a first memory space; configuring a second memory space based on the first request, the second memory space including a first region and a second region, the first region being a simulated memory space of the first memory space, the access permissions of memory addresses in the first region being accessible, and the access permissions of memory addresses in the second region being inaccessible; obtaining a second request for accessing the first region; and determining that the second request has encountered an error if the access permissions of the memory addresses indicated by the second request are inaccessible. In this way, when the program requests memory space, an additional segment of memory space is allocated as a protected area, whose access permissions differ from those of a normally requested memory space, which helps to detect corresponding memory errors when the program accesses memory.

Description

Technical Field

[0001] This application relates to the field of computers, and more particularly to a data processing method and related apparatus. Background Technology

[0002] A bare-metal scenario typically refers to an environment where programs or systems run directly on the hardware, without operating system support or with only very limited operating system services. Due to its characteristics of low latency, high efficiency, and direct hardware access, bare-metal scenarios are widely used in embedded systems, IoT devices, and high-performance computing.

[0003] However, in this environment, due to the lack of operating system memory management and protection mechanisms, program memory issues become particularly prominent. Therefore, how to detect memory allocation problems in program code has become a pressing technical challenge. Summary of the Invention

[0004] This application provides a data processing method and related apparatus for detecting how memory is allocated in program code in a bare-core scenario.

[0005] In a first aspect, embodiments of this application provide a data processing method. This method is executed by a data processing device, or by a component (e.g., a processor, chip, or chip system) within the data processing device, or by a logic module or software capable of implementing all or part of the functions of the data processing device. The method involves executing the program code to be tested in a test environment simulating a bare-core scenario. The test environment deploys the data processing device, which provides the memory environment required to execute the program code. The data processing device serves as a detection plugin or application within this test environment. In this first aspect and its possible implementations, the method is described using the execution of the data processing device as an example. The method includes:

[0006] Obtain a first request, which is used to request a first memory space; based on the first request, configure a second memory space, which includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state; obtain a second request, which is used to access the first region; if the access permissions of the memory addresses indicated by the second request are in an inaccessible state, determine that an error has occurred in the second request.

[0007] In one possible implementation, the test environment is built on a quick emulator (QEMU) capable of simulating various hardware platforms, including but not limited to chips. QEMU provides the program code with a simulated chip memory environment.

[0008] Specifically, the system detects all memory-related operation requests within the program, including key aspects such as memory allocation, access, and deallocation. When the system receives a memory request, it doesn't directly allocate memory according to the original request. Instead, it allocates an additional memory space beyond the original request, designating it as a protected area (or restricted area, or poisoned area). The memory addresses within this protected area are inaccessible, preventing other processes from requesting memory in that region. During program execution, when a memory access request is detected, the target address (i.e., the location pointed to by the pointer) is checked. If the access permission status of that address is detected as inaccessible, it's determined to be an illegal memory access—either an out-of-bounds access (or memory overflow) or access to already deallocated memory—allowing for rapid problem localization and reporting.

[0009] In one possible implementation, obtaining the first request includes:

[0010] Once the first request is detected in the process, the first request is intercepted.

[0011] In this application, when the test system starts, it first registers a series of event callbacks related to memory processing. When the program code is executed, if the previously registered event is detected to be triggered in the process, the event is intercepted and the corresponding callback method of the event is executed.

[0012] For example, the test system registers a memory allocation event when it starts up. When memory is requested, the memory allocation function in the program code is executed. The memory allocation function may include at least one of the functions malloc, calloc, realloc, vmalloc, and get_free_page, etc., and this embodiment of the application is not limited to this.

[0013] In one possible implementation, the first request includes a first byte length, which is the memory size of the first memory space;

[0014] Based on the first request, configure a second memory space, including:

[0015] The length of the second byte is determined based on the length of the first byte;

[0016] Configure a first region and a second region based on the length of the first byte and the length of the second byte. The memory size of the first region is the length of the first byte, and the memory size of the second region is the length of the second byte.

[0017] Optionally, after allocating the first region, the start and end memory addresses of the first region can be obtained. Based on these start and end memory addresses and the length of the second byte, the second region can then be allocated.

[0018] In one possible implementation, the memory address of the second region is adjacent to the memory address of the first region.

[0019] In one possible implementation, the second region includes a first sub-region and a second sub-region, with the memory address of the first region falling between the memory addresses of the first sub-region and the second sub-region.

[0020] When the memory address of the second region is adjacent to the memory address of the first region, memory fragmentation can be reduced. The first and second sub-regions can serve as the front and back protections of the first region, respectively, which helps to detect data overflow during the writing or reading process.

[0021] In one possible implementation, the access status of the memory address indicated by the second request is determined based on the value of the shadow memory mapped to the memory address.

[0022] For example, the address returned by the Malloc function is typically at least 8 bytes aligned. A shadow memory value is used to record information at the memory address, which is 8 bytes long.

[0023] The value of shadow memory can represent the following states:

[0024] When the value is 0, it means that all 8 bytes are addressable (accessible).

[0025] When the value is k (1≤k≤7), it means that the first k bytes are addressable, and the last 8-k bytes are not addressable (inaccessible).

[0026] When the value is negative (e.g., -1), it means that none of the 8 bytes are addressable.

[0027] Based on this, according to the value mapped to the shadow memory, the first region can be marked as "accessible" or "allocated", and the second region can be marked as "inaccessible" or "special state".

[0028] In one possible implementation, the method further includes:

[0029] Obtain first instruction information, which is used to instruct the first process to terminate. The first process is the process that handles the first request.

[0030] Based on the first instruction information, check whether the memory address of the first region has been released;

[0031] If the memory address of the first region is not freed, a first memory error message is determined.

[0032] The triggering event for obtaining this first indication information could be a process termination event bound to QEMU, or a memory leak detection event bound to QEMU upon exit. If the memory space allocated during the process's execution is not properly released upon process termination, it indicates a memory leak problem.

[0033] Secondly, embodiments of this application provide a data processing apparatus, the apparatus comprising:

[0034] The event handling module is used to handle memory events during system operation. Memory events are determined based on memory processing requests in the process. Memory processing requests include a first request and a second request. The first request is used to request a first memory space, and the second request is used to access the first memory space.

[0035] The request processing module is used to configure a second memory space based on the first request. The second memory space includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state.

[0036] The request processing module is also used to access the memory address indicated by the second request based on the second request;

[0037] The verification module is used to verify the access permissions of the memory address indicated by the second request. If the access permissions of the memory address indicated by the second request are inaccessible, it is determined that the second request has encountered an error.

[0038] In one possible implementation, the first request includes a first byte length, which is the memory size of the first memory space;

[0039] The request processing module is specifically used to determine the length of the second byte based on the length of the first byte.

[0040] Configure a first region and a second region based on the length of the first byte and the length of the second byte. The memory size of the first region is the length of the first byte, and the memory size of the second region is the length of the second byte.

[0041] In one possible implementation, the request processing module includes an address translation module, a memory allocation module, a memory safety module, and an alarm module. The address translation module is used to translate virtual memory addresses into physical memory addresses, the memory allocation module is used to configure the memory space of the first region, the memory safety module is used to configure the memory space of the second region, and the alarm module is used to output error information.

[0042] In one possible implementation, the memory address of the second region is adjacent to the memory address of the first region.

[0043] In one possible implementation, the second region includes a first sub-region and a second sub-region, with the memory address of the first region falling between the memory addresses of the first sub-region and the second sub-region.

[0044] In one possible implementation, the access status of the memory address indicated by the second request is determined based on the value of the shadow memory mapped to the memory address.

[0045] In one possible implementation, the device further includes:

[0046] The exit module is used to obtain the first indication information, which is used to indicate the termination of the first process, which is the process that processed the first request.

[0047] The verification module is also used to detect whether the memory address of the first region has been released based on the first indication information;

[0048] If the memory address of the first region is not freed, a first memory error message is determined.

[0049] Thirdly, embodiments of this application provide a computing device, including: a processor, a memory, and a transceiver. The memory stores computer programs or computer instructions, and the processor is used to call and run the computer programs or computer instructions stored in the memory, causing the processor to perform processing operations as described in the first aspect and any implementation thereof. The transceiver is used to transmit and receive signals, such as implementing the receiving and sending operations as described in the first aspect and any implementation thereof.

[0050] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0051] Fifthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0052] Sixthly, this application provides a chip system including a processor for supporting an electronic device in performing the functions involved in the foregoing aspects, such as transmitting or processing data or information involved in the foregoing methods. In one possible design, the chip system further includes a memory for storing necessary program instructions and data of the electronic device. The chip system may be composed of chips or may include chips and other discrete devices.

[0053] The technical effects of the second, third, fourth, fifth, and sixth aspects of this application can be understood in conjunction with the technical effects of the first aspect and any implementation thereof. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0056] Figure 2 This is a schematic diagram of shadow memory;

[0057] Figure 3 This is a schematic flowchart of a data processing method provided in an embodiment of this application;

[0058] Figure 4 A schematic diagram of a protected area provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram illustrating the shadow memory value retrieval provided in an embodiment of this application;

[0060] Figure 6 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application;

[0061] Figure 7 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0062] Figure 8 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0065] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a testing system, such as... Figure 1 As shown, the test system includes simulated memory and a data processing device 100. The data processing device 100 includes an acquisition module 101 and a processing module 102. The data processing device 100 is deployed in the test system and interacts with the memory environment provided by the test system to acquire memory information. In one possible implementation, the test system can be the fast simulator QEMU, and the memory environment can be the simulated memory provided by QEMU.

[0066] The testing system can provide a client 201 to the outside world, so that users 200 (such as designers) can interact with the client 201. The client 201 can be, for example, a web browser provided by the testing system; or, it can be an application running on a user's terminal.

[0067] User 200 can use client 201 to initiate a program testing request to the testing system for the object under test. The object under test can be, for example, an application deployed on a chip, or a system, device, or component connected to a network. In this embodiment, the specific implementation of the object under test is not limited. In practice, user 200 generates test instructions for the object under test through client 201. After receiving these test instructions, the testing system tests the program under test. Acquisition module 101 is responsible for capturing memory-related functions in the program under test, and processing module 102 processes these functions and applies the processing results to the memory environment to obtain the generated relevant information. Based on this information, a test report is generated. Finally, the test report is displayed to user 200 through client 201.

[0068] In one possible implementation, the data processing device 100 further includes an output module (not shown) for outputting the generated detection report to the client 201.

[0069] It is worth noting that, Figure 1 The specific structure of the data processing device 100 shown is only one implementation example. In other possible implementations, the data processing device 100 may include more functional modules to support the data processing device in performing more other functions; or, the functional division of the various modules in the data processing device 100 is not limited to Figure 1 As shown in the example, multiple modules of the data processing device 100 can be merged into one module, or some modules in the data processing device 100 can be split into multiple modules. This embodiment does not limit the specific structure of the data processing device to... Figure 1 Example shown.

[0070] As examples, the data processing device 100 can be deployed in the cloud to provide cloud services for program testing to users; in this case, the data processing device 100 may be implemented by a computing device in the cloud, for example. Alternatively, the data processing device 100 can be deployed locally to provide local program testing services to users.

[0071] In practical applications, the aforementioned data processing device 100 can be implemented through software or through hardware.

[0072] Data processing device 100, as an example of a software functional unit, may include code running on a computing instance. The computing instance may include at least one of a host, a virtual machine, and a container. Further, the aforementioned computing instance may be one or more. For example, data processing device 100 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0073] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0074] As an example of a hardware functional unit, the data processing device 100 may include a computing device, such as a server. Alternatively, the data processing device 100 may be implemented using a central processing unit (CPU), an application-specific integrated circuit (ASIC), or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a neural network processing unit (NPU), a system-on-chip (SoC), an offload card, an accelerator card, or any combination thereof.

[0075] First, some terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0076] (1) Shadow memory, also known as shadow storage or mapped memory, is mainly used to allocate a corresponding "shadow" memory space for each block of actual memory in an application to track and detect memory access errors. In practice, memory is usually aligned to 8 bytes (depending on the specific system and memory allocator). For each 8-byte block of actual memory, there is a corresponding byte in the shadow memory to record its status.

[0077] Please see Figure 2 , Figure 2 This is a diagram illustrating shadow memory within the entire memory space. Shadow memory is additional memory set up to manage the allocation and use of regular memory; it is invisible to the program being monitored. In memory management, a mapping algorithm is typically used to map regular memory addresses to shadow memory addresses (the shadow area). The addresses of shadow memory itself cannot be accessed by the program as regular memory; through mapping, they fall into bad areas (or inaccessible regions), and accessing them will result in an error.

[0078] (2) Quick Emulator (QEMU): This is a virtualization software whose main function is to simulate different hardware platforms and operating systems, such as Linux, Windows, macOS, and FreeBSD. QEMU's hardware emulation function allows users to create a virtual machine environment on different hardware architectures and detect memory problems.

[0079] (3) Simulated memory space: This is a virtual memory environment constructed by software to simulate the behavior and characteristics of actual physical memory. It allows programs to run in a simulated memory environment, thereby enabling the simulation and testing of memory operations.

[0080] (4) Out-of-bounds access: This is a common program memory problem, which refers to a program attempting to access data beyond its allocated memory space. Specifically, when a program requests a block of memory from the system, and then uses that memory beyond the requested range, an out-of-bounds memory access occurs.

[0081] For example, process 1 is allocated memory space from address 1 to 10, while process 2 is allocated memory space from address 11 to 20. If process 1 experiences a memory access out of bounds during execution, its access pointer might incorrectly point to the memory region of process 2 (i.e., addresses 11 to 20), resulting in the reading or modification of process 2's stored data. This data is invalid or undefined for process 1, and could therefore lead to program exceptions, data corruption, or even system crashes.

[0082] In bare-core scenarios, programs or systems typically run directly on the hardware, especially on bare-core chips without an operating system. In this environment, program code can directly access the chip's registers during execution. However, due to the lack of operating system memory management and protection mechanisms, programs are more prone to memory problems during runtime. These problems may include memory leaks, illegal access, and out-of-bounds access, which not only reduce system stability and reliability but can also lead to serious consequences such as hardware damage or data loss.

[0083] Therefore, effectively detecting memory problems in program code has become a pressing technical challenge in bare-core environments. Currently, static analysis tools are commonly used to identify potential memory vulnerabilities by analyzing the program code structure, variable scope, and memory allocation. However, these tools struggle to detect problems during dynamic program execution and cannot comprehensively cover all possible memory errors.

[0084] Based on this, this application provides a data processing method, such as... Figure 3 As shown, the data processing method provided in this application embodiment includes the following steps 301-304. This method can be applied to the above... Figure 1 The data processing apparatus 100 shown may also be applied to other suitable apparatuses. The following describes an application... Figure 1 The data processing device 100 shown is used as an example for explanation.

[0085] In one possible implementation, the test system deployed with the data processing device 100 is QEMU, and the client 201 runs QEMU to simulate a chip environment that includes custom simulation memory.

[0086] 301. Obtain the first request. The first request is used to request the first memory space.

[0087] In this application, the first request refers to any instruction in the program code to be tested that needs to request memory space from an electronic device.

[0088] When QEMU starts, it registers a series of event callbacks, including initialization events, jump instruction events, memory access events, and exit events. Memory-related events include memory allocation, access, and deallocation events. The corresponding callback method is activated when a specific event occurs. Specifically, the first request is a memory allocation function in the program code running in the simulated chip environment, triggering the corresponding memory allocation event. This application embodiment does not limit the programming language or achievable functions of the program code under test.

[0089] Specifically, memory allocation functions can include at least one of the following: malloc, calloc, realloc, vmalloc, and get_free_page. These functions are used for memory allocation needs in different scenarios. When a request for memory space is detected, the request is intercepted.

[0090] Optionally, the memory allocation function may include at least one of the following: the name of the thread that generated the call request, the thread number, and the size of the memory to be allocated.

[0091] For example, the first request could be the malloc function from the C standard library, used to dynamically allocate memory of a specified size. When QEMU generates a memory request event in the simulated memory environment, the data processing device 100 intercepts the event after detecting it and calls the corresponding event callback method.

[0092] 302. Based on the first request, configure a second memory space, which includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state.

[0093] Specifically, after receiving the first memory request, an additional memory space is configured (requested) in the test system's memory environment. The size of the first region's memory space is consistent with the size indicated by the first request, and the access permissions of the memory addresses in the first region are in an accessible state to satisfy the process's original memory requirements. The memory space in the first region can also be called the target memory space or the original memory space. The second region is the additional memory space requested, serving as a protected area for the target memory space. The access permissions of the memory addresses in the protected area are in an inaccessible state to ensure that other processes cannot encroach on this region when requesting memory space.

[0094] The first request includes the length of the first byte of the requested memory space, which is the size of the memory space in the first region. Based on this first byte length, the size of the memory space in the protected region is determined, which is the second byte length.

[0095] Specifically, based on the length of the first byte and the length of the second byte, the second memory space is requested from QEMU.

[0096] Optionally, after allocating the first region, the QEMU-simulated memory can obtain the start and end memory addresses of the first region. Based on these start and end memory addresses and the second byte length, the second region can then be allocated.

[0097] In one possible implementation, the memory address of the protected area (second region) is adjacent to the memory address of the target memory space (first region).

[0098] In one possible implementation, the protected area surrounds the target memory space. For example... Figure 4 As shown, the additional second region requested includes a first sub-region and a second sub-region. The memory address of the first region is between the memory address of the first sub-region and the memory address of the second sub-region, forming a protected memory block.

[0099] For example, the first region is allocated memory address space from 10 to 90, the first subregion of the second region is allocated space from 1 to 9, and the second subregion of the second region is allocated space from 91 to 100.

[0100] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating normal memory and its mapped shadow memory. The state of the shadow memory corresponding to the protected area (second region) differs from the state of the shadow memory corresponding to the target memory space (first region). Shadow memory addresses are used to record the state of the regular memory address, such as whether it has been allocated, accessed, or written to. Normal memory regions may be marked as "accessible" or "allocated," while protected areas may be marked as "inaccessible" or "special state," allowing for immediate identification upon detection of unauthorized access.

[0101] In one possible implementation, the address returned by the Malloc function is typically at least 8 bytes aligned. A shadow memory value is used to store information about the 8-byte memory address.

[0102] Specifically, the value of shadow memory can represent the following states:

[0103] When the value is 0, it means that all 8 bytes are addressable (accessible).

[0104] When the value is k (1≤k≤7), it means that the first k bytes are addressable, and the last 8-k bytes are not addressable (inaccessible).

[0105] When the value is negative (e.g., -1), it means that all 8 bytes are not addressable. Different negative numbers can represent different states or memory regions (e.g., freed memory, stack memory, etc. The specific definition of negative numbers depends on the specific design).

[0106] like Figure 5 As shown, normal memory consists of three 8-byte memory blocks. The first 8 bytes belong to the memory address in the first region, and all 8 bytes are accessible; therefore, its shadow memory value is 0. In the middle 8-byte block, the first 5 bytes belong to the memory address in the first region, and the last 3 bytes belong to an additional protected area (the second region); therefore, only the first 5 bytes are accessible, and its shadow memory value is 5. The last 8 bytes belong to the additional protected area, and all 8 bytes are inaccessible; therefore, its shadow memory value is -1.

[0107] In one possible implementation, QEMU returns a pointer to the starting address of the first region after configuring the second memory space. If the returned pointer is null, it indicates that memory allocation failed. If the returned pointer is not null, this pointer information is recorded in a variable.

[0108] 303. Obtain the second request, which is used to access the first region.

[0109] In this application, the second request refers to the instruction in the program code to be tested used to request memory access from the electronic device, and the second request includes pointer information of the target memory address.

[0110] In one possible implementation, the second request and the first request are memory access and memory allocation requests within the same process. Access is performed through the memory pointer variable corresponding to the previously allocated memory space. Specifically, the second request is a memory access instruction in the program code running in the QEMU emulation chip environment; when this instruction calls the pointer variable, a corresponding memory access event is triggered.

[0111] 304. If the access permission of the memory address indicated by the second request is inaccessible, determine that an error has occurred in the second request.

[0112] Specifically, the status of the target address pointed to by the memory access instruction is verified to determine whether an error has occurred in the second request. In a normal memory access process, the target address should be in an accessible state. Once the target address of the memory access instruction points to an inaccessible state, it means that there is a problem with the program code corresponding to the memory access instruction.

[0113] Optionally, the inaccessible memory address is the address corresponding to the protected area. The second request attempts to access a protected memory region, thus triggering a memory access out-of-bounds error.

[0114] Optionally, the inaccessible memory address can be a memory address that has already been freed. For example, after freeing a block of memory using the `free` function (in C) or the `delete` function (in C++), that memory no longer belongs to the program's valid memory space. If the program then attempts to access that memory again through the previously accessed pointer, it will trigger an error accessing freed memory.

[0115] In one possible implementation, the method further includes: obtaining first indication information, which is used to indicate the termination of a first process, the first process being the process that processed the first request.

[0116] When a process terminates, all memory space allocated during its execution should be properly released. If memory space remains unreleased after process termination, this memory cannot be effectively utilized by other processes, thus constituting a memory leak problem.

[0117] For example, the memory space allocated can be freed using the free function.

[0118] It is important to note that the extra protected area (second region) allocated when allocating memory space does not need to be released, so that the released memory may be isolated to prevent it from being used by other processes.

[0119] The triggering event for obtaining the first indication information may be a process termination event bound to QEMU, or a memory leak detection event bound to QEMU when it exits.

[0120] Based on the first instruction information, it is checked whether the memory address of the first region has been released. If the memory address of the first region has not been released, it is determined that the first process has not properly released the requested memory space, and there is a memory leak error in the program code.

[0121] In one possible implementation, the method further includes: obtaining a third request, which is used to release the memory address of the first region. If the memory address of the first region has already been released, then the third request contains a duplicate memory release error.

[0122] Please see Figure 6 , Figure 6 This is a schematic diagram of a data processing device. For example... Figure 6 As shown, the data processing device 100 is deployed in the test system and includes multiple functional modules, such as an event processing module, an address translation module, a memory allocation module, a memory security module, an alarm module, and a verification module.

[0123] The event handling module is responsible for listening to and processing various internal and external events. These events may include memory allocation requests, memory release requests, and exception detection signals. The event handling module forwards events to the appropriate processing modules, such as the memory allocation module, memory safety module, or alarm module, to ensure timely response and processing.

[0124] The address translation module is responsible for translating virtual memory addresses into physical memory addresses to ensure that programs can access memory correctly. It also maintains an address mapping table, recording which memory regions are valid and which are protected. This helps prevent programs from accessing illegal memory addresses, thereby improving system stability.

[0125] The memory allocation module is responsible for responding to memory allocation requests and allocating appropriate memory space based on the size and type of the request. Optionally, it also maintains a memory allocation record table to record the allocation status of each memory block, including allocation time, size, and the process to which it belongs.

[0126] The shadow stack is used to record context information such as the return address of function calls. When the memory safety module receives a memory allocation instruction, it allocates an additional protected area and associates this area with the shadow memory to ensure that the state of the normally allocated memory address is different from that of the protected area memory address (verified by the value of the shadow memory).

[0127] The verification module detects anomalies by monitoring memory access or checking data integrity, and generates anomaly reports. Upon receiving the anomaly report from the verification module, the alarm module uses context information from the shadow stack to locate and report the code segment where the memory error occurred.

[0128] When an exit event is triggered (such as process termination or program termination), the data processing device 100 releases the relevant information and corresponding shadow memory originally recorded in the shadow stack. Simultaneously, it uses data structures such as red-black trees to manage and inspect the memory allocation record table to detect and report potential memory leak errors. The red-black tree is used to store and manage memory block allocation information for quick lookup and verification during memory release. By traversing the red-black tree and checking whether each memory block has been correctly released, the data processing device 100 can accurately detect memory leak problems and generate corresponding reports.

[0129] In this embodiment, when the program needs to allocate memory space, an additional inaccessible protected area is allocated. Based on the aforementioned detection process, memory erroneous operations in the program can be detected. Furthermore, the testing system provided by QEMU is used to simulate the program's runtime environment, making the memory space a simulated and isolated environment. This avoids instrumentation detection in the compiler or original program code, thereby reducing the risk of performance loss and memory consumption. When the process or the QEMU testing environment exits, a comprehensive check of the memory environment is performed to determine if any memory leaks exist.

[0130] The methods provided in the embodiments of this application have been described in detail above. Next, the device for performing the above methods provided in the embodiments of this application will be described.

[0131] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a data processing apparatus 700 provided in an embodiment of this application. Figure 7 As shown, the device includes:

[0132] The acquisition module 701 is used to acquire the first request, which is used to request the first memory space;

[0133] The processing module 702 is used to configure a second memory space based on a first request. The second memory space includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state.

[0134] The acquisition module 701 is also used to acquire a second request, which is used to access the first area;

[0135] The processing module 702 is further configured to determine the access status of the memory address indicated by the second request, and if the access permission of the memory address indicated by the second request is inaccessible, determine that the second request has encountered an error.

[0136] In one possible implementation, module 701 is specifically used for:

[0137] Once the first request is detected in the process, the first request is intercepted.

[0138] In one possible implementation, the first request includes a first byte length, which is the memory size of the first memory space;

[0139] Processing module 702 is specifically used for:

[0140] The length of the second byte is determined based on the length of the first byte;

[0141] Configure a first region and a second region based on the length of the first byte and the length of the second byte. The memory size of the first region is the length of the first byte, and the memory size of the second region is the length of the second byte.

[0142] In one possible implementation, the memory address of the second region is adjacent to the memory address of the first region.

[0143] In one possible implementation, the second region includes a first sub-region and a second sub-region, with the memory address of the first region falling between the memory addresses of the first sub-region and the second sub-region.

[0144] In one possible implementation, the access status of the memory address indicated by the second request is determined based on the value of the shadow memory mapped to the memory address.

[0145] In one possible implementation, module 701 is also used for:

[0146] Obtain first instruction information, which is used to instruct the first process to terminate. The first process is the process that handles the first request.

[0147] The processing module 702 is also configured to detect whether the memory address of the first region has been released based on the first instruction information;

[0148] If the memory address of the first region is not freed, a first memory error message is determined.

[0149] This application also provides a computing device 100. For example... Figure 8 As shown, the computing device 100 includes a bus 102, a processor 104, a memory 106, and a communication interface 108. The processor 104, the memory 106, and the communication interface 108 communicate with each other via the bus 102. The computing device 100 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computing device 100.

[0150] Bus 102 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 8 The bus 104 may be represented by a single line, but this does not mean that there is only one bus or one type of bus. The bus 104 may include a path for transmitting information between various components of the computing device 100 (e.g., memory 106, processor 104, communication interface 108).

[0151] The processor 104 may include any one or more processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0152] Memory 106 may include volatile memory, such as random access memory (RAM). Processor 104 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0153] The memory 106 stores executable program code, which the processor 104 executes to implement the functions of the aforementioned acquisition module and processing module, thereby realizing the data processing method. In other words, the memory 106 stores instructions for executing the data processing method.

[0154] Alternatively, the memory 106 stores executable code, which the processor 104 executes to implement the functions of the aforementioned path lookup device, thereby implementing the data processing method. That is, the memory 106 stores instructions for executing the data processing method.

[0155] The communication interface 108 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 100 and other devices or communication networks.

[0156] This application also relates to a computer storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0157] This application also relates to a computer program product that stores instructions that, when executed by a computer, cause the computer to perform steps as performed by the aforementioned execution device, or to perform steps as performed by the aforementioned training device.

[0158] The computing device provided in this application embodiment can specifically be a chip, which includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip in the execution device to execute the data processing method described in the above embodiments, or to cause the chip in the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit is a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0159] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0160] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0161] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose GPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0162] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0163] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A data processing method, characterized in that, include: Obtain the first request, which is used to request the first memory space; Based on the first request, a second memory space is configured. The second memory space includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state. Obtain a second request, which is used to access the first region; If the access permission of the memory address indicated by the second request is inaccessible, it is determined that the second request has encountered an error.

2. The method according to claim 1, characterized in that, The first request includes: Once the first request is detected in the process, the first request is intercepted.

3. The method according to claim 1 or 2, characterized in that, The first request includes a first byte length, which is the memory size of the first memory space; The step of configuring the second memory space based on the first request includes: The length of the second byte is determined based on the length of the first byte; Configure the first region and the second region according to the first byte length and the second byte length, wherein the memory size of the first region is the first byte length and the memory size of the second region is the second byte length.

4. The method according to any one of claims 1-3, characterized in that, The memory address of the second region is adjacent to the memory address of the first region.

5. The method according to any one of claims 1-4, characterized in that, The second region includes a first sub-region and a second sub-region, and the memory address of the first region is between the memory address of the first sub-region and the memory address of the second sub-region.

6. The method according to any one of claims 1-5, characterized in that, The access rights to the memory address indicated in the second request are determined based on the value of the shadow memory mapped to the memory address.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: Obtain first indication information, which is used to indicate the termination of the first process, the first process being the process that processed the first request; Based on the first instruction information, detect whether the memory address of the first region has been released; If the memory address of the first region is not released, a first memory error message is determined.

8. A data processing apparatus, characterized in that, include: An event handling module is used to handle memory events during system operation. The memory events are determined based on memory processing requests in a process. The memory processing requests include a first request and a second request. The first request is used to request a first memory space, and the second request is used to access the first memory space. The request processing module is configured to configure a second memory space based on the first request. The second memory space includes a first region and a second region. The first region is a simulated memory space of the first memory space. The access permissions of the memory addresses in the first region are in an accessible state, and the access permissions of the memory addresses in the second region are in an inaccessible state. The request processing module is also configured to access the memory address indicated by the second request based on the second request; The verification module is used to verify the access permissions of the memory address indicated by the second request. If the access permissions of the memory address indicated by the second request are inaccessible, it is determined that the second request has encountered an error.

9. The apparatus according to claim 8, characterized in that, The first request includes a first byte length, which is the memory size of the first memory space; The request processing module is specifically used to determine the length of the second byte based on the length of the first byte; Configure the first region and the second region according to the first byte length and the second byte length, wherein the memory size of the first region is the first byte length and the memory size of the second region is the second byte length.

10. The apparatus according to claim 8 or 9, characterized in that, The request processing module includes an address translation module, a memory allocation module, a memory security module, and an alarm module. The address translation module is used to convert virtual memory addresses into physical memory addresses. The memory allocation module is used to configure the memory space of the first region. The memory security module is used to configure the memory space of the second region. The alarm module is used to output error information.

11. The apparatus according to any one of claims 8-10, characterized in that, The memory address of the second region is adjacent to the memory address of the first region.

12. The apparatus according to any one of claims 8-11, characterized in that, The second region includes a first sub-region and a second sub-region, and the memory address of the first region is between the memory address of the first sub-region and the memory address of the second sub-region.

13. The apparatus according to any one of claims 8-12, characterized in that, The access status of the memory address indicated by the second request is determined based on the value of the shadow memory mapped to the memory address.

14. The apparatus according to any one of claims 8-13, characterized in that, The device further includes: The exit module is used to obtain first indication information, which is used to indicate the termination of the first process, and the first process is the process that processed the first request; The verification module is further configured to detect whether the memory address of the first region has been released based on the first indication information; If the memory address of the first region is not released, a first memory error message is determined.

15. A communication device, characterized in that, include: Communication interface and processor; The communication interface and the processor perform the method as described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that, The medium stores instructions that, when executed by a processor, implement the method of any one of claims 1 to 7.

17. A computer program product, characterized in that, Includes instructions that, when executed on a processor, perform the method as described in any one of claims 1 to 7.

18. A chip, characterized in that, It includes at least one processing unit and an interface circuit, the interface circuit being used to provide program instructions or data to the at least one processing unit, the at least one processing unit being used to execute the program instructions to implement the method of any one of claims 1 to 7.

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