Low noise amplifier

Abstract

The application belongs to the field of radio frequency technology, and particularly relates to a low-noise amplifier. The low-noise amplifier comprises an amplification circuit and a bypass circuit. An input end of the amplification circuit and a first input end of the bypass circuit are connected to each other and used for receiving a radio frequency signal. A second input end of the bypass circuit is connected to a first control voltage. An output end of the amplification circuit and an output end of the bypass circuit are connected and used for outputting the radio frequency signal. A power supply and power consumption adjusting unit is used for adjusting power consumption of the amplification circuit according to a second control voltage. A shutdown unit is used for controlling on or off of the amplification circuit according to a third control voltage. Compared with the prior art, the low-noise amplifier comprises multiple working modes, the working mode of the low-noise amplifier can be controlled through the shutdown unit and the power supply and power consumption adjusting unit, and therefore high gain, low noise, high applicable frequency, high circuit integration, low cost, adjustable power consumption and gain, and high frequency application can be realized.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and in particular to a low-noise amplifier. Background Technology

[0002] As the active module at the front end of the wireless receiver's receiving link, the core function of a low-noise amplifier (LNOA) is to amplify weak input signals while minimizing the noise it introduces, thereby improving the signal-to-noise ratio of the entire receiving system. This provides high-quality signal input for subsequent signal processing circuits (such as mixers, filters, and demodulators), and its performance directly determines the overall receiving sensitivity, signal processing accuracy, and anti-interference capability of the receiving link. Gain, noise figure, and linearity are key performance indicators for LNOA, and their quality directly affects the wireless receiver's ability to acquire weak signals and the reliability of signal processing.

[0003] With the rapid development of technologies such as mobile communication, satellite communication, and remote control and telemetry systems, application scenarios have placed higher demands on low-noise amplifiers in terms of functional integration, operating frequency band adaptability, miniaturization, cost control, and low power consumption. This is driving the development of low-noise amplifiers towards wider bandwidth, higher gain, lower noise, smaller size, lower power consumption, and higher integration. However, existing low-noise amplifier technologies all have their own shortcomings and cannot simultaneously meet the above-mentioned multi-dimensional performance requirements, as detailed below:

[0004] Low-noise amplifiers with bypass function based on silicon-on-insulator (SiI) technology and common-source cascode structure: The core limitation of this type of amplifier is that it operates at a low frequency and introduces a large amount of noise, which makes it only suitable for consumer electronics products with low performance requirements and unable to meet the application needs of high-frequency and high-sensitivity scenarios.

[0005] Uniformly distributed low-noise amplifiers: To achieve signal amplification and impedance matching, this type of amplifier requires a large number of inductors, which significantly increases the chip area and directly drives up the manufacturing cost of the device. In addition, in CMOS process technology, the quality factor (Q value) of inductors is low, which introduces a lot of additional noise when the amplifier is operating at high frequencies. At the same time, the parasitic effect of inductors will generate parasitic resistance, which will bring a non-negligible insertion loss, thus limiting the gain improvement of the amplifier and making it difficult to meet the requirements of high-frequency operation and high gain and low noise performance.

[0006] Differential cascode low-noise amplifier: Under the same transistor size and bias conditions, the layout area of ​​this type of amplifier is twice that of a single-ended amplifier, and the power consumption is also doubled accordingly, without any substantial improvement in noise figure and gain. More importantly, the input signal of a wireless receiver is usually a single-ended signal. To adapt to the differential input requirements of the differential cascode amplifier, an additional RF balanced-to-unbalanced impedance converter (Balun) must be configured to convert the single-ended signal to the differential signal. However, Balun devices not only have the problem of high integration difficulty, but also introduce 0.5dB to 2dB of signal loss. This loss directly leads to an increase in the amplifier's noise figure and a decrease in gain, which seriously affects the signal reception sensitivity of the receiver link.

[0007] In summary, existing low-noise amplifier technologies suffer from irreconcilable contradictions in terms of operating frequency band, noise control, chip area, power consumption, integration density, and cost, failing to meet the high performance and comprehensive characteristics requirements of low-noise amplifiers in various current applications. Therefore, a new low-noise amplifier is urgently needed to solve these technical problems. Summary of the Invention

[0008] This invention provides a low-noise amplifier, which aims to provide a low-noise amplifier that can take into account wide frequency band adaptability, low noise, high gain, small size, low power consumption and high integration.

[0009] In a first aspect, the present invention provides a low-noise amplifier, the low-noise amplifier including an amplification circuit and a bypass circuit, the input terminal of the amplification circuit and the first input terminal of the bypass circuit being interconnected and used to receive radio frequency signals, the second input terminal of the bypass circuit being connected to a first control voltage, the output terminal of the amplification circuit and the output terminal of the bypass circuit being connected and used to output the radio frequency signals, the first control voltage being used to control the conduction or disconnection of the bypass circuit; The amplifier circuit includes an input matching unit, a first amplification unit, an interstage matching unit, a second amplification unit, an output matching unit, a feedback unit, a power supply and power consumption adjustment unit, a shutdown unit, a first resistor, and a first stabilizing capacitor. The input terminal of the input matching unit serves as the input terminal of the amplifier circuit, and the output terminal of the input matching unit is connected to the first input terminal of the first amplifier unit. The output of the first amplification unit is connected to the first input of the interstage matching unit; The output of the inter-stage matching unit is connected to the input of the second amplification unit; The output terminal of the second amplification unit is connected to the input terminal of the output matching unit, and the output terminal of the output matching unit serves as the output terminal of the amplification circuit. The first end of the feedback unit is connected to the first input end of the first amplification unit, and the second end of the feedback unit is connected to the second input end of the inter-stage matching unit; the feedback unit is used to feed the signal back to the first amplification unit. The input terminal of the power supply and power consumption adjustment unit is connected to a second control voltage; the first output terminal of the power supply and power consumption adjustment unit is connected to the second input terminal of the first amplification unit; the second output terminal of the power supply and power consumption adjustment unit is connected to the third input terminal of the interstage matching unit; the third output terminal of the power supply and power consumption adjustment unit is connected to the input terminal of the second amplification unit; the fourth output terminal of the power supply and power consumption adjustment unit is connected to the first input terminal of the first amplification unit after being connected in series with the first resistor; the power supply and power consumption adjustment unit is used to adjust the power consumption of the amplification circuit according to the second control voltage. The first terminal of the first stabilizing capacitor is grounded, and the second terminal of the first stabilizing capacitor is connected to the second input terminal of the first amplifying unit. The input terminal of the shutdown unit is connected to a third control voltage, the first output terminal of the shutdown unit is connected to the second input terminal of the first amplification unit, and the second output terminal of the shutdown unit is connected to the input terminal of the second amplification unit; the shutdown unit is used to control the amplification circuit to be turned on or off according to the third control voltage.

[0010] Preferably, the input matching unit includes a first capacitor and a first inductor; the first end of the first capacitor serves as the input terminal of the input matching unit, the second end of the first capacitor is connected to the first end of the first inductor, and the second end of the first inductor serves as the output terminal of the input matching unit.

[0011] Preferably, the feedback unit includes a second capacitor and a second resistor, the first end of the second resistor serves as the first end of the feedback unit, the second end of the second resistor is connected to the first end of the second capacitor, and the second end of the second capacitor serves as the second end of the feedback unit.

[0012] Preferably, the first amplification unit includes a first MOS transistor, a second MOS transistor, and a second inductor; the gate of the first MOS transistor serves as the first input terminal of the first amplification unit, the source of the first MOS transistor is connected to the first terminal of the second inductor, the second terminal of the second inductor is grounded, the drain of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor serves as the second input terminal of the first amplification unit, and the drain of the second MOS transistor serves as the output terminal of the first amplification unit.

[0013] Preferably, the interstage matching unit includes a third resistor, a third inductor, and a third capacitor; the first end of the third inductor serves as the first input terminal of the interstage matching unit, the second end of the third inductor is connected to the first end of the third capacitor and the power supply, the first end of the third capacitor serves as the second input terminal of the interstage matching unit, the second end of the third capacitor serves as the output terminal of the interstage matching unit, the first end of the third resistor is connected to the first end of the third inductor, and the second end of the third resistor serves as the third input terminal of the interstage matching unit.

[0014] Preferably, the second amplification unit includes a third MOS transistor and a fourth inductor. The gate of the third MOS transistor serves as the input terminal of the second amplification unit, the source of the third MOS transistor is connected to the first terminal of the fourth inductor, the second terminal of the fourth inductor is grounded, and the drain of the third MOS transistor serves as the output terminal of the second amplification unit.

[0015] Preferably, the output matching unit includes a fourth capacitor, a fifth inductor, and a fourth resistor; the first terminal of the fourth capacitor serves as the input terminal of the output matching unit, the second terminal of the fourth capacitor serves as the output terminal of the output matching unit, the first terminal of the fifth inductor is connected to the first terminal of the fourth capacitor, the second terminal of the fifth inductor is connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the power supply.

[0016] Preferably, the power supply and power consumption adjustment unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; the input terminal of the power supply and power consumption adjustment unit includes a first input terminal and a second input terminal; The first end of the fifth resistor serves as the first output terminal of the power supply and power consumption adjustment unit. The second end of the fifth resistor is connected to the first end of the sixth resistor. The first end of the sixth resistor serves as the second output terminal of the power supply and power consumption adjustment unit. The second end of the sixth resistor is connected to the first ends of the seventh resistor, the eighth resistor, and the ninth resistor, and together they serve as the fourth output terminal of the power supply and power consumption adjustment unit. The second end of the seventh resistor, the source of the fourth MOS transistor, and the source of the fifth MOS transistor are connected to each other and grounded. The second end of the eighth resistor is connected to the drain of the fourth MOS transistor. The second end of the ninth resistor is connected to the drain of the fifth MOS transistor. The gates of the fourth MOS transistor and the sixth MOS transistor are connected to each other and together they serve as the first input terminal of the power supply and power consumption adjustment unit. The gates of the fifth MOS transistor and the seventh MOS transistor are connected to each other and together they serve as the second input terminal of the power supply and power consumption adjustment unit. The first end of the tenth resistor is connected to the power supply. The second end of the tenth resistor is connected to the first end of the eleventh resistor, the first end of the twelfth resistor, the first end of the thirteenth resistor, and the first end of the fourteenth resistor. The second end of the eleventh resistor serves as the third output terminal of the power supply and power consumption adjustment unit. The second end of the twelfth resistor, the source of the sixth MOS transistor, and the source of the seventh MOS transistor are interconnected and grounded. The second end of the thirteenth resistor is connected to the drain of the sixth MOS transistor, and the second end of the fourteenth resistor is connected to the drain of the seventh MOS transistor.

[0017] Preferably, the shutdown unit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a fifth capacitor, a sixth capacitor, a first diode, and a second diode; The first terminal of the fifteenth resistor and the first terminal of the twenty-third resistor are interconnected and together serve as the input terminal of the turn-off unit. The second terminal of the fifteenth resistor is connected to the first terminal of the sixteenth resistor and the gate of the eighth MOS transistor. The second terminal of the sixteenth resistor is connected to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is grounded. The source of the eighth MOS transistor is connected to the first terminal of the seventeenth resistor and the gate of the ninth MOS transistor. The drain of the eighth MOS transistor is connected to the first terminal of the eighteenth resistor. The second terminal of the seventeenth resistor is grounded. The source of the ninth MOS transistor is connected to the first terminal of the twentieth resistor and the first terminal of the twenty-first resistor, and the second terminal of the twentieth resistor is grounded. The drain of the ninth MOS transistor is connected to the second terminal of the eighteenth resistor, the first terminal of the nineteenth resistor, the second terminal of the twenty-first resistor, and the tenth resistor. The gates of a MOSFET and a twelfth MOSFET are connected. The second terminal of the nineteenth resistor is connected to the source of the tenth MOSFET. The gate of the tenth MOSFET is connected to the second terminal of the twenty-third resistor. The drain of the tenth MOSFET is connected to the cathode of the first diode. The anode of the first diode is connected to the cathode of the second diode. The anode of the second diode is connected to the first terminal of the twenty-third resistor. The first terminal of the twenty-second resistor is connected to the gate of the eleventh MOSFET. The second terminal of the twenty-second resistor is grounded. The first terminal of the sixth capacitor is connected to the gate of the eleventh MOSFET. The second terminal of the sixth capacitor is connected to the source of the twelfth MOSFET. The source of the eleventh MOSFET is grounded. The drain of the eleventh MOSFET serves as the first output terminal of the shutdown unit. The drain of the twelfth MOSFET serves as the second output terminal of the shutdown unit.

[0018] Preferably, the bypass circuit includes a seventh capacitor, an eighth capacitor, a thirteenth MOSFET, and a twenty-fourth resistor; the first terminal of the seventh capacitor serves as the first input terminal of the bypass circuit, the second terminal of the seventh capacitor is connected to the drain of the thirteenth MOSFET, the gate of the thirteenth MOSFET serves as the second input terminal of the bypass circuit, the source of the thirteenth MOSFET is connected to the first terminal of the twenty-fourth resistor, the second terminal of the twenty-fourth resistor is connected to the first terminal of the eighth capacitor, and the second terminal of the eighth capacitor serves as the output terminal of the bypass circuit.

[0019] Compared with existing technologies, the low-noise amplifier of this invention includes an amplification circuit and a bypass circuit. The input terminal of the amplification circuit and the first input terminal of the bypass circuit are interconnected and used to receive radio frequency signals. The second input terminal of the bypass circuit is connected to a first control voltage. The output terminal of the amplification circuit and the output terminal of the bypass circuit are connected and used to output radio frequency signals. The first control voltage is used to control the conduction or disconnection of the bypass circuit. The amplification circuit includes an input matching unit, a first amplification unit, an inter-stage matching unit, a second amplification unit, an output matching unit, a feedback unit, a power supply and power consumption adjustment unit, and a shutdown unit. The feedback unit is used for signal feedback. The power supply and power consumption adjustment unit is used to adjust the power consumption of the amplification circuit according to the second control voltage. The shutdown unit is used to control the conduction or disconnection of the amplification circuit according to a third control voltage. The low-noise amplifier of this invention includes multiple operating modes, and the operating mode of the low-noise amplifier can be controlled by the shutdown unit and the power supply and power consumption adjustment unit, thereby achieving high gain, low noise, and high applicable frequency. It has high circuit integration and low cost, while power consumption and gain are adjustable, applicable to high frequencies, and has a wider range of applications. Attached Figure Description

[0020] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Fig. 1 This is a circuit block diagram of a low-noise amplifier provided in an embodiment of the present invention; Fig. 2 This is a circuit diagram of a low-noise amplifier provided in an embodiment of the present invention; Fig. 3 This is an amplifier circuit diagram of a low-noise amplifier provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Please refer to Figs. 1 to 3This invention provides a low-noise amplifier 100, which adopts a two-stage amplification structure. The first stage adopts a common-source cascode structure, and the second stage adopts a common-source structure. The low-noise amplifier 100 includes an amplification circuit 01 and a bypass circuit 02. The input terminal of the amplification circuit 01 and the first input terminal of the bypass circuit 02 are interconnected and used to receive radio frequency signals. The second input terminal of the bypass circuit 02 is connected to a first control voltage VC1. The output terminal of the amplification circuit 01 and the output terminal of the bypass circuit 02 are connected and used to output the radio frequency signals. The first control voltage VC1 is used to control the conduction or disconnection of the bypass circuit 02. The amplifier circuit 01 includes an input matching unit 011, a first amplification unit 012, an interstage matching unit 013, a second amplification unit 014, an output matching unit 015, a feedback unit 016, a power supply and power consumption adjustment unit 017, a shutdown unit 018, a first resistor R1, and a first stabilizing capacitor Cs1. The input terminal of the input matching unit 011 serves as the input terminal of the amplifier circuit 01, and the output terminal of the input matching unit 011 is connected to the first input terminal of the first amplifier unit 012. The output of the first amplification unit 012 is connected to the first input of the interstage matching unit 013; The output of the inter-stage matching unit 013 is connected to the input of the second amplification unit 014; The output terminal of the second amplification unit 014 is connected to the input terminal of the output matching unit 015, and the output terminal of the output matching unit 015 serves as the output terminal of the amplification circuit 01. The first end of the feedback unit 016 is connected to the first input end of the first amplification unit 012, and the second end of the feedback unit 016 is connected to the second input end of the inter-stage matching unit 013; the feedback unit 016 is used to feed the signal back to the first amplification unit 012. The input terminal of the power supply and power consumption adjustment unit 017 is connected to the second control voltage (VC2a, VC2b). The first output terminal of the power supply and power consumption adjustment unit 017 is connected to the second input terminal of the first amplification unit 012. The second output terminal of the power supply and power consumption adjustment unit 017 is connected to the third input terminal of the interstage matching unit 013. The third output terminal of the power supply and power consumption adjustment unit 017 is connected to the input terminal of the second amplification unit 014. The fourth output terminal of the power supply and power consumption adjustment unit 017 is connected to the first input terminal of the first amplification unit 012 via the first resistor R1 in series. The first resistor R1 is used to supply power to the first input terminal of the first amplification unit 012. The resistance value of the first resistor R1 cannot be too small. If the resistance value of the first resistor R1 is too small, it will participate in matching and affect the noise figure. Therefore, the resistance value of the first resistor R1 needs to be set to at least the kiloohm level, so that it only serves to supply power to the first input terminal of the first amplification unit 012. The power supply and power consumption adjustment unit 017 is used to adjust the power consumption of the amplification circuit 01 according to the second control voltage (VC2a, VC2b).

[0023] The first terminal of the first stabilizing capacitor Cs1 is grounded, and the second terminal of the first stabilizing capacitor Cs1 is connected to the second input terminal of the first amplifying unit 012; the first stabilizing capacitor Cs1 is used to improve the stability of the circuit.

[0024] The input terminal of the shutdown unit 018 is connected to the third control voltage VC3, the first output terminal of the shutdown unit 018 is connected to the second input terminal of the first amplification unit 012, and the second output terminal of the shutdown unit 018 is connected to the input terminal of the second amplification unit 014; the shutdown unit 018 is used to control the amplification circuit 01 to be turned on or off according to the third control voltage VC3.

[0025] In this embodiment of the invention, the input matching unit 011 includes a first capacitor C1 and a first inductor L1; the first end of the first capacitor C1 serves as the input end of the input matching unit 011, the second end of the first capacitor C1 is connected to the first end of the first inductor L1, and the second end of the first inductor L1 serves as the output end of the input matching unit 011.

[0026] In this embodiment of the invention, the feedback unit 016 includes a second capacitor C2 and a second resistor R2. The first end of the second resistor R2 serves as the first end of the feedback unit 016, and the second end of the second resistor R2 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 serves as the second end of the feedback unit 016. By connecting the second resistor R2 and the second capacitor C2 in series, the feedback unit 016 feeds back from the first amplification unit 012 to the second amplification unit 014, which helps improve circuit stability and expand bandwidth. Furthermore, the value of the feedback unit 016 can affect input matching.

[0027] In this embodiment of the invention, the first amplification unit 012 includes a first MOSFET M1, a second MOSFET M2, and a second inductor L2. The first amplification unit 012 proposed in this application adopts a common-source, common-gate architecture with source negative feedback, significantly improving reverse isolation and effectively suppressing the Miller effect. The gate of the first MOSFET M1 serves as the first input terminal of the first amplification unit 012. The source of the first MOSFET M1 is connected to the first terminal of the second inductor L2, the second terminal of the second inductor L2 is grounded, the drain of the first MOSFET M1 is connected to the source of the second MOSFET M2, the gate of the second MOSFET M2 serves as the second input terminal of the first amplification unit 012, and the drain of the second MOSFET M2 serves as the output terminal of the first amplification unit 012. Input matching and noise matching are achieved by using a first inductor L1 connected in series with the gate of the first MOSFET M1, a second inductor L2 for negative feedback at the source of the first MOSFET M1, and the first MOSFET M1 as the gate-source capacitance resonance of the field-effect transistor itself. Adding a negative feedback inductor at the source of the first MOSFET M1 effectively improves circuit stability.

[0028] In this embodiment of the invention, the interstage matching unit 013 includes a third resistor R3, a third inductor L3, and a third capacitor C3. The first terminal of the third inductor L3 serves as the first input terminal of the interstage matching unit 013. The second terminal of the third inductor L3 is connected to the first terminal of the third capacitor C3 and the power supply VDD. The first terminal of the third capacitor C3 serves as the second input terminal of the interstage matching unit 013 and the second terminal of the third capacitor C3 serves as the output terminal of the interstage matching unit 013. The first terminal of the third resistor R3 is connected to the first terminal of the third inductor L3, and the second terminal of the third resistor R3 serves as the third input terminal of the interstage matching unit 013. The value of the third inductor L3 affects the bandwidth.

[0029] In this embodiment of the invention, the second amplification unit 014 includes a third MOS transistor M3 and a fourth inductor L4. The gate of the third MOS transistor M3 serves as the input terminal of the second amplification unit 014. The source of the third MOS transistor M3 is connected to the first terminal of the fourth inductor L4, and the second terminal of the fourth inductor L4 is grounded. The drain of the third MOS transistor M3 serves as the output terminal of the second amplification unit 014. The fourth inductor L4 serves as the source negative feedback inductor, and its value affects the gain. The larger the fourth inductor L4 is, the greater the feedback and the smaller the gain.

[0030] In this embodiment of the invention, the output matching unit 015 includes a fourth capacitor C4, a fifth inductor L5, and a fourth resistor R4; the first end of the fourth capacitor C4 serves as the input end of the output matching unit 015, the second end of the fourth capacitor C4 serves as the output end of the output matching unit 015, the first end of the fifth inductor L5 is connected to the first end of the fourth capacitor C4, the second end of the fifth inductor L5 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the power supply VDD.

[0031] In this embodiment of the invention, the power supply and power consumption adjustment unit 017 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, and a seventh MOSFET M7; the input terminals of the power supply and power consumption adjustment unit 017 include a first input terminal and a second input terminal; The first end of the fifth resistor R5 serves as the first output terminal of the power supply and power consumption adjustment unit 017. The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6. The first end of the sixth resistor R6 serves as the second output terminal of the power supply and power consumption adjustment unit 017. The second end of the sixth resistor R6 is connected to the first ends of the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, and together they serve as the fourth output terminal of the power supply and power consumption adjustment unit 017. The second end of the seventh resistor R7, the source of the fourth MOS transistor M4, and the source of the fifth MOS transistor M5 are connected to each other and grounded. The second end of the eighth resistor R8 is connected to the drain of the fourth MOS transistor M4. The second end of the ninth resistor R9 is connected to the drain of the fifth MOS transistor M5. The gate of the fourth MOS transistor M4 and the gate of the sixth MOS transistor M6 are connected to each other and together they serve as the first input terminal of the power supply and power consumption adjustment unit 017. The gate of the fifth MOS transistor M5 and the gate of the seventh MOS transistor M7 are connected to each other and together they serve as the second input terminal of the power supply and power consumption adjustment unit 017. The first end of the tenth resistor R10 is connected to the power supply VDD. The second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11, the first end of the twelfth resistor R12, the first end of the thirteenth resistor R13, and the first end of the fourteenth resistor R14. The second end of the eleventh resistor R11 serves as the third output terminal of the power supply and power consumption adjustment unit 017. The second end of the twelfth resistor R12, the source of the sixth MOSFET M6, and the source of the seventh MOSFET M7 are interconnected and grounded. The second end of the thirteenth resistor R13 is connected to the drain of the sixth MOSFET M6, and the second end of the fourteenth resistor R14 is connected to the drain of the seventh MOSFET M7.

[0032] Specifically, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are used as switches. The second control voltage (VC2a, VC2b) controls the voltage divider resistors (such as the eighth resistor R8, the ninth resistor R9, the thirteenth resistor R13, and the fourteenth resistor R14), thereby controlling the gate supply voltage Vg1 of the first MOSFET M1, thus achieving three power consumption modes. When both the second control voltage VC2a and the second control voltage VC2b at the first and second input terminals of the power supply and power consumption adjustment unit 017 are low, the amplifier circuit 01 operates in high power consumption mode; when VC2a is high and VC2b is low, the amplifier circuit 01 operates in medium power consumption mode; and when VC2b is high and VC2a is low, the amplifier circuit 01 operates in low power consumption mode.

[0033] In this embodiment of the invention, the shutdown unit 018 is controlled by a third control voltage VC3. When the third control voltage VC3 is below 1V, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are all turned off, the shutdown unit 018 does not work, and the amplifier circuit 01 is normally turned on. When the third control voltage VC3 is 2-5V, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are all turned on, the shutdown unit 018 works, and pulls the power supply voltage (Vg2) and the power supply voltage (Vg3) to ground, thereby turning off the amplifier circuit 01.

[0034] The shutdown unit 018 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a fifth capacitor C5, a sixth capacitor C6, a first diode D1, and a second diode D2. The first terminal of the fifteenth resistor R15 and the first terminal of the twenty-third resistor R23 are interconnected and serve as the input terminal of the turn-off unit 018. The second terminal of the fifteenth resistor R15 is connected to the first terminal of the sixteenth resistor R16 and the gate of the eighth MOS transistor M8. The second terminal of the sixteenth resistor R16 is connected to the first terminal of the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is grounded. The source of the eighth MOS transistor M8 is connected to the first terminal of the seventeenth resistor R17 and the gate of the ninth MOS transistor M9. The drain of the eighth MOS transistor M8 is connected to the first terminal of the eighteenth resistor R18, and the second terminal of the seventeenth resistor R17 is grounded. The source of the ninth MOS transistor M9 is connected to the first terminal of the twentieth resistor R20 and the first terminal of the twenty-first resistor R21, and the second terminal of the twentieth resistor R20 is grounded. The drain of the ninth MOS transistor M9 is connected to the second terminal of the eighteenth resistor R18, the first terminal of the nineteenth resistor R19, the second terminal of the twenty-first resistor R21, and the eleventh MOS transistor M8. The gate of MOSFET M11 and the gate of 12th MOSFET M12 are connected. The second terminal of the 19th resistor R19 is connected to the source of 10th MOSFET M10. The gate of 10th MOSFET M10 is connected to the second terminal of 23rd resistor R23. The drain of 10th MOSFET M10 is connected to the cathode of the first diode D1. The anode of the first diode D1 is connected to the cathode of the second diode D2. The anode of the second diode D2 is connected to the first terminal of 23rd resistor R23. The first terminal of 22nd resistor R22 is connected to the gate of 11th MOSFET M11. The second terminal of 22nd resistor R22 is grounded. The first terminal of the sixth capacitor C6 is connected to the gate of 11th MOSFET M11. The second terminal of the sixth capacitor C6 is connected to the source of 12th MOSFET M12. The source of 11th MOSFET M11 is grounded. The drain of 11th MOSFET M11 serves as the first output terminal of the shutdown unit 018. The drain of 12th MOSFET M12 serves as the second output terminal of the shutdown unit 018.

[0035] In this embodiment of the invention, the bypass circuit 02 includes a seventh capacitor C7, an eighth capacitor C8, a thirteenth MOSFET M13, and a twenty-fourth resistor R24. The first terminal of the seventh capacitor C7 serves as the first input terminal of the bypass circuit 02, the second terminal of the seventh capacitor C7 is connected to the drain of the thirteenth MOSFET M13, the gate of the thirteenth MOSFET M13 serves as the second input terminal of the bypass circuit 02, the source of the thirteenth MOSFET M13 is connected to the first terminal of the twenty-fourth resistor R24, the second terminal of the twenty-fourth resistor R24 ​​is connected to the first terminal of the eighth capacitor C8, and the second terminal of the eighth capacitor C8 serves as the output terminal of the bypass circuit 02.

[0036] In this embodiment of the invention, Vg1, Vg2, and Vg3 represent the power supply voltage of the gate of the first MOS transistor M1, the power supply voltage of the gate of the second MOS transistor M2, and the power supply voltage of the gate of the third MOS transistor M3, respectively. The low-noise amplifier 100 is fabricated based on the gallium arsenide pHEMT 0.25um process. The low-noise amplifier 100 includes five operating modes, namely high power mode, medium power mode, low power mode, shutdown mode, and bypass mode. By adding a filter before the low-noise amplifier 100, which detects the useful signal and transmits it to the low-noise amplifier 100, the system can avoid using the low-noise amplifier 100 when receiving strong signals (e.g., near a wireless base station or signal source). The amplifier circuit 01 will be turned off and put into bypass mode (e.g., when the first control voltage VC1 is high and the third control voltage VC3 is 2-5V, the bypass circuit 02 is turned on, the amplification mode of the low-noise amplifier 100 is turned off, and the radio frequency signal enters the first input terminal of the bypass circuit 02). The system can directly pass the received signal to the subsequent processing stage without going through the amplification circuit 01 of the low-noise amplifier 100. This function is particularly useful when the signal strength is sufficient, because in these cases, the gain of the amplifier circuit 01 is not needed, and sometimes the amplifier circuit 01 may introduce additional noise or nonlinear distortion.

[0037] When a signal enters the amplifier circuit 01, three different power consumption modes can be selected through the power supply and power consumption adjustment unit 017. This allows the gain to change along with the power consumption. The appropriate power consumption mode can be selected as needed by controlling the switch of the power supply and power consumption adjustment unit 017. When the amplifier circuit 01 and bypass circuit 02 are not needed, the signal can be blocked by using the shutdown mode.

[0038] Compared with existing technologies, the low-noise amplifier of this invention includes an amplification circuit and a bypass circuit. The input terminal of the amplification circuit and the first input terminal of the bypass circuit are interconnected and used to receive radio frequency signals. The second input terminal of the bypass circuit is connected to a first control voltage. The output terminal of the amplification circuit and the output terminal of the bypass circuit are connected and used to output radio frequency signals. The first control voltage is used to control the conduction or disconnection of the bypass circuit. The amplification circuit includes an input matching unit, a first amplification unit, an inter-stage matching unit, a second amplification unit, an output matching unit, a feedback unit, a power supply and power consumption adjustment unit, and a shutdown unit. The feedback unit is used for signal feedback. The power supply and power consumption adjustment unit is used to adjust the power consumption of the amplification circuit according to the second control voltage. The shutdown unit is used to control the conduction or disconnection of the amplification circuit according to a third control voltage. The low-noise amplifier of this invention includes multiple operating modes, and the operating mode of the low-noise amplifier can be controlled by the shutdown unit and the power supply and power consumption adjustment unit, thereby achieving high gain, low noise, and high applicable frequency. It has high circuit integration and low cost, while power consumption and gain are adjustable, applicable to high frequencies, and has a wider range of applications.

[0039] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0040] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A low-noise amplifier, characterized in that, The low-noise amplifier includes an amplification circuit and a bypass circuit. The input terminal of the amplification circuit and the first input terminal of the bypass circuit are connected to each other and used to receive radio frequency signals. The second input terminal of the bypass circuit is connected to a first control voltage. The output terminal of the amplification circuit and the output terminal of the bypass circuit are connected and used to output the radio frequency signals. The first control voltage is used to control the conduction or disconnection of the bypass circuit. The amplifier circuit includes an input matching unit, a first amplification unit, an interstage matching unit, a second amplification unit, an output matching unit, a feedback unit, a power supply and power consumption adjustment unit, a shutdown unit, a first resistor, and a first stabilizing capacitor. The input terminal of the input matching unit serves as the input terminal of the amplifier circuit, and the output terminal of the input matching unit is connected to the first input terminal of the first amplifier unit. The output of the first amplification unit is connected to the first input of the interstage matching unit; The output of the inter-stage matching unit is connected to the input of the second amplification unit; The output terminal of the second amplification unit is connected to the input terminal of the output matching unit, and the output terminal of the output matching unit serves as the output terminal of the amplification circuit. The first end of the feedback unit is connected to the first input end of the first amplification unit, and the second end of the feedback unit is connected to the second input end of the inter-stage matching unit; the feedback unit is used to feed the signal back to the first amplification unit. The input terminal of the power supply and power consumption adjustment unit is connected to a second control voltage; the first output terminal of the power supply and power consumption adjustment unit is connected to the second input terminal of the first amplification unit; the second output terminal of the power supply and power consumption adjustment unit is connected to the third input terminal of the interstage matching unit; the third output terminal of the power supply and power consumption adjustment unit is connected to the input terminal of the second amplification unit; the fourth output terminal of the power supply and power consumption adjustment unit is connected to the first input terminal of the first amplification unit after being connected in series with the first resistor; the power supply and power consumption adjustment unit is used to adjust the power consumption of the amplification circuit according to the second control voltage. The first terminal of the first stabilizing capacitor is grounded, and the second terminal of the first stabilizing capacitor is connected to the second input terminal of the first amplifying unit. The input terminal of the shutdown unit is connected to a third control voltage, the first output terminal of the shutdown unit is connected to the second input terminal of the first amplification unit, and the second output terminal of the shutdown unit is connected to the input terminal of the second amplification unit; the shutdown unit is used to control the amplification circuit to be turned on or off according to the third control voltage.

2. The low-noise amplifier as described in claim 1, characterized in that, The input matching unit includes a first capacitor and a first inductor; the first end of the first capacitor serves as the input terminal of the input matching unit, the second end of the first capacitor is connected to the first end of the first inductor, and the second end of the first inductor serves as the output terminal of the input matching unit.

3. The low-noise amplifier as described in claim 1, characterized in that, The feedback unit includes a second capacitor and a second resistor. The first end of the second resistor serves as the first end of the feedback unit, and the second end of the second resistor is connected to the first end of the second capacitor. The second end of the second capacitor serves as the second end of the feedback unit.

4. The low-noise amplifier as described in claim 1, characterized in that, The first amplification unit includes a first MOSFET, a second MOSFET, and a second inductor; the gate of the first MOSFET serves as the first input terminal of the first amplification unit, the source of the first MOSFET is connected to the first terminal of the second inductor, the second terminal of the second inductor is grounded, the drain of the first MOSFET is connected to the source of the second MOSFET, the gate of the second MOSFET serves as the second input terminal of the first amplification unit, and the drain of the second MOSFET serves as the output terminal of the first amplification unit.

5. The low-noise amplifier as described in claim 1, characterized in that, The interstage matching unit includes a third resistor, a third inductor, and a third capacitor; the first end of the third inductor serves as the first input terminal of the interstage matching unit, the second end of the third inductor is connected to the first end of the third capacitor and the power supply, the first end of the third capacitor serves as the second input terminal of the interstage matching unit, the second end of the third capacitor serves as the output terminal of the interstage matching unit, the first end of the third resistor is connected to the first end of the third inductor, and the second end of the third resistor serves as the third input terminal of the interstage matching unit.

6. The low-noise amplifier as described in claim 1, characterized in that, The second amplification unit includes a third MOS transistor and a fourth inductor. The gate of the third MOS transistor serves as the input terminal of the second amplification unit, the source of the third MOS transistor is connected to the first terminal of the fourth inductor, the second terminal of the fourth inductor is grounded, and the drain of the third MOS transistor serves as the output terminal of the second amplification unit.

7. The low-noise amplifier as claimed in claim 1, characterized in that, The output matching unit includes a fourth capacitor, a fifth inductor, and a fourth resistor; the first terminal of the fourth capacitor serves as the input terminal of the output matching unit, the second terminal of the fourth capacitor serves as the output terminal of the output matching unit, the first terminal of the fifth inductor is connected to the first terminal of the fourth capacitor, the second terminal of the fifth inductor is connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the power supply.

8. The low-noise amplifier as described in claim 1, characterized in that, The power supply and power consumption adjustment unit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; the input terminals of the power supply and power consumption adjustment unit include a first input terminal and a second input terminal; The first end of the fifth resistor serves as the first output terminal of the power supply and power consumption adjustment unit. The second end of the fifth resistor is connected to the first end of the sixth resistor. The first end of the sixth resistor serves as the second output terminal of the power supply and power consumption adjustment unit. The second end of the sixth resistor is connected to the first ends of the seventh resistor, the eighth resistor, and the ninth resistor, and together they serve as the fourth output terminal of the power supply and power consumption adjustment unit. The second end of the seventh resistor, the source of the fourth MOS transistor, and the source of the fifth MOS transistor are connected to each other and grounded. The second end of the eighth resistor is connected to the drain of the fourth MOS transistor. The second end of the ninth resistor is connected to the drain of the fifth MOS transistor. The gates of the fourth MOS transistor and the sixth MOS transistor are connected to each other and together they serve as the first input terminal of the power supply and power consumption adjustment unit. The gates of the fifth MOS transistor and the seventh MOS transistor are connected to each other and together they serve as the second input terminal of the power supply and power consumption adjustment unit. The first end of the tenth resistor is connected to the power supply. The second end of the tenth resistor is connected to the first end of the eleventh resistor, the first end of the twelfth resistor, the first end of the thirteenth resistor, and the first end of the fourteenth resistor. The second end of the eleventh resistor serves as the third output terminal of the power supply and power consumption adjustment unit. The second end of the twelfth resistor, the source of the sixth MOS transistor, and the source of the seventh MOS transistor are interconnected and grounded. The second end of the thirteenth resistor is connected to the drain of the sixth MOS transistor, and the second end of the fourteenth resistor is connected to the drain of the seventh MOS transistor.

9. The low-noise amplifier as claimed in claim 1, characterized in that, The shutdown unit includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a fifth capacitor, a sixth capacitor, a first diode, and a second diode; The first terminal of the fifteenth resistor and the first terminal of the twenty-third resistor are interconnected and together serve as the input terminal of the turn-off unit. The second terminal of the fifteenth resistor is connected to the first terminal of the sixteenth resistor and the gate of the eighth MOS transistor. The second terminal of the sixteenth resistor is connected to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is grounded. The source of the eighth MOS transistor is connected to the first terminal of the seventeenth resistor and the gate of the ninth MOS transistor. The drain of the eighth MOS transistor is connected to the first terminal of the eighteenth resistor. The second terminal of the seventeenth resistor is grounded. The source of the ninth MOS transistor is connected to the first terminal of the twentieth resistor and the first terminal of the twenty-first resistor, and the second terminal of the twentieth resistor is grounded. The drain of the ninth MOS transistor is connected to the second terminal of the eighteenth resistor, the first terminal of the nineteenth resistor, the second terminal of the twenty-first resistor, and the tenth resistor. The gates of a MOSFET and a twelfth MOSFET are connected. The second terminal of the nineteenth resistor is connected to the source of the tenth MOSFET. The gate of the tenth MOSFET is connected to the second terminal of the twenty-third resistor. The drain of the tenth MOSFET is connected to the cathode of the first diode. The anode of the first diode is connected to the cathode of the second diode. The anode of the second diode is connected to the first terminal of the twenty-third resistor. The first terminal of the twenty-second resistor is connected to the gate of the eleventh MOSFET. The second terminal of the twenty-second resistor is grounded. The first terminal of the sixth capacitor is connected to the gate of the eleventh MOSFET. The second terminal of the sixth capacitor is connected to the source of the twelfth MOSFET. The source of the eleventh MOSFET is grounded. The drain of the eleventh MOSFET serves as the first output terminal of the shutdown unit. The drain of the twelfth MOSFET serves as the second output terminal of the shutdown unit.

10. The low-noise amplifier as claimed in claim 1, characterized in that, The bypass circuit includes a seventh capacitor, an eighth capacitor, a thirteenth MOSFET, and a twenty-fourth resistor. The first terminal of the seventh capacitor serves as the first input terminal of the bypass circuit, the second terminal of the seventh capacitor is connected to the drain of the thirteenth MOSFET, the gate of the thirteenth MOSFET serves as the second input terminal of the bypass circuit, the source of the thirteenth MOSFET is connected to the first terminal of the twenty-fourth resistor, the second terminal of the twenty-fourth resistor is connected to the first terminal of the eighth capacitor, and the second terminal of the eighth capacitor serves as the output terminal of the bypass circuit.

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