A novel random phase difference real-time mapping system

Abstract

This invention discloses a novel real-time random phase difference mapping system, comprising: a real-time random phase difference measurement unit for capturing the random phase difference between an external trigger signal and a system clock signal, and outputting a start node signal START and an end node signal STOP; and a time amplitude mapping unit, including a capacitor initial voltage circuit, a capacitor charging circuit, and a voltage holding sub-circuit. The START signal initiates capacitor charging, and the STOP signal locks the capacitor terminal voltage, linearly mapping the phase difference to voltage amplitude. The voltage holding sub-circuit operates in analog mode when the holding time does not exceed a threshold; after exceeding the threshold, it switches to digital drive mode, with the digital-to-analog converter output replacing the capacitor voltage, fundamentally eliminating voltage drops caused by analog leakage and achieving long-term drift-free, high-precision holding. The measurement range is extended by cascading multiple internal clock triggers, effectively eliminating the metastable measurement blind zone of boundary phase differences; and the range is flexibly configured through an adjustable reference voltage source and an adjustable constant current source.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement technology, and in particular to a novel real-time mapping technology for random phase differences. Background Technology

[0002] This invention belongs to the field of electronic measurement and signal processing technology, specifically relating to a high-precision time interval measurement technology, and more particularly to a circuit module for real-time measurement and linear mapping of the random phase difference between an external asynchronous trigger signal and the system clock. In radar detection, LiDAR, high-energy physics experiments, and high-speed automated testing equipment, accurately capturing the arrival time of external random events (trigger signals) relative to the system's internal clock is crucial, and its measurement accuracy directly determines the overall performance of the system.

[0003] In existing time measurement techniques, a combination of "coarse counting + fine measurement" is typically used. For minute time differences (i.e., random phase differences) less than one system clock cycle, time-to-amplitude conversion (TAC) technology is often used to convert the time interval into a voltage signal for processing. However, traditional TAC circuits have several limitations: First, most circuits have fixed integration starting voltage and charging slope, making it impossible to flexibly adjust the dynamic range according to different measurement duration requirements, resulting in limited accuracy when measuring extremely short or long phase differences; second, after the analog integrator circuit completes the conversion, it relies on a capacitor to store the voltage for subsequent ADC acquisition, but due to the influence of capacitor dielectric absorption, leakage current, and op-amp input bias current, there is an unavoidable "drop" or drift phenomenon during the voltage holding phase, making it impossible to achieve high-precision holding for a long time, which severely limits the reading speed and processing timing of the back-end system. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a real-time random phase difference mapping system that can flexibly configure the range and achieve long-term high-precision voltage maintenance.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is a novel real-time random phase difference mapping system, comprising:

[0006] The random phase difference real-time measurement unit is used to receive an external trigger signal and a system clock signal, capture the rising edge of the external trigger signal as the start node of the time interval, and capture the rising edge of the system clock signal as the end node of the time interval, so as to extract the time information corresponding to the random phase difference between the external trigger signal and the system clock signal, and output the corresponding start node signal START and end node signal STOP.

[0007] A time-amplitude mapping unit is used to receive the START signal and the STOP signal. The time-amplitude mapping unit includes a capacitor initial voltage circuit, a capacitor charging circuit, and a voltage holding sub-circuit.

[0008] The capacitor initial voltage circuit is configured to include an adjustable reference voltage source for providing the initial charging voltage of the controllable charging capacitor; the capacitor charging circuit is configured to include an adjustable constant current source for charging the controllable charging capacitor; the time amplitude mapping unit responds to a START signal to trigger the capacitor charging circuit to start charging, and responds to a STOP signal to trigger a voltage holding sub-circuit to lock the terminal voltage of the controllable charging capacitor, thereby realizing a linear mapping of time information corresponding to random phase differences into amplitude signals;

[0009] The voltage holding sub-circuit is configured to operate in analog holding mode when the holding time does not exceed a preset threshold; and to switch from analog holding mode to digital drive mode when the holding time exceeds the preset threshold, thereby outputting the terminal voltage of the controllable charging capacitor through a digital-to-analog converter to achieve long-term voltage holding.

[0010] Furthermore, the real-time random phase difference measurement unit also includes multi-stage internal clock triggers; after the START signal is processed by the multi-stage internal clock triggers, its output signal is forced to align with the internal system clock; the random phase difference occurs before the first-stage internal clock trigger operates, and the time difference between the actions of the internal clock triggers is equal to the system clock cycle. The time from the occurrence of the actual random phase difference to the action of the first-stage internal clock trigger is defined as the phase time difference X.

[0011] Furthermore, the capacitor charging circuit satisfies the charging slope K=I / C, where I is the charging current provided by the adjustable constant current source, and C is the capacitance value of the controllable charging capacitor.

[0012] Furthermore, in digital drive mode, the system obtains the digital quantity corresponding to the current capacitor voltage through analog-to-digital conversion in the early stage of the analog hold phase. During switching, the digital quantity is placed into the digital-to-analog converter, so that the output of the digital-to-analog converter is at the same potential as the current capacitor terminal voltage. The connection between the capacitor and the output buffer operational amplifier is disconnected, and the output of the digital-to-analog converter is connected to the input terminal of the operational amplifier.

[0013] This invention proposes a novel real-time random phase difference mapping system. Employing an architecture of edge-triggered and multi-stage internal clock triggers cascaded, it can accurately extract the phase time difference between the external trigger signal and the system clock. By introducing an adjustable reference voltage source and an adjustable constant current source, and flexibly configuring the initial voltage and charging slope of the integrator circuit, it can adapt to different measurement range requirements. More importantly, this invention designs a voltage holding sub-circuit with switching characteristics and innovatively combines it with digital domain control. Under long-term holding requirements, it uses the DAC output to replace the analog capacitor voltage, fundamentally solving the problem of analog signal drift over time and achieving high linearity and high stability time-amplitude mapping.

[0014] The beneficial effects of this invention are:

[0015] 1. Achieve long-term drift-free voltage maintenance

[0016] In traditional solutions, capacitor voltage can only be maintained for tens of microseconds due to leakage, and even with the introduction of operational amplifier buffers, the duration can only be extended to the millisecond level, making drift unavoidable. This invention innovatively proposes a hybrid analog and digital architecture for the voltage holding sub-circuit. When the holding time is detected to be approaching the preset threshold of the analog device, instead of continuing to optimize the analog loop, control is transferred to the digital domain: first, the ADC acquires the current capacitor voltage, and then the DAC reconstructs the output at the same potential and replaces the capacitor. This fundamentally eliminates voltage drops caused by analog leakage, achieving stable output with quasi-DC characteristics under long-term observation, and removing the stringent timing constraints of the back-end acquisition.

[0017] 2. Improve the reliability of boundary phase difference acquisition

[0018] By employing a multi-stage cascaded internal clock trigger structure, the total measurement interval is extended to X+nT. s This allows the boundary phase difference, which was originally close to the clock edge and prone to falling into the metastable window, to be far away from the action time of the first stage flip-flop on the extended time scale, thereby effectively eliminating the inherent measurement blind zone of a single-stage flip-flop and ensuring the reliability of phase difference capture across the entire range.

[0019] 3. Balancing accuracy and dynamic range

[0020] By using an adjustable reference voltage source and an adjustable constant current source, the initial charging voltage and charging slope can be adjusted independently, allowing the mapped voltage range to be flexibly scaled according to the measured phase difference range, thus avoiding the accuracy loss of fixed parameter circuits under extreme ranges. Attached Figure Description

[0021] Figure 1 This is a structural block diagram of a real-time random phase difference mapping system provided in an embodiment of the present invention;

[0022] Figure 2This is a timing diagram of a real-time random phase difference mapping system provided in an embodiment of the present invention; Figure 2 In the diagram, A: fixed delay, B: shortest capacitor charging time, c: longest capacitor charging time, D: self-reset recovery time, V0: initial voltage, V1: minimum holding voltage after charging, and V2: maximum holding voltage after charging. Detailed Implementation

[0023] Figure 1 This is a block diagram of a real-time random phase difference mapping system.

[0024] In this embodiment, as Figure 1 As shown, this system mainly includes a random phase difference real-time measurement unit and a time amplitude mapping unit.

[0025] The random phase difference real-time measurement unit is equipped with a synchronization circuit and a gating circuit, and includes a trigger source interface, an edge-triggered D flip-flop, and a high-precision fixed delay device. The trigger source interface is used to connect an external trigger signal and a system clock signal. The edge-triggered D flip-flop captures the rising edge of the external trigger signal after being delayed by the high-precision fixed delay device as the start node of the time interval, and captures the rising edge of the system clock signal as the end node of the time interval, to extract the time information corresponding to the random phase difference between the external trigger signal and the system clock signal. This time information specifically includes the start node time, the end node time, and the corresponding start node signal START and end node signal STOP.

[0026] Among them, high-precision fixed-delay devices are used to compensate for the inherent delay of the signal transmission path, ensuring that the phase relationship between the external trigger signal and the system clock signal is accurately transmitted to subsequent timing circuits; the end-of-line signal STOP is generated by the output of the last stage of the cascaded internal clock flip-flop. This cascaded structure expands the total time interval from the START signal to the STOP signal to the sum of the phase time difference X and n system clock cycles, i.e. This provides a sufficient charging time window for the subsequent time-amplitude mapping unit and effectively eliminates the metastable measurement blind zone of a single-stage trigger under boundary phase difference.

[0027] When a trigger signal is detected, the pre-trigger unit is activated and sets the relevant devices in the system to a ready-to-trigger state. Since both the pre-trigger unit and the triggering device are activated by the same trigger signal, a timing delay link needs to be set between the pre-trigger unit and the triggering device to ensure the triggering device responds to the trigger after the pre-trigger unit has completed initialization. This ensures the rationality of the triggering timing. After the triggering device responds to the trigger, it generates a mapping start node signal START, which serves as the starting marker for the time-amplitude mapping process. After being processed by multiple internal clock flip-flops in the circuit link, the output signal of this signal is forced to align with the internal system clock. From a timing perspective, the random phase difference occurs before the first-stage internal clock flip-flop operates, and the time difference between the actions of the internal clock flip-flops is equal to the system clock cycle. Therefore, a random phase difference can occur before the operation of the first-stage internal clock trigger. At any point within the time period, the time from the actual random phase difference occurrence to the action of the first-stage internal clock trigger is defined as the phase time difference X. Since the phase time difference X needs to be converted into a voltage signal through a time amplitude mapping unit, the required level can be set by cascading multiple internal clock triggers.

[0028] An n-stage flip-flop is cascaded after the first-stage internal clock flip-flop; since the action time difference between the internal clock flip-flops is equal to the system clock cycle. (Default phase time difference X and) (Since they are of the same order of magnitude), the time from the appearance of the random phase difference to the action of the last stage trigger is... This duration is the charging time of the capacitor in the time amplitude mapping unit; when selecting the number of cascaded capacitors, it is necessary to consider the limiting voltage of the subsequent capacitors and the power supply voltage of the circuit, so that the capacitors pass through... The voltage after charging is within a suitable range.

[0029] The time amplitude mapping unit is used to receive the start node signal START and the end node signal STOP output by the random phase difference real-time measurement unit; the time amplitude mapping unit includes a switch control unit and a capacitor initial voltage circuit, a capacitor charging circuit and a voltage holding sub-circuit controlled by it.

[0030] The switch control unit controls the on / off state of subsequent circuit modules based on the received start and stop signals (START and STOP). The capacitor initial voltage circuit is configured to include an adjustable reference voltage source to calibrate the initial charging voltage of the controllable charging capacitor. The capacitor charging circuit is configured to include an adjustable constant current source to regulate the charging slope of the controllable charging capacitor. The time-amplitude mapping unit, through the logic scheduling of the switch control unit, triggers the capacitor charging circuit to start charging in response to the start signal (START) and triggers the voltage holding sub-circuit to lock the terminal voltage of the controllable charging capacitor in response to the stop signal (STOP), thereby achieving a linear mapping of time information corresponding to random phase differences into amplitude signals.

[0031] Key information for capacitor charging circuits includes the initial charging voltage. Charging end voltage The charging slope K is such that the external adjustable reference voltage circuit needs to have switching characteristics to achieve the switching from the initial state to the charging state; the charging circuit also needs to have switching characteristics to maintain the charging end voltage.

[0032] For the capacitor charging slope K, based on the core formula of capacitor charging... The quantitative relationship between it and the charging current I can be derived:

[0033] ;

[0034] Wherein, C is the capacitance value. After selection, the value of C is fixed, and its value will affect the order of magnitude of K. The specific selection is determined according to the user's needs. The circuit needs to ensure that the charging current I is stable. In combination with the limiting conditions of claim 2, the capacitor charging circuit needs to have switching characteristics. Therefore, the circuit includes a switching circuit and a constant current source. Similarly, the capacitor initial voltage circuit also includes a switching circuit and a voltage source.

[0035] Based on the time dimension, the effective range of each circuit can be divided into three stages: (1) (2) (3) after.

[0036] The capacitor initial voltage circuit, charging circuit, and voltage holding sub-circuit respectively act on the above three stages. Charging begins at the moment the START signal is generated (the rising edge of the external trigger), and the capacitor initial voltage circuit is cut off. The STOP signal is generated at the rising edge of the system clock, marking the end of charging and the activation of the voltage holding sub-circuit. Before the START signal arrives, the capacitor initial voltage circuit begins to provide the initial voltage, corresponding to stage (1). When the START signal arrives but the STOP signal has not arrived, the capacitor initial voltage circuit is turned off and the charging circuit is turned on, allowing the capacitor to charge, corresponding to stage (2). Finally, when the STOP signal arrives, the charging circuit is turned off, and the voltage holding sub-circuit begins to function, corresponding to stage (3).

[0037] Phase (1) Initial voltage circuit of capacitor

[0038] In practical applications, the voltage source can be one output of a DAC, which is then inverted and amplified to a suitable voltage via an operational amplifier circuit and a matched resistor value. This voltage serves as the bottom clamping voltage (i.e., minimum voltage) of the initial voltage circuit. After the minimum voltage is fixed by the operational amplifier circuit, subsequent circuits need to boost the voltage. Since the initial voltage is positive, two diodes are added at the clamping point to ensure unidirectional conduction (the forward voltage drop of a single diode is approximately 0.5V, and a boost of approximately 1V can be achieved after reverse connection). Because the effective period of this circuit ends at... Time, therefore includes The START signal at a given time needs to be applied to this part of the circuit. Therefore, the START signal is connected to one end of another operational amplifier, and the operational amplifier and feedback network are used to adjust the voltage value of a certain node.

[0039] This part of the circuit includes the operational amplifier connected to one end, and a minimum voltage with a boost amplitude of approximately 1V. The other end of the operational amplifier needs to be connected to a specific boost circuit and the minimum voltage. This allows one end of the capacitor to obtain an initial voltage value, and the START signal can adjust this initial voltage value to increase the voltage. The operational amplifier's proportional amplifier circuit is the preferred circuit for this part; the minimum voltage... Through resistance This node is connected to the other end of the operational amplifier, and is also connected to another resistor. The output of the operational amplifier circuit is obtained accordingly. for:

[0040] ;

[0041] in, This refers to the output voltage of the operational amplifier circuit. The high-level voltage of the start node signal; This is the bottom clamping voltage (minimum voltage reference) of the capacitor initial voltage circuit. For connection in The input resistance between the op-amp and its inverting input terminal; This is the feedback resistor connected between the inverting input and output terminals of the operational amplifier.

[0042] Since all the circuit components mentioned above operate on the same capacitor, isolation between each component is necessary. Connect a diode to the capacitor in reverse; based on the voltage continuity characteristic of the capacitor, when... When the time arrives, the START signal goes high. Due to the control effect of the switch, the diode changes from the conducting state to the cut-off state, thereby realizing the switching and isolation of the capacitor initial voltage circuit.

[0043] Phase (2) Capacitor charging circuit

[0044] when When the time arrives, the capacitor initial voltage circuit fails, and at this time the initial charging voltage... satisfy:

[0045]

[0046] Capacitor based on the During charging, the core objective of this stage is to ensure the stability of the charging slope K. Since the constant current source is the key component for maintaining K stability, a constant current source needs to be designed. This constant current source adopts a high-side voltage-controlled architecture based on an operational amplifier to achieve precise control of the load current: the DAC input control signal is first impedance isolated by a unity-gain buffer, and then connected to a differential error amplification stage composed of another operational amplifier and a precision resistor array. By monitoring the voltage drop across the sampling resistor in real time, and using a negative feedback mechanism to dynamically adjust the base current of the PNP regulating transistor, the conduction degree of its emitter-collector is changed, so that the current flowing through the load strictly follows the changes in the input control voltage. At the same time, the integrating capacitor introduced in the circuit provides phase compensation for the feedback loop, effectively suppressing self-oscillation caused by high-frequency noise.

[0047] After the constant current source design is completed, the stop signal (STOP) needs to be introduced into the circuit to ensure that... When the time arrives, the charging circuit is cut off and the constant current source stops supplying power to the capacitor. This part adopts a high-speed current-guided switching mechanism based on PNP transistor differential pairs. The switching circuit used to respond to the STOP signal can adopt a differential switch structure to quickly cut off the charging path to the controllable charging capacitor when the STOP signal arrives. The STOP signal exists in the form of differential signals STOP_P and STOP_N. After impedance matching and level shifting by a buffer stage composed of two transistors, the differential signals are applied to the bases of the two differential switching transistors respectively. The circuit establishes a voltage difference between the bases of the two switching transistors by reversing the polarity of the input signal, so that the common emitter current is quickly and completely switched between branches, thereby realizing signal on / off control with high common-mode rejection ratio and fast response characteristics.

[0048] In summary, the overall structure of the charging circuit in this stage is a constant current source combined with a differential pair switching circuit. In this stage, the phase time difference X corresponding to the random phase difference is mapped to the corresponding voltage value within a preset voltage range. In practical applications, the specific value of the phase time difference X can be determined by observing the position of the voltage within this range.

[0049] Phase (3) Next: Voltage holding sub-circuit

[0050] Without additional control, the passive hold-up time of the capacitor is only... Therefore, a voltage holding sub-circuit is introduced to ensure that the holding time of the measurement results meets the user's subsequent requirements.

[0051] To address the voltage drop issue caused by the leakage current of the sampling capacitor, the circuit enters an active feedback hold mode by closing a switch using sequential logic. In this stage, the operational amplifier intervenes, constructing a high-input-impedance closed-loop buffer system. The high impedance of the op-amp is used to read the voltage of the sampling capacitor, and its low-impedance drive capability is used to maintain the output node level. The maximum hold time in this mode is [duration missing]. Applicable to The need to maintain.

[0052] When the holding time exceeds Due to the physical limitations of analog devices, the analog sample-and-hold method cannot eliminate long-term drift errors. At this point, the system activates a control signal, transferring control to the digital domain. Specifically, in the early stages of the analog hold phase, the system initiates a fast analog-to-digital conversion to acquire the digital value corresponding to the current capacitor voltage. When the timer determines that the hold duration is approaching 3ms, the system generates a switching enable signal, setting the input of the digital-to-analog converter to the aforementioned digital value, causing its output to be at the same analog level as the current capacitor terminal voltage. Simultaneously, the connection between the capacitor and the output buffer operational amplifier is disconnected, and the output of the digital-to-analog converter is connected to the input of this operational amplifier, achieving a seamless switch from analog hold to digital drive.

[0053] Compared to traditional analog hold-up schemes where voltage drops continuously after 3ms due to leakage, this embodiment, after switching to digital-to-analog converter (DAC) drive mode, ensures that the output voltage stability is determined solely by the quantization noise of the DAC. Under long-term macroscopic observation, the average voltage variation is less than one least significant bit, achieving stable output with quasi-DC characteristics. This fundamentally eliminates the stringent timing requirements of the backend data acquisition window, ensuring the stability and accuracy of the system during long-term operation.

[0054] During the holding phase, the back-end analog-to-digital converter samples and quantizes the output voltage of the voltage holding sub-circuit. The system then calculates the voltage based on the sampled voltage value according to the preset charging slope K and cascade parameter n. The precise value of the random phase difference X is calculated, completing the measurement closed loop from time to amplitude and from amplitude to time.

[0055] Figure 2 This is a timing diagram of a real-time random phase difference mapping system provided in an embodiment of the present invention;

[0056] like Figure 2 As shown, under ideal holding conditions, the charging end voltage of the capacitor is the initial holding voltage of the holding phase. The charging end voltage (i.e., minimum holding voltage) corresponding to the minimum value of phase difference X. The charging end voltage (i.e., the maximum holding voltage) corresponding to the maximum value of the phase difference X. and It means The charging end voltage at a given moment also indicates the target holding voltage value for the subsequent holding phase.

[0057] In this embodiment, the system clock is 100MHz, and the initial charging voltage of the charging circuit is... Charging end voltage For the capacitor charging slope K, based on the core formula for capacitor charging, the amount of charge... Where C is capacitance and U is voltage, their quantitative relationship with the charging current I can be derived:

[0058] ;

[0059] For the first stage after a fixed delay, that is, the range of 0-7ns:

[0060] ;

[0061] Because a resistor of approximately 50Ω is connected next to the capacitor, and the current is 10mA, the initial voltage... :

[0062] ;

[0063] The high level of the START signal is 2.5V, and the reference voltage of the digital-to-analog converter (DAC) is 4.096V. The actual voltage is approximately 4.5V as shown in the diagram. Since only two internal clock triggers are connected (the START signal is aligned to the system clock domain by the first internal clock trigger, and then outputs the STOP signal via a cascaded internal clock trigger), the time difference between the action time of the first internal clock trigger and the occurrence time of the random phase difference is the phase time difference X, while the action time difference between the two internal clock triggers is the system clock cycle. Therefore, the total charging time for:

[0064] ;

[0065] Change in capacitor terminal voltage during charging satisfy:

[0066] ;

[0067] This involves linearly mapping the random phase difference X to a direct representation of the voltage amplitude. By measuring the specific position of the final holding voltage within the V1~V2 range, the precise value of X can be deduced. In this embodiment, the minimum final holding voltage is approximately 5.8V for V1 and approximately 6.8V for V2. After the conversion ends and the capacitor discharges to its initial level, the value of the random phase difference can be measured again.

[0068] In applications requiring long-term hold, compared to traditional analog hold circuits where voltage drops are caused by leakage, this embodiment, after entering the digital hold stage, has its output characteristics dominated by the DAC, and voltage stability is limited only by the DAC's quantization error, thus exhibiting quasi-DC characteristics on a macroscopic time scale.

Claims

1. A novel real-time random phase difference mapping system, characterized in that, include: The random phase difference real-time measurement unit is used to receive an external trigger signal and a system clock signal, capture the rising edge of the external trigger signal as the start node of the time interval, and capture the rising edge of the system clock signal as the end node of the time interval, so as to extract the time information corresponding to the random phase difference between the external trigger signal and the system clock signal, and output the corresponding start node signal START and end node signal STOP. A time-amplitude mapping unit is used to receive the START signal and the STOP signal. The time-amplitude mapping unit includes a capacitor initial voltage circuit, a capacitor charging circuit, and a voltage holding sub-circuit. The capacitor initial voltage circuit is configured to include an adjustable reference voltage source for providing the initial charging voltage of the controllable charging capacitor; the capacitor charging circuit is configured to include an adjustable constant current source for charging the controllable charging capacitor; the time amplitude mapping unit responds to a START signal to trigger the capacitor charging circuit to start charging, and responds to a STOP signal to trigger a voltage holding sub-circuit to lock the terminal voltage of the controllable charging capacitor, thereby realizing a linear mapping of time information corresponding to random phase differences into amplitude signals; The voltage holding sub-circuit is configured to operate in analog holding mode when the holding time does not exceed a preset threshold; and to switch from analog holding mode to digital drive mode when the holding time exceeds the preset threshold, thereby outputting the terminal voltage of the controllable charging capacitor through a digital-to-analog converter to achieve long-term voltage holding.

2. The system as described in claim 1, characterized in that, The random phase difference real-time measurement unit includes an edge-triggered D flip-flop and a high-precision fixed delay device; the edge-triggered D flip-flop is used to capture the rising edge of the external trigger signal as the start node, and to capture the rising edge of the system clock signal calibrated by the high-precision fixed delay device as the end node.

3. The system as described in claim 1, characterized in that, The random phase difference real-time measurement unit also includes a multi-level internal clock trigger; after the START signal is processed by the multi-level internal clock trigger, its output signal is forced to align with the internal system clock. The random phase difference occurs before the first-stage internal clock trigger operates, and the time difference between the actions of the internal clock triggers is equal to the system clock cycle. The time from the occurrence of the actual random phase difference to the action of the first-stage internal clock trigger is defined as the phase time difference X.

4. The system as described in claim 3, characterized in that, After the first-stage internal clock flip-flop, n stages of flip-flops are cascaded. The time from the occurrence of the random phase difference to the activation of the last stage flip-flop is: This duration is the charging time of the capacitor in the time amplitude mapping unit.

5. The system as described in claim 1, characterized in that, The capacitor charging circuit satisfies the charging slope K=I / C, where I is the charging current provided by the adjustable constant current source, and C is the capacitance value of the controllable charging capacitor.

6. The system as described in claim 1, characterized in that, The effective range of each circuit is divided into three stages based on the time dimension: stage, stage, The next stage; among which The time when the START signal is generated. This is the time when the STOP signal is generated; exist During this phase, the capacitor initial voltage circuit operates to provide the initial charging voltage; exist During this phase, the capacitor charging circuit operates, and the adjustable constant current source charges the controllable charging capacitor. exist In subsequent stages, the voltage holding sub-circuit operates to lock and maintain the terminal voltage of the controllable charging capacitor.

7. The system as described in claim 6, characterized in that, In the Phase, the change in capacitor terminal voltage during the charging phase ,in The charging time is used to calculate the phase time difference X by measuring the position of the final holding voltage within the preset voltage range.

8. The system as described in claim 1, characterized in that, In the digital drive mode, during the early stage of the analog hold phase, the system obtains the digital quantity corresponding to the current capacitor voltage through analog-to-digital conversion. During the switching, the digital quantity is loaded into the digital-to-analog converter, so that the output of the digital-to-analog converter is at the same potential as the current capacitor terminal voltage. The output of the digital-to-analog converter is connected to the input terminal of the operational amplifier to achieve continuous maintenance of the capacitor terminal potential.

9. The system as described in claim 1, characterized in that, The preset threshold is 3ms.

10. The system as claimed in claim 1, characterized in that, The time amplitude mapping unit also includes a switch control unit, which controls the conduction and cutoff of the capacitor initial voltage circuit, capacitor charging circuit and voltage holding sub-circuit according to the state of the received START signal and STOP signal.

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