Semiconductor memory device

Abstract

A semiconductor memory device includes: a channel pattern; a gate electrode layer configured to surround at least a portion of each of an upper surface and a lower surface of the channel pattern and extend in a first horizontal direction; a bit line structure connected to a first end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction and configured to extend in a vertical direction; a capacitor structure connected to a second end of the channel pattern in the second horizontal direction; a gate dielectric layer located between the channel pattern and the gate electrode layer and configured to cover the upper surface, the lower surface, and two side surfaces in the first horizontal direction of the channel pattern; and a bit line shield structure located on both sides of the bit line structure in the first horizontal direction and configured to extend in the vertical direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor storage device. Background Technology

[0002] With the increasing demands for miniaturization, multifunctionality, and high performance in electronic products, high-capacity semiconductor memory devices are needed. Therefore, to provide high-capacity semiconductor memory devices, it is necessary to increase their integration density. Since the integration density of traditional two-dimensional semiconductor memory devices is mainly determined by the area occupied by a single memory cell, the integration density of two-dimensional semiconductor memory devices is increasing, but is still limited. This paper proposes a three-dimensional semiconductor memory device that increases storage capacity by vertically stacking multiple memory cells on a substrate. Summary of the Invention

[0003] This disclosure relates to a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device.

[0004] This disclosure provides a three-dimensional semiconductor memory device that improves operational reliability and operational characteristics, and can increase integration density by simplifying the manufacturing process.

[0005] According to one aspect of this disclosure, a semiconductor memory device includes: a channel pattern; a gate electrode layer configured to surround at least a portion of each of an upper surface and a lower surface of the channel pattern and extending in a first horizontal direction; a bit line structure connected to one end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction and configured to extend in a vertical direction; a capacitor structure connected to the other end of the channel pattern in the second horizontal direction; and a gate dielectric layer disposed between the channel pattern and the gate electrode layer and configured to cover... The channel structure includes an upper surface, a lower surface, and two side surfaces in the first horizontal direction covering the channel pattern; and a bit line shielding structure disposed on both sides of the bit line structure in the first horizontal direction and configured to extend in the vertical direction, wherein the gate dielectric layer comprises: a substrate insulating layer covering at least one of the upper surface and the lower surface of the channel pattern; and a channel cover insulating layer covering the upper surface, the lower surface, and two side surfaces in the first horizontal direction of the channel structure, the channel structure including the channel pattern and the substrate insulating layer.

[0006] According to another aspect of this disclosure, a semiconductor memory device includes: a plurality of channel patterns separated from each other in a first horizontal direction, a second horizontal direction orthogonal to the first horizontal direction, and a vertical direction; a plurality of gate electrode layers, each gate electrode layer surrounding at least a portion of an upper surface and a lower surface of each of the plurality of channel patterns and extending in the first horizontal direction; a plurality of bit line structures connected to a first end of the plurality of channel patterns in the second horizontal direction, separated from each other in the first horizontal direction, and configured to extend in the vertical direction; a plurality of bit line shielding structures arranged alternately with the plurality of bit line structures in the first horizontal direction and configured to extend in the vertical direction; and a plurality of electrical... A container structure, wherein the plurality of capacitor structures are connected to the second ends of the plurality of channel patterns in the second horizontal direction; and a plurality of gate dielectric layers, the plurality of gate dielectric layers being disposed between the plurality of channel patterns and the plurality of gate electrode layers, configured to respectively cover the upper surface, the lower surface and two side surfaces in the first horizontal direction of the plurality of channel patterns, wherein each of the plurality of gate dielectric layers includes: a pair of substrate insulating layers, the pair of substrate insulating layers respectively covering the upper surface and the lower surface of each of the plurality of channel patterns; and a channel covering insulating layer, the channel covering insulating layer covering the upper surface, the lower surface and the two side surfaces in the first horizontal direction of the channel structure, the channel structure including each of the plurality of channel patterns and the pair of substrate insulating layers.

[0007] According to another aspect of this disclosure, a semiconductor memory device includes: a plurality of channel patterns, the plurality of channel patterns being separated from each other in a first horizontal direction, a second horizontal direction orthogonal to the first horizontal direction, and a vertical direction, and each comprising an oxide semiconductor material; a plurality of gate electrode layers, the plurality of gate electrode layers being configured to surround at least a portion of an upper surface and a lower surface of each of the plurality of channel patterns, and extending in the first horizontal direction; a plurality of bit line structures, the plurality of bit line structures being connected to a first end of the plurality of channel patterns in the second horizontal direction, being separated from each other in the first horizontal direction, and being configured to extend in the vertical direction, and each of the plurality of bit line structures including a core conductive layer and an oxide semiconductor layer, the oxide semiconductor layer being located between the core conductive layer and each of the plurality of channel patterns; and a plurality of bit line shielding structures, the plurality of bit line shielding structures being located in the first horizontal direction. The plurality of bit line structures are arranged alternately and configured to extend in the vertical direction and are separated from the plurality of channel patterns; a plurality of capacitor structures are connected to the second ends of the plurality of channel patterns in the second horizontal direction; and a plurality of gate dielectric layers are respectively disposed between the plurality of channel patterns and the plurality of gate electrode layers and configured to respectively cover the upper surface, lower surface and two side surfaces in the first horizontal direction of the plurality of channel patterns, wherein each of the plurality of gate dielectric layers includes: a pair of substrate insulating layers that respectively cover the upper surface and lower surface of each of the plurality of channel patterns; and a channel cover insulating layer that covers the upper surface, lower surface and two side surfaces in the first horizontal direction of the channel structure, the channel structure including each of the plurality of channel patterns and the pair of substrate insulating layers.

[0008] According to another aspect of this disclosure, a method of manufacturing a semiconductor memory device includes: forming a plurality of sacrificial insulating layers, a plurality of substrate insulating layers, and a plurality of sacrificial semiconductor layers on a substrate; partially removing the plurality of sacrificial insulating layers, the plurality of substrate insulating layers, and the plurality of sacrificial semiconductor layers to form a plurality of first element isolation cleaving regions separated from each other in a first horizontal direction and extending in a second horizontal direction orthogonal to the first horizontal direction; partially removing the plurality of sacrificial insulating layers, the plurality of substrate insulating layers, and the plurality of sacrificial semiconductor layers to form a plurality of second element isolation cleaving regions and a plurality of capacitor isolation cleaving regions, the second element isolation cleaving regions and the capacitor isolation cleaving regions being separated from each other and alternately arranged in the second horizontal direction and extending in the first horizontal direction; partially removing the plurality of sacrificial insulating layers, the plurality of substrate insulating layers, and the plurality of sacrificial semiconductor layers through the plurality of capacitor isolation cleaving regions; and forming a plurality of capacitor junctions in the space in which a portion of each of the plurality of substrate insulating layers and a portion of each of the plurality of sacrificial semiconductor layers has been removed. The plurality of capacitor structures include a plurality of first electrodes, a plurality of second electrodes covering the plurality of first electrodes, and a plurality of capacitor dielectric layers disposed between the plurality of first electrodes and the plurality of second electrodes; the plurality of sacrificial semiconductor layers are removed through the plurality of second element isolation dicing regions, and then a plurality of channel patterns are formed in the space where the plurality of sacrificial semiconductor layers have been removed; the plurality of sacrificial insulating layers are removed through the plurality of first element isolation dicing regions and the plurality of second element isolation dicing regions, and then a plurality of channel cover insulating layers are formed in a portion of each of the plurality of first element isolation dicing regions and a portion of the space where the plurality of sacrificial insulating layers have been removed, and a plurality of gate dielectric layers including the plurality of substrate insulating layers and the plurality of channel cover insulating layers are formed; a plurality of gate electrode layers covering the plurality of channel cover insulating layers are formed; and a plurality of bit line structures are formed, the plurality of bit line structures being connected to a first end of the plurality of channel patterns opposite to the plurality of first electrodes, being separated from each other in a first horizontal direction, and extending in the vertical direction.

[0009] The plurality of sacrificial insulating layers, the plurality of substrate insulating layers, and the plurality of sacrificial semiconductor layers can be formed by a deposition process.

[0010] The plurality of substrate insulating layers can be respectively disposed between the plurality of sacrificial insulating layers and the plurality of sacrificial semiconductor layers.

[0011] The plurality of sacrificial insulating layers, the plurality of sacrificial semiconductor layers, and the plurality of substrate insulating layers may be alternately stacked on the substrate.

[0012] The plurality of sacrificial insulating layers, the plurality of substrate insulating layers, and the plurality of sacrificial semiconductor layers may be alternately stacked on the substrate.

[0013] Each of the plurality of channel patterns may comprise an oxide semiconductor material. The plurality of gate electrode layers may be formed such that the horizontal width of each of the plurality of gate electrode layers in the second horizontal direction is smaller than the horizontal width of each of the plurality of channel patterns.

[0014] The method may further include forming a plurality of bit line shielding structures, which are arranged alternately with the plurality of bit line structures in the first horizontal direction and extend in the vertical direction.

[0015] The plurality of bit line shielding structures can be configured such that the horizontal width of each of the plurality of bit line shielding structures in the first horizontal direction is smaller than the horizontal width of each of the plurality of bit line structures in the first horizontal direction, and the horizontal width of each of the plurality of bit line shielding structures in the second horizontal direction is equal to the horizontal width of the plurality of bit line structures in the second horizontal direction.

[0016] Each of the plurality of bit line structures may include a core conductive layer and an oxide semiconductor layer, wherein the oxide semiconductor layer has a ring shape that extends continuously in a plane and surrounds the core conductive layer. Attached Figure Description

[0017] The embodiments will become clearer through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is an equivalent circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment; Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment; Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a view showing a semiconductor memory device according to an embodiment; Figures 4A to 38C This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment; Figure 39 This is a perspective view showing a semiconductor memory device according to an embodiment, and Figures 40A to 40C This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 41A and Figure 41B This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figures 42A to 42C This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 43A and Figure 43B This is a cross-sectional view showing a semiconductor memory device according to an embodiment; Figure 44A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 44B This is a view showing a semiconductor memory device according to an embodiment; Figure 45A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 45B This is a view showing a semiconductor memory device according to an embodiment; Figure 46A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 46B This is a view showing a semiconductor memory device according to an embodiment; Figure 47A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 47B This is a view showing a semiconductor memory device according to an embodiment; Figure 48A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 48B This is a view showing a semiconductor memory device according to an embodiment; Figure 49A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 49B This is a view showing a semiconductor memory device according to an embodiment; Figure 50A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 50B This is a view showing a semiconductor memory device according to an embodiment. Detailed Implementation

[0018] Figure 1 This is an equivalent circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment.

[0019] refer to Figure 1 The memory cell array of the semiconductor memory device 1 according to the embodiment may include multiple sub-cell arrays SCA. Each of the multiple sub-cell arrays SCA may include multiple bit lines BL, multiple word lines WL, and multiple memory cells MC. Each of the multiple memory cells MC may include a cell transistor CT and an information memory SP. The cell transistor CT may be located between a word line WL and a bit line BL. The information memory SP may be a memory element capable of storing data.

[0020] Multiple word lines (WL) can each be a conductive pattern (e.g., a metal line) separated from and arranged on the substrate. Multiple word lines (WL) can extend in a first horizontal direction (X direction). Multiple word lines (WL) in a subcell array (SCA) can be separated from each other in the vertical direction (Z direction). Multiple bit lines (BL) can extend from the substrate in the vertical direction (Z direction). Multiple bit lines (BL) in a subcell array (SCA) can be separated from each other in the first horizontal direction (X direction).

[0021] In the memory cell array of semiconductor memory device 1, multiple word lines WL can extend in a first horizontal direction (X direction) and can be separated from each other in a second horizontal direction (Y direction) and a vertical direction (Z direction). In the memory cell array of semiconductor memory device 1, multiple bit lines BL can extend in the vertical direction (Z direction) and can be separated from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Multiple sub-cell arrays SCA can be arranged along the second horizontal direction (Y direction).

[0022] In some embodiments, the information memory SP can be a memory element using a capacitor, a memory element using a magnetic tunnel junction pattern, or a memory element using a variable resistor including a phase change material. For example, the memory cell MC can be a dynamic random access memory (DRAM) cell, while the information memory SP can be a capacitor. In another embodiment, the information memory SP can be a transistor capable of storing data together with the cell transistor CT.

[0023] The gate of the unit transistor CT can be connected to the word line WL, and the source region of the unit transistor CT can be connected to the bit line BL. The information memory SP can be connected to the drain region of the unit transistor CT. In some embodiments, the information memory SP can be a capacitor including a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode, and the first electrode of the capacitor can be connected to the drain region of the unit transistor CT, while the second electrode of the capacitor can be connected to the ground line PP. In some embodiments, the second electrode of the capacitor can be part of the ground line PP.

[0024] The memory cell array of the semiconductor memory device 1 may include multiple sub-cell arrays SCA. Each sub-cell array SCA includes multiple memory cells MC arranged in rows and columns and separated from each other in a first horizontal direction (X direction) and a vertical direction (Z direction), multiple bit lines BL connected to multiple cell transistors CT connected to the multiple memory cells MC arranged in the vertical direction (Z direction) and separated from each other in the first horizontal direction (X direction), and multiple word lines WL extending in the first horizontal direction (X direction) and separated from each other in the vertical direction (Z direction). The multiple sub-cell arrays SCA may be arranged along a second horizontal direction (Y direction). The semiconductor memory device 1 may include multiple memory cell arrays.

[0025] The first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction) can be referred to as the first direction, the second direction, and the third direction, respectively. Alternatively, the first horizontal direction (X direction), the vertical direction (Z direction), and the second horizontal direction (Y direction) can be referred to as the first direction, the second direction, and the third direction, respectively. The first direction, the second direction, and the third direction can be orthogonal to each other.

[0026] Two adjacent sub-cell arrays (SCAs) in the second horizontal direction (Y direction) can share multiple bit lines BL. The source regions of the cell transistors CT in each of the two sub-cell arrays (SCAs) can be connected to the bit lines BL shared by the two sub-cell arrays (SCAs). Starting from each bit line BL shared by the two sub-cell arrays (SCAs), the source and drain regions of the cell transistors CT of the two sub-cell arrays (SCAs) and the information memory SP can be arranged in opposite directions. For example, the source and drain regions of the cell transistors CT of one sub-cell array (SCA) connected to a bit line BL shared by the two sub-cell arrays (SCAs) and the information memory SP can be arranged sequentially in the second horizontal direction (Y direction), while the source and drain regions of the cell transistors CT of the other sub-cell array (SCA) and the information memory SP can be arranged in the opposite direction to the second horizontal direction (Y direction). For example, multiple bit lines BL can be arranged sequentially in the second horizontal direction (Y direction), and two memory cells MC can be arranged at the same vertical height in the second horizontal direction (Y direction) between a pair of adjacent bit lines BL.

[0027] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment.

[0028] refer to Figure 2The semiconductor memory device 1000 may include a memory cell array 1010, which includes DRAM cells as memory cells and various circuit blocks for driving the DRAM cells. For example, a timer register 1020 may be activated when the chip select signal CSB changes from a deactivation level (e.g., logic high) to an activation level (e.g., logic low). The timer register 1020 may receive command signals from the outside, such as a clock signal CLK, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a data input / output masking signal DQM, and may process the received command signals to generate various internal command signals LRAS, LCBR, LWE, LCAS, LWCBR, and LDQM for controlling the circuit blocks.

[0029] Some of the internal command signals generated by the timer register 1020 are stored in the programming register 1040. For example, delay information or burst length information related to data output can be stored in the programming register 1040. The internal command signals stored in the programming register 1040 can be provided to the delay / burst length controller 1060, and the delay / burst length controller 1060 can provide control signals for controlling the delay or burst length of data output through the column address buffer 1080 to the column decoder 1100 or the output buffer 1120.

[0030] Address register 1200 can receive clock signal CLK and address signal ADD from an external source. Row address signals can be provided to row decoder 1240 via row address buffer 1220. Similarly, column address signals can be provided to column decoder 1100 via column address buffer 1080. Row address buffer 1220 can further receive refresh address signals generated by the refresh counter in response to refresh commands LRAS and LCBR, and can provide row address signals or refresh address signals to row decoder 1240. Additionally, address register 1200 can provide a memory bank signal for selecting a memory bank to memory bank selector 1260.

[0031] Row decoder 1240 can decode row address signals or refresh address signals received from row address buffer 1220. Row decoder 1240 may include multiple sub-word line drivers (SWDs) 1250. Sub-word line drivers 1250 can activate multiple word lines (WL) of memory cell array 1010. Sub-word line drivers 1250 can be arranged in blocks at predetermined intervals within row decoder 1240 and are arranged adjacent to memory cell array 1010. For example, sub-word line drivers 1250 can be arranged adjacent to one end of memory cell array 1010 perpendicular to sense amplifier 1300.

[0032] The column decoder 1100 can decode the column address signal and perform selection operations on multiple bit lines BL of the memory cell array 1010. For example, column selection lines can be provided in the semiconductor memory device 1000, and selection operations can be performed through the column selection lines.

[0033] The sense amplifier 1300 amplifies the data in the memory cells selected by the row decoder 1240 and the column decoder 1100, and provides the amplified data to the output buffer 1120. Data to be stored in the data cells can be provided to the memory cell array 1010 through the data input register 1320, and the input / output controller 1340 can control the data transfer operation through the data input register 1320.

[0034] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 3A It is along Figure 3B A cross-sectional view taken from line A-A'. Figure 3B It is along Figure 3A A cross-sectional view taken from line B-B'. Figure 3C It is along Figure 3B A cross-sectional view taken from line C-C'. Figure 3D It is along Figure 3B The cross-sectional view taken by line D-D', and Figure 3E It is along Figure 3B and Figure 3C The cross-sectional view taken from line PC'.

[0035] refer to Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The semiconductor memory device 1 includes a substrate 110, a plurality of channel patterns 270 located on the substrate 110, a plurality of gate electrode layers 285 disposed between a plurality of gate dielectric layers 270 and surrounding at least a portion of the plurality of channel patterns 270, a plurality of bit line structures 320 connected to the plurality of channel patterns 270, and a plurality of capacitor structures 260 connected to the plurality of channel patterns 270. A second horizontal direction (Y direction) may be orthogonal to a first horizontal direction (X direction). In the second horizontal direction (Y direction), the plurality of bit line structures 320 may each be connected to one end of each of the plurality of channel patterns 270, and the plurality of capacitor structures 260 may each be connected to the other end of each of the plurality of channel patterns 270. The plurality of gate electrode layers 285 may be... Figure 1The multiple word lines WL shown are illustrated. The multiple bit line structure 320 can be... Figure 1 The multiple bit lines BL shown are illustrated. Multiple capacitor structures 260 can each be... Figure 1 The information memory SP shown in the figure. Channel pattern 270, gate dielectric layer Gox, gate electrode layer 285, and bit line structure 320 can be configured to... Figure 1 The unit transistor CT shown is shown.

[0036] Multiple channel patterns 270 may be spaced apart on the substrate 110 along a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction). The multiple channel patterns 270 may be arranged in rows in a matrix-like manner in a plane along the first horizontal direction (X direction) and the second horizontal direction (Y direction), and may be aligned along the vertical direction (Z direction). In some embodiments, the multiple channel patterns 270 may all be formed of an oxide semiconductor material. In some embodiments, the multiple channel patterns 270 may all have the same overall impurity concentration, or may all be intrinsic semiconductors that are not entirely impurity-implanted. For example, the multiple channel patterns 270 may all have a junctionless structure.

[0037] Multiple gate dielectric layers (Gox) may surround multiple channel patterns 270. The multiple gate dielectric layers (Gox) may respectively cover the upper and lower surfaces of the multiple channel patterns 270 and the two side surfaces of the multiple channel patterns 270 in a first horizontal direction (X direction). Each of the multiple gate dielectric layers (Gox) may include a substrate insulating layer 220 and a channel covering insulating layer 280. The substrate insulating layer 220 may cover the upper and lower surfaces of the channel pattern 270, and the channel covering insulating layer 280 may cover the upper surface, lower surface, and two side surfaces of the channel structure in the first horizontal direction (X direction). The channel structure includes the channel pattern 270 and a pair of substrate insulating layers 220 covering the upper and lower surfaces of the channel pattern 270. The substrate insulating layer 220 covering the lower surface of the channel pattern 270 may be referred to as the first substrate insulating layer, and the substrate insulating layer 220 covering the upper surface of the channel pattern 270 may be referred to as the second substrate insulating layer. The substrate insulating layer 220 may cover the upper or lower surface of one of the plurality of channel patterns 270. In some embodiments, the upper surface, lower surface and side surface of each channel structure that is separated from each other in the first horizontal direction (X direction) may be covered by a channel covering insulating layer 280.

[0038] Multiple gate electrode layers 285 may extend in a first horizontal direction (X direction) and may be separated from each other in a second horizontal direction (Y direction) and a vertical direction (Z direction). The multiple gate electrode layers 285 may extend in the first horizontal direction (X direction) along the upper and lower surfaces of a channel cover insulating layer 280 covering a channel structure separated from each other in the first horizontal direction (X direction). The gate electrode layer 285 extending along the lower surface of the channel cover insulating layer 280 may be referred to as the first gate electrode layer, while the gate electrode layer 285 extending along the upper surface of the channel cover insulating layer 280 may be referred to as the second gate electrode layer. A pair of gate electrode layers 285 separated from each other in the vertical direction (Z direction) may be arranged between a pair of adjacent channel patterns 270 in the vertical direction (Z direction). The upper gate electrode layer 285 of a pair of gate electrode layers 285 may be a first gate electrode layer corresponding to the upper channel pattern 270 of a pair of channel patterns 270, while the lower gate electrode layer 285 of a pair of gate electrode layers 285 may be a second gate electrode layer corresponding to the lower channel pattern 270 of a pair of channel patterns 270. An interlayer insulating layer 292 may be located between the pair of gate electrode layers 285, which are arranged between a pair of channel patterns 270 that are adjacent to each other in the vertical direction (Z direction) and separated from each other in the vertical direction (Z direction). The interlayer insulating layer 292 may extend in a first horizontal direction (X direction), which is the extension direction of the gate electrode layers 285. In some embodiments, the first gate electrode layer and the second gate electrode layer corresponding to one channel pattern 270 may be integrally formed.

[0039] The horizontal width of each of the plurality of gate electrode layers 285 in the second horizontal direction (Y direction) may be smaller than the horizontal width of each of the plurality of channel patterns 270 or the horizontal width of each of the plurality of substrate insulating layers 220. For example, a plurality of gate dielectric layers Gox may be present between pairs of gate electrode layers 285 and surrounding a portion of the upper surface and a portion of the lower surface of each of the plurality of channel patterns 270.

[0040] Multiple bitline structures 320 may be separated from each other in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and may extend in a vertical direction (Z direction). Each end of the bitline structure 320 in the second horizontal direction (Y direction) may be connected to a channel pattern 270 that is aligned in the vertical direction (Z direction) among a plurality of channel patterns 270.

[0041] Multiple bit line structures 320 may each include a core conductive layer 324 and an oxide semiconductor layer 322. The oxide semiconductor layer 322 may be located between the core conductive layer 324 and the channel pattern 270. The oxide semiconductor layer 322 may cover the side surfaces of the core conductive layer 324. In some embodiments, the oxide semiconductor layer 322 may cover all side surfaces of the core conductive layer 324. For example, the oxide semiconductor layer 322 may have a ring shape that extends continuously in a plane and surrounds the core conductive layer 324. Although Figure 3E The planar shape of the core conductive layer 324 is shown to be square, but this disclosure is not limited thereto. For example, the planar shape of the core conductive layer 324 may be square, a polygon with five or more corners, a circle, or an ellipse. To correspond to the planar shape of the core conductive layer 324, the planar shape of the oxide semiconductor layer 322 may be a square ring, a polygonal ring with five or more corners, a circular ring, or an elliptical ring.

[0042] Bit line shielding structures 330 can be located between bit line structures 320 arranged in a row along a first horizontal direction (X direction). Bit line structures 320 and bit line shielding structures 330 can be arranged alternately and separated from each other in the first horizontal direction (X direction). For example, a pair of bit line shielding structures 330 can be arranged on either side of each of the plurality of bit line structures 320 in the first horizontal direction (X direction). The plurality of bit line shielding structures 330 can be separated from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction), and can extend in the vertical direction (Z direction). The plurality of bit line shielding structures 330 can be separated from each other so as not to connect to the plurality of channel patterns 270.

[0043] Multiple spacer layers 300 may be located between multiple bit line structures 320 and multiple bit line shielding structures 330, and between multiple bit line structures 320 and multiple gate electrode layers 285. The spacer layer 300 disposed between the bit line structures 320 and the bit line shielding structures 330 may be referred to as a bit line spacer layer, while the spacer layer 300 located between the bit line structures 320 and the gate electrode layers 285 may be referred to as a gate spacer layer. The bit line spacer layer and the gate spacer layer may be formed of the same material.

[0044] In the second horizontal direction (Y direction), a gate spacer layer may be connected to one end of the gate electrode layer 285, while a gate isolation insulating pattern 290P may be connected to the other end of the gate electrode layer 285. In the second horizontal direction (Y direction), one gate spacer layer may be connected to one end of one gate electrode layer 285. An interlayer insulating layer 292 may be located between a pair of gate electrode layers 285 and a pair of gate spacer layers, the pair of gate electrode layers 285 being arranged between a pair of channel patterns 270 that are adjacent to each other in the vertical direction (Z direction) and separated from each other in the vertical direction (Z direction), the pair of gate spacer layers being connected to the other end of the pair of gate electrode layers 285.

[0045] Gate isolation insulating pattern 290P can be connected to the other end of a pair of gate electrode layers 285 arranged between a pair of channel patterns 270 that are adjacent to each other in the vertical direction (Z direction) and separated from each other in the vertical direction (Z direction). In some embodiments, the plurality of gate isolation insulating patterns 290P may each have a U-shaped vertical cross section in a vertical cross section (YZ vertical cross section) formed by a second horizontal direction (Y direction) and a vertical direction (Z direction), and may each have a U-shaped vertical cross section rotated 90 degrees such that the opening portion of the U-shaped vertical cross section faces the gate electrode layer 285. For example, the plurality of gate isolation insulating patterns 290P may each have a pair of horizontal portions located between the channel cover insulating layer 280 and the interlayer insulating layer 292 and a vertical portion located between the second electrode 266 and the interlayer insulating layer 292. A pair of horizontal portions of the gate isolation insulating pattern 290P can be connected to the other end of a pair of gate electrode layers 285 disposed between a pair of channel patterns 270 that are adjacent to each other in the vertical direction (Z direction) and separated from each other in the vertical direction (Z direction). One end of each of the pair of horizontal portions of the gate isolation insulating pattern 290P in the second horizontal direction (Y direction) can be connected to the other end of each of the pair of gate electrode layers 285, and the other end of each of the pair of horizontal portions of the gate isolation insulating pattern 290P in the second horizontal direction (Y direction) can be connected to each of the two ends of the vertical portion of the gate isolation insulating pattern 290P in the vertical direction (Z direction). The thickness of each of the pair of horizontal portions of the gate isolation insulating pattern 290P can be less than the thickness of the gate electrode layer 285. The gate isolation insulating pattern 290P can be formed of a nitride.

[0046] Multiple spacer layers 300 may have multiple vertical vias 300H. The multiple vertical vias 300H may penetrate the multiple spacer layers 300 in the vertical direction (Z direction). In some embodiments, the multiple vertical vias 300H may penetrate the multiple spacer layers 300 and extend into the substrate 110. The multiple vertical vias 300H may include multiple first vertical vias 300H1 and multiple second vertical vias 300H2 alternately arranged in a first horizontal direction (X direction). Multiple channel patterns 270 may be exposed within the multiple first vertical vias 300H1. The multiple channel patterns 270 may not be exposed within the multiple second vertical vias 300H2. Multiple bit line structures 320 may fill the multiple first vertical vias 300H1, while multiple bit line shielding structures 330 may fill the multiple second vertical vias 300H2. In some embodiments, the horizontal width of the first vertical via 300H1 in the first horizontal direction (X direction) may be greater than the horizontal width of the second vertical via 300H2 in the first horizontal direction (X direction). In the second horizontal direction (Y direction), the horizontal width of the first vertical aperture 300H1 and the horizontal width of the second vertical aperture 300H2 can be substantially equal to each other. For example, the horizontal width of the bit line structure 320 in the first horizontal direction (X direction) can be greater than the horizontal width of the bit line shielding structure 330 in the first horizontal direction (X direction), and in the second horizontal direction (Y direction), the horizontal width of the bit line structure 320 can be substantially equal to the horizontal width of the bit line shielding structure 330. The plurality of oxide semiconductor layers 322 included in the plurality of bit line structures 320 can cover the inner surfaces of the plurality of first vertical apertures 300H1, and the plurality of core conductive layers 324 included in the plurality of bit line structures 320 can cover the plurality of oxide semiconductor layers 322 and fill the plurality of first vertical apertures 300H1.

[0047] In the second horizontal direction (Y direction), capacitor structure 260 can be connected to the other end of channel pattern 270 opposite to one end facing bit line structure 320. Multiple capacitor structures 260 can be separated from each other in the first horizontal direction (X direction) and the vertical direction (Z direction). In some embodiments, a pair of capacitor structures 260 adjacent to each other in the second horizontal direction (Y direction) can have a mirror-symmetric structure in the second horizontal direction (Y direction). For example, multiple capacitor structures 260 can be separated from each other in the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction), but a pair of capacitor structures 260 adjacent to each other in the second horizontal direction (Y direction) can have a mirror-symmetric structure in the second horizontal direction (Y direction).

[0048] The capacitor structure 260 may include a first electrode 262, a second electrode 266, and a capacitor dielectric layer 264 located between the first electrode 262 and the second electrode 266. The first electrode 262 may be connected to the other end of the channel pattern 270, the capacitor dielectric layer 264 may cover the first electrode 262, and the second electrode 266 may cover the capacitor dielectric layer 264. For example, one side surface of the first electrode 262 in the second horizontal direction (Y direction) may be connected to the other end of the channel pattern 270. For example, the capacitor dielectric layer 264 may conformally cover the other side surface of the first electrode 262 in the second horizontal direction (Y direction), the upper and lower surfaces of the first electrode 262, and one and the other side surfaces of the first electrode 262 in the first horizontal direction (X direction). In some embodiments, the second electrode 266 may be integrally formed with and cover the first electrode 262 and the capacitor dielectric layer 264 located between the second electrode 266 and the first electrode 262. A capacitor spacer layer 268 may be disposed between multiple capacitor structures 260. For example, the capacitor spacer layer 268 may cover the second electrode 266. In some embodiments, the capacitor spacer layer 268 may fill the space defined by the multiple second electrodes 266. For example, the capacitor spacer layer 268 may fill the space between multiple capacitor structures 260 that are separated from each other in a first horizontal direction (X direction), a second horizontal direction (Y direction), and a vertical direction (Z direction).

[0049] The channel pattern 270 included in the semiconductor memory device 1 according to the present disclosure can be formed from an oxide semiconductor material having a junctionless structure. Therefore, in the semiconductor memory device 1 according to the present disclosure, leakage current can be reduced, a relatively small channel pattern 270 can be formed, and thus, integration density can be increased.

[0050] According to the semiconductor memory device 1 disclosed herein, the gate dielectric layer Gox includes a structure with a stacked substrate insulating layer 220 and a channel covering insulating layer 280. Therefore, the substrate insulating layer 220, which contacts the channel pattern 270, may not directly contact the nitride-containing structure, such as the gate isolation insulating pattern 290P. Thus, hydrogen can be prevented from permeating from the nitride-containing structure into the channel pattern 270, preventing degradation of the channel pattern 270, thereby improving the operational reliability of the semiconductor memory device 1.

[0051] Furthermore, since the bit line structure 320 included in the semiconductor memory device 1 according to this disclosure includes an oxide semiconductor layer 322 in contact with the channel pattern 270, the contact area between the bit line structure 320 and the channel pattern 270 can be increased, thereby reducing the contact resistance between the channel pattern 270 and the bit line structure 320. Therefore, the operating characteristics of the semiconductor memory device 1 can be improved.

[0052] In the semiconductor memory device 1 according to the present disclosure, the main components (such as the substrate insulating layer 220) can be formed by a deposition process rather than an epitaxial growth process, so the process for manufacturing the semiconductor memory device 1 can be easily performed.

[0053] Figure 4A and Figure 4B , Figure 5A and Figure 5B , Figure 6A and Figure 6B , Figure 7A and Figure 7B , Figure 8A and Figure 8B , Figures 9A to 9C , Figures 10A to 10C , Figures 11A to 11C , Figures 12A to 12C , Figures 13A to 13C , Figures 14A to 14C , Figures 15A to 15C , Figures 16A to 16C , Figures 17A to 17C , Figures 18A to 18C , Figures 19A to 19C , Figure 20A and Figure 20B , Figure 21A and Figure 21B , Figure 22A and Figure 22B , Figure 23A and Figure 23B , Figure 24A and Figure 24B , Figure 25A and Figure 25B , Figure 26A and Figure 26B , Figure 27A and Figure 27B , Figure 28A and Figure 28B , Figure 29A and Figure 29B , Figure 30A and Figure 30B , Figure 31A and Figure 31B , Figure 32A and Figure 32B , Figure 33A and Figure 33B , Figures 34A to 34C , Figures 35A to 35C , Figures 36A to 36C , Figures 37A to 37Cand Figures 38A to 38C This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Specifically, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A and Figure 38A They are respectively along Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B , Figure 34B , Figure 35B , Figure 36B , Figure 37B and Figure 38B A cross-sectional view taken from line A-A'. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B , Figure 34B , Figure 35B , Figure 36B , Figure 37B and Figure 38B They are respectively along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A , Figure 33A , Figure 34A , Figure 35A , Figure 36A , Figure 37A and Figure 38A The cross-sectional view taken by line B-B'. Figure 34C , Figure 35C , Figure 36C , Figure 37C and Figure 38C They are respectively along Figure 34B , Figure 35B , Figure 36B , Figure 37B and Figure 38B The cross-sectional view taken from line C-C'. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C and Figure 19C They are respectively along Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B and Figure 19B The cross-sectional view taken by line D-D'.

[0054] refer to Figure 4A and Figure 4B Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 are formed on substrate 110. The multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD).

[0055] In some embodiments, the substrate insulating layer 220 may be located between the sacrificial insulating layer 210 and the sacrificial semiconductor layer 230. For example, the substrate insulating layer 220 may be located above and below the sacrificial insulating layer 210, and the substrate insulating layer 220 may be located above and below the sacrificial semiconductor layer 230. For example, a plurality of sacrificial insulating layers 210 and a plurality of sacrificial semiconductor layers 230 may be alternately arranged between a pair of substrate insulating layers 220 that are adjacent to each other in the vertical direction (Z direction).

[0056] although Figure 4A and Figure 4BThe illustration shows a substrate insulating layer 220 located at the top of a stacked structure in which multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 are stacked; however, this disclosure is not limited thereto. For example, multiple sub-stacked structures may be stacked on substrate 110, wherein sacrificial insulating layers 210, one substrate insulating layer 220, one sacrificial semiconductor layer 230, and another substrate insulating layer 220 are sequentially stacked in the vertical direction (Z direction). The substrate insulating layer 220 below the sacrificial semiconductor layer 230 may be referred to as the first substrate insulating layer, while the substrate insulating layer 220 above the sacrificial semiconductor layer 230 may be referred to as the second substrate insulating layer. In some embodiments, the sacrificial insulating layer 210 may be located at the top of a stacked structure in which multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 are stacked. For example, a plurality of sub-stacked structures and a sacrificial insulating layer 210 located on the plurality of sub-stacked structures can be provided on the substrate 110. Each sub-stacked structure includes a sacrificial insulating layer 210, a substrate insulating layer 220, a sacrificial semiconductor layer 230 and another substrate insulating layer 220.

[0057] Substrate 110 may include, for example, silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, substrate 110 may include at least one compound semiconductor selected from semiconductor elements such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, substrate 110 may include a buried oxide layer (BOX). Substrate 110 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0058] The sacrificial insulating layer 210, the substrate insulating layer 220, and the sacrificial semiconductor layer 230 may be formed of materials that are etch-selective relative to each other. In some embodiments, the sacrificial insulating layer 210 may include a nitride, while the substrate insulating layer 220 may include an oxide. For example, the sacrificial insulating layer 210 may include silicon nitride. The substrate insulating layer 220 may be formed of at least one selected from silicon oxide, a high-k dielectric material with a higher dielectric constant than silicon oxide, and a ferroelectric material. For example, the high-k dielectric material and the ferroelectric material can each be formed from at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxysilane (HfSiON), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the substrate insulating layer 220 can be formed of a metal oxide. In some embodiments, the sacrificial semiconductor layer 230 can be formed of silicon (Si). For example, the sacrificial semiconductor layer 230 can be formed of polycrystalline silicon.

[0059] The sacrificial insulating layer 210 may have a first thickness T1, the substrate insulating layer 220 may have a second thickness T2, and the sacrificial semiconductor layer 230 may have a third thickness T3. The first thickness T1 may be greater than the second thickness T2 and the third thickness T3. The second thickness T2 may be less than or equal to the third thickness T3. For example, the first thickness T1 may be tens of nanometers, while the second thickness T2 and the third thickness T3 may each be a few nanometers.

[0060] refer to Figure 5A and Figure 5B Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 can be partially removed to form multiple first element isolation dicing regions ISC1. The multiple first element isolation dicing regions ISC1 can be separated from each other in a first horizontal direction (X direction) and extend in a second horizontal direction (Y direction). The second horizontal direction (Y direction) can be orthogonal to the first horizontal direction (X direction). In some embodiments, the multiple first element isolation dicing regions ISC1 can each have a substantially constant width in the first horizontal direction (X direction) and can extend in the second horizontal direction (Y direction). In some embodiments, the substrate 110 can be exposed on the bottom surface of the multiple first element isolation dicing regions ISC1.

[0061] Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220 and multiple sacrificial semiconductor layers 230 can each be divided into multiple parts by multiple first element isolation cutting regions ISC1 in a first horizontal direction (X direction).

[0062] refer to Figure 6A and Figure 6B A plurality of first filler insulating sacrificial layers 215 are formed to fill a plurality of first element isolation cut regions ISC1. Each of the plurality of first filler insulating sacrificial layers 215 may comprise a nitride. In some embodiments, the plurality of first filler insulating sacrificial layers 215 may be formed of the same material as the plurality of sacrificial insulating layers 210 or of a material having similar etching properties. For example, each of the plurality of first filler insulating sacrificial layers 215 may comprise silicon nitride.

[0063] refer to Figure 7A and Figure 7B Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, multiple sacrificial semiconductor layers 230, and multiple first filling insulating sacrificial layers 215 can be partially removed to form multiple second element isolation cut regions ISC2 and multiple capacitor isolation cut regions CPC. The multiple second element isolation cut regions ISC2 and multiple capacitor isolation cut regions CPC can be arranged alternately in a second horizontal direction (Y direction). For example, each of the multiple capacitor isolation cut regions CPC can be arranged between a pair of adjacent second element isolation cut regions ISC2 in the second horizontal direction (Y direction), and each of the multiple second element isolation cut regions ISC2 can be arranged between a pair of adjacent capacitor isolation cut regions CPC in the second horizontal direction (Y direction).

[0064] Multiple second-element isolation cut regions ISC2 and multiple capacitor isolation cut regions CPC can be separated from each other in a second horizontal direction (Y direction) and can each extend in a first horizontal direction (X direction). The multiple second-element isolation cut regions ISC2 and multiple capacitor isolation cut regions CPC can be formed to intersect with multiple first-element isolation cut regions ISC1.

[0065] In some embodiments, the horizontal widths of the plurality of second element isolation cut regions ISC2 and the plurality of capacitor isolation cut regions CPC in the second horizontal direction (Y direction) may be greater than the horizontal widths of the plurality of first element isolation cut regions ISC1 in the first horizontal direction (X direction). In some embodiments, the plurality of second element isolation cut regions ISC2 and the plurality of capacitor isolation cut regions CPC may have substantially constant widths in the second horizontal direction (Y direction) and may extend in the first horizontal direction (X direction). In some embodiments, the substrate 110 may be exposed on the bottom surface of the plurality of second element isolation cut regions ISC2 and the plurality of capacitor isolation cut regions CPC.

[0066] Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 can each be divided into multiple portions in a second horizontal direction (Y direction) by multiple second element isolation cut regions ISC2 and multiple capacitor isolation cut regions CPC. That is, multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 can each be divided into multiple portions in a first horizontal direction (X direction) and a second horizontal direction (Y direction) by multiple first element isolation cut regions ISC1, multiple second element isolation cut regions ISC2, and multiple capacitor isolation cut regions CPC. For example, multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple sacrificial semiconductor layers 230 isolated by multiple first element isolation cut regions ISC1, multiple second element isolation cut regions ISC2, and multiple capacitor isolation cut regions CPC can each be arranged in a single row in a matrix-like manner in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0067] refer to Figure 8A and Figure 8B A plurality of second filler insulating sacrificial layers 217 may be formed to fill a plurality of second element isolation cut regions ISC2 and a plurality of capacitor isolation cut regions CPC. The plurality of second filler insulating sacrificial layers 217 may each be formed of a material having etch selectivity relative to each of the plurality of first filler insulating sacrificial layers 215. The plurality of second filler insulating sacrificial layers 217 may each be formed of a material having etch selectivity relative to each of the plurality of substrate insulating layers 220. In some embodiments, the plurality of second filler insulating sacrificial layers 217 may each comprise an oxide. For example, the plurality of second filler insulating sacrificial layers 217 may each comprise silicon oxide.

[0068] refer to Figures 9A to 9CThe second filler insulating sacrificial layer 217 that fills the multiple capacitor isolation cut regions (CPC) can be removed from the multiple second filler insulating sacrificial layers 217. The second filler insulating sacrificial layer 217 that fills the multiple second element isolation cut regions ISC2 can be retained instead of being removed.

[0069] refer to Figures 10A to 10C Multiple sacrificial insulating layers 210 and multiple first filler insulating sacrificial layers 215 can be partially removed through multiple capacitor isolation cut regions (CPC) to form multiple first removal spaces (RS1). Multiple first removal spaces (RS1) can be formed by partially removing multiple sacrificial insulating layers 210, so that multiple second filler insulating sacrificial layers 217 are not exposed. Among the multiple first filler insulating sacrificial layers 215, portions adjacent to the multiple capacitor isolation cut regions (CPC) can be removed, while portions adjacent to the multiple second element isolation cut regions (ISC2) can be retained without removal.

[0070] In the plurality of first removal spaces RS1, the portion from which a plurality of first filler insulating sacrificial layers 215 are partially removed may be part of a plurality of first element isolation cut regions ISC1.

[0071] refer to Figures 11A to 11C A first covering insulation layer 240 can be formed to cover the surface. Figures 10A to 10C The resulting exposed surfaces. For example, the first cover insulating layer 240 may conformally cover the upper surface of the stacked structure in which a plurality of sacrificial insulating layers 210, a plurality of substrate insulating layers 220, and a plurality of sacrificial semiconductor layers 230 are stacked, the substrate 110 exposed in a plurality of capacitor isolation cut regions CPC and a plurality of first removal spaces RS1, and the surfaces of the plurality of sacrificial insulating layers 210, the plurality of substrate insulating layers 220, the plurality of sacrificial semiconductor layers 230, and the plurality of first fill insulating sacrificial layers 215. In some embodiments, the first cover insulating layer 240 may fill all the spaces in the plurality of first removal spaces RS1 that are adjacent to each other in the first horizontal direction (X direction) between sacrificial insulating layers 210, between substrate insulating layers 220, and between sacrificial semiconductor layers 230, and may not fill all the spaces in the plurality of capacitor isolation cut regions CPC that are adjacent to each other in the first horizontal direction (X direction) between sacrificial insulating layers 210, between substrate insulating layers 220, and between sacrificial semiconductor layers 230. The first covering insulating layer 240 may include a nitride. For example, the first covering insulating layer 240 may include silicon nitride.

[0072] refer to Figures 12A to 12CA second cover insulating layer 242 may be formed covering the surface of the first cover insulating layer 240, and multiple pre-filled insulating layers 250P may be formed filling the multiple capacitor isolation cut regions CPC and the multiple first removal spaces RS1. The second cover insulating layer 242 may conformally cover the surface of the first cover insulating layer 240. The second cover insulating layer 242 may not fill all of the multiple capacitor isolation cut regions CPC. In some embodiments, the thickness of the second cover insulating layer 242 may be less than the thickness of the first cover insulating layer 240. The multiple pre-filled insulating layers 250P may cover the second cover insulating layer 242 and fill all of the multiple capacitor isolation cut regions CPC. The second cover insulating layer 242 may include a nitride. For example, the second cover insulating layer 242 may include silicon nitride. The multiple pre-filled insulating layers 250P may each include an oxide. For example, the multiple pre-filled insulating layers 250P may each include silicon oxide.

[0073] refer to Figures 12A to 12C and Figures 13A to 13C Multiple pre-filled insulating layers 250P can be partially removed to form multiple filled insulating layers 250. For example, multiple filled insulating layers 250 can be formed by partially removing multiple pre-filled insulating layers 250P through multiple capacitor isolation cut regions CPC. The multiple filled insulating layers 250 can completely fill multiple first removal spaces RS1, but may not fill at least a portion of the multiple capacitor isolation cut regions CPC. The multiple filled insulating layers 250 can each have a substantially constant horizontal width in a second horizontal direction (Y direction) and have a strip shape extending in a first horizontal direction (X direction).

[0074] Multiple filler insulating layers 250 can be formed by partially removing multiple initial filler insulating layers 250P, such that the side surfaces of the multiple filler insulating layers 250 exposed within the multiple capacitor isolation cut regions CPC are offset more towards the multiple first removal spaces RS1 than the side surfaces of the second cover insulating layer 242. For example, in the multiple capacitor isolation cut regions CPC, the horizontal width of the space defined by the filler insulating layers 250 facing each other in the second horizontal direction (Y direction) can be greater than the horizontal width of the space defined by the second cover insulating layers 242 facing each other in the second horizontal direction (Y direction).

[0075] refer to Figures 14A to 14C A third insulating layer 244 can be formed to cover the surface. Figures 13A to 13CThe resulting exposed surfaces. For example, the third cover insulating layer 244 may conformally cover the surface of the second cover insulating layer 242 and the surfaces of the plurality of fill insulating layers 250. The third cover insulating layer 244 may not completely fill the plurality of capacitor isolation cut regions (CPC). In some embodiments, the thickness of the third cover insulating layer 244 may be greater than the thickness of the second cover insulating layer 242. The third cover insulating layer 244 may include a nitride. For example, the third cover insulating layer 244 may include silicon nitride. The first cover insulating layer 240, the second cover insulating layer 242, and the third cover insulating layer 244 may have substantially the same etching characteristics, but are not limited thereto. In some embodiments, at least one of the first cover insulating layer 240, the second cover insulating layer 242, and the third cover insulating layer 244 may have etch selectivity relative to at least one of the other cover insulating layers.

[0076] In the multiple capacitor isolation cut regions (CPC), the horizontal width of the space defined by the portions of the third covering insulation layer 244 that face each other in the second horizontal direction (Y direction) and cover the multiple filling insulation layers 250 can be greater than the horizontal width of the space defined by the portions of the third covering insulation layer 244 that face each other in the second horizontal direction (Y direction) and cover the second covering insulation layer 242.

[0077] refer to Figures 15A to 15C The third cover insulating layer 244 can be partially removed. In some embodiments, the third cover insulating layer 244 can be removed by performing an anisotropic etching process. For example, portions of the third cover insulating layer 244 covering the plurality of fill insulating layers 250 can be retained without removal. Subsequently, in the plurality of capacitor isolation cut regions (CPC), a portion of the second cover insulating layer 242 and a portion of the first cover insulating layer 240 can be removed to expose a plurality of substrate insulating layers 220 and a plurality of sacrificial semiconductor layers 230, and then the plurality of substrate insulating layers 220 can be partially removed to form a plurality of second removal spaces RS2. The plurality of substrate insulating layers 220, the plurality of sacrificial semiconductor layers 230 and the first cover insulating layer 240 can be partially exposed within the plurality of second removal spaces RS2.

[0078] In the process of forming multiple second removal spaces RS2, the portion of the third cover insulating layer 244 covering the multiple fill insulating layers 250 and the multiple sacrificial semiconductor layers 230 can be retained without being removed. The multiple fill insulating layers 250 can be surrounded by the remaining portions of the first cover insulating layer 240, the remaining portions of the second cover insulating layer 242, and the remaining portions of the third cover insulating layer 244.

[0079] refer to Figures 15A to 15C as well as Figures 16A to 16CMultiple sacrificial semiconductor layers 230 can be partially removed. Multiple second removal spaces RS2 and the spaces from which multiple sacrificial semiconductor layers 230 have been removed can constitute multiple third removal spaces RS3.

[0080] Within the multiple third removal spaces RS3, multiple substrate insulating layers 220, multiple sacrificial semiconductor layers 230, and a first cover insulating layer 240 may be partially exposed.

[0081] refer to Figures 17A to 17C Multiple first electrodes 262 can be formed to fill multiple third removal spaces RS3. Each of the multiple first electrodes 262 may comprise a metal or a conductive metal nitride. For example, each of the multiple first electrodes 262 may comprise a high-melting-point metal such as cobalt, titanium, nickel, tungsten, and molybdenum, and / or a conductive metal nitride such as titanium nitride, silicon titanium nitride, aluminum titanium nitride, tantalum nitride, silicon tantalum nitride, aluminum tantalum nitride, and tungsten nitride.

[0082] refer to Figures 17A to 17C as well as Figures 18A to 18C The first covering insulating layer 240, the second covering insulating layer 242, the third covering insulating layer 244, and the plurality of filler insulating layers 250 can be removed to form a plurality of fourth removal spaces RS4. A plurality of sacrificial insulating layers 210 and a plurality of first electrodes 262 can be exposed within the plurality of fourth removal spaces RS4.

[0083] In some embodiments, after removing the first covering insulating layer 240, the second covering insulating layer 242, the third covering insulating layer 244, and the plurality of filling insulating layers 250 to form a plurality of fourth removal spaces RS4, a plurality of first electrodes 262 may be partially removed to reduce the horizontal width of the plurality of first electrodes 262 in the second horizontal direction (Y direction) and the height of the plurality of first electrodes 262 in the vertical direction (Z direction). For example, the surfaces of the plurality of first electrodes 262 exposed in the plurality of capacitor isolation cut regions CPC and the plurality of fourth removal spaces RS4 may be partially removed.

[0084] refer to Figures 18A to 18C as well as Figures 19A to 19C Multiple capacitor dielectric layers 264 covering multiple first electrodes 262 and multiple second electrodes 266 can be sequentially formed to form multiple capacitor structures 260. In some embodiments, the multiple capacitor dielectric layers 264 can conformally cover the surfaces of the multiple first electrodes 262. In some embodiments, the multiple second electrodes 266 can conformally cover the surfaces of the multiple capacitor dielectric layers 264 and the surfaces of the multiple sacrificial insulating layers 210. Subsequently, multiple capacitor spacer layers 268 can be formed to cover the multiple second electrodes 266 and fill the capacitor isolation cut regions CPC and multiple fourth removal spaces RS4.

[0085] The plurality of capacitor dielectric layers 264 may each be formed from at least one of high-k dielectric materials and ferroelectric materials with a dielectric constant higher than that of silicon oxide. For example, the plurality of capacitor dielectric layers 264 may each comprise at least one of metal oxides and dielectric materials having a perovskite structure. In some embodiments, the plurality of capacitor dielectric layers 264 may each be formed from at least one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the plurality of second electrodes 266 may each be formed of silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof. In some embodiments, the plurality of second electrodes 266 may each comprise tungsten (W).

[0086] refer to Figures 19A to 19C as well as Figure 20A and Figure 20B Multiple second filler insulating sacrificial layers 217 that fill multiple second element isolation cutting regions ISC2 can be removed.

[0087] refer to Figure 20A and Figure 20B as well as Figure 21A and Figure 21B Multiple sacrificial semiconductor layers 230 can be removed by isolating the dicing region ISC2 with multiple second elements to form multiple fifth removal spaces RS5. For example, multiple fifth removal spaces RS5 can be formed by removing all of the multiple sacrificial semiconductor layers 230.

[0088] refer to Figure 22A and Figure 22BMultiple channel material layers 270P can be formed that fill multiple fifth removal spaces RS5 and partially fill multiple second element isolation dicing regions ISC2. The multiple channel material layers 270P can fill all of the multiple fifth removal spaces RS5, but not all of the multiple second element isolation dicing regions ISC2. Each of the multiple channel material layers 270P can comprise an oxide semiconductor material. For example, each of the multiple channel material layers 270P can comprise In... x Ga y Zn z O and Sn doped In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O and W doped InO and InZn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O and Y (yttrium) doped ZnO and Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or combinations thereof.

[0089] refer to Figure 22A and Figure 22B as well as Figure 23A and Figure 23B Multiple channel material layers 270P can be partially removed to form multiple channel patterns 270 that fill multiple fifth removal spaces RS5. Multiple channel patterns 270 can be formed by removing portions of the multiple channel material layers 270P that partially fill multiple second element isolation cut regions ISC2. In some embodiments, the multiple channel patterns 270 can fill all of the multiple fifth removal spaces RS5.

[0090] refer to Figure 24A and Figure 24B Multiple first filler insulating sacrificial layers 215 filling multiple first element isolation cut regions ISC1 can be removed, and multiple sacrificial insulating layers 210 can be removed to form multiple sixth removal spaces RS6. The multiple sixth removal spaces RS6 can be connected to multiple first element isolation cut regions ISC1 and multiple second element isolation cut regions ISC2.

[0091] Multiple substrate insulating layers 220 and multiple second electrodes 266 can be exposed within multiple sixth removal spaces RS6.

[0092] refer to Figure 25A and Figure 25B This can form a trench covering insulation layer 280 to cover the Figure 24A and Figure 24B The resulting exposed surfaces. The channel cover insulating layer 280 may conformally cover the surfaces of each of the substrate 110, the plurality of substrate insulating layers 220, the plurality of channel patterns 270, and the plurality of capacitor spacer layers 268. In some embodiments, the channel cover insulating layer 280 may fill all the spaces between the substrate insulating layers 220 adjacent to each other in the first horizontal direction (X direction) and between the channel patterns 270 in the plurality of first element isolation cut regions ISC1, but may not fill all the spaces between the substrate insulating layers 220 adjacent to each other in the second horizontal direction (Y direction) and between the channel patterns 270 in the plurality of second element isolation cut regions ISC2. The channel cover insulating layer 280 may not fill a portion of each of the plurality of sixth removal spaces RS6 and a portion of each of the plurality of second element isolation cut regions ISC2. The channel cover insulating layer 280 may be formed of at least one material selected from silicon oxide, a high-k dielectric material with a dielectric constant higher than silicon oxide, and a ferroelectric material. The channel cover insulating layer 280 may be formed of the same material as the substrate insulating layer 220, but is not limited thereto. For example, the substrate insulating layer 220 and the channel cover insulating layer 280 may each be formed of another material selected from silicon oxide, a high-k dielectric material with a dielectric constant higher than silicon oxide, and a ferroelectric material.

[0093] refer to Figure 26A and Figure 26BA gate isolation insulating layer 290 can be formed covering the channel covering insulating layer 280. The gate isolation insulating layer 290 can conformally cover the channel covering insulating layer 280. The gate isolation insulating layer 290 may not fill a portion of each of the plurality of sixth removal spaces RS6, a portion of each of the plurality of first element isolation cut regions ISC1, and a portion of each of the plurality of second element isolation cut regions ISC2. The gate isolation insulating layer 290 may include a nitride. For example, the gate isolation insulating layer 290 may include silicon nitride.

[0094] refer to Figure 27A and Figure 27B An interlayer insulating layer 292 may be formed covering the gate isolation insulating layer 290. The interlayer insulating layer 292 may be formed to fill all of the plurality of sixth removal spaces RS6, but not all of the plurality of second element isolation cleavage regions ISC2. The interlayer insulating layer 292 may include oxides. For example, the interlayer insulating layer 292 may include silicon oxide.

[0095] refer to Figure 28A and Figure 28B The portion of the interlayer insulating layer 292 covering the side surface of the gate isolation insulating layer 290 can be removed to divide the interlayer insulating layer 292 into multiple portions within a plurality of second element isolation cut regions ISC2. In some embodiments, the side surface of the gate isolation insulating layer 290 can be aligned with the side surface of the interlayer insulating layer 292 in the vertical direction (Z direction) within the plurality of second element isolation cut regions ISC2.

[0096] refer to Figure 28A and Figure 28B as well as Figure 29A and Figure 29B The gate isolation insulating layer 290 can be partially removed to form a plurality of gate isolation insulating patterns 290P. The plurality of gate isolation insulating patterns 290P can be formed by removing portions of the gate isolation insulating layer 290 located within a plurality of second element isolation cleavage regions ISC2 and at least portions located between a plurality of channel cover insulating layers 280 and a plurality of interlayer insulating layers 292. By removing a portion of the gate isolation insulating layer 290, a gate space 290G can be defined between the channel cover insulating layers 280 and the plurality of interlayer insulating layers 292 that are adjacent to each other in the vertical direction (Z direction).

[0097] In some embodiments, the plurality of gate isolation insulating patterns 290P may each have a U-shaped vertical cross-section in a vertical cross-section (YZ vertical cross-section) formed by a second horizontal direction (Y direction) and a vertical direction (Z direction), but may have a U-shaped vertical cross-section rotated by 90 degrees such that the closed portion of the U-shape faces the plurality of second electrodes 266, and the open portion of the U-shape faces the plurality of second element isolation cut regions ISC2. For example, each of the plurality of gate isolation insulating patterns 290P may have a pair of horizontal portions located between a pair of channel cover insulating layers 280 and interlayer insulating layers 292, and a vertical portion located between the second electrodes 266 and interlayer insulating layers 292. The vertical height of the gate space 290G may be substantially equal to the vertical height (i.e., thickness) of the horizontal portions of the gate isolation insulating patterns 290P.

[0098] In some embodiments, a plurality of gate isolation insulating patterns 290P can be formed by removing portions of the gate isolation insulating layer 290 located within the plurality of second element isolation cut regions ISC2, and removing portions of the gate isolation insulating layer 290 located between the plurality of channel cover insulating layers 280 and the plurality of interlayer insulating layers 292. For example, the plurality of gate isolation insulating patterns 290P may have an I-shaped vertical shape separated from the plurality of second electrodes 266, while having a plurality of channel cover insulating layers 280 between the plurality of gate isolation insulating patterns 290P in a vertical cross-section (YZ vertical cross-section) formed by the second horizontal direction (Y direction) and the vertical direction (Z direction). Each of the plurality of gate isolation insulating patterns 290P may consist only of the vertical portion between the second electrode 266 and the interlayer insulating layer 292.

[0099] refer to Figure 30A and Figure 30B Multiple trench cover insulation layers 280 and multiple interlayer insulation layers 292 can be partially removed to expose the side surfaces of multiple substrate insulation layers 220 and multiple trench patterns 270 within multiple second element isolation cut regions ISC2.

[0100] By partially removing multiple channel cover insulating layers 280 and multiple interlayer insulating layers 292, the vertical height of multiple gate spaces 290G defined between the multiple channel cover insulating layers 280 and the multiple interlayer insulating layers 292 can be increased. For example, the vertical height of the multiple gate spaces 290G can be greater than the vertical height (i.e., thickness) of the horizontal portion of the multiple gate isolation insulating patterns 290P. The multiple substrate insulating layers 220 and the multiple channel cover insulating layers 280 can constitute multiple gate dielectric layers Gox.

[0101] refer to Figure 31A and Figure 31B An electrode material layer of 285P can be formed to cover the surface. Figure 30Aand Figure 30B The resulting exposed surfaces. The electrode material layer 285P can be formed to fill all of the plurality of gate spaces 290G. The electrode material layer 285P can include a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the electrode material layer 285P can be formed of a conductive barrier layer and a conductive filling layer covering the conductive barrier layer. The conductive barrier layer can include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conductive barrier layer can be formed of TiN. The conductive filling layer can be formed of, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SrRuO (SRO), (Ba,Sr)RuO (BSRO), CaRuO (CRO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some embodiments, the conductive filling layer can include tungsten (W).

[0102] refer to Figure 31A and Figure 31B as well as Figure 32A and Figure 32B A portion of the electrode material layer 285P can be removed to form multiple gate electrode layers 285. Multiple gate electrode layers 285 can be formed by retaining only a portion of the electrode material layer 285P located within the multiple gate spaces 290G and removing the remaining portion. The multiple gate electrode layers 285 can contact multiple gate isolation insulating patterns 290P and can fill some inner portions of the multiple gate spaces 290G.

[0103] refer to Figure 33A and Figure 33B A spacer layer 300 can be formed to fill multiple gate spaces 290G and multiple second element isolation cleaved regions ISC2. The spacer layer 300 may include oxides, nitrides, oxynitrides, carbonitrides, or combinations thereof.

[0104] refer to Figures 34A to 34C A portion of the spacer layer 300 filling the plurality of second element isolation cut regions ISC2 can be removed to form a plurality of vertical holes 300H. The plurality of vertical holes 300H can be arranged in rows within each of the plurality of second element isolation cut regions ISC2 to be separated from each other in a first horizontal direction (X direction). In some embodiments, the plurality of vertical holes 300H can be formed by partially removing the spacer layer 300 and the upper side of the substrate 110. For example, the plurality of vertical holes 300H can penetrate the spacer layer 300 and extend into the substrate 110.

[0105] The plurality of vertical holes 300H may include a plurality of first vertical holes 300H1 and a plurality of second vertical holes 300H2 arranged alternately in a first horizontal direction (X direction). A plurality of channel patterns 270 may be exposed within the plurality of first vertical holes 300H1. The plurality of channel patterns 270 may not be exposed within the plurality of second vertical holes 300H2. In some embodiments, the horizontal width of the plurality of first vertical holes 300H1 in the first horizontal direction (X direction) may be greater than the horizontal width of the plurality of second vertical holes 300H2 in the first horizontal direction (X direction). In the second horizontal direction (Y direction), the horizontal width of the plurality of first vertical holes 300H1 may be substantially equal to the horizontal width of the plurality of second vertical holes 300H2.

[0106] refer to Figures 35A to 35C Multiple molding layers 310 can be formed to fill multiple vertical holes 300H. The multiple molding layers 310 can each be formed of a material that has etch selectivity relative to the spacer layer 300. In some embodiments, the multiple molding layers 310 may each comprise an oxide. For example, the multiple molding layers 310 may each comprise silicon oxide.

[0107] refer to Figures 35A to 35C as well as Figures 36A to 36C The molding layer 310 that fills the plurality of first vertical holes 300H1 can be removed to expose the plurality of channel patterns 270 within the plurality of first vertical holes 300H1. The molding layer 310 that fills the plurality of second vertical holes 300H2 can be retained without being removed.

[0108] refer to Figures 37A to 37C Multiple oxide semiconductor layers 322 can be formed to cover the inner surfaces of multiple first vertical holes 300H1. The multiple oxide semiconductor layers 322 can conformally cover the inner surfaces of the multiple first vertical holes 300H1 to cover only a portion of each of the multiple first vertical holes 300H1. The multiple oxide semiconductor layers 322 can contact multiple channel patterns 270. In some embodiments, the multiple oxide semiconductor layers 322 may not cover at least a portion of the bottom surface of the substrate 110 exposed to the multiple first vertical holes 300H1. The multiple oxide semiconductor layers 322 can each be free in In x Ga y Zn z O and Sn doped In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、Inx Zn y O and W doped InO and InZn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O and Y (yttrium) doped ZnO and Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or combinations thereof are formed.

[0109] refer to Figures 38A to 38C Multiple core conductive layers 324, each filling multiple first vertical vias 300H1, can be formed on multiple oxide semiconductor layers 322 to form multiple bit line structures 320, each including a core conductive layer 324 and an oxide semiconductor layer 322. Each of the multiple core conductive layers 324 may each comprise a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the multiple core conductive layers 324 may each be formed from a conductive barrier layer and a conductive fill layer covering the conductive barrier layer.

[0110] Subsequently, the multiple molding layers 310 that fill the multiple second vertical holes 300H2 can be removed, and a formation can be formed. Figures 3A to 3E The bit line shielding structure 330 shown is filled with a plurality of second vertical vias 300H2 to form a semiconductor memory device 1. Each bit line shielding structure 330 may comprise a metal, a conductive metal nitride, or a combination thereof. In some embodiments, each bit line shielding structure 330 may be formed of the same material as the core conductive layer 324. In some embodiments, prior to forming the plurality of core conductive layers 324, a plurality of molding layers 310 filling the plurality of second vertical vias 300H2 may be removed, and then a plurality of conductive material layers filling the plurality of first vertical vias 300H1 and the plurality of second vertical vias 300H2 may be formed to form the plurality of core conductive layers 324 and the bit line shielding structure 330.

[0111] According to this disclosure, in the method of manufacturing semiconductor memory device 1, the main components of semiconductor memory device 1 can be formed by deposition process instead of epitaxial growth process, so semiconductor memory device 1 can be easily manufactured.

[0112] Figure 39 This is a perspective view showing a semiconductor memory device according to an embodiment, and Figures 40A to 40C This is a cross-sectional view showing a semiconductor memory device according to an embodiment. Specifically, Figures 40A to 40C They are respectively along Figure 39 Cross-sectional views taken from planes C1, C2, and C3. For Figure 39 and Figures 40A to 40C The description above can be omitted. Figures 3A to 3E Descriptions that have been performed.

[0113] refer to Figure 39 and Figures 40A to 40C The semiconductor memory device 2 may include a substrate 110, a plurality of channel patterns 270 located on the substrate 110, a plurality of gate electrode layers 285 disposed between a plurality of gate dielectric layers Gox and surrounding at least a portion of the plurality of channel patterns 270, a plurality of bit line structures 320 connected to the plurality of channel patterns 270, and a plurality of capacitor structures 260 connected to the plurality of channel patterns 270. In a second horizontal direction (Y direction), each of the plurality of bit line structures 320 may be connected to one end of each of the plurality of channel patterns 270, and each of the plurality of capacitor structures 260 may be connected to the other end of each of the plurality of channel patterns 270. The plurality of gate dielectric layers Gox may each surround the plurality of channel patterns 270. The plurality of gate electrode layers 285 may each surround the upper surface, lower surface, and two side surfaces of each of the plurality of channel patterns 270 in a first horizontal direction (X direction), while the plurality of gate dielectric layers Gox are located between the plurality of gate electrode layers 285 and the plurality of channel patterns 270. In a vertical cross-section (XZ vertical cross-section) formed by the first horizontal direction (X direction) and the vertical direction (Z direction), the gate electrode layer 285 may extend continuously and surround the channel pattern 270. For example, the gate electrode layer 285 may have a gate all-around (GAA) structure that completely surrounds the channel pattern 270 in the vertical cross-section (XZ vertical cross-section) formed by the first horizontal direction (X direction) and the vertical direction (Z direction).

[0114] Figure 41A and Figure 41B This is a cross-sectional view showing a semiconductor memory device according to an embodiment. Specifically, Figure 41A and Figure 41B They are respectively along Figures 3A to 3E The semiconductor memory device 1 and Figure 39The cross-sectional view of planes C1 and C3 corresponding to each other.

[0115] refer to Figure 41A and Figure 41B The semiconductor memory device 1 includes multiple gate dielectric layers Gox that can surround multiple channel patterns 270. Figure 41A and Figure 41B In the semiconductor memory device 1 shown, along with... Figure 39 The cross-sectional view taken from the plane corresponding to plane C2 can be compared with... Figure 40B The cross-sectional views are substantially the same. Each of the plurality of gate electrode layers 285 may surround a portion of the upper surface, a portion of the lower surface, and two side surfaces of each of the plurality of channel patterns 270, while each of the plurality of gate dielectric layers Gox is located between the plurality of gate electrode layers 285 and the plurality of channel patterns 270. In a vertical cross-section (XZ vertical cross-section) formed by a first horizontal direction (X direction) and a vertical direction (Z direction), the gate electrode layer 285 may have a dual-gate shape covering the upper and lower surfaces of the channel pattern 270.

[0116] Figures 42A to 42C This is a cross-sectional view showing a semiconductor memory device according to an embodiment. Figure 42A Is along with Figure 3A A cross-sectional view taken at the position corresponding to line B-B'. Figure 42B It is along Figure 42A The cross-sectional view taken along line C-C', and Figure 43C is along... Figure 42A and Figure 42B The cross-sectional view taken from line PC'.

[0117] refer to Figures 42A to 42C The semiconductor memory device 1a may include a substrate 110, a plurality of channel patterns 270 located on the substrate 110, a plurality of gate electrode layers 285 disposed between a plurality of gate dielectric layers Gox and surrounding at least a portion of each of the plurality of channel patterns 270, a plurality of bit line structures 320a connected to the plurality of channel patterns 270, and a plurality of capacitor structures 260 connected to the plurality of channel patterns 270. In a second horizontal direction (Y direction), the plurality of bit line structures 320a may each be connected to one end of each of the plurality of channel patterns 270, and the plurality of capacitor structures 260 may each be connected to the other end of each of the plurality of channel patterns 270.

[0118] Multiple bitline structures 320a may each include a core conductive layer 324a and an oxide semiconductor layer 322a. The oxide semiconductor layer 322a may be located between the core conductive layer 324a and the channel pattern 270. The oxide semiconductor layer 322a may cover the side surfaces of the core conductive layer 324a. In some embodiments, the oxide semiconductor layer 322a may cover both side surfaces of the core conductive layer 324a in the second horizontal direction (Y direction). The oxide semiconductor layer 322a may not cover the two side surfaces of the core conductive layer 324a in the first horizontal direction (X direction).

[0119] Figure 43A and Figure 43B This is a cross-sectional view showing a semiconductor memory device according to an embodiment. Specifically, Figure 43A Is along with Figure 3A The cross-sectional view taken at the position corresponding to line B-B', and Figure 43B It is along Figure 43A The cross-sectional view taken from line C-C'.

[0120] refer to Figure 43A and Figure 43B The semiconductor memory device 1b includes a substrate 110, a plurality of channel patterns 270 located on the substrate 110, a plurality of gate electrode layers 285 disposed between a plurality of gate dielectric layers Gox and surrounding at least a portion of the plurality of channel patterns 270, a plurality of bit line structures 320b connected to the plurality of channel patterns 270, and a plurality of capacitor structures 260 connected to the plurality of channel patterns 270. In a second horizontal direction (Y direction), each of the plurality of bit line structures 320b can be connected to one end of each of the plurality of channel patterns 270, and each of the plurality of capacitor structures 260 can be connected to the other end of each of the plurality of channel patterns 270.

[0121] Multiple bit line structures 320b may each include a core conductive layer 324b and an oxide semiconductor layer 322b. The oxide semiconductor layer 322b may be located between the core conductive layer 324b and the channel pattern 270. The oxide semiconductor layer 322b may cover a portion of the side surface of the core conductive layer 324b. In some embodiments, the oxide semiconductor layer 322b may cover a portion of a side surface of the core conductive layer 324b facing the channel pattern 270. The oxide semiconductor layer 322b may only cover the end of the channel pattern 270 facing the bit line structure 320b. For example, the oxide semiconductor layer 322b may not be disposed between the core conductive layer 324b and the gate dielectric layer Gox, between the core conductive layer 324b and the spacer layer 300, or between the core conductive layer 324b and the interlayer insulating layer 292.

[0122] Figure 44AThis is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 44B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 44A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 44B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0123] refer to Figure 44A and Figure 44B Multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple channel material layers 270aP are formed on the substrate 110. The multiple sacrificial insulating layers 210, multiple substrate insulating layers 220, and multiple channel material layers 270aP can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD).

[0124] In some embodiments, the substrate insulating layer 220 may be located between the sacrificial insulating layer 210 and the channel material layer 270aP. For example, the substrate insulating layer 220 may be located above and below the sacrificial insulating layer 210, and the substrate insulating layer 220 may be located above and below the channel material layer 270aP. For example, a plurality of sacrificial insulating layers 210 and a plurality of channel material layers 270aP may be alternately arranged between a pair of substrate insulating layers 220 that are adjacent to each other in the vertical direction (Z direction).

[0125] After that, you can refer to Figures 5A to 20B as well as Figures 24A to 37B To manufacture semiconductor memory devices 3. The channel material layer 270aP can be divided into multiple channel patterns 270a, as... Figures 5A to 16C The sacrificial semiconductor layer 230 shown can be divided into multiple channel patterns 270a. For example, when the channel material layer 270aP has a larger diameter than the channel material layer 270a, the channel material layer 270aP can be divided into multiple channel patterns 270a. Figure 22A and Figure 22B When the channel material layer 270P shown in the figure exhibits relatively excellent thermal stability, the formation of the channel material layer 270aP can be omitted instead of... Figure 4A and Figure 4B The process of the sacrificial semiconductor layer 230 shown in the figure and in Figures 21A to 23B The process of forming the channel pattern 270 after removing the sacrificial semiconductor layer 230 shown in the figure can simplify the process of manufacturing the semiconductor memory device 3.

[0126] Figure 45A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 45BThis is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 45A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 45B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0127] refer to Figure 45A and Figure 45B Multiple sacrificial insulating layers 210, multiple sacrificial semiconductor layers 230, and multiple base insulating layers 220a are formed on the substrate 110. The multiple sacrificial insulating layers 210, multiple sacrificial semiconductor layers 230, and multiple base insulating layers 220a can be stacked alternately on the substrate 110.

[0128] For example, the substrate insulating layer 220a may be located below the sacrificial insulating layer 210, but may not be located on the sacrificial insulating layer 210, and the substrate insulating layer 220a may be located on the sacrificial semiconductor layer 230, but may not be located below the sacrificial semiconductor layer 230.

[0129] After that, you can refer to Figures 5A to 37B To manufacture semiconductor memory devices 4. Figure 45B The semiconductor memory device 4 shown does not include Figures 3A to 3E The semiconductor memory device 1 shown includes a first substrate insulating layer among a plurality of substrate insulating layers 220, and a second substrate insulating layer as a plurality of substrate insulating layers 220a. The semiconductor memory device 4 may include a plurality of gate dielectric layers Goxa. Each of the plurality of gate dielectric layers Goxa may include a substrate insulating layer 220a and a channel covering insulating layer 280. The substrate insulating layer 220a may cover the upper surface of the channel pattern 270, and the channel covering insulating layer 280 may cover the upper surface, lower surface, and two side surfaces in the first horizontal direction (X direction) of the channel structure including the channel pattern 270 and the substrate insulating layer 220a covering the upper surface of the channel pattern 270.

[0130] Figure 46A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 46B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 46A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 46B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0131] refer to Figure 46A and Figure 46BMultiple sacrificial insulating layers 210, multiple channel material layers 270aP, and multiple base insulating layers 220a can be formed on the substrate 110. The multiple sacrificial insulating layers 210, multiple channel material layers 270aP, and multiple base insulating layers 220a can be stacked alternately on the substrate 110.

[0132] After that, you can refer to Figures 5A to 20B as well as Figures 24A to 37B To manufacture semiconductor memory devices 5.

[0133] Figure 47A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 47B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 47A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 47B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0134] refer to Figure 47A and Figure 47B Multiple sacrificial insulating layers 210, multiple base insulating layers 220b, and multiple sacrificial semiconductor layers 230 are formed on the substrate 110. The multiple sacrificial insulating layers 210, multiple base insulating layers 220b, and multiple sacrificial semiconductor layers 230 can be stacked alternately on the substrate 110.

[0135] For example, the substrate insulating layer 220b may be located on the sacrificial insulating layer 210, but may not be located below the sacrificial insulating layer 210, and the substrate insulating layer 220b may be located below the sacrificial semiconductor layer 230, but may not be located on the sacrificial semiconductor layer 230.

[0136] After that, you can refer to Figures 5A to 37B To manufacture semiconductor memory devices 6. Figure 47B The semiconductor memory device 6 shown does not include Figures 3A to 3E The semiconductor memory device 1 shown includes a second substrate insulating layer among a plurality of substrate insulating layers 220, while a first substrate insulating layer is included as a plurality of substrate insulating layers 220b. The semiconductor memory device 6 may include a plurality of gate dielectric layers Goxb. Each of the plurality of gate dielectric layers Goxb may include a substrate insulating layer 220b and a channel covering insulating layer 280. The substrate insulating layer 220b may cover the lower surface of the channel pattern 270, and the channel covering insulating layer 280 may cover the upper surface, lower surface, and two side surfaces in the first horizontal direction (X direction) of the channel structure including the channel pattern 270 and the substrate insulating layer 220b covering the lower surface of the channel pattern 270.

[0137] Figure 48A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 48B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 48A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 48B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0138] refer to Figure 48A and Figure 48B Multiple sacrificial insulating layers 210, multiple base insulating layers 220b, and multiple channel material layers 270aP are formed on the substrate 110. The multiple sacrificial insulating layers 210, multiple base insulating layers 220b, and multiple channel material layers 270aP can be stacked alternately on the substrate 110.

[0139] After that, you can refer to Figures 5A to 20B as well as Figures 24A to 37B To manufacture semiconductor memory devices 7.

[0140] Figure 49A This is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 49B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 49A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 49B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0141] refer to Figure 49A and Figure 49B Multiple sacrificial insulating layers 210 and multiple sacrificial semiconductor layers 230 are formed on the substrate 110. The multiple sacrificial insulating layers 210 and multiple sacrificial semiconductor layers 230 may be stacked alternately on the substrate 110.

[0142] After that, you can refer to Figures 5A to 37B To manufacture semiconductor memory devices. Figure 49B The semiconductor memory device 8 shown may not include Figures 3A to 3E The semiconductor memory device 1 shown includes multiple substrate insulating layers 220. The semiconductor memory device 8 may include multiple gate dielectric layers (Goxc). Each of the multiple gate dielectric layers (Goxc) may include a channel covering insulating layer 280. The channel covering insulating layer 280 may cover the upper surface, lower surface, and two side surfaces in the first horizontal direction (X direction) of the channel pattern 270.

[0143] Figure 50AThis is a view illustrating a method for manufacturing a semiconductor memory device according to an embodiment, and Figure 50B This is a view illustrating a semiconductor memory device according to an embodiment. Specifically, Figure 50A Is along with Figure 4B A cross-sectional view taken at the position corresponding to line A-A', and Figure 50B Is along with Figure 3B A cross-sectional view taken from the position corresponding to line A-A'.

[0144] refer to Figure 50A and Figure 50B Multiple sacrificial insulating layers 210 and multiple channel material layers 270aP are formed on the substrate 110. The multiple sacrificial insulating layers 210 and multiple channel material layers 270aP can be stacked alternately on the substrate 110.

[0145] After that, you can refer to Figures 5A to 20B as well as Figures 24A to 37B To manufacture semiconductor memory devices.

[0146] Although the present disclosure has been described in detail with reference to preferred embodiments, the present disclosure is not limited to the above embodiments, and those skilled in the art can make various modifications and changes within the technical concept and scope of the present disclosure.

[0147] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims. Specific functions described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, in some cases, one or more features from the combination may be removed from that combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Channel pattern; A gate electrode layer, the gate electrode layer surrounding at least a portion of each of the upper and lower surfaces of the channel pattern, the gate electrode layer extending in a first horizontal direction; Bit line structure, the bit line structure being connected to a first end of the channel pattern in a second horizontal direction orthogonal to the first horizontal direction, the bit line structure extending in a vertical direction; A capacitor structure connected to a second end of the channel pattern in the second horizontal direction; A gate dielectric layer is located between the channel pattern and the gate electrode layer, and the gate dielectric layer covers the upper surface of the channel pattern, the lower surface of the channel pattern, and the two side surfaces of the channel pattern that are opposite to each other in the first horizontal direction. as well as The bit line shielding structure is located on both sides of the bit line structure in the first horizontal direction, and extends in the vertical direction. The gate dielectric layer includes: A substrate insulating layer, the substrate insulating layer covering at least one of the upper surface and the lower surface of the trench pattern; and A trench covering insulation layer covers the upper surface of the trench structure, the lower surface of the trench structure, and two side surfaces of the trench structure that are opposite to each other in the first horizontal direction. The trench structure includes the trench pattern and the substrate insulation layer.

2. The semiconductor memory device according to claim 1, wherein, The substrate insulating layer includes a pair of substrate insulating layers that respectively cover the upper surface and the lower surface of the channel pattern.

3. The semiconductor memory device according to claim 1, wherein, The bitline structure includes a core conductive layer and an oxide semiconductor layer, with the oxide semiconductor layer located between the core conductive layer and the channel pattern.

4. The semiconductor memory device according to claim 1, wherein, The channel pattern comprises an oxide semiconductor material.

5. The semiconductor memory device according to claim 1, wherein, The horizontal width of the gate electrode layer in the second horizontal direction is smaller than the horizontal width of the channel pattern in the second horizontal direction.

6. The semiconductor memory device of claim 5, further comprising a gate spacer layer connected to a first end of the gate electrode layer in the second horizontal direction, and the gate spacer layer being located between the gate electrode layer and the bit line structure.

7. The semiconductor memory device of claim 6, further comprising a gate isolation insulating pattern connected to a second end of the gate electrode layer in the second horizontal direction. in, The gate isolation insulating pattern has a U-shaped vertical cross-section comprising a pair of horizontal portions and a vertical portion connected to the pair of horizontal portions. Wherein, the first end of each of the pair of horizontal portions in the second horizontal direction is connected to the second end of the gate electrode layer, and Wherein, the second end of each of the pair of horizontal portions in the second horizontal direction is connected to the corresponding end of the vertical portion at both ends in the vertical direction.

8. The semiconductor memory device according to claim 7, wherein, The thickness of each of the pair of horizontal portions of the gate isolation insulating pattern along the vertical direction is less than the thickness of the gate electrode layer along the vertical direction.

9. The semiconductor memory device of claim 6, further comprising a bit line spacer layer located between the bit line structure and the bit line shielding structure. in, The gate spacer layer and the bit line spacer layer comprise the same material.

10. The semiconductor memory device according to claim 1, wherein, The horizontal width of the bit line structure in the first horizontal direction is greater than the horizontal width of the bit line shielding structure in the first horizontal direction, and The horizontal width of the bit line structure in the second horizontal direction is equal to the horizontal width of the bit line shielding structure in the second horizontal direction.

11. A semiconductor memory device, the semiconductor memory device comprising: Multiple channel patterns, the multiple channel patterns being separated from each other in a first horizontal direction, a second horizontal direction orthogonal to the first horizontal direction, and a vertical direction; A plurality of gate electrode layers, the plurality of gate electrode layers respectively surrounding at least a portion of the upper surface and lower surface of each of the plurality of channel patterns, the plurality of gate electrode layers extending in the first horizontal direction; Multiple bit line structures are connected to a first end of the multiple channel patterns in the second horizontal direction, the multiple bit line structures are separated from each other in the first horizontal direction and extend in the vertical direction; Multiple bit line shielding structures are arranged alternately with multiple bit line structures in the first horizontal direction, and the multiple bit line shielding structures extend in the vertical direction. Multiple capacitor structures are connected to the second ends of the multiple channel patterns in the second horizontal direction; as well as A plurality of gate dielectric layers are respectively located between the plurality of channel patterns and the plurality of gate electrode layers, and the plurality of gate dielectric layers respectively cover the upper surface, the lower surface and two side surfaces opposite to each other in the first horizontal direction of the plurality of channel patterns. Each of the plurality of gate dielectric layers includes: A pair of substrate insulating layers, the pair of substrate insulating layers respectively covering the upper surface and the lower surface of a corresponding channel pattern in the plurality of channel patterns; and A trench covering insulation layer covers the upper surface, lower surface, and two side surfaces opposite each other in the first horizontal direction of a corresponding trench structure, the corresponding trench structure including the corresponding trench pattern and the pair of substrate insulation layers.

12. The semiconductor memory device according to claim 11, wherein, The channel patterns aligned in the vertical direction among the plurality of channel patterns are all connected to the two ends of the corresponding bit line structures in the second horizontal direction among the plurality of bit line structures.

13. The semiconductor memory device according to claim 11, wherein, Each of the plurality of bit line structures includes a core conductive layer and an oxide semiconductor layer, wherein the oxide semiconductor layer is located between the core conductive layer and each of the plurality of channel patterns, and Each of the plurality of channel patterns comprises an oxide semiconductor material.

14. The semiconductor memory device according to claim 13, wherein, The oxide semiconductor layer covers the two side surfaces of the core conductive layer in the second horizontal direction.

15. The semiconductor memory device according to claim 13, wherein, The oxide semiconductor layer is ring-shaped in a plane orthogonal to the vertical direction, and the oxide semiconductor layer surrounds the core conductive layer.

16. The semiconductor memory device of claim 11, further comprising: A plurality of gate spacer layers, the plurality of gate spacer layers being respectively connected to a first end of the plurality of gate electrode layers in the second horizontal direction, the plurality of gate spacer layers being respectively located between the plurality of gate electrode layers and the plurality of bit line structures; as well as Multiple gate isolation insulating patterns are respectively connected to the second ends of the multiple gate electrode layers in the second horizontal direction. In the second horizontal direction, the horizontal width of each of the plurality of gate electrode layers is smaller than the horizontal width of each of the plurality of channel patterns.

17. The semiconductor memory device according to claim 16, wherein, Each of the gate isolation insulating patterns has a U-shaped vertical cross-section comprising a pair of horizontal portions and a vertical portion connected to the pair of horizontal portions, and The plurality of channel patterns include a pair of channel patterns adjacent to each other in the vertical direction, and the plurality of gate electrode layers include a pair of gate electrode layers located between the pair of channel patterns in the vertical direction. The first ends of the pair of gate electrode layers are respectively connected to the first ends of the pair of horizontal portions in the second horizontal direction, and the two ends of the vertical portion in the vertical direction are respectively connected to the second ends of the pair of horizontal portions in the second horizontal direction.

18. A semiconductor memory device, the semiconductor memory device comprising: Multiple channel patterns, the multiple channel patterns being separated from each other in a first horizontal direction, a second horizontal direction orthogonal to the first horizontal direction, and a vertical direction, and each of the multiple channel patterns comprising an oxide semiconductor material; A plurality of gate electrode layers, the plurality of gate electrode layers respectively surrounding at least a portion of the upper surface and lower surface of each of the plurality of channel patterns, the plurality of gate electrode layers extending in the first horizontal direction; A plurality of bit line structures are connected to a first end of a plurality of channel patterns in a second horizontal direction, the plurality of bit line structures are separated from each other in the first horizontal direction and extend in the vertical direction, each of the plurality of bit line structures includes a core conductive layer and an oxide semiconductor layer, the oxide semiconductor layer being located between the core conductive layer and each of the plurality of channel patterns; Multiple bit line shielding structures are arranged alternately with multiple bit line structures in the first horizontal direction, and the multiple bit line shielding structures extend in the vertical direction and are separated from the multiple channel patterns. Multiple capacitor structures are connected to the second ends of the multiple channel patterns in the second horizontal direction; as well as A plurality of gate dielectric layers are respectively located between the plurality of channel patterns and the plurality of gate electrode layers, and the plurality of gate dielectric layers respectively cover the upper surface, the lower surface and two side surfaces opposite to each other in the first horizontal direction of the plurality of channel patterns. Each of the plurality of gate dielectric layers includes: A pair of substrate insulating layers, the pair of substrate insulating layers respectively covering the upper surface and the lower surface of a corresponding channel pattern in the plurality of channel patterns; and A trench covering insulation layer covers the upper surface, lower surface, and two side surfaces opposite each other in the first horizontal direction of a corresponding trench structure, the corresponding trench structure including the corresponding trench pattern and the pair of substrate insulation layers.

19. The semiconductor memory device according to claim 18, wherein, The channel patterns aligned in the vertical direction among the plurality of channel patterns are all connected to the two ends of the corresponding bit line structures in the second horizontal direction among the plurality of bit line structures, and The oxide semiconductor layer is ring-shaped in a plane orthogonal to the vertical direction, and the oxide semiconductor layer surrounds the core conductive layer.

20. The semiconductor memory device of claim 18, further comprising: A plurality of gate spacer layers, the plurality of gate spacer layers being respectively connected to a first end of the plurality of gate electrode layers in the second horizontal direction, the plurality of gate spacer layers being respectively located between the plurality of gate electrode layers and the plurality of bit line structures; as well as Multiple bit line spacer layers are respectively located between the multiple bit line structures and the multiple bit line shielding structures. Wherein, the plurality of gate spacer layers comprise the same material as the plurality of bit line spacer layers, and Wherein, the horizontal width of each of the plurality of gate electrode layers in the second horizontal direction is smaller than the horizontal width of each of the plurality of channel patterns in the second horizontal direction.

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