A two-dimensional flash memory of a barrier / capture layer integrated structure and a method of manufacturing the same

Abstract

This application relates to a two-dimensional flash memory with an integrated barrier / trap layer structure and its fabrication method. The memory includes an insulating substrate, a gate bottom electrode, a barrier layer, a tunneling layer, a two-dimensional semiconductor channel layer, and source and drain electrodes. The barrier layer is a high-dielectric-constant dielectric layer with inherent point defects, serving both charge blocking and charge trapping functions. The tunneling layer is a two-dimensional insulating layer with low defect state density, forming a van der Waals interface with the two-dimensional channel layer without dangling bonds. By optimizing the thickness ratio of the barrier layer and the tunneling layer and the interface cleanliness design, reversible injection and release of electrons under positive and negative gate voltage pulses are achieved. The method includes steps such as photolithography to define the gate, dielectric atomic layer deposition, two-dimensional material transfer, and annealing. This application features a simplified structure, high tunneling efficiency, ultrafast erase / write characteristics, and excellent data retention capabilities.

Description

Technical Field

[0001] This application relates to the field of semiconductor non-volatile memory, and in particular to a charge-trapping flash memory based on a barrier / trapping layer integrated with a two-dimensional van der Waals heterostructure and a method for fabricating the same. Background Technology

[0002] In recent years, with the rapid development of mobile internet, the Internet of Things, artificial intelligence, and big data technologies, the demand for data storage has exploded. As one of the mainstream non-volatile storage technologies, flash memory has been widely used in mobile terminals, embedded systems, solid-state drives, and data center storage systems due to its advantages such as simple structure, low power consumption, fast read and write speeds, ease of large-scale integration, and continuously decreasing unit cost. As application scenarios increasingly demand high-speed storage, low-latency access, and high reliability, flash memory technology continues to evolve towards higher density, lower power consumption, and faster erase and write speeds.

[0003] Traditional flash memory devices mainly include two basic structures: floating-gate NOR flash memory and NAND flash memory. Floating-gate flash memory achieves electron injection and storage by placing a conductive floating gate between the control gate and the channel, thereby changing the threshold voltage and completing data storage. However, as process nodes shrink to below 32 nm, traditional floating-gate structures face severe miniaturization bottlenecks. The core problem lies in the fact that the memory stack-up structure typically includes relatively thick tunneling oxide and barrier oxide layers. To ensure good data retention characteristics, the thickness of the tunneling oxide layer generally needs to be greater than 8 nm; otherwise, electrons stored in the floating gate are prone to leakage through the Frenkel-Poole mechanism or direct tunneling, leading to a decrease in retention time. During continuous device miniaturization, the oxide layer thickness is difficult to further reduce, thus limiting the size scaling of floating-gate flash memory.

[0004] For NOR flash memory, the programming mechanism primarily relies on hot-electron (CHE) injection. The generation of CHE requires a strong lateral electric field near the drain, necessitating a deep and steep drain junction structure. As process nodes descend below 45 nm, junction breakdown, short-channel effects, and leakage current increase significantly, drastically reducing device design space. Because the tunneling oxide layer is difficult to reduce simultaneously, gate control capability decreases, and short-channel effects become even more difficult to suppress, thus impacting programming efficiency and device reliability.

[0005] For NAND flash memory, its advantages lie in its high cell density and large storage capacity per unit area. However, under high-density integration, it also faces the problem of crosstalk between floating gates. As the cell spacing continues to decrease, the parasitic capacitive coupling between adjacent floating gates increases, leading to increased charge interference and read / write noise. Furthermore, due to space constraints, the control gate cannot completely surround the floating gate structure, limiting the gate coupling ratio and affecting the accuracy of threshold voltage regulation. These issues collectively restrict the further development of traditional silicon-based floating gate flash memory at advanced nodes.

[0006] To overcome the physical limitations of traditional silicon-based materials, researchers have begun exploring novel materials and structures. In recent years, two-dimensional (2D) materials have attracted widespread attention due to their unique physical properties. Each layer of a 2D material is atomically thin, with no dangling bonds on the surface. Adjacent layers are bonded by van der Waals forces, enabling high-quality interface stacking without considering lattice mismatch issues. Single-layer or few-layer 2D materials can be prepared by mechanical exfoliation from bulk crystals or through methods such as chemical vapor deposition. Utilizing the stackable nature of 2D materials, various van der Waals heterostructures can be constructed, thereby achieving structural engineering control.

[0007] Two-dimensional semiconductor materials, with their atomic-level thickness and extremely thin channels, restrict electron movement within the two-dimensional plane. This allows for more precise control of the channel via the gate electric field, effectively suppressing short-channel effects. Therefore, two-dimensional materials are considered one of the key potential alternatives in the post-Moore's Law era. Furthermore, the two-dimensional material system is rich, including various types such as transition metal chalcogenides, black phosphorus, and boron nitride. Different materials can form heterostructures, providing ample space for the design of novel memory mechanisms. Existing research has shown that flash memory devices built based on two-dimensional materials have significant advantages in programming speed, with some reports indicating that programming times can be reduced to the picosecond level.

[0008] Regarding the aforementioned technologies, the inventors believe that silicon-based flash memory devices are still generally limited by insufficient charge tunneling efficiency. Traditional floating gate structures require a thick oxide layer to achieve charge isolation, which sacrifices programming speed to some extent. Although charge-trapping memory structures can improve this problem to some extent, there is still room for optimization in terms of interface quality and charge retention. Summary of the Invention

[0009] To address the technical problem of insufficient charge tunneling efficiency in current silicon-based flash memory devices, this application provides a two-dimensional flash memory with an integrated barrier / trap layer structure and its fabrication method.

[0010] This application provides a two-dimensional flash memory with an integrated barrier / capture layer structure, employing the following technical solution: In a first aspect, a two-dimensional flash memory with an integrated barrier / capture layer structure includes an insulating substrate, wherein a gate bottom electrode is disposed on the surface of the insulating substrate; Includes a barrier layer covering the gate bottom electrode and part of the insulating substrate; Includes a tunneling layer covering the barrier layer; Includes a two-dimensional semiconductor channel layer covering the tunneling layer; Includes the source and drain electrodes disposed on the two-dimensional semiconductor channel layer; Wherein: the barrier layer is a high dielectric constant layer containing inherent point defects, used to realize charge trapping and storage functions; The tunneling layer is a two-dimensional insulating layer with low defect state density, forming a van der Waals heterostructure interface with the two-dimensional semiconductor channel layer. The two-dimensional semiconductor channel layer completely covers the area of ​​the tunneling layer; The source and drain electrodes respectively overlap with the two-dimensional semiconductor channel layer, and the channel region between the source and drain is completely within the coverage area of ​​the tunneling layer; The barrier layer has both charge blocking and charge trapping functions, forming an integrated barrier / trap layer structure.

[0011] By adopting the above technical solution, a storage stack structure integrating the functions of a blocking layer and a trapping layer is constructed in a two-dimensional material system. This achieves the synergistic effect of charge blocking and charge trapping in the same high-dielectric-constant dielectric, simplifying the complex stacking design of traditional floating gate or multi-layer charge trapping structures. Utilizing the dangling-bond-free van der Waals interface formed between the two-dimensional insulating tunneling layer with low defect state density and the two-dimensional semiconductor channel layer, the interface scattering and trap state density can be effectively reduced, improving interface quality and gate control efficiency, thereby enhancing charge tunneling efficiency. By optimizing the thickness and material combination of the tunneling layer and the blocking layer, electrons can be rapidly and controllably injected into the inherent defects in the blocking layer and stably stored under the action of an applied gate voltage pulse. At the same time, reversible release is achieved under the action of reverse voltage, improving programming / erasing speed, enhancing data retention capability and polymorphic storage adjustability, effectively suppressing crosstalk between adjacent cells and short-channel effects, and meeting the application requirements of high-density integration and low-power non-volatile memory.

[0012] Optionally, the insulating substrate is a Si / SiO2 substrate, and the SiO2 layer has a thickness of 100 nm or 300 nm. The gate bottom electrode material is selected from one or more combinations of Cr, Ti, Sb, Au, and Pt; The barrier layer is an HfO2 layer with a thickness of 10-20 nm, preferably 15 nm. The tunneling layer is a hexagonal boron nitride (BN) layer with a thickness of 5-15 nm, preferably 10 nm.

[0013] By adopting the above technical solutions, stable device support and gate isolation are achieved using Si / SiO2 substrates, and a high work function metal is selected as the gate bottom electrode to improve the electric field control capability. HfO2 is used as a high dielectric constant barrier layer to provide sufficient charge trapping centers while ensuring a good gate coupling ratio. Hexagonal boron nitride with low defect states is used as a tunneling layer to effectively reduce interface traps and optimize the tunneling barrier, thereby improving erase and write speed and device reliability while maintaining data retention capability.

[0014] Optionally, the two-dimensional semiconductor channel layer (5) is selected from one or more of MoS2, WSe2, WS2, and InSe; The source (6) and drain (7) materials are selected from one or more combinations of Cr, Ti, Sb, Au, Pt and Pd, and the thickness is 40-60 nm.

[0015] By adopting the above technical solution and selecting two-dimensional semiconductor materials such as MoS2, WSe2, WS2, and InSe as the channel layer, their atomic-level thickness and excellent carrier mobility characteristics can be utilized to improve gate control capability and suppress short-channel effects. At the same time, by using metals such as Cr, Ti, Au, Pt, and Pd as source and drain electrodes and optimizing the thickness range, it is beneficial to form good ohmic contacts, reduce contact resistance, and improve the device switching ratio and read / write stability.

[0016] Optionally, the barrier layer is formed by atomic layer deposition, creating uniformly distributed inherent point defects within it to serve as charge trapping centers.

[0017] By adopting the above technical solution, atomic-level precise control of film thickness and excellent uniformity are achieved. At the same time, controllable and uniformly distributed inherent point defects are introduced during the growth process to serve as stable charge trapping centers, thereby improving charge storage density and consistency. While ensuring good insulation performance, data retention capability is enhanced, and the repeatability and reliability of batch device fabrication are improved.

[0018] Optionally, the tunneling layer and the two-dimensional semiconductor channel layer are connected by a van der Waals interface without dangling bonds.

[0019] By adopting the above technical solutions, the interface state density and defect traps are effectively reduced, carrier scattering and interface charge trapping phenomena are reduced, thereby improving channel carrier mobility and gate control efficiency; at the same time, the interface stability and bandgap matching accuracy are improved, the tunneling barrier structure is optimized, faster programming and erasing speeds are achieved while ensuring data retention characteristics, and the reliability of device operation is enhanced.

[0020] Optionally, the device enables electrons to be injected from the channel through the tunneling layer into the barrier layer defect under the action of a positive gate pulse to complete the programming operation, and enables electrons to be released in the reverse direction under the action of a negative gate pulse to complete the erasure operation.

[0021] By adopting the above technical solution, the reversible injection and release of electrons between the channel and barrier layer defects is controlled by positive and negative gate pulses to achieve stable programming and erasing functions. This mechanism features fast response speed and precise threshold voltage control, forming a clear storage window. It also supports multi-level charge modulation, improves data storage density, and enhances data retention reliability while ensuring low-power operation.

[0022] In a second aspect, a method for fabricating a two-dimensional flash memory with an integrated blocking / capturing layer structure as described in any one of claims 1-6, comprising the following steps: Step S1: Clean the Si / SiO2 substrate by sequentially cleaning it with acetone, isopropanol and deionized water; Step S2: Define the gate pattern using photolithography, deposit the gate metal material and then peel it off to form a patterned gate bottom electrode; Step S3: A high dielectric constant barrier layer is grown on the bottom gate electrode using atomic layer deposition. Step S4: The BN tunneling layer is transferred to the surface of the barrier layer using a dry transfer method, and then subjected to thermal annealing in an inert gas atmosphere. Step S5: The two-dimensional semiconductor channel material is transferred to the surface of the BN tunneling layer using a polystyrene-assisted transfer method, and after removing the polystyrene protective layer, it is subjected to inert gas atmosphere thermal annealing. Step S6: Define the trench region using photolithography and etching processes; Step S7: Define the source and drain regions using electron beam lithography, deposit metal, and strip to form the source and drain electrodes.

[0023] By employing the above technical solutions, step S1, multi-stage solvent cleaning, effectively removes organic contaminants and particulate impurities from the substrate surface, providing a clean substrate for subsequent thin film deposition. Step S2 uses photolithography and metal deposition lift-off processes to form patterned gate bottom electrodes, ensuring precise control over the gate position and size and improving device consistency. Step S3 uses atomic layer deposition technology to grow a high-dielectric-constant barrier layer, achieving atomic-level thickness control and excellent coverage, while simultaneously forming controllable inherent defects within the film layer as charge trapping centers. Steps S4 and S5 construct the BN tunneling layer and the two-dimensional semiconductor channel layer using dry transfer and polystyrene-assisted transfer, respectively, and combine them with inert gas annealing to effectively remove transfer residues, improve interface quality, and form a clean van der Waals heterostructure interface. Steps S6 and S7 use fine photolithography and electron beam lithography to define the channel and source / drain regions, ensuring that the channel is completely within the coverage area of ​​the tunneling layer and achieves good ohmic contact. The overall process combines the advantages of high precision, good interface cleanliness, and strong repeatability, effectively improving device tunneling efficiency, storage consistency, and batch fabrication reliability.

[0024] Optionally, the heat annealing temperature in steps S4 and S5 is 200°C, and the annealing time is 2-3 hours.

[0025] By adopting the above technical solution, organic residues and adsorbed impurities during the transfer process can be effectively removed without damaging the two-dimensional material structure. This repairs micro-defects at the interface, improves the interface cleanliness and bonding stability between the BN tunneling layer and the two-dimensional channel layer, thereby improving carrier transport characteristics and enhancing device consistency and long-term operational reliability.

[0026] Optionally, step S2 may include oxygen plasma treatment of the gate bottom electrode surface to obtain a clean interface.

[0027] By adopting the above technical solutions, organic contaminants and adsorbed impurities on the metal surface can be effectively removed, surface activity and wettability can be improved, the interfacial bonding quality during subsequent barrier layer deposition can be enhanced, and the density of interfacial defects and accumulation of parasitic charges can be reduced, thereby improving the gate electric field coupling efficiency and the overall stability and consistency of the device.

[0028] Optionally, the inert gas is nitrogen or argon.

[0029] By adopting the above technical solutions, oxidation or other chemical reactions of materials under high temperature conditions are avoided, preventing damage to the interface layer or the introduction of new defects. At the same time, a stable and controllable heat treatment atmosphere is provided, which is conducive to removing residual organic matter and maintaining the structural integrity of the two-dimensional material and dielectric layer, thereby improving the device interface quality and electrical performance stability.

[0030] In summary, this application includes at least one of the following beneficial technical effects: 1. By constructing a high-dielectric-constant dielectric structure that integrates the functions of the blocking layer and the trapping layer, charge blocking and charge trapping can be completed synergistically in the same layer, simplifying the complex stacking design of traditional floating gate or multilayer charge trapping structures, reducing the complexity of device structure and fabrication difficulty, while improving structural stability and process compatibility. 2. By relying on the dangling bond-free van der Waals interface formed between the low-defect-state two-dimensional insulating tunneling layer and the two-dimensional semiconductor channel layer, the interface state density and carrier scattering are significantly reduced, the channel mobility and gate control efficiency are improved, the band matching relationship is optimized, and the controllability of charge injection and release processes is enhanced. 3. By precisely controlling the materials and thickness of the barrier layer and tunneling layer, rapid and reversible tunneling and stable capture and storage of electrons under the action of an external gate pulse are achieved, expanding the storage window, improving programming / erasing speed and data retention capability, and supporting multi-level charge modulation to improve storage density; 4. Effectively suppresses short-channel effects and crosstalk between adjacent memory cells, enhances device electrical consistency and long-term operational reliability, while also possessing high integration and low power consumption characteristics, meeting the application requirements of high-density two-dimensional non-volatile memory. Attached Figure Description

[0031] Figure 1 This is a side view of a charge-trapping two-dimensional flash memory with an integrated blocking / trapping layer structure.

[0032] Figure 2 This is a top view of a charge-trapping two-dimensional flash memory with an integrated barrier / trapping layer structure.

[0033] Figure 3 A flowchart illustrating the fabrication method of a charge-trapping two-dimensional flash memory with an integrated barrier / trapping layer structure.

[0034] Figure 4 Flat band voltage energy band diagram of a charge-trapping two-dimensional flash memory with an integrated blocking / trapping layer structure.

[0035] Figure 5 The ultrafast erase / write characteristics of a charge-trapping two-dimensional flash memory with an integrated barrier / trapping layer structure.

[0036] Figure 6 A stepwise variation diagram of the conductance of a charge-trapping two-dimensional flash memory with an integrated blocking / trapping layer structure.

[0037] Figure 7 Retention characteristic curves of a charge-trapping two-dimensional flash memory with an integrated barrier / trapping layer structure.

[0038] Explanation of reference numerals in the attached figures: 1. Insulating substrate; 2. Gate bottom electrode; 3. Barrier layer; 4. Tunneling layer; 5. Two-dimensional material channel layer; 6. Source; 7. Drain. Detailed Implementation

[0039] The following is in conjunction with the appendix Figure 1-7 This application will be described in further detail.

[0040] This application discloses a two-dimensional flash memory with an integrated barrier / capture layer structure. (Refer to...) Figure 1 , Figure 2 It includes an insulating substrate 1, a gate bottom electrode 2 disposed on the surface of the insulating substrate 1; a barrier layer 3 covering the gate bottom electrode 2 and part of the insulating substrate 1; a tunneling layer 4 covering the barrier layer 3; a two-dimensional semiconductor channel layer 5 covering the tunneling layer 4; and a source electrode 6 and a drain electrode 7 disposed on the two-dimensional semiconductor channel layer 5. Wherein: the barrier layer 3 is a high dielectric constant layer containing inherent point defects, used to realize charge trapping and storage functions; the tunneling layer 4 is a two-dimensional insulating layer with low defect state density, forming a van der Waals heterostructure interface with the two-dimensional semiconductor channel layer 5; the two-dimensional semiconductor channel layer 5 completely covers the tunneling layer 4; the source 6 and drain 7 respectively partially overlap with the two-dimensional semiconductor channel layer 5, and the channel region between the source and drain is completely located within the coverage of the tunneling layer 4; the barrier layer 3 has both charge blocking and charge trapping functions, forming an integrated barrier / trapping layer structure.

[0041] The above technical solution achieves synergistic optimization of structural simplification and performance improvement by constructing an integrated barrier / trapping layer structure in a two-dimensional material system. First, the barrier layer uses a high-dielectric-constant dielectric material with inherent point defects. While providing good insulation and electric field coupling capabilities, it can be directly used as a charge trapping and storage medium, integrating the functions of the barrier and trapping layers, which were previously independent in traditional memory, into a single layer. This reduces the number of stacked layers and interfaces, effectively reducing interface defect accumulation and process complexity, and improving device structural stability and fabrication consistency. Second, the tunneling layer uses a two-dimensional insulating material with low defect state density and forms a dangling-bond-free van der Waals heterostructure interface with the two-dimensional semiconductor channel layer. This significantly suppresses interface state density and carrier scattering, reduces charge recombination and instability effects caused by interface traps, improves channel carrier mobility and gate control efficiency, and makes electric field modulation more precise and controllable. Simultaneously, the tunneling layer... With the two-dimensional semiconductor channel layer completely covering the tunneling layer, the entire effective channel region between the source and drain is under the control of the tunneling layer. This ensures that charge injection and release processes occur within a controlled area, avoiding edge leakage and local electric field distortion, and improving the electrical consistency and repeatability of the device. The structural design of partial overlap between the source and drain and the channel layer facilitates the formation of stable electrical contacts, reduces contact resistance, and improves read / write current modulation capability and on / off ratio. Under the action of an electric field, electrons can be injected through the tunneling layer into inherent point defects in the barrier layer and stably captured, achieving significant threshold voltage drift and a considerable storage window. Reversible release can be achieved under the action of a reverse electric field, providing excellent programming / erasing characteristics. Overall, it improves charge storage density and data retention capability, effectively suppresses short-channel effects and crosstalk between adjacent cells, and combines high integration, low power consumption, and good reliability, making it suitable for the application requirements of novel high-density two-dimensional non-volatile memory devices.

[0042] The insulating substrate 1 is a Si / SiO2 substrate, which provides a mature and stable process foundation and excellent electrical isolation performance. The SiO2 layer thickness is 100 nm or 300 nm, which not only ensures good gate insulation capability, but also optimizes the electric field distribution and parasitic capacitance according to the device control requirements, thereby improving the overall stability and consistency of the device. The material of the gate bottom electrode 2 is selected from one or more combinations of Cr, Ti, Sb, Au, and Pt; The barrier layer 3 is an HfO2 layer with a thickness of 10-20 nm, preferably 15 nm; The tunneling layer 4 is a hexagonal boron nitride (BN) layer with a thickness of 5-15 nm, preferably 10 nm; The two-dimensional semiconductor channel layer 5 is selected from one or more of MoS2, WSe2, WS2, and InSe. The threshold voltage and electric field coupling efficiency of the device are adjusted according to the difference in work function, thereby improving the gate's ability to control the channel carriers. The source electrode 6 and drain electrode 7 are made of one or more of Cr, Ti, Sb, Au, Pt and Pd, with a thickness of 40-60 nm. Using metals such as Cr, Ti, Sb, Au, Pt and Pd for the source electrode 6 and drain electrode 7 and controlling the thickness within the range of 40-60 nm is beneficial for forming low contact resistance and stable ohmic contact, thereby enhancing the read / write current drive capability and switching ratio. The barrier layer 3 is formed by atomic layer deposition, which creates uniformly distributed intrinsic point defects within it to serve as charge trapping centers. The barrier layer uses HfO2, a high dielectric constant material, and its thickness is controlled within the range of 10-20 nm. This provides sufficient charge trapping space while improving the gate coupling ratio. Forming this layer by atomic layer deposition enables atomic-level thickness control and excellent film uniformity. At the same time, the uniformly distributed intrinsic point defects within the film serve as charge trapping centers, improving charge storage density, data retention capability, and batch fabrication consistency. The tunneling layer 4 and the two-dimensional semiconductor channel layer 5 are connected by a van der Waals interface without dangling bonds. The tunneling layer is made of hexagonal boron nitride (BN) with a thickness of 5-15 nm. It has a low intrinsic defect density and a wide band gap, which can form a stable and controllable tunneling barrier. This enables efficient and reversible electron tunneling while ensuring data retention. At the same time, the van der Waals interface without dangling bonds between BN and the two-dimensional semiconductor channel layer can significantly reduce the interface state density and carrier scattering, improve the channel mobility and gate control efficiency, and reduce charge instability caused by interface traps. The combination of materials and structure ensures a high storage window and fast programming / erasing characteristics, while also taking into account data retention capabilities, low power consumption operation and long-term reliability, significantly improving the overall performance of 2D flash memory.

[0043] The fabrication method of a two-dimensional flash memory with an integrated barrier / capture layer structure is described in reference [reference]. Figures 3-7 It includes the following steps: Step S1: Clean the Si / SiO2 substrate by sequentially cleaning it with acetone, isopropanol and deionized water; Step S2: Define the gate pattern using photolithography, deposit the gate metal material and strip it to form a patterned gate bottom electrode. Before step S2, oxygen plasma treatment is performed on the surface of the gate bottom electrode to obtain a clean interface. Step S3: A high dielectric constant barrier layer is grown on the bottom gate electrode using atomic layer deposition. Step S4: The BN tunneling layer is transferred to the surface of the barrier layer using a dry transfer method, and then subjected to thermal annealing in an inert gas atmosphere. The thermal annealing temperature is 200℃ and the annealing time is 2-3 hours. The inert gas is nitrogen or argon. Step S5: The two-dimensional semiconductor channel material is transferred to the surface of the BN tunneling layer using a polystyrene-assisted transfer method. After removing the polystyrene protective layer, the material is subjected to inert gas atmosphere thermal annealing at a temperature of 200°C for 2-3 hours. Step S6: Define the trench region using photolithography and etching processes; Step S7: Define the source and drain regions using electron beam lithography, deposit metal, and strip to form the source and drain electrodes.

[0044] The preparation method also includes the design of the storage stack structure and the engineering of the clean interface; Storage stack-up architecture design: A high-dielectric-constant dielectric is used as the barrier layer, and a low-dielectric-constant dielectric BN with high lattice quality is used as the tunneling layer. The thickness ratio is optimized to achieve the best tunneling barrier and gate-control coupling ratio, thereby improving tunneling efficiency. For example, reducing the tunneling layer thickness can improve tunneling efficiency, but it will increase the probability of electron leakage through the tunneling layer and reduce the retention characteristics. Increasing the tunneling layer thickness enhances the retention characteristics, but it also increases the tunneling difficulty and reduces the operating speed and storage capacity. Decreasing the barrier layer thickness will increase the gate capacitance, but it may lead to gate injection. Increasing the barrier layer thickness will increase the operating voltage, which is not conducive to low-power operation. Cleanroom interface engineering: In step 2, the bottom electrode surface is cleaned and activated by oxygen plasma treatment to obtain an ultra-clean interface; in steps 4 and 5, organic residues from the sample preparation process are removed by inert gas atmosphere thermal annealing treatment, and the interface is characterized by optical microscopy (OM), atomic force microscopy (AFM), and scanning electron microscopy (SEM) to ensure the cleanliness and smoothness of the interface.

[0045] Reference Figure 4 , Figure 4 The energy band diagram of the flash memory device under flat-band voltage is shown. When a positive voltage pulse is applied to the gate, electrons in the channel tunnel through the BN barrier into defects on the upper part of the HfO2 barrier layer and are trapped. After the external electric field is removed, due to the large barrier, the electrons trapped by the HfO2 defects cannot return to the channel, thus completing the programming operation and causing a positive shift in the threshold voltage, making the channel exhibit a high-resistivity state when the gate voltage is 0 V. Conversely, when a negative voltage pulse is applied, electrons trapped by the HfO2 defects can be injected into the channel in the reverse direction, completing the erase operation and causing a negative shift in the threshold voltage. After the negative gate voltage is removed, the device adjusts to a high-conductivity state.

[0046] This application provides a charge-trapping two-dimensional flash memory device with an integrated barrier / trapping layer structure by combining the excellent properties of two-dimensional materials with the inherent defects in oxide dielectrics. This memory exhibits superior performance indicators, possessing a high on / off ratio (>10).6 With its ultra-fast programming speed (50 nanoseconds) and data retention capability of over ten years, it can drive the development of advanced high-performance non-volatile storage technologies.

[0047] The beneficial technical effects of the technical solution in this application are as follows: 1. The memory has a large storage window, which can display multiple distinguishable states (>8) through changes in pulse amplitude. 2. Under the stimulation of multiple consecutive identical weak pulses, a distinguishable stepwise change in conductance was achieved, demonstrating the ability to switch conductance stepwise in an analog manner controlled by the number of pulses; 3. By utilizing two-dimensional material band engineering and interface engineering, the tunneling barrier is reduced and the tunneling efficiency is improved, enabling the memory to achieve ultra-fast erasure and write speeds in the tens of nanoseconds. 4. Thanks to the excellent interface properties and high-quality lattice structure of two-dimensional materials, the memory's fast erase and write operations have a ten-year non-volatile data retention characteristic; This technical solution overcomes the bottlenecks such as crosstalk between adjacent device cells during the miniaturization of traditional silicon-based floating gate flash memory, realizing a multi-bit memory device that combines ultra-fast erase and write characteristics with excellent retention characteristics. It solves the shortcomings of traditional flash memory in terms of operating speed due to the limitation of charge tunneling efficiency, and provides a foundation for the next generation of high-speed non-volatile memory technology, with the potential for ultra-large-scale applications.

[0048] The key technical points of this application are as follows: The advantage of this technical solution lies in its integrated barrier / trap layer structure. The charge-trapping two-dimensional flash memory device with an integrated barrier / trap layer has a simplified storage stack-up structure. While possessing ultra-fast erase and write characteristics, it also exhibits excellent data retention characteristics. The memory can perform erase and write operations with pulses of tens of nanoseconds in width, and the retention time at room temperature exceeds 10... 4 The test measured the conductance in seconds and verified its non-volatile properties over ten years. Under stimulation by multiple consecutive identical weak pulses, it achieved distinguishable conductance level changes, demonstrating the ability to switch conductance level by level in an analog manner controlled by the number of pulses.

[0049] The key technical protections of this application are as follows: The core technology of this application lies in the oxide dielectric barrier layer containing inherent defects and the BN / MoS2 van der Waals heterostructure. These defects have an equilibrium amount of point defects at any temperature. The inherent defects in the ALD-grown barrier layer oxide trap charges, resulting in a simpler device structure compared to floating-gate flash memory. When the floating gate thickness is close to zero, the charge is stored on the upper part of the insulating layer. BN has a low defect state density and no dangling bonds or charge traps on its surface. The BN / MoS2 van der Waals heterostructure possesses an atomically flat layered interface, effectively reducing the tunneling barrier and enabling ultra-fast programming / erasing characteristics for flash memory devices.

[0050] The implementation principle of this application's embodiment of a two-dimensional flash memory with an integrated barrier / trapping layer structure and its fabrication method is as follows: Based on the excellent interface physical properties of two-dimensional materials and the charge trapping mechanism of inherent point defects in high-dielectric-constant oxides, a vertical stacked structure of "two-dimensional semiconductor channel / BN tunneling layer / defective HfO2 barrier layer" is constructed to achieve controllable tunneling, trapping, and release of charges. The inherent point defects naturally present and uniformly distributed in the high-dielectric-constant HfO2 dielectric formed by atomic layer deposition (ALD) serve as stable charge trapping centers, achieving charge storage and retention under an applied electric field. Simultaneously, the dangling-bond-free van der Waals heterostructure interface formed between BN and a two-dimensional semiconductor (such as MoS2) reduces the interface state density and carrier scattering, improving the efficiency and controllability of the tunneling process. During programming, when a positive voltage pulse is applied to the gate, electrons in the channel are driven by the vertical electric field... Electrons, driven by the BN tunneling layer barrier, are injected into the inherent defects in the HfO2 barrier layer and captured. Due to the large band gap and high barrier height of HfO2, electrons are difficult to spontaneously return to the channel after the applied electric field is removed, thus achieving stable storage. This causes a positive shift in the device threshold voltage, and the channel is in a high-resistivity state at zero gate voltage. During the erase process, when a negative gate voltage pulse is applied, the electric field direction is reversed. The captured electrons return to the channel through the BN tunneling layer under the action of the reverse electric field, realizing charge release. The device threshold voltage shifts negatively, and the channel returns to a high-conductivity state, thus completing the reversible erase operation. By optimizing the thickness ratio of the BN tunneling layer and the HfO2 barrier layer, a balance is achieved between tunneling efficiency and retention characteristics: a thinner BN layer is beneficial to improve the tunneling rate and achieve nanosecond-level programming / erasing; an appropriately thick HfO2 layer enhances the charge confinement capability and ensures long-term non-volatile storage. The atomically flat interface and low-defect characteristics of two-dimensional materials further reduce parasitic traps and random charge fluctuations, improving device consistency and repeatability; enabling two-dimensional charge-trapping flash memory devices with simplified structure, ultra-fast erasure and write speeds, and long-term retention, providing a new path for the realization of next-generation non-volatile memory technology with high density, low power consumption, and multi-bit controllability.

[0051] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A two-dimensional flash memory with an integrated blocking / capturing layer structure, characterized in that: include An insulating substrate (1) and a gate bottom electrode (2) disposed on the surface of the insulating substrate (1). Includes a barrier layer (3) covering the gate bottom electrode (2) and part of the insulating substrate (1); Including a tunneling layer (4) covering the barrier layer (3); Includes a two-dimensional semiconductor channel layer (5) covering the tunneling layer (4); Includes a source (6) and a drain (7) disposed on the two-dimensional semiconductor channel layer (5); Wherein: the barrier layer (3) is a high dielectric constant dielectric layer containing inherent point defects, used to realize charge trapping and storage functions; The tunneling layer (4) is a two-dimensional insulating layer with low defect state density, forming a van der Waals heterostructure interface with the two-dimensional semiconductor channel layer (5); The two-dimensional semiconductor channel layer (5) completely covers the area of ​​the tunneling layer (4); The source (6) and drain (7) partially overlap with the two-dimensional semiconductor channel layer (5), and the channel region between the source and drain is completely within the coverage area of ​​the tunneling layer (4). The barrier layer (3) has both charge blocking and charge trapping functions, forming an integrated barrier / trap layer structure.

2. The two-dimensional flash memory according to claim 1, characterized in that: The insulating substrate (1) is a Si / SiO2 substrate, and the SiO2 layer has a thickness of 100 nm or 300 nm. The material of the gate bottom electrode (2) is selected from one or more combinations of Cr, Ti, Sb, Au, and Pt; The barrier layer (3) is an HfO2 layer with a thickness of 10-20 nm, preferably 15 nm; The tunneling layer (4) is a hexagonal boron nitride (BN) layer with a thickness of 5-15 nm, preferably 10 nm.

3. The two-dimensional flash memory according to claim 1, characterized in that: The two-dimensional semiconductor channel layer (5) is selected from one or more of MoS2, WSe2, WS2, and InSe; The source (6) and drain (7) materials are selected from one or more combinations of Cr, Ti, Sb, Au, Pt and Pd, and the thickness is 40-60 nm.

4. The two-dimensional flash memory according to claim 1, characterized in that: The barrier layer (3) is formed by atomic layer deposition, which creates uniformly distributed inherent point defects within it to serve as charge trapping centers.

5. The two-dimensional flash memory according to claim 1, characterized in that: The tunneling layer (4) and the two-dimensional semiconductor channel layer (5) are connected by a van der Waals interface without dangling bonds.

6. The two-dimensional flash memory according to claim 1, characterized in that: The device performs programming operations by injecting electrons from the channel through the tunneling layer into the barrier layer defects under the action of a positive gate pulse, and performs erasure operations by releasing electrons in the reverse direction under the action of a negative gate pulse.

7. A method for fabricating a two-dimensional flash memory with an integrated blocking / capturing layer structure as described in any one of claims 1-6, characterized in that, Includes the following steps: Step S1: Clean the Si / SiO2 substrate by sequentially cleaning it with acetone, isopropanol and deionized water; Step S2: Define the gate pattern using photolithography, deposit the gate metal material and then peel it off to form a patterned gate bottom electrode; Step S3: A high dielectric constant barrier layer is grown on the bottom gate electrode using atomic layer deposition. Step S4: The BN tunneling layer is transferred to the surface of the barrier layer using a dry transfer method, and then subjected to thermal annealing in an inert gas atmosphere. Step S5: The two-dimensional semiconductor channel material is transferred to the surface of the BN tunneling layer using a polystyrene-assisted transfer method, and after removing the polystyrene protective layer, it is subjected to inert gas atmosphere thermal annealing. Step S6: Define the trench region using photolithography and etching processes; Step S7: Define the source and drain regions using electron beam lithography, deposit metal, and strip to form the source and drain electrodes.

8. The preparation method according to claim 7, characterized in that: The heat annealing temperature in steps S4 and S5 is 200°C, and the annealing time is 2-3 hours.

9. The preparation method according to claim 7, characterized in that: Prior to step S2, the surface of the gate bottom electrode is subjected to oxygen plasma treatment to obtain a clean interface.

10. The preparation method according to claim 7, characterized in that: The inert gas is nitrogen or argon.

Images