Transistor element and method for manufacturing the same

Abstract

The present application provides a kind of transistor element and its manufacturing method, the manufacturing method of transistor element includes the following steps: first, provide first conductive type epitaxial layer, set on substrate.Second, first conductive type epitaxial layer is implanted with second conductive type ion using first mask, to form second conductive type body region.Then, second conductive type body region is implanted with first conductive type ion using second mask, to form first conductive type heavily doped region in second conductive type body region.Finally, the second conductive type body region of two side edges of first conductive type heavily doped region is implanted with second conductive type oblique angle ion using second mask, to form two in-situ self-aligned second conductive type doped channel in the second conductive type body region of two side edges of first conductive type heavily doped region.

Description

Technical Field

[0001] This invention relates to a transistor device and a method for manufacturing the same, and more particularly, to a transistor device with low channel resistance and a method for manufacturing the same. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs), commonly known simply as power transistors, are field-effect transistors widely used in analog and digital circuits. They have become the mainstream power devices, dominating the market and frequently applied in various electronic and electrical fields. In particular, power transistors made using silicon carbide (SiC) substrates have gradually replaced traditional silicon-based power devices, and are widely used in high-voltage, high-temperature, and low-on-resistance high-speed power devices.

[0003] For example, compared to traditional insulated-gate bipolar transistors (IGBTs) using silicon substrates, silicon carbide (SiC) transistors offer higher breakdown voltages, allowing for smaller sizes and lower on-resistance. Furthermore, the high electron mobility of SiC results in faster switching speeds, making them more suitable for next-generation high-voltage and high-frequency applications. Therefore, optimizing power transistor structures to further reduce on-resistance (Ron) and improve switching speeds is a pressing issue for the industry. Summary of the Invention

[0004] The main objective of this invention is to provide an innovative transistor device and its manufacturing method, which has two synchronous self-aligned oblique ion implantation channels, which can reduce the channel length and avoid the problems caused by short-channel effect due to mask misalignment, thereby achieving the purpose of reducing on-resistance and improving switching speed and other device performance.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a transistor device, the method comprising the following steps: First, providing a first conductivity epitaxial layer disposed on a substrate. Second, performing second conductivity ion implantation on the first conductivity epitaxial layer using a first mask to form a second conductivity body region. Next, performing first conductivity ion implantation on the second conductivity body region using a second mask to form a first conductivity heavily doped region within the second conductivity body region. Finally, performing second conductivity angled ion implantation on the second conductivity body regions on both sides of the first conductivity heavily doped region using a second mask to form two in-situ self-aligned second conductivity doped channels within the second conductivity body regions on both sides of the first conductivity heavily doped region.

[0006] In an embodiment of the transistor device manufacturing method of the present invention, the second conductivity type oblique ion implantation has an implantation oblique angle between the second conductivity type oblique ion implantation and the vertical normal, the implantation oblique angle being between 35° and 45°.

[0007] In an embodiment of the transistor device manufacturing method of the present invention, the second conductivity type oblique ion implantation is performed with a doping energy of 20 to 100 (Kev).

[0008] In embodiments of the transistor device manufacturing method of the present invention, each in-situ self-aligned second conductivity type doped channel has a density of 1E13 to 5E13 (cm²). -2 The aluminum (Al) ion doping concentration per unit area.

[0009] In an embodiment of the transistor device manufacturing method of the present invention, the step of providing a first conductivity epitaxial layer includes providing an N-type lightly doped silicon carbide epitaxial layer.

[0010] In an embodiment of the transistor device manufacturing method of the present invention, the step of forming a second conductivity type body region includes forming a P-type lightly doped body region having a density of 1E12~1E13 (cm²). -2 The doping concentration per unit area.

[0011] In an embodiment of the transistor device manufacturing method of the present invention, the step of forming a first conductivity type heavily doped region includes forming an N-type heavily doped region having a density of 1E19~1E20 (cm²). -3 The doping concentration of ).

[0012] To achieve the above objectives, the present invention provides a transistor device comprising a silicon carbide substrate, an N-type drift layer, a P-type body region, an N-type heavily doped region, and two in-situ self-aligned P-type doped channels. The N-type drift layer is disposed on the silicon carbide substrate, the P-type body region is disposed within the N-type drift layer, the N-type heavily doped region is disposed within the P-type body region, and the two in-situ self-aligned P-type doped channels are disposed in the P-type body regions on either side of the heavily doped N-type body region.

[0013] In embodiments of the transistor device of the present invention, each in-situ self-aligned P-type doped channel has a diameter of 1E13 to 5E13 (cm²). -2 The aluminum (Al) ion doping concentration per unit area.

[0014] In embodiments of the transistor element of the present invention, each in-situ self-aligned P-type doped channel has a length of 0.5 to 1 micrometer (µm).

[0015] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0016] Figures 1 to 4 This is a schematic diagram illustrating the manufacture of a power transistor element in an embodiment of the present invention; Figure 5 This is a cross-sectional schematic diagram of a power transistor element in an embodiment of the present invention; and Figure 6 This is a schematic diagram of the process for manufacturing power transistor devices in an embodiment of the present invention. Detailed Implementation

[0017] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to this invention have been omitted and are not drawn, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0018] There are several ways to reduce on-resistance (Ron) to improve transistor device performance. For example, the silicon carbide substrate can be thinned; however, silicon carbide is a high-hardness material, and the thinning process is inefficient and costly. Another feasible approach is to shorten the channel length to reduce channel resistance, thereby reducing on-resistance and also accelerating switching speed, effectively reducing switching losses. Equation 1 below shows the relationship between channel resistance (Ron) and on-resistance (Ron). CH The relevant formulas are: (Equation 1) in, R CH This represents the channel resistance, indicating the resistance of the channel region of a transistor element.

[0019] L This represents the channel length, which is the distance between the source and the drain.

[0020] t ox This represents the thickness of the oxide layer, typically the thickness of the gate oxide layer.

[0021] W The channel width represents the lateral dimension of the transistor element's channel.

[0022] μ n Electron mobility describes the ability of electrons to move within a semiconductor.

[0023] ε 0 This represents the vacuum permittivity, with a value of approximately 8.85 × 10⁻⁶. -12 F / m.

[0024] ε r The relative permittivity of the oxide layer (e.g., silicon dioxide is about 3.9).

[0025] V GS,use Represents the gate-source voltage, which is the voltage applied between the gate and source under operating conditions.

[0026] V th This represents the threshold voltage (critical voltage), which is the gate-source voltage at which a transistor element begins to conduct.

[0027] From Equation 1, it can be seen that the channel resistance (R) CH The channel resistance (R) is directly proportional to the channel length (L), therefore, reducing the channel length (L) will reduce the channel resistance (R). CH This reduces the on-resistance (Ron). Please refer to the following for details. Figures 1 to 4 , Figures 1 to 4 A cross-sectional schematic diagram of a power transistor device manufactured according to an embodiment of the present invention is shown. Specifically, this power transistor device is a vertically diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET), as detailed below. The power transistor device has a substrate 100. In this embodiment, the substrate 100 is a first conductivity type silicon carbide substrate, for example, an N-type heavily doped silicon carbide substrate, to provide a low-resistance channel. A first conductivity type epitaxial layer 101 is provided on the substrate 100. The first conductivity type epitaxial layer 101 may be, but is not limited to, an N-type lightly doped silicon carbide epitaxial layer, serving as an N-type drift layer. The first conductivity type epitaxial layer 101 has a thickness of several micrometers (µm) to tens of micrometers (µm) and a thickness of 1E14~1E16 (cm²). -3 A lower doping concentration is used for power transistor devices to withstand high voltages. In a specific embodiment, the thickness and doping concentration of the first conductivity epitaxial layer 101 are designed according to the voltage withstand requirements of the power transistor device. Next, as... Figure 1 As shown, photoresist is deposited on the first conductive epitaxial layer 101. After a photolithography process, a patterned first mask (or first photomask) 102 is finally formed on the first conductive epitaxial layer 101.

[0028] Please refer to Figure 2 , Figure 2 The diagram illustrates a patterned first mask 102 used as an ion implantation mask to perform blanket ion implantation of a first conductivity epitaxial layer 101 with a second conductivity type, thereby defining and forming a second conductivity type body region 103 within the first conductivity type epitaxial layer 101. In a specific embodiment, the second conductivity type body region 103 is a lightly doped p-type body region, typically with aluminum (Al) or boron (B) as the p-type dopant. Preferably, because aluminum (Al) can form a shallower acceptor level and has good thermal stability, the present invention uses aluminum (Al) as the primary p-type dopant, and it has a p-type density of 1E12~1E13 (cm²). -2 The doping concentration per unit area.

[0029] Please refer to Figure 3 , Figure 3The diagram shows a patterned second mask (or second photomask) 104 deposited on a first conductivity epitaxial layer 101. Next, using the patterned second mask 104 as an ion implantation mask, a first conductivity ion implantation is performed overlay on the second conductivity bulk region 103 to define and form a first conductivity heavily doped region 105 within the second conductivity bulk region 103. In a specific embodiment, the first conductivity heavily doped region 105 is an N-type heavily doped region, typically with nitrogen (N) or phosphorus (P) as the dopant element. Preferably, the present invention uses nitrogen (N) as the primary N-type dopant element, and it has a density of 1E19~1E20 (cm²). -3 The doping concentration is adjusted to ensure that the source region of the device has low resistance and forms a good ohmic contact with the source metal.

[0030] Next, the manufacturing process of the channel layer for the power transistor device is carried out. It should be noted that, as mentioned earlier, this invention aims to reduce the channel resistance (R0). CH The technical means employed to achieve this goal is to reduce the channel length (L) according to the aforementioned Equation 1. Accordingly, there are two ways to achieve this reduction: firstly, using two masks in a two-stage exposure and development process to define the channel length (L). However, in practical applications, this method must consider the difference in channel length between adjacent active regions caused by process errors due to mask misalignment, which can lead to a short-channel effect (Drain-induced Barrier Lowering, DIBL) and affect the gate and source threshold voltages (V). th This leads to a decrease in equipotential properties. Therefore, when using this mask-limited channel length design method, the extent to which the channel length can be reduced is limited by the accuracy of the mask overlay.

[0031] In view of this, to avoid the limitation of channel length reduction caused by the short-channel effect, this invention discloses a synchronous (in-situ) self-aligned channel manufacturing method. Please refer to... Figure 4 In this invention, after forming the first conductivity type heavily doped region 105, a second conductivity type tilt ion implantation is simultaneously performed on the second conductivity type body regions 103 on both sides of the first conductivity type heavily doped region 105 using a second mask 104, so as to form two synchronous (in-situ) self-aligned second conductivity type doped channels 106 in the second conductivity type body regions 103 on both sides of the first conductivity type heavily doped region 105. Figure 4 As shown, the second type of conduction-type angled ion implantation has an implantation angle between it and the vertical normal. Inject at an angle Between 35° and 45°. On the other hand, in a specific embodiment, the second conductivity type oblique ion implantation uses P-type ions (e.g., aluminum (Al) ions) at a doping concentration of 1E13 to 5E13 (cm²) per unit area. -2 Ion implantation is performed with a doping energy of 20-250 keV, preferably 20-100 keV. It should be noted that the second conductivity type angled ion implantation provides sufficient P-type carriers at the surface of the second conductivity type body region 103 to handle situations where the gate voltage of the power transistor element exceeds a threshold voltage. Vth During the process, sufficient electron concentration is provided at the surface of the second conductivity type body region 103 to form a continuous inversion layer, thereby forming the second conductivity type doped channel 106. In a preferred embodiment, the length of the synchronously self-aligned second conductivity type doped channel 106 formed using the aforementioned disclosed process can be substantially shortened to 0.5 to 1 micrometer (µm), or even shorter, while also avoiding problems arising from mask stacking errors.

[0032] like Figure 5 As shown, preferably, to further reduce the contact resistance with the metal and suppress the base resistance of the parasitic PNP bipolar junction transistor (BJT), a second conductivity-type doped region 107 is further formed in the first conductivity-type heavily doped region 105. Specifically, it can be a P-type heavily doped region. Next, a gate metal 108, a source metal 109, and a drain metal 110 are formed on the transistor element, respectively, and then a metal contact process is performed with the gate region, the source region, and the back-side drain region of the element to complete the final structure of the power transistor element of the present invention. Please refer to... Figure 5 , Figure 5 A cross-sectional schematic diagram of the power transistor element of the present invention is shown.

[0033] Please refer to Figure 6 , Figure 6This diagram illustrates the process of manufacturing a power transistor device according to the present invention. First, in step S01, a first conductivity epitaxial layer is provided and disposed on a substrate. In step S02, second conductivity ions are implanted into the first conductivity epitaxial layer using a first mask to form a second conductivity body region. Next, in step S03, first conductivity ions are implanted into the second conductivity body region using a second mask to form a first conductivity heavily doped region within the second conductivity body region. Finally, in step S04, second conductivity angled ions are implanted into the second conductivity body regions on both sides of the first conductivity heavily doped region using a second mask to form two in-situ self-aligned second conductivity doped channels within the second conductivity body regions on both sides of the first conductivity heavily doped region. The descriptions of the relevant components in the aforementioned process steps are provided above and will not be repeated here.

[0034] In summary, this invention does not use mask stacking to control the channel length of the inversion region of the device. Instead, it adds an oblique second conductive ion implantation process after the first conductive ion (N+) implantation process to form a channel layer that is synchronously self-aligned to the N+ heavily doped region. This allows for precise control of the reduced channel length, significantly reducing on-resistance while avoiding problems such as short-channel effects caused by mask misalignment. This effectively improves device performance, such as switching speed.

[0035] The above embodiments are merely illustrative of the present invention and to explain its technical features, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims.

[0036] [Symbol Explanation] 100 substrate 101 First Conductivity Epitaxial Layer 102 First Mask 103 Second Conductivity Type Body Region 104 Second Mask 105 First conductivity type heavily doped region 106 Synchronous Self-Aligned Second Conductivity Doped Channel 107 Second conductivity type doped region 108 gate metal 109 Source Metal 110 drain metal Inject at an angle.

Claims

1. A method for manufacturing a transistor device, the method comprising: A first conductivity epitaxial layer is provided and disposed on the substrate; Using a first mask, second conductivity type ion implantation is performed on the first conductivity type epitaxial layer to form a second conductivity type body region; The second conductive body region is implanted with first conductive ions using a second mask to form a first conductive heavily doped region in the second conductive body region; as well as Using the second mask, second conductive type oblique ion implantation is performed on the second conductive type body regions on both sides of the first conductive type heavily doped region to form two synchronously self-aligned second conductive type doped channels in the second conductive type body regions on both sides of the first conductive type heavily doped region.

2. The method for manufacturing a transistor device as described in claim 1, wherein, The second conductive oblique ion implantation has an implantation oblique angle between itself and the vertical normal, the implantation oblique angle being between 35° and 45°.

3. The method for manufacturing a transistor device as described in claim 1, wherein, The second type of conductive oblique ion implantation is performed with a doping energy of 20~100 keV.

4. The method for manufacturing a transistor device as described in claim 1, wherein, Each synchronously self-aligned second conductivity type doped channel has a diameter of 1E13~5E13 cm. -2 The aluminum ion doping concentration per unit area.

5. The method for manufacturing a transistor device as described in claim 1, wherein, The step of providing the first conductivity epitaxial layer includes providing an N-type lightly doped silicon carbide epitaxial layer.

6. The method for manufacturing a transistor device as claimed in claim 1, wherein, The step of forming the second conductivity type body region includes forming a P-type lightly doped body region having a diameter of 1E12~1E13 cm. -2 The doping concentration per unit area.

7. The method for manufacturing a transistor device as claimed in claim 1, wherein, The step of forming the first conductivity type heavily doped region includes forming an N-type heavily doped region, the N-type heavily doped region having a diameter of 1E19~1E20 cm. -3 The doping concentration.

8. A transistor element, the transistor element comprising: silicon carbide substrate; An N-type drift layer is disposed on the silicon carbide substrate; The P-type body region is disposed in the N-type drift layer; An N-type heavily doped region is disposed in the P-type body region; as well as Two synchronously self-aligned P-type doped channels are disposed in the P-type body region on both sides of the heavily doped N-type region.

9. The transistor device of claim 8, wherein, Each synchronously self-aligned P-type doped channel has a diameter of 1E13~5E13 cm. -2 The aluminum ion doping concentration per unit area.

10. The transistor element of claim 8, wherein, Each synchronously self-aligned P-type doped channel has a length of 0.5 to 1 micrometer.

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