Back contact solar cell and method of manufacturing the same

Abstract

This application provides a back-contact solar cell and a method for fabricating the same. The back-contact solar cell includes: a silicon substrate, the back side of which has a first region, a second region, and an isolation region located between the first and second regions; a first carrier collection layer disposed in the first region; a second carrier collection layer, having a conductivity type opposite to that of the first carrier collection layer, disposed in the second region; a conductive layer disposed in both the first and second regions, and located on the side of the first and second carrier collection layers away from the silicon substrate, the conductive layer being disconnected in the isolation region; and a carbon-oxygen-doped silicon layer disposed between the first carrier collection layer and the conductive layer, and / or, between the second carrier collection layer and the conductive layer. This improves the photoelectric conversion efficiency of the back-contact solar cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and its fabrication method. Background Technology

[0002] Back-contact (BC) solar cells are a type of solar cell that integrates both positive and negative electrodes on the back side. Because the front side is unobstructed, the effective light-receiving area can be increased, thereby improving the conversion efficiency of photovoltaic modules.

[0003] Typically, the carrier collection layer and the conductive layer of a back-contact solar cell are in direct contact. However, in practice, it has been found that in this case, there is severe interfacial recombination between the carrier collection layer and the conductive layer, resulting in a large series resistance and affecting the photoelectric conversion efficiency.

[0004] The above statements are for the purpose of providing background information in relation to this application only, and do not necessarily constitute prior art. Summary of the Invention

[0005] One of the technical problems this application aims to solve is to improve the photoelectric conversion efficiency of back-contact solar cells.

[0006] To address the aforementioned technical problems, this application provides a back-contact solar cell, comprising:

[0007] A silicon substrate, the back side of which has a first region, a second region, and an isolation region located between the first and second regions;

[0008] The first carrier collection layer is located in the first region;

[0009] The second carrier collection layer, having the opposite conductivity type to the first carrier collection layer, is located in the second region;

[0010] A conductive layer is disposed in the first region and the second region, and is located on the side of the first carrier collection layer and the second carrier collection layer away from the silicon substrate; the conductive layer is disconnected in the isolation region; and

[0011] A carbon-oxygen-doped silicon layer is disposed between a first carrier collection layer and a conductive layer, and / or between a second carrier collection layer and a conductive layer.

[0012] In some embodiments, the ratio of carbon to oxygen atoms in the carbon-oxygen doped silicon layer is 1:4 to 1:2; and / or, the thickness of the carbon-oxygen doped silicon layer is 1 to 5 nm.

[0013] In some embodiments, the first carrier collection layer includes a tunneling oxide layer and a doped polycrystalline silicon layer arranged sequentially along a direction away from the silicon substrate, and the second carrier collection layer includes an intrinsic amorphous silicon layer and a doped silicon-containing layer arranged sequentially along a direction away from the silicon substrate.

[0014] In some embodiments, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped silicon-containing layer is an n-type doped silicon-containing layer.

[0015] In some embodiments, the n-type doped silicon-containing layer includes at least one of an n-type doped amorphous silicon layer, an n-type doped microcrystalline silicon layer, and an n-type doped nanocrystalline silicon layer; and / or, a carbon-oxygen doped silicon layer is disposed between the doped silicon-containing layer and the conductive layer in the second region, and is not disposed in the first region.

[0016] In some embodiments, there is a height difference between the conductive layer located in the first region and the conductive layer located in the second region.

[0017] In some embodiments, the conductive layer of the first region is farther away from the silicon substrate than the conductive layer of the second region.

[0018] In some embodiments, at least a portion of the isolation region is provided with a carbon-oxygen-doped silicon layer.

[0019] In some embodiments, the isolation region includes a first sub-region connected to the first region, and the first sub-region is provided with a first carrier collection layer, a second carrier collection layer, a carbon-oxygen doped silicon layer and a conductive layer in sequence along the direction away from the silicon substrate.

[0020] In some embodiments, the isolation region further includes a second sub-region located between the first sub-region and the second sub-region, and the second sub-region is connected to the first sub-region. The second sub-region is provided with a first carrier collection layer, a second carrier collection layer and a carbon-oxygen doped silicon layer in sequence along the direction away from the silicon substrate, and the conductive layer does not extend to the second sub-region.

[0021] In some embodiments, the isolation region further includes a third subregion connected between the second subregion and the second subregion, wherein a second carrier collection layer and a carbon-oxygen-doped silicon layer are sequentially disposed in the third subregion along a direction away from the silicon substrate.

[0022] In some embodiments, the third sub-region includes a fourth sub-region and a fifth sub-region, which are arranged sequentially along the direction from the first region to the second region, and there is a height difference between the surfaces of the carbon-oxygen doped silicon layers of the fourth and fifth sub-regions that are away from the silicon substrate.

[0023] In some embodiments, the back-contact solar cell further includes: a first electrode electrically connected to the conductive layer of the first region and a second electrode electrically connected to the conductive layer of the second region; and / or,

[0024] The back-contact solar cell also includes a passivation layer and an anti-reflection layer disposed on the front side of the silicon substrate, with the anti-reflection layer located on the side of the passivation layer away from the silicon substrate.

[0025] In addition, this application also provides a method for fabricating a back-contact solar cell, which includes:

[0026] A first carrier collection layer and a second carrier collection layer are formed in the first and second regions on the back side of the silicon substrate, respectively.

[0027] A conductive layer is formed on the side of the first and second carrier collection layers away from the silicon substrate, and the conductive layer is disconnected in the isolation region between the first and second regions on the back side of the silicon substrate; and

[0028] Before forming a conductive layer on the side of the first carrier collection layer away from the silicon substrate, a carbon-oxygen-doped silicon layer is also formed on the side of the first carrier collection layer away from the silicon substrate, and / or, before forming a conductive layer on the side of the second carrier collection layer away from the silicon substrate, a carbon-oxygen-doped silicon layer is also formed on the side of the second carrier collection layer away from the silicon substrate.

[0029] In some embodiments, a carbon-oxygen-doped silicon layer is formed by plasma vapor deposition.

[0030] In some embodiments, forming a carbon-oxygen-doped silicon layer by plasma vapor deposition includes:

[0031] After forming a first carrier collection layer and a second carrier collection layer in the first and second regions on the back side of the silicon substrate, respectively, the silicon substrate is placed in a plasma device. The power of the plasma device is controlled at 500-1500W and the pressure at 50-150Pa. CO2 with a flow rate of 200-1000SCCM is introduced into the plasma device to form a carbon-oxygen doped silicon layer.

[0032] In some embodiments, forming a first carrier collection layer in a first region on the back side of a silicon substrate includes:

[0033] A tunneling oxide layer and a doped polycrystalline silicon layer are sequentially formed on the entire back side of the silicon substrate along a direction away from the silicon substrate.

[0034] A protective layer is formed on the outside of the doped polycrystalline silicon layer on the back side of the silicon substrate;

[0035] The protective layer in the second zone is removed using a laser;

[0036] The tunneling oxide layer and the doped polysilicon layer in the second region are removed by cleaning to form a first carrier collection layer in the first region, which includes the tunneling oxide layer and the doped polysilicon layer.

[0037] In some embodiments, forming a second carrier collection layer in a second region on the back side of the silicon substrate includes:

[0038] An intrinsic amorphous silicon layer and a doped silicon-containing layer are formed on the entire back side of the silicon substrate;

[0039] Laser is used to remove the intrinsic amorphous silicon layer and the doped silicon layer located in the first region to form a second carrier collection layer located in the second region, which includes the intrinsic amorphous silicon layer and the doped silicon layer.

[0040] The embodiments provided in this application have at least the following beneficial effects:

[0041] By providing a carbon-oxygen-doped silicon layer between the first carrier collection layer and the conductive layer in the first region of the back-contact solar cell, and / or between the second carrier collection layer and the conductive layer in the second region, interfacial recombination between the carrier collection layer and the conductive layer can be reduced, interfacial contact with the conductive layer can be improved, series resistance can be reduced, and the fill factor and photoelectric conversion efficiency of the back-contact solar cell can be effectively improved.

[0042] Other features and advantages of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the back-contact solar cell in an embodiment of this application.

[0044] Figures 2-12 This is a schematic diagram of the fabrication process of the back-contact solar cell in the embodiments of this application.

[0045] Explanation of reference numerals in the attached figures:

[0046] 10. Back-contact solar cell;

[0047] 1. Silicon substrate; 11. Front side; 12. Back side;

[0048] 2. Zone 1;

[0049] 3. Second District;

[0050] 4. Isolation Zone; 41. First Sub-zone; 42. Second Sub-zone; 43. Third Sub-zone; 44. Fourth Sub-zone; 45. Fifth Sub-zone;

[0051] 51. Doped silicon glass layer; 52. Protective layer; 53. Tunneling oxide layer; 54. Doped polycrystalline silicon layer; 55. Intrinsic amorphous silicon layer; 56. Doped silicon-containing layer; 57. First carrier collection layer; 58. Second carrier collection layer;

[0052] 6. Carbon-oxygen doped silicon layer;

[0053] 7. Conductive layer;

[0054] 81. First electrode; 82. Second electrode;

[0055] 91. Passivation layer; 92. Anti-reflection layer. Detailed Implementation

[0056] In existing technology, a back-contact solar cell includes: a silicon substrate, a first carrier collection layer, a second carrier collection layer, a conductive layer, a first electrode, and a second electrode. The silicon substrate has two surfaces opposite each other in the thickness direction, designated as the front and back sides. In practical applications, the front and back sides are generally the light-facing side and the back-facing side, respectively. The back side of the silicon substrate has a first region, a second region, and an isolation region, with the isolation region located between the first and second regions. The first carrier collection layer is located in the first region, the second carrier collection layer is located in the second region, and the conductive layer is located on the side of the first carrier collection layer facing away from the silicon substrate, as well as on the side of the second carrier collection layer facing away from the silicon substrate. The conductive layer is disconnected in the isolation region. The first electrode is electrically connected to the conductive layer located in the first region, and the second electrode is electrically connected to the conductive layer located in the second region.

[0057] In this design, the first and second carrier collection layers have opposite conductivity types, forming one of the n-region and the other of the p-region, respectively. Thus, both the n-region and p-region are located on the back side of the silicon substrate, allowing both the positive and negative electrodes to be integrated on the back side. Therefore, no grid lines are needed on the front side of the silicon substrate, preventing shading and resulting in a larger effective light-illuminated area. This makes back-contact solar cells exhibit higher photoelectric conversion efficiency compared to traditional bifacial solar cells such as TOPCon (Tunnel Oxide Passivated Contact) and HJT (Heterojunction).

[0058] Although the photoelectric conversion efficiency of back-contact solar cells has improved compared to traditional TOPCon and HJT solar cells, further improving the photoelectric conversion efficiency of back-contact solar cells remains a challenge.

[0059] To further improve the photoelectric conversion efficiency of back-contact solar cells, some measures have been taken, but the photoelectric conversion efficiency of back-contact solar cells still needs to be further improved.

[0060] In the process of filing this application, it was discovered that the interaction between the carrier collection layer and the conductive layer is also a significant factor limiting the photoelectric conversion efficiency of back-contact solar cells. Here, the carrier collection layer refers to the first carrier collection layer and / or the second carrier collection layer.

[0061] Specifically, the carrier collection layer and the conductive layer are in direct contact, resulting in severe interfacial recombination and poor contact. This leads to a high series resistance (Rs), significant carrier loss, and low transport efficiency, resulting in a low fill factor (FF). Consequently, the photoelectric conversion efficiency of back-contact solar cells is affected, making it difficult to further improve the photoelectric conversion efficiency of back-contact solar cells.

[0062] In view of the above situation, this application provides a back-contact solar cell.

[0063] Figure 1 The structure of the back-contact solar cell 10 in this application is illustrated by way of example.

[0064] See Figure 1 The back-contact solar cell 10 of this application includes a silicon substrate 1, a first carrier collection layer 57, a second carrier collection layer 58, a conductive layer 7, and a carbon-oxygen-doped silicon layer 6. The back surface 12 of the silicon substrate 1 has a first region 2, a second region 3, and an isolation region 4 located between the first region 2 and the second region 3. The first carrier collection layer 57 is disposed in the first region 2. The second carrier collection layer 58, having the opposite conductivity type to the first carrier collection layer 57, is disposed in the second region 3. The conductive layer 7 is disposed in the first region 2 and the second region 3, located on the side of the first carrier collection layer 57 and the second carrier collection layer 58 away from the silicon substrate 1 (i.e., the outer side), and is disconnected in the isolation region 4. The carbon-oxygen-doped silicon layer 6 is disposed between the first carrier collection layer 57 and the conductive layer 7, and / or between the second carrier collection layer 58 and the conductive layer 7.

[0065] It should be noted that "conductive layer 7 is disconnected in isolation region 4" means that conductive layer 7 is not disposed in isolation region 4, or that conductive layer 7 is disposed in a portion of isolation region 4. The silicon substrate 1 can be an n-type silicon substrate or a p-type silicon substrate.

[0066] By providing a carbon-oxygen-doped silicon layer 6 between the first carrier collection layer 57 and the conductive layer 7 in the first region 2 of the back contact solar cell 10, and / or between the second carrier collection layer 58 and the conductive layer 7 in the second region 3, the interfacial recombination between the carrier collection layer and the conductive layer 7 can be reduced, the interfacial contact between the carrier collection layer and the conductive layer 7 can be improved, the series resistance can be reduced, and the photoelectric conversion efficiency of the back contact solar cell 10 can be effectively improved.

[0067] Specifically, since the carbon-oxygen doped silicon layer 6 contains oxygen and carbon, and both oxygen and carbon elements can saturate dangling bonds, reduce defects, reduce interface recombination, reduce carrier loss, optimize band energy matching, improve interface compactness, enhance conductivity, reduce series resistance, and improve carrier transport efficiency, the fill factor (FF) can be effectively improved, thereby improving the photoelectric conversion efficiency of the back contact solar cell 10.

[0068] In carbon-oxygen doped silicon layer 6, oxygen acts as a stronger saturated dangling bond than carbon. Specifically, the Si-O bond energy between oxygen and silicon is higher than the CO bond energy between carbon and silicon. Furthermore, carbon has low solid solubility in silicon. Through the synergistic effect of carbon and oxygen, the diffusion depth of oxygen can be adjusted, and the formation of new defects by carbon in silicon can be avoided. This facilitates the reduction of interfacial recombination, decreases carrier loss, optimizes band energy matching, improves interfacial density, enhances conductivity, reduces series resistance, and increases the fill factor (FF).

[0069] In the carbon-oxygen doped silicon layer 6, the ratio of carbon to oxygen atoms is 1:4 to 1:2, such as 1:4, 1:3, or 1:2. This ratio is suitable because the carbon content is not excessive, minimizing the introduction of defects that could affect interfacial recombination. Conversely, the oxygen content is also moderate, preventing excessive diffusion into the carrier collection layer and avoiding a thicker carbon-oxygen doped silicon layer that could impair carrier transport or introduce new defects, thus affecting passivation and negatively impacting the fill factor. Therefore, at this ratio, carbon and oxygen work synergistically to effectively reduce interfacial recombination, decrease carrier losses, optimize band matching, improve interfacial density, enhance conductivity, reduce series resistance, and improve the fill factor.

[0070] In some embodiments, the thickness of the carbon-oxygen-doped silicon layer 6 is 1~5 nm, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm. This thickness is suitable, preventing both insufficient thickness from affecting interfacial recombination and excessive thickness from affecting carrier transport, introducing new defects, affecting passivation, and reducing the fill factor. Therefore, a carbon-oxygen-doped silicon layer 6 of appropriate thickness is more conducive to carrier collection and transport, improves interfacial contact, reduces series resistance (Rs), and enhances photoelectric conversion efficiency.

[0071] In the foregoing embodiments, the carrier collection layers of the first region 2 and the second region 3 can adopt various structural forms. For example, see... Figure 1 In some embodiments, the first carrier collection layer 57 includes a tunneling oxide layer 53 and a doped polycrystalline silicon layer 54 arranged sequentially along a direction away from the silicon substrate 1, and the second carrier collection layer 58 includes an intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56 arranged sequentially along a direction away from the silicon substrate 1. The doped polycrystalline silicon layer 54 can be a p-type doped polycrystalline silicon layer, and the doped silicon-containing layer 56 can be an n-type doped silicon-containing layer. The n-type doped silicon-containing layer includes at least one of an n-type doped amorphous silicon layer, an n-type doped microcrystalline silicon layer, and an n-type doped nanocrystalline silicon layer. The silicon substrate is an n-type silicon substrate.

[0072] Based on the above configuration, the back contact solar cell 10 is a hybrid back contact solar cell that combines the heterojunction passivation advantages of HJT solar cells with the tunneling / polycrystalline conductivity characteristics of TOPCon solar cells, and the first region 2 and the second region 3 are the p region and the n region, respectively.

[0073] In existing back-contact solar cells, the carrier collection layer in the p-region typically includes an intrinsic amorphous silicon layer and a p-type doped amorphous silicon layer, while the carrier collection layer in the n-region includes a tunneling oxide layer and an n-type doped polycrystalline silicon layer. However, research has found that in this case, due to the high electron mobility (n-region carriers) and the fact that the n-region polycrystalline silicon structure and high-temperature processing support high doping, while the low hole mobility (p-region carriers) and the fact that the p-region amorphous silicon structure and low-temperature processing limit high doping, the doping concentration difference between the n-region and p-region is significant. The doping concentration in the n-region is much greater than that in the p-region, which affects the average distribution of carriers, resulting in a lower short-circuit current and affecting the photoelectric conversion efficiency.

[0074] Therefore, to promote the even distribution of charge carriers and increase short-circuit current, it is necessary to reduce the doping concentration difference between the n-region and the p-region, making their doping concentrations more uniform. However, phosphorus diffusion in n-type polysilicon is a high-temperature process, which is difficult to precisely control, making it hard to reduce the doping concentration. Therefore, it is difficult to reduce the doping concentration difference between the n-region and the p-region and make their doping concentrations more uniform simply by directly reducing the doping concentration of the n-region.

[0075] Therefore, how to reduce the difference in doping concentration between the n-region and the p-region, so that the doping concentrations of the n-region and the p-region tend to be consistent, in order to promote the average distribution of charge carriers and improve the short-circuit current, has become a difficult problem.

[0076] To address these challenges, in the aforementioned embodiments, the back-contact solar cell no longer includes an intrinsic amorphous silicon layer and a p-type doped amorphous silicon layer in the p-region carrier collection layer, nor does the n-region carrier collection layer include a tunneling oxide layer and an n-type doped polycrystalline silicon layer. Instead, the p-region carrier collection layer includes a tunneling oxide layer 53 and a p-type doped polycrystalline silicon layer, and the n-region carrier collection layer includes an intrinsic amorphous silicon layer 55 and an n-type doped silicon-containing layer. In this case, since the p-region doped layer uses a polycrystalline silicon structure, it supports increased doping concentration and high-temperature heat treatment for boron diffusion, resulting in faster boron diffusion and shallower doping depth, making it easier to increase the boron doping concentration. In contrast, the n-region doped layer uses a silicon-containing layer such as amorphous silicon or microcrystalline silicon, limiting the doping concentration and increasing the doping depth, making it easier to reduce the phosphorus doping concentration. Therefore, it is advantageous to increase the doping concentration in the p-region and decrease the doping concentration in the n-region to reduce the difference in doping concentration between the n-region and p-region, making the doping concentrations in the n-region and p-region more consistent. This promotes the average distribution of carriers, increases the short-circuit current, and improves the photoelectric conversion efficiency.

[0077] It can be seen that by setting the first region 2 to include a tunneling oxide layer 53 and a p-type doped polycrystalline silicon layer arranged sequentially along the direction away from the silicon substrate 1, and setting the second region 3 to include an intrinsic amorphous silicon layer 55 and an n-type doped silicon-containing layer arranged sequentially along the direction away from the silicon substrate 1, the problems of large differences in doping concentration between the n-region and p-region of existing back-contact solar cells, uneven carrier distribution, and small short-circuit current can be effectively solved, thereby achieving the purpose of promoting the average distribution of carriers, increasing the short-circuit current, and improving the photoelectric conversion efficiency.

[0078] In some embodiments, the doping concentration of the doped atoms in both the first region 2 and the second region 3 can be 1×10¹. 6 -1×10 21 Units per cubic centimeter, for example, could be 1×10 16 Units / cubic centimeter, 1×10 18 Units / cubic centimeter, 1×10 20 Units per cubic centimeter or 1×10 21 The doping concentration difference between Region 2 and Region 3 is small and low, which is beneficial for achieving selective carrier collection while suppressing interface recombination, optimizing series resistance, and improving process compatibility.

[0079] When the first region 2 is configured as a tunneling oxide layer 53 and a doped polycrystalline silicon layer 54, and the second region 3 is configured as an intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56, the carbon-oxygen doped silicon layer 6 can be disposed between the doped silicon-containing layer 56 and the conductive layer 7 in the second region 3, instead of being disposed in the first region 2. In this way, on the one hand, since the doped silicon-containing layer 56 is in an amorphous silicon, microcrystalline silicon, or nanocrystalline silicon state, its surface defects are more numerous than those of the doped polycrystalline silicon layer 54, resulting in greater recombination between the doped silicon-containing layer 56 and the conductive layer 7. By placing the carbon-oxygen doped silicon layer 6 between the doped silicon-containing layer 56 and the conductive layer 7, recombination can be reduced, and the fill factor can be improved. On the other hand, the fabrication process difficulty can be reduced, facilitating mass production.

[0080] In this embodiment, the thickness of the tunneling oxide layer 53 can be 0.5-3 nm, such as 0.5 nm, 1 nm, 2 nm, or 3 nm. The thickness of the doped polycrystalline silicon layer 54 can be 20-100 nm, such as 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm. The thickness of the intrinsic amorphous silicon layer 55 can be 1-10 nm, such as 1 nm, 3 nm, 5 nm, 7 nm, 9 nm, or 10 nm. The thickness of the doped silicon-containing layer 56 can be 1-50 nm, such as 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm.

[0081] In the foregoing embodiments, the conductive layers 7 located in the first region 2 and the second region 3 may be coplanar or non-coplanar, but have a height difference. When there is a height difference between the conductive layers 7 in the first region 2 and the conductive layers 7 in the second region 3, for example, when the conductive layer 7 in the first region 2 is farther from the silicon substrate 1 than the conductive layer 7 in the second region 3 (i.e., the conductive layer 7 in the first region 2 is located at a higher position than the conductive layer 7 in the second region 3), vertical isolation can be formed between the first region 2 and the second region 3. This more reliably prevents the films in the first region 2 and the second region 3 from conducting, thereby more effectively reducing the risk of leakage and improving photoelectric conversion efficiency.

[0082] In some embodiments, at least a portion of the isolation region 4 is provided with a carbon-oxygen-doped silicon layer 6. For example, the entire isolation region 4 may be provided with a carbon-oxygen-doped silicon layer 6, or only a portion of the isolation region 4 may be provided with a carbon-oxygen-doped silicon layer 6. When the entire isolation region 4 is provided with a carbon-oxygen-doped silicon layer 6, interfacial recombination can be reduced, and the process steps for removing the carbon-oxygen-doped silicon layer 6 can be reduced.

[0083] See Figure 1 The isolation region 4 includes a first sub-region 41 connected to the first region 2. In the first sub-region 41, a first carrier collection layer 57, a second carrier collection layer 58, a carbon-oxygen-doped silicon layer 6, and a conductive layer 7 are sequentially arranged (from the inside to the outside) along a direction away from the silicon substrate 1. Exemplarily, the first sub-region 41 is provided with a tunneling oxide layer 53, a doped polycrystalline silicon layer 54, an intrinsic amorphous silicon layer 55, a doped silicon-containing layer 56, a carbon-oxygen-doped silicon layer 6, and a conductive layer 7 arranged from the inside to the outside. Thus, the conductive layer 7 extends into the first sub-region 41 of the isolation region 4, increasing the area for collecting carriers, which helps reduce contact resistance, improves carrier collection performance, and enhances photoelectric conversion efficiency.

[0084] In addition, the tunneling oxide layer 53 and the p-type doped polycrystalline silicon layer corresponding to the first region 2 are located below the intrinsic amorphous silicon layer 55 and the n-type doped silicon-containing layer corresponding to the second region 3, and are closer to the silicon substrate 1. During the solar cell fabrication process, the first carrier collection layer 57 is disposed on the back side 12 before the second carrier collection layer 58. The first carrier collection layer 57, which includes polycrystalline silicon, can be fabricated under high-temperature processes, which facilitates the high-temperature heat treatment boron diffusion process, increases the doping concentration of the first region 2, and the first carrier collection layer 57 can withstand the process intensity of laser film opening, reducing the damage to the film layer caused by the laser film opening process.

[0085] See also Figure 1The isolation region 4 also includes a second sub-region 42 located between the first sub-region 41 and the second sub-region 3, and the second sub-region 42 is connected to the first sub-region 41. In the second sub-region 42, a first carrier collection layer 57, a second carrier collection layer 58, and a carbon-oxygen-doped silicon layer 6 are sequentially disposed along a direction away from the silicon substrate 1. The conductive layer 7 does not extend into the second sub-region 42. Thus, the conductive layer 7 is only disposed in a portion of the isolation region 4, and is disconnected in the isolation region 4, preventing leakage problems.

[0086] See also Figure 1 The isolation region 4 also includes a third sub-region 43 connected between the second sub-region 42 and the second sub-region 3. A second carrier collection layer 58 and a carbon-oxygen doped silicon layer 6 are sequentially disposed in the third sub-region 43 along the direction away from the silicon substrate 1. In this way, neither the second sub-region 42 nor the third sub-region 43 is provided with a conductive layer 7, which is beneficial to forming effective electrical isolation between the first region 2 and the second region 3 and preventing the risk of leakage.

[0087] Further, see Figure 1 The third sub-region 43 includes a fourth sub-region 44 and a fifth sub-region 45, which are arranged sequentially along the direction from the first region to the second region. There is a height difference between the surfaces of the carbon-oxygen-doped silicon layer 6 of the fourth sub-region 44 and the fifth sub-region 45 that are furthest from the silicon substrate 1. In this way, the first region 2 and the second region 3 form vertical electrical isolation in the vertical direction and horizontal electrical isolation in the horizontal direction, effectively preventing the risk of leakage.

[0088] For example, an intrinsic amorphous silicon layer 55, a doped silicon-containing layer 56, and a carbon-oxygen-doped silicon layer 6 are sequentially disposed in the third sub-region 43 along the direction away from the silicon substrate 1. Among them, the intrinsic amorphous silicon layer 55 is more effective at passivating the surface of the silicon substrate 1 than the tunneling oxide layer 53. This arrangement is beneficial to improving the passivation effect, reducing recombination, and improving the photoelectric conversion efficiency.

[0089] In this embodiment, the width of the first sub-region 41 can be 50-150 μm, for example, 50 μm, 100 μm, or 150 μm. The width of the second sub-region 42 can be 30-90 μm, for example, 30 μm, 50 μm, 70 μm, or 90 μm. The width of the third sub-region 43 is 30-100 μm, for example, 30 μm, 50 μm, 70 μm, 90 μm, or 100 μm. The width of the fourth sub-region 44 is 0-10 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. The width of the fifth sub-region 45 is 30-90 μm, for example, 30 μm, 35 μm, 45 μm, 55 μm, 65 μm, 75 μm, 85 μm, or 90 μm. By setting the width of each sub-zone of isolation zone 4 in this way, the width of the first zone 2 and the second zone 3 can be increased, while effectively isolating the first zone 2 and the second zone 3, thus preventing leakage problems.

[0090] See also Figure 1 The back-contact solar cell provided in this application embodiment further includes: a first electrode 81 electrically connected to the conductive layer 7 of the first region 2; and a second electrode 82 electrically connected to the conductive layer 7 of the second region 3.

[0091] The first electrode 81 and the second electrode 82 can be one or more of the following stacked layers: silver electrode, silver alloy electrode, copper electrode, copper alloy electrode, and nickel / copper / silver multilayer electrode.

[0092] The conductive layer 7 may include one or more metal oxides or nitrides, and may be a single layer or a multilayer stack. The conductive layer may be a TCO (Transparent Conductive Oxide) layer, such as an indium tin oxide layer.

[0093] In some embodiments, the back-contact solar cell provided in this application further includes a passivation layer 91 and an antireflection layer 92 disposed on the front side 11 of the silicon substrate 1, wherein the antireflection layer 92 is located outside the passivation layer 91. This arrangement is beneficial to improving the passivation effect and antireflection performance of the back-contact solar cell 10. The passivation layer 91 can be at least one of an aluminum oxide layer, an aluminum nitride layer, and an aluminum oxynitride layer, and the antireflection layer 92 can be at least one of a silicon nitride layer and a silicon oxynitride layer. The thickness of the passivation layer 91 can be 1-10 nm, such as 1 nm, 3 nm, 5 nm, 7 nm, or 10 nm, and the thickness of the antireflection layer can be 40-200 nm, such as 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 170 nm, or 200 nm.

[0094] Based on the back-contact solar cell 10 of the foregoing embodiments, this application also provides a method for fabricating the back-contact solar cell 10, the method comprising:

[0095] Step S1: A first carrier collection layer 57 and a second carrier collection layer 58 are formed in the first region 2 and the second region 3 on the back side 12 of the silicon substrate 1, respectively.

[0096] Step S2: A conductive layer 7 is formed on the outside of the first carrier collection layer 57 and the second carrier collection layer 58, and the conductive layer 7 is disconnected from the isolation region 4 located between the first region 2 and the second region 3 on the back side of the silicon substrate 1.

[0097] Prior to step S2, a carbon-oxygen-doped silicon layer 6 is formed on the side of the first carrier collection layer 57 away from the silicon substrate 1 and / or on the side of the second carrier collection layer 58 away from the silicon substrate 1.

[0098] The fabrication method provided in this application forms a carbon-oxygen-doped silicon layer 6 between the first carrier collection layer 57 and the conductive layer 7 in the first region 2 of the back contact solar cell 10, and / or between the second carrier collection layer 58 and the conductive layer 7 in the second region 3. This reduces interfacial recombination between the carrier collection layer and the conductive layer 7, improves the interfacial contact between the carrier collection layer and the conductive layer 7, reduces the series resistance, and effectively improves the photoelectric conversion efficiency of the back contact solar cell 10.

[0099] See Figures 2-12 The preparation method specifically includes:

[0100] Step S110: Polish and clean the silicon substrate 1 using an alkaline solution.

[0101] Step S120: A first carrier collection layer 57 is formed in the first region 2 on the back side 12 of the silicon substrate 1.

[0102] When the first carrier collection layer 57 includes a tunneling oxide layer 53 and a doped polysilicon layer 54, step S120 may specifically include:

[0103] Step S121, see Figure 2 A tunneling oxide layer 53 and a doped polycrystalline silicon layer 54 are formed from the inside to the outside on the back side 12 of the silicon substrate 1.

[0104] Specifically, a tunnel oxide layer 53 can be formed on the back side 12 of the silicon substrate 1 using a furnace tube thermal oxidation method.

[0105] Then, a polycrystalline silicon layer can be deposited on the outside of the tunneling oxide layer 53 of the silicon substrate using LPCVD (Low Pressure Chemical Vapor Deposition) equipment; next, the doped polycrystalline silicon layer 54 is doped and diffused using a tube diffusion furnace to obtain the doped polycrystalline silicon layer 54 and the doped silicon glass layer 51. For example, the doping element is boron, and the doped silicon glass layer is a borosilicate glass (BSG) layer.

[0106] The BSG layer can then be removed by cleaning with hydrofluoric acid solution.

[0107] Step S122, see Figure 3 A protective layer 52 is formed on the outside of the doped polycrystalline silicon layer 54 on the back side 12 of the silicon substrate 1.

[0108] Specifically, the protective layer can be a silicon nitride layer. In the furnace tube, using silane and ammonia as reaction precursors, a silicon nitride layer is deposited on the surface of the doped polycrystalline silicon layer 54 on the back side 12 of the silicon substrate 1. The thickness can be 50-100 nm, such as 50 nm, 70 nm, 90 nm or 100 nm.

[0109] Step S123: Use a laser to remove the protective layer of the second region 3 located on the back side 12 of the silicon substrate 1.

[0110] Specifically, a laser is used to treat the protective layer of the second region 3 on the back side 12 of the silicon substrate 1 to remove the protective layer corresponding to the second region 3, forming... Figure 4 The structure shown.

[0111] Step S124: Clean and remove the tunneling oxide layer 53 and the doped polysilicon layer 54 in the second region 3 to form the tunneling oxide layer 53 and the doped polysilicon layer 54 in the first region 2.

[0112] Specifically, an alkaline solution is used to clean and remove the doped polysilicon layer 54 on the front side 11 of the silicon substrate 1, the unprotected area on the back side 12, and the doped polysilicon layer 54 at the edge of the first region 2. Then, an acid solution is used to clean the exposed tunneling oxide layer 53 in the corresponding areas, the tunneling oxide layer 53 at the edge of the second region 3, and the protective layer, to obtain... Figure 5 The structure shown. In Figure 5 In the middle, steps were formed to create isolation zone 4.

[0113] Step S130: A passivation layer 91 and an antireflection layer 92 are formed on the front side 11 of the silicon substrate 1, see [link to previous step]. Figure 6 .

[0114] Specifically, an ALD (Atomic Layer Deposition) device can be used to form a passivation layer 91 on the front side 11 of the silicon substrate 1. Subsequently, an antireflection layer 92 can be formed on the surface of the passivation layer 91 using PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment.

[0115] Step S140: A second carrier collection layer 58 is formed in the second region 3 on the back side 12 of the silicon substrate 1.

[0116] When the second carrier collection layer 58 includes an intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56, step S140 specifically includes:

[0117] Step S141, see Figure 7 An intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56 are formed on the back side 12 of the silicon substrate 1.

[0118] Specifically, an intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56 are formed on the back side 12 of the silicon substrate 1 using a PECVD device.

[0119] Step S142, see Figure 8 A carbon-oxygen-doped silicon layer 6 is formed on the outer side of the second carrier collection layer 58 (i.e., the side away from the silicon substrate 1).

[0120] Specifically, a carbon-oxygen-doped silicon layer 6 can be formed on the outside of the second carrier collection layer 58 by plasma vapor deposition. For example, if the second carrier collection layer 58 includes an intrinsic amorphous silicon layer 55 and a doped silicon-containing layer 56 arranged sequentially along a direction away from the silicon substrate 1, the carbon-oxygen-doped silicon layer 6 can be formed on the outside of the doped silicon-containing layer 56 by plasma vapor deposition.

[0121] When forming a carbon-oxygen-doped silicon layer 6 using ion vapor deposition, the carbon-oxygen-doped silicon layer 6 can be prepared simply by treating the surface of the carrier collection layer with plasma. For example, treating the surface of the carrier collection layer with oxygen- and carbon-containing plasma yields an oxygen- and carbon-containing carbon-oxygen-doped silicon layer 6, which is simple and convenient. Therefore, it is easy to set up a carbon-oxygen-doped silicon layer 6, especially one with a thickness in the range of 1~5 nm. Furthermore, using plasma vapor deposition to set up the carbon-oxygen-doped silicon layer 6 causes less damage to the carrier collection layer, is less likely to affect the distribution of dopants (phosphorus or boron) within the doped silicon layer, and is beneficial for enhancing the conductivity of the outer surface of the carrier collection layer, reducing resistance, and improving photoelectric conversion efficiency.

[0122] In the process of forming the carbon-oxygen-doped silicon layer 6 using ion vapor deposition, the operating power of the plasma equipment can be controlled to be 500-1500W, for example, 500 W, 1000 W or 1500 W; and the operating pressure can be 50-150Pa, for example, 50 Pa, 100 Pa or 150 Pa; under the corresponding power and pressure, CO2 with a flow rate of 200-1000SCCM is introduced into the plasma equipment, for example, 200SCCM, 400SCCM, 600SCCM, 800SCCM or 1000SCCM, so as to form the carbon-oxygen-doped silicon layer 6 on the outside of the second carrier collection layer 58.

[0123] In addition, when CO2 is introduced into the plasma device, oxygen can also be introduced into the plasma device to adjust the atomic ratio of carbon and oxygen in the carbon-oxygen doped silicon layer 6.

[0124] Oxygen plasma and carbon plasma are deposited and partially diffused on the surface of the silicon-doped layer 56, and the deposited portion and the diffused portion together form the carbon-oxygen-doped silicon layer 6.

[0125] Step S143: Use a laser to remove the intrinsic amorphous silicon layer 55 and the doped silicon-containing layer 56 located in the first region 2.

[0126] Specifically, a 532nm laser can be used to laser-open the first region 2 to remove the intrinsic amorphous silicon layer 55 and the doped silicon-containing layer 56 located in the first region 2, forming... Figure 9 The structure shown.

[0127] Steps 120 and 140 above employ a method of first setting the first carrier collection layer 57 across the entire back surface, then removing the first carrier collection layer 57 located in the second region 3, and then setting the second carrier collection layer 58 in the second region 3, thereby establishing the carrier collection layers in the first region 2 and the second region 3. This method is particularly suitable for cases where the carrier collection layer in the first region 2 includes a tunneling oxide layer 53 and a p-type doped polycrystalline silicon layer arranged sequentially along the direction away from the silicon substrate 1, and the carrier collection layer in the second region 3 includes an intrinsic amorphous silicon layer 55 and an n-type doped silicon-containing layer arranged sequentially along the direction away from the silicon substrate 1. This facilitates the fabrication of a polycrystalline silicon carrier collection layer in the p-region (corresponding to the first region 2) under high-temperature processes, enabling the high-temperature heat treatment boron diffusion process, increasing the doping concentration in the p-region, and ensuring that the first carrier collection layer 57 meets the high-temperature resistance requirements of laser film cutting, reducing damage to the film layer caused by the laser film cutting process.

[0128] Furthermore, when forming the second carrier collection layer 58 in the second region 3, the second region 3 is not simply provided with the second carrier collection layer 58 to make the second region 3 have the required carrier collection layer. Instead, the second carrier collection layer 58 is provided on the entire back surface 12 to make the second region 3 have the required carrier collection layer. In this case, the second carrier collection layer 58 can be provided over a large area, which is more convenient.

[0129] Furthermore, when setting the carbon-oxygen doped silicon layer 6, the carbon-oxygen doped silicon layer 6 is first set on the entire back side 12 of the silicon substrate 1, and then a portion of the carbon-oxygen doped silicon layer 6 is removed. In this case, the area of ​​the carbon-oxygen doped silicon layer 6 is larger, which makes it easier to set the carbon-oxygen doped silicon layer 6.

[0130] In step S150, a conductive layer 7 is formed on the outside of the first carrier collection layer 57 and the second carrier collection layer 58, and the conductive layer 7 is disconnected from the isolation region 4 on the back side of the silicon substrate. The isolation region 4 is located between the first region 2 and the second region 3.

[0131] Specifically, a TCO layer can be deposited on the back side 12 of the silicon substrate 1 using a PVD (Physical Vapor Deposition) device to form a TCO layer. Figure 10 The conductive layer 7 is shown.

[0132] The TCO layer (i.e., conductive layer 7) corresponding to the second and third sub-regions of isolation region 4 is etched away using an etching paste to form Figure 11 The structure is shown. The etching paste is prior art and will not be described in detail here.

[0133] Step S160: A first electrode 81 electrically connected to the conductive layer 7 is formed in the first region 2; a second electrode 82 electrically connected to the conductive layer 7 is formed in the second region 3. See below. Figure 12 .

[0134] Specifically, conductive silver paste is printed on the conductive layer 7 of the first region 2 and the second region 3, and then dried and sintered to prepare the first electrode 81 and the second electrode 82.

[0135] To better understand the preparation method provided in this application, the following detailed embodiments are given:

[0136] Example 1

[0137] This embodiment 1 provides a method for fabricating a back-contact solar cell 10, including the following steps:

[0138] A. Select n-type silicon substrate.

[0139] B. The silicon wafer is isotropically etched using a 25% sodium hydroxide alkaline solution to form a double-sided polished silicon substrate 1.

[0140] C. A tunnel oxide layer 53 with a thickness of 1 nm was prepared on the entire surface of silicon substrate 1 (back side 12 and front side 11) using a furnace tube thermal oxidation method.

[0141] D. Polycrystalline silicon is deposited on the surface of the tunneling oxide layer 53 using LPCVD (low-pressure chemical vapor deposition), and then boron diffusion is performed on the polycrystalline silicon using furnace tube diffusion to obtain a p-type doped polycrystalline silicon layer 54 with a thickness of 20~100nm; simultaneously, a BSG layer (Boro-Silicate Glass) is formed on the surface of the p-type doped polycrystalline silicon layer 54 to serve as the doped silicon glass layer 51. Figure 2 As shown.

[0142] E. Wash away the BSG layer with 5% HF (hydrofluoric acid).

[0143] F. Preparation of SiNx protective layer (silicon nitride protective layer): as follows Figure 3 As shown, on the surface of the p-type doped polycrystalline silicon layer 54 on the back side 12 of the silicon substrate 1, a SiNx film with a thickness of 60 nm is deposited using a high-temperature furnace tube with silane and ammonia as reaction precursors, forming a SiNx protective layer used as a protective layer 52.

[0144] G. The second region 3 (region n in this embodiment) on the back side of the silicon substrate 1 is etched using a 532nm laser to open the SiNx protective layer, as shown below. Figure 4 As shown.

[0145] H, such as Figure 5 As shown, a 25% KOH solution is used to etch and remove the p-type doped polysilicon layer 54 on the front side of the silicon substrate 1, the exposed p-type doped polysilicon layer 54 without silicon nitride film protection in the second region 3 on the back side, and the p-type doped polysilicon layer 54 at the edge of the first region 2 (p region in this embodiment). Then, an HF solution is used to clean and remove the exposed tunneling oxide layer 53, the tunneling oxide layer 53 at the edge of the first region 2 (p region in this embodiment), and the SiNx protective layer in the corresponding areas.

[0146] I. Such as Figure 6 As shown, a 4nm passivation layer 91 made of aluminum oxide is prepared on the front side of the silicon substrate 1 using an ALD device, and then a 60nm antireflection layer 92 made of silicon nitride is deposited on the surface of the passivation layer 91.

[0147] J, such as Figure 7As shown, an 8 nm thick hydrogenated amorphous silicon layer and a 20 nm thick n-type doped microcrystalline silicon layer are deposited on the entire back side using a PECVD device to obtain an intrinsic amorphous silicon layer 55 and an n-type doped silicon-containing layer 56.

[0148] K, such as Figure 8 As shown, the surface of the n-type doped silicon layer 56 is treated with carbon-oxygen plasma to generate a phosphorus-doped carbon oxide amorphous silicon film, resulting in a carbon-oxygen doped silicon layer 6 with a thickness of 3 nm.

[0149] L, such as Figure 9 As shown, the first region 2 (p region) on the back side of the silicon substrate 1 is etched with a 532nm laser to remove the carbon-oxygen doped silicon layer 6, the intrinsic amorphous silicon layer 55 and the n-type doped silicon-containing layer 56 on the surface of the first region 2.

[0150] M, such as Figure 10 As shown, a conductive layer 7 is deposited on the back side of a silicon substrate 1 using a PVD device.

[0151] N. Etching printing: such as Figure 11 As shown, using a designed and developed stencil, the conductive layer 7 of the second sub-region 42 of the isolation region 4 is etched away with an etching paste, so that the p-region and the n-region are isolated from each other.

[0152] O. Electrode preparation: such as Figure 12 As shown, conductive silver paste is applied to the first region 2 and the second region 3 on the back of the solar cell. After drying and sintering, the first electrode 81 and the second electrode 82 are formed, thereby obtaining a back contact solar cell.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them; although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of this application or equivalent substitutions can be made to some technical features, all of which should be covered within the scope of the technical solutions claimed in this application.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate (1) has a first region (2), a second region (3) and an isolation region (4) located between the first region (2) and the second region (3) on its back side (12). The first carrier collection layer (57) is located in the first region (2); The second carrier collection layer (58) is disposed in the second region (3) with the opposite conductivity type to the first carrier collection layer (57). A conductive layer (7) is disposed in the first region (2) and the second region (3), and is located on the side of the first carrier collection layer (57) and the second carrier collection layer (58) away from the silicon substrate (1), wherein the conductive layer (7) is disconnected in the isolation region (4); and A carbon-oxygen-doped silicon layer (6) is disposed between the first carrier collection layer (57) and the conductive layer (7), and / or, is disposed between the second carrier collection layer (58) and the conductive layer (7).

2. The back-contact solar cell according to claim 1, characterized in that, The ratio of carbon to oxygen atoms in the carbon-oxygen doped silicon layer (6) is 1:4 to 1:2; and / or the thickness of the carbon-oxygen doped silicon layer (6) is 1 to 5 nm.

3. The back-contact solar cell according to claim 1, characterized in that, The first carrier collection layer (57) includes a tunneling oxide layer (53) and a doped polycrystalline silicon layer (54) arranged sequentially along a direction away from the silicon substrate (1), and the second carrier collection layer (58) includes an intrinsic amorphous silicon layer (55) and a doped silicon-containing layer (56) arranged sequentially along a direction away from the silicon substrate (1). Preferably, the doped polysilicon layer (54) is a p-type doped polysilicon layer, and the doped silicon-containing layer (56) is an n-type doped silicon-containing layer; Preferably, the n-type doped silicon layer includes at least one of an n-type doped amorphous silicon layer, an n-type doped microcrystalline silicon layer, and an n-type doped nanocrystalline silicon layer; and / or, the carbon-oxygen doped silicon layer (6) is disposed between the doped silicon layer (56) and the conductive layer (7) in the second region (3), and is not disposed in the first region (2).

4. The back-contact solar cell according to any one of claims 1-3, characterized in that, There is a height difference between the conductive layer (7) located in the first region (2) and the conductive layer (7) located in the second region (3); Preferably, the conductive layer (7) of the first region (2) is farther away from the silicon substrate (1) than the conductive layer (7) of the second region (3).

5. The back-contact solar cell according to any one of claims 1-3, characterized in that, At least a portion of the isolation region (4) is provided with the carbon-oxygen-doped silicon layer (6).

6. The back-contact solar cell according to claim 5, characterized in that, The isolation region (4) includes a first sub-region (41) connected to the first region (2). The first sub-region (41) is provided with a first carrier collection layer (57), a second carrier collection layer (58), a carbon-oxygen doped silicon layer (6) and a conductive layer (7) in sequence along the direction away from the silicon substrate (1). Preferably, the isolation region (4) further includes a second sub-region (42) located between the first sub-region (41) and the second region (3), and the second sub-region (42) is connected to the first sub-region (41). The second sub-region (42) is provided with the first carrier collection layer (57), the second carrier collection layer (58) and the carbon-oxygen doped silicon layer (6) in sequence along the direction away from the silicon substrate (1). The conductive layer (7) does not extend to the second sub-region (42). Preferably, the isolation region (4) further includes a third sub-region (43) connected between the second sub-region (42) and the second region (3), wherein the second carrier collection layer (58) and the carbon-oxygen doped silicon layer (6) are sequentially disposed in the third sub-region (43) along a direction away from the silicon substrate (1). Preferably, the third sub-region (43) includes a fourth sub-region (44) and a fifth sub-region (45), the fourth sub-region (44) and the fifth sub-region (45) are arranged sequentially along the direction from the first region (2) to the second region (3), and there is a height difference between the carbon-oxygen doped silicon layer (6) of the fourth sub-region (44) and the fifth sub-region (45) on the surface away from the silicon substrate (1).

7. The back-contact solar cell according to any one of claims 1-3, characterized in that, The back-contact solar cell further includes: a first electrode (81) electrically connected to the conductive layer of the first region and a second electrode (82) electrically connected to the conductive layer of the second region; and / or, The back-contact solar cell further includes a passivation layer (91) and an anti-reflection layer (92) disposed on the front side (11) of the silicon substrate (1), wherein the anti-reflection layer (92) is located on the side of the passivation layer (91) away from the silicon substrate (1).

8. A method for fabricating a back-contact solar cell, characterized in that, include: A first carrier collection layer (57) and a second carrier collection layer (58) are formed in the first region (2) and the second region (3) on the back side (12) of the silicon substrate (1), respectively. A conductive layer (7) is formed on the side of the first carrier collection layer (57) and the second carrier collection layer (58) away from the silicon substrate (1), and the conductive layer (7) is disconnected in the isolation region (4) between the first region (2) and the second region (3) on the back side (12) of the silicon substrate (1); and Before forming a conductive layer (7) on the side of the first carrier collecting layer (57) away from the silicon substrate (1), a carbon-oxygen doped silicon layer (6) is also formed on the side of the first carrier collecting layer (57) away from the silicon substrate (1), and / or, a carbon-oxygen doped silicon layer (6) is also formed on the side of the second carrier collecting layer (58) away from the silicon substrate (1).

9. The preparation method according to claim 8, characterized in that, The carbon-oxygen-doped silicon layer (6) is formed by plasma vapor deposition. Preferably, forming the carbon-oxygen-doped silicon layer (6) by plasma vapor deposition includes: After forming a first carrier collection layer (57) and a second carrier collection layer (58) in the first region (2) and the second region (3) on the back side (12) of the silicon substrate (1), the silicon substrate (1) is placed in a plasma device, the power of the plasma device is controlled to be 500-1500W, the pressure is 50-150Pa, and CO2 with a flow rate of 200-1000SCCM is introduced into the plasma device to form the carbon-oxygen doped silicon layer (6).

10. The preparation method according to claim 8, characterized in that, The formation of a first carrier collection layer (57) in a first region (2) on the back side (12) of the silicon substrate (1) includes: A tunneling oxide layer (53) and a doped polycrystalline silicon layer (54) are sequentially formed on the entire back side (12) of the silicon substrate (1) in a direction away from the silicon substrate (1). A protective layer is formed on the outside of the doped polycrystalline silicon layer (54) on the back side (12) of the silicon substrate (1); The protective layer located in the second region (3) is removed by laser; The tunneling oxide layer (53) and the doped polysilicon layer (54) of the second region (3) are removed by cleaning to form a first carrier collection layer (57) including the tunneling oxide layer (53) and the doped polysilicon layer (54) in the first region (2). Preferably, forming a second carrier collection layer (58) in the second region (3) on the back side (12) of the silicon substrate (1) includes: An intrinsic amorphous silicon layer (55) and a doped silicon-containing layer (56) are formed on the entire back side (12) of the silicon substrate (1). The intrinsic amorphous silicon layer (55) and the doped silicon layer (56) in the first region (2) are removed by laser to form a second carrier collection layer (58) in the second region (3) consisting of the intrinsic amorphous silicon layer (55) and the doped silicon layer (56).

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