Back contact cells, cell assemblies and photovoltaic systems

Abstract

This application relates to the field of solar cell technology, providing a back-contact cell, a cell module, and a photovoltaic system. In the back-contact cell, the surfaces of a first recessed region and a second recessed region are both recessed into a silicon substrate relative to the surface of a protruding region. An isolation layer is provided in the protruding region. A second portion of a first dielectric layer extends to a first side surface of the first recessed region and to the side surface of the isolation layer facing the first recessed region. A first extension of a first doped polycrystalline silicon layer is separated from the isolation layer by a second portion. A fourth portion of a second dielectric layer extends to a second side surface of the second recessed region and to the side surface of the isolation layer facing the second recessed region. A second extension of the second doped polycrystalline silicon layer is separated from the isolation layer by a second portion. This effectively suppresses the formation of conductive recombination channels between the p-region and the n-region, thereby improving the overall conversion efficiency of the cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0002] Back-contact solar cells integrate both the emitter and base contact electrodes on the back of the cell, completely avoiding the blocking of light-receiving surfaces by metal electrodes, thereby improving light capture capability and short-circuit current output.

[0003] In related technologies, in order to avoid creating deep trenches in the silicon substrate to achieve electrical isolation between the p-type and n-type regions, an intrinsic polycrystalline silicon layer is usually deposited on the back side of the silicon substrate, and the p-type, n-type, and isolation regions between them are formed by local doping, thereby achieving effective isolation between the p-type and n-type regions.

[0004] However, in such a technical solution, during the operation of the battery, the surface of the p-type region of the silicon substrate is enriched with positive charge, while the surface of the n-type region is enriched with negative charge. The back passivation film layer of the back contact battery usually has fixed positive or fixed negative charge. Under such circumstances, opposite polarity charges accumulate at the surface of the isolation region. The negative pole of this charge will recombine with the holes enriched in the p-type region or the electrons enriched in the n-type region to form a conductive channel, which leads to increased recombination and lateral leakage between the p-type and n-type regions, thereby affecting the efficiency of the back contact battery. Summary of the Invention

[0005] This application provides a back-contact battery, a battery module, and a photovoltaic system.

[0006] This application is implemented as follows: the back contact battery in the embodiments of this application includes: A silicon substrate having opposing front and back sides, the back side including a protruding region and a first recessed region and a second recessed region located on both sides of the protruding region and adjacent to the protruding region, the surface of the first recessed region being recessed into the silicon substrate relative to the surface of the protruding region, and the surface of the second recessed region also being recessed into the silicon substrate relative to the surface of the protruding region, the first recessed region including a first bottom surface and a first side surface connected to the protruding region, and the second recessed region including a second bottom surface and a second side surface connected to the protruding region; An isolation layer is disposed on the protruding area; A first dielectric layer, the first dielectric layer comprising a first portion stacked on the first bottom surface and a second portion extending from the first portion to the first side surface and the side surface of the insulating layer facing the first recessed area; A first doped polysilicon layer, the first doped polysilicon layer including a first body portion stacked on the first portion and a first extension portion stacked on the second portion, the first extension portion being separated from the isolation layer by the second portion; The second dielectric layer includes a third portion stacked on the second bottom surface and a fourth portion extending from the third portion to the second side surface and the side surface of the insulating layer facing the second recessed area. A second doped polysilicon layer, the second doped polysilicon layer including a second body portion stacked on the third portion and a second extension portion stacked on the fourth portion, the second extension portion being separated from the isolation layer by the fourth portion; and A back passivation layer is stacked on the side of the first doped polysilicon layer, the second doped polysilicon layer, and the isolation layer that is away from the silicon substrate.

[0007] In some embodiments, the depth of the first recessed region recessed into the silicon substrate relative to the protruding region is 2μm-20μm; The second recessed region is recessed into the silicon substrate to a depth of 2μm-20μm relative to the protruding region.

[0008] In some embodiments, the first doped polysilicon layer is a p-type doped polysilicon layer, and the second doped polysilicon layer is an n-type doped polysilicon layer; The depth of the first recessed region recessed into the silicon substrate relative to the protruding region is greater than the depth of the second recessed region recessed into the silicon substrate relative to the protruding region.

[0009] In some embodiments, the thickness of the second portion is different from the thickness of the first portion; and / or The thickness of the fourth part is different from the thickness of the third part.

[0010] In some embodiments, the thickness of the second portion is greater than the thickness of the first portion; and / or The thickness of the fourth part is greater than the thickness of the third part.

[0011] In some embodiments, the thickness of the second portion is 1.2 to 5 times the thickness of the first portion; and / or The thickness of the fourth part is 1.2 to 5 times the thickness of the third part.

[0012] In some embodiments, the thickness of the first portion is 0.5 nm-4 nm, and the thickness of the second portion is 0.6 nm-20 nm; and / or The thickness of the third part is 0.5nm-4nm, and the thickness of the fourth part is 0.6nm-20nm.

[0013] In some embodiments, the back contact battery further includes a third dielectric layer disposed between the isolation layer and the silicon substrate.

[0014] In some embodiments, the material of the third dielectric layer is different from that of the first dielectric layer and the second dielectric layer.

[0015] In some embodiments, the first dielectric layer and the second dielectric layer are both silicon oxide layers, and the third dielectric layer is a silicon nitride layer.

[0016] In some embodiments, the first doped polysilicon layer is a p-type doped polysilicon layer, the second doped polysilicon layer is an n-type doped polysilicon layer, and a plurality of first holes are formed on the first portion. Wherein, the third part does not have holes; or The third part has a number of second holes, and the number of second holes is less than the number of first holes.

[0017] In some embodiments, the isolation layer includes a middle portion, a first edge portion, and a second edge portion, the first edge portion being located between the middle portion and the second portion, the second portion extending to a side surface of the first edge portion near the first recessed area, the second edge portion being located between the middle portion and the fourth portion, the fourth portion extending to a side surface of the second edge portion toward the second recessed area; Both the first doped polysilicon layer and the first edge portion are doped with a third group element, and the doping concentration of the third group element in the first edge portion is less than the doping concentration of the third group element in the first doped polysilicon layer. Both the second doped polysilicon layer and the second edge portion are doped with a fifth group element, and the doping concentration of the fifth group element in the second edge portion is less than the doping concentration of the fifth group element in the second doped polysilicon layer. Wherein, the intermediate part does not contain elements of the third main group and the fifth main group; or The doping concentrations of Group 3 elements and Group 5 elements in the intermediate portion are both less than 5E17 / cm³. 3 .

[0018] In some embodiments, the doping concentration of a third group element in the first edge portion gradually decreases in the direction away from the first recessed region; and / or, the doping concentration of a fifth group element in the second edge portion gradually decreases in the direction away from the second recessed region.

[0019] In some embodiments, the width of the first edge portion is greater than the width of the second edge portion.

[0020] In some embodiments, the width of the second edge portion is 0.4 to 0.8 times the width of the first edge portion.

[0021] In some embodiments, the width of the middle portion is greater than the width of the first edge portion, and the width of the middle portion is greater than the width of the second edge portion.

[0022] In some embodiments, the width of the first edge portion is 1μm-10μm, the width of the second edge portion is 1μm-10μm, and the width of the middle portion is 60μm-600μm.

[0023] In some embodiments, the ratio between the width of the first edge portion and the overall width of the isolation layer is less than or equal to 0.2; The ratio between the width of the second edge portion and the overall width of the isolation layer is less than or equal to 0.2; The ratio between the width of the middle section and the overall width of the isolation layer is greater than or equal to 0.6.

[0024] In some embodiments, the insulating layer is doped with at least one of oxygen, nitrogen and carbon. The oxygen doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 And / or the nitrogen doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 And / or the carbon doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 .

[0025] In some embodiments, the width of the isolation layer is 50μm-700μm.

[0026] In some embodiments, the first doped polysilicon layer further includes a third extension extending from the first extension to a portion of the surface of the isolation layer away from the silicon substrate, wherein a first insulating layer is provided between the third extension and the isolation layer.

[0027] In some embodiments, the thickness of the first insulating layer is greater than the thickness of the first portion and is 200 to 10,000 times the thickness of the first portion.

[0028] In some embodiments, the width of the third extension is 1 μm-10 μm.

[0029] In some embodiments, the ratio between the width of the portion of the isolation layer covered by the third extension and the overall width of the isolation layer is less than or equal to 0.2.

[0030] In some embodiments, the second doped polysilicon layer further includes a fourth extension extending from the second extension to a portion of the surface of the isolation layer away from the silicon substrate, wherein a second insulating layer is provided between the fourth extension and the isolation layer.

[0031] In some embodiments, the thickness of the second insulating layer is greater than the thickness of the third portion and is 200 to 10,000 times the thickness of the third portion.

[0032] In some embodiments, the width of the fourth extension is 1 μm-10 μm.

[0033] In some embodiments, the ratio between the width of the portion of the isolation layer covered by the fourth extension and the overall width of the isolation layer is less than or equal to 0.2.

[0034] In some embodiments, the back contact battery further includes a third doped polysilicon layer and a third insulating layer located between the fourth extension and the second insulating layer. The polarity of the third doped polysilicon layer is the same as that of the first doped polysilicon layer. The third doped polysilicon layer is stacked on the second insulating layer. The third insulating layer is stacked on the third doped polysilicon layer. The fourth extension is stacked on the third insulating layer. The fourth extension extends to the side surface of the third doped polysilicon layer facing the second recessed region.

[0035] This application also provides a battery assembly comprising a plurality of back contact batteries as described in any of the preceding claims.

[0036] This application also provides a photovoltaic system, which includes the aforementioned battery components.

[0037] In the back-contact battery, battery module, and photovoltaic system of this application embodiment, the surfaces of the first recessed region and the second recessed region are both recessed into the silicon substrate relative to the surface of the protruding region. An isolation layer is provided in the protruding region. A second portion of the first dielectric layer extends to the first side surface of the first recessed region and the side surface of the isolation layer facing the first recessed region. The first extension of the first doped polysilicon layer is separated from the isolation layer by the second portion. A fourth portion of the second dielectric layer extends to the second side surface of the second recessed region and the side surface of the isolation layer facing the second recessed region. The second extension of the second doped polysilicon layer is separated from the isolation layer by the second portion. Thus, on one hand, the first doped polysilicon layer and the second doped polysilicon layer are directly isolated from each other by the isolation layer, the second portion, and the fourth portion, eliminating the need to create deep trenches in the silicon substrate to achieve isolation between two regions of different polarities. On the other hand, when the battery operates under illumination, photogenerated carriers generated in the silicon substrate are collected. Holes accumulate on the surface of the first recessed region, while electrons accumulate on the surface of the second recessed region. Since the protrusion and the two recessed regions form a physical height difference, the first and second dielectric layers not only cover the bottom surface of their respective recessed regions but also extend to cover the sides of the recessed regions and the side surface of the isolation layer facing the recessed regions. Furthermore, the first and second doped polysilicon layers are separated from the isolation layer by these dielectric layers. Even if the back passivation layer has a fixed charge, the charge induced on the surface of the protrusion corresponding to the isolation layer needs to cross a longer insulating path to interact with the electrons or holes accumulated on the surfaces of the first and second recessed regions. This makes it difficult for the charge induced in the region corresponding to the isolation layer to directly form a conductive channel with the p-type or n-type polysilicon layer, thereby significantly reducing the risk of recombination and leakage caused by charge accumulation.

[0038] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the photovoltaic system provided in the embodiments of this application; Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application; Figure 3 This is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this application; Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure of the back contact battery along line IV-IV. Figure 5 yes Figure 3 Another cross-sectional structural diagram of the back contact battery along line IV-IV; Figure 6yes Figure 3 Another cross-sectional structural diagram of the back contact battery along line IV-IV.

[0040] Explanation of key component symbols: Photovoltaic system 1000, battery module 200, back contact cell 100, silicon substrate 10, front side 11, back side 12, first recessed area 121, second recessed area 122, protruding area 123, isolation layer 20, middle part 21, first edge part 22, second edge part 23, first dielectric layer 30, first part 31, second part 32, first doped polycrystalline silicon layer 40, first body part 41, first extension part 42, third extension part 43, second dielectric layer 50, third part 51, fourth part 52, second doped polycrystalline silicon layer 60, second body part 61, second extension part 62, fourth extension part 63, back passivation layer 70, first electrode 80, second electrode 90, third dielectric layer 110, first insulating layer 120, second insulating layer 130, third doped polycrystalline silicon layer 140, third insulating layer 150. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0042] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "several" means two or more, unless otherwise explicitly specified.

[0044] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0045] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0046] Please see Figure 1 and Figure 2 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment, and the battery module 200 in this application embodiment may include a plurality of back contact batteries 100 in this application embodiment.

[0047] In embodiments of this application, multiple back-contact batteries 100 in the battery assembly 200 can be connected in series to form multiple battery strings. Each battery string can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual battery cells can be achieved by welding solder strips, or the connection between individual battery strings can be achieved by busbars. In some embodiments, the individual battery strings can form a battery cell array, and then be packaged together by a front plate, a front adhesive film, a rear adhesive film, and a back plate to form the battery assembly 200.

[0048] In the embodiments of this application, please refer to Figure 3 and Figure 4 The back contact battery 100 in this embodiment may include a silicon substrate 10, an isolation layer 20, a first dielectric layer 30, a first doped polysilicon layer 40, a second dielectric layer 50, a second doped polysilicon layer 60, and a back passivation layer 70.

[0049] like Figure 5As shown, the silicon substrate 10 has a front side 11 and a back side 12. The back side 12 of the silicon substrate 10 may include a protruding region 123 and a first recessed region 121 and a second recessed region 122 located on both sides of the protruding region 123, respectively. The first recessed region 121 is adjacent to the protruding region 123, and the second recessed region 122 is also adjacent to the protruding region 123.

[0050] like Figure 4 As shown, the surface of the first recessed region 121 is recessed into the silicon substrate 10 relative to the surface of the protruding region 123, and the surface of the second recessed region 122 is also recessed into the silicon substrate 10 relative to the surface of the protruding region 123. The first recessed region 121 includes a first bottom surface 1211 and a first side surface 1212 connected to the protruding region 123, and the second recessed region 122 includes a second bottom surface 1221 and a second side surface 1222 connected to the protruding region 123.

[0051] Specifically, such as Figure 3 and Figure 4 As shown, the back surface 12 may include a plurality of first recessed areas 121, a plurality of second recessed areas 122, and a plurality of protruding areas 123. The plurality of first recessed areas 121 and the plurality of second recessed areas 122 may be arranged alternately along a first direction and all extend along a second direction. The protruding areas 123 are located between adjacent first recessed areas 121 and second recessed areas 122, that is, the protruding areas 123 are located between adjacent first recessed areas 121 and second recessed areas 122, and the protruding areas 123 also extend along the second direction. Figure 3 As shown, in some possible embodiments, the first direction and the second direction can be the longitudinal direction and the lateral direction of the back contact battery 100, respectively, without any specific limitation.

[0052] like Figure 4 As shown, the isolation layer 20 is stacked and covered on the protruding area 123, and each protruding area 123 may be provided with the isolation layer 20. The first dielectric layer 30 may include a first portion 31 and a second portion 32. The first portion 31 is stacked on the first bottom surface 1211, and the second portion 32 extends from the first portion 31 to the first side surface 1212 and the side surface of the isolation layer 20 facing the first recessed area 121.

[0053] The first doped polysilicon layer 40 includes a first body portion 41 and a first extension portion 42. The first body portion 41 is stacked on a first portion 31, and the first extension portion 42 is connected to the first body portion 41 and extends from the first body portion 41 and is stacked on a second portion 32. The first extension portion 42 is separated from the isolation layer 20 by the second portion 32. The number of first dielectric layers 30 and first doped polysilicon layers 40 corresponds to the number of first recessed regions 121.

[0054] The second dielectric layer 50 may include a third portion 51 and a fourth portion 52. The third portion 51 is stacked on the second bottom surface 1221, and the fourth portion 52 extends from the third portion 51 to the second side surface 1222 and the side surface of the isolation layer 20 facing the second recessed region 122. The second doped polysilicon layer 60 includes a second body portion 61 and a second extension portion 62. The second body portion 61 is stacked on the third portion 51, and the second extension portion 62 is connected to the second body portion 61 and extends from the second body portion 61 and is stacked on the fourth portion 52. The second extension portion 62 is separated from the isolation layer 20 by the fourth portion 52. The number of second dielectric layers 50 and second doped polysilicon layers 60 corresponds to the number of second recessed regions 122.

[0055] A back passivation layer 70 is stacked on the side of the first doped polysilicon layer 40, the second doped polysilicon layer 60, and the isolation layer 20 away from the silicon substrate 10. Specifically, the back passivation layer 70 is the outermost film layer of the back contact cell 100 located on the back side 12, and the back passivation layer 70 can completely cover the entire back side 12.

[0056] In the back contact battery 100, battery module 200 and photovoltaic system 1000 of this application embodiment, the surfaces of the first recessed region 121 and the second recessed region 122 are recessed into the silicon substrate 10 relative to the surface of the protruding region 123. The protruding region 123 is provided with an isolation layer 20. The second portion 32 of the first dielectric layer 30 extends to the first side surface 1212 of the first recessed region 121 and the side surface of the isolation layer 20 facing the first recessed region 121. The first extension 42 of the first doped polysilicon layer 40 is separated from the isolation layer 20 by the second portion 32. The fourth portion 52 of the second dielectric layer 50 extends to the second side surface 1222 of the second recessed region 122 and the side surface of the isolation layer 20 facing the second recessed region 122. The second extension 62 of the second doped polysilicon layer 60 is separated from the isolation layer 20 by the second portion 32. Thus, on the one hand, the first doped polysilicon layer 40 and the second doped polysilicon layer 60 are directly isolated by the isolation layer 20, the second portion 32, and the fourth portion 52, eliminating the need to create deep trenches in the silicon substrate 10 to achieve isolation between two regions of different polarities. On the other hand, when the battery operates under illumination, photogenerated carriers generated in the silicon substrate 10 are collected, holes accumulate on the surface of the first recessed region 121, and electrons accumulate on the surface of the second recessed region 122. Since the protrusion region 123 and the two recessed regions form a physical height difference, the first dielectric layer 30 and the second dielectric layer 50 not only cover the bottom surface of their respective recessed regions but also extend to cover the sides of the recessed regions and the side surface of the isolation layer 20 facing the recessed regions. Furthermore, the first doped polysilicon layer 40 and the second doped polysilicon layer 60 are separated from the isolation layer 20 by these dielectric layers, even if the back passivation layer 70 is... The fixed charge induced on the surface of the protrusion 123 corresponding to the isolation layer 20 requires a longer insulating path (it needs to cross the portions located on the side of the dielectric layer recess (such as the second portion 32 and the fourth portion 52) and the surface height difference between the recess and the protrusion 123) to interact with the electrons or holes enriched on the surfaces of the first recess 121 and the second recess 122. This makes it difficult for the charge induced in the region corresponding to the isolation layer 20 to directly form a conductive channel with the p-type or n-type polysilicon layer, thereby significantly reducing the risk of recombination and leakage caused by charge accumulation. In addition, due to the presence of the second portion 32 and the fourth portion 52, the doping elements in the first doped polysilicon layer 40 and the second doped polysilicon layer 60 can be effectively blocked, effectively suppressing the diffusion of doping elements from both into the isolation layer 20, thereby further reducing recombination between the p-region and the n-region.

[0057] In other words, in the embodiments of this application, by adopting this multi-layered and multi-dimensional isolation mechanism, the formation of conductive recombination channels between the p-region and the n-region is effectively suppressed, thereby improving the overall conversion efficiency of the battery.

[0058] Specifically, in the embodiments of this application, the silicon substrate 10 can be a p-type silicon substrate or an n-type silicon substrate, and there is no specific limitation. One of the first doped polycrystalline silicon layer 40 and the second doped polycrystalline silicon layer 60 is doped with a p-type doping type, that is, doped with a Group 3 element, such as boron, gallium, etc., and the other is doped with an n-type doping type, that is, doped with a Group 5 element, such as phosphorus, arsenic, antimony, etc.

[0059] In some embodiments, the isolation layer 20 may include at least one of amorphous silicon, polycrystalline silicon, and microcrystalline silicon. In some possible embodiments, the isolation layer 20 may be amorphous silicon, which has weaker lateral conductivity and can effectively improve the isolation effect of the first doped polycrystalline silicon layer 40 and the second doped polycrystalline silicon layer 60. Of course, in some embodiments, the isolation layer 20 may also be polycrystalline silicon and / or microcrystalline silicon.

[0060] In some embodiments, the isolation layer 20 may be a completely undoped intrinsic layer or a doped layer with a low doping concentration, effectively ensuring the isolation effect.

[0061] In some embodiments, the isolation layer 20 may have an amorphous silicon-microcrystalline silicon mixed phase and / or an amorphous silicon-polycrystalline silicon mixed phase and / or a microcrystalline silicon-polycrystalline silicon mixed phase, and the crystallinity of the isolation layer 20 is 60%-98%.

[0062] Thus, by setting the isolation layer 20 to have the aforementioned mixed phase and strictly controlling the crystallinity of the isolation layer 20 within the range of 60%-98%, the isolation performance of the isolation layer 20 can be effectively guaranteed while improving the passivation effect. At the same time, it can also avoid excessive light absorption and too many crystal orientation defects caused by an excessively low crystallinity of the isolation layer 20.

[0063] Specifically, in such embodiments, the crystallinity of the isolation layer 20 may be, for example, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, or other values ​​between 60% and 98%.

[0064] In some embodiments, the first dielectric layer 30 and the second dielectric layer 50 can both be tunneling layers with tunneling function. The first dielectric layer 30 and the second dielectric layer 50 can be, for example, at least one of silicon oxide layer, silicon nitride layer, and silicon oxynitride layer, and there is no specific limitation here.

[0065] Of course, in some possible embodiments, the first dielectric layer 30 and the second dielectric layer 50 may also be dielectric layers without tunneling function. In such cases, a plurality of holes penetrating the first dielectric layer 30 and the second dielectric layer 50 are formed. The first doped polysilicon layer 40 and the second doped polysilicon layer 60 can achieve conductivity with the silicon substrate 10 through the holes in the dielectric layers, thereby realizing carrier transport and collection. In addition, in some embodiments, the first dielectric layer 30 and the second dielectric layer 50 may have a plurality of holes while having tunneling function; the specifics are not limited here.

[0066] The back passivation layer 70 is the outermost film layer located on the back side 12 of the back contact battery 100. The back passivation layer 70 may include at least one of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide, and there is no specific limitation herein. The back passivation layer 70 may be a film layer with a fixed positive charge or a film layer with a fixed negative charge, and there is no specific limitation herein.

[0067] like Figure 4 As shown, in the back contact battery 100, a first electrode 80 is disposed on the first recessed region 121, and a second electrode 90 is disposed on the second recessed region 122. The first electrode 80 at least partially penetrates the back passivation layer 70 and makes conductive contact with the first doped polysilicon layer 40, and the second electrode 90 at least partially penetrates the back passivation layer 70 and makes conductive contact with the second doped polysilicon layer 60.

[0068] In some embodiments, the depth of the first recessed region 121 recessed relative to the protruding region 123 into the silicon substrate 10 (i.e., the recess depth in the thickness direction of the silicon substrate 10) is 2μm-20μm, for example, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm or other values ​​between 2μm and 20μm.

[0069] Thus, by precisely limiting the depth of the first recessed region 121 recessed into the silicon substrate 10 relative to the protruding region 123 to within the range of 2μm-20μm, it is possible to avoid the situation where the recessed depth of the first recessed region 121 is too small, causing the charge induced on the surface of the protruding region 123 to recombine with the charge enriched in the p-type region simply by traversing a small height difference path. This further reduces the risk of recombination and leakage caused by charge accumulation. At the same time, it is also possible to avoid the situation where the recessed depth of the first recessed region 121 is too large, causing a significant reduction in the mechanical strength of the silicon substrate 10 and increasing the risk of microcracks and wafer cracks.

[0070] In other words, in this embodiment, if the depth of the first recessed region 121 is less than 2 μm, the ability to suppress recombination and leakage current will be poor. If the depth of the first recessed region 121 is greater than 20 μm, the mechanical strength of the silicon substrate 10 is likely to decrease significantly, leading to an increased risk of microcracks and wafer cracking. This embodiment, by optimizing the depth of the first recessed region 121, can reduce the risk of recombination and leakage current, and also effectively avoid microcracks and wafer cracking.

[0071] In some embodiments, the depth of the second recessed region 122 recessed into the silicon substrate 10 relative to the protruding region 123 is 2μm-20μm, for example, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm or other values ​​between 2μm and 20μm.

[0072] Thus, by precisely limiting the depth of the second recessed region 122 recessed into the silicon substrate 10 relative to the protruding region 123 to within the range of 2μm-20μm, it is possible to avoid the situation where the recessed depth of the second recessed region 122 is too small, causing the charge induced on the surface of the protruding region 123 to recombine with the charge enriched in the n-type region simply by traversing a small height difference path. This further reduces the risk of recombination and leakage caused by charge accumulation. At the same time, it is also possible to avoid the situation where the recessed depth of the second recessed region 122 is too large, causing a significant reduction in the mechanical strength of the silicon substrate 10 and increasing the risk of microcracks and wafer breakage.

[0073] In other words, in such an embodiment, if the depth of the second recessed region 122 is less than 2 μm, the ability to suppress recombination and leakage current will be poor. If the depth of the second recessed region 122 is greater than 20 μm, the mechanical strength of the silicon substrate 10 is likely to decrease significantly, leading to an increased risk of microcracks and wafer cracking. This embodiment, by optimizing the recess depth of the first recessed region 121, can reduce the risk of recombination and leakage current, and also effectively avoid microcracks and wafer cracking.

[0074] In some embodiments, the first doped polysilicon layer 40 is a p-type doped polysilicon layer, the second doped polysilicon layer 60 is an n-type doped polysilicon layer, and the depth of the first recessed region 121 recessed into the silicon substrate 10 relative to the protruding region 123 is greater than the depth of the second recessed region 122 recessed into the silicon substrate 10 relative to the protruding region 123.

[0075] Thus, since electron carriers in the n-type region can be collected and transported more quickly, while hole carriers in the p-type region transport more slowly, setting the depth of the depression in the p-type region to be greater can further reduce the recombination of the charge induced at the protrusion 123 with the hole carriers in the p-type region, thereby further reducing the risk of recombination and leakage.

[0076] In some embodiments, the thickness of the second portion 32 (the dimension of the second portion 32 in the first direction) is different from the thickness of the first portion 31 (the dimension of the first portion 31 in the thickness direction of the back contact battery 100); and / or, the thickness of the fourth portion 52 (the dimension of the fourth portion 52 in the first direction) is different from the thickness of the third portion 51 (the dimension of the third portion 51 in the thickness direction of the back contact battery 100).

[0077] Thus, by differentiating the thickness of each portion of the first dielectric layer 30 and the second dielectric layer 50, the electrical performance of the back contact battery 100 can be finely controlled. Specifically, the first portion 31 and the second portion 32 of the first dielectric layer 30 cover the bottom and side surfaces of the first recessed region 121, respectively, while the third portion 51 and the fourth portion 52 of the second dielectric layer 50 cover the bottom and side surfaces of the second recessed region 122, respectively. By adjusting the thickness of the dielectric layers in these different regions, the passivation effect at the interface between the dielectric layer and the silicon substrate 10 can be optimized in a targeted manner. For example, in the sidewall region of the recessed region, due to its geometry and possible crystal orientation differences, the passivation requirements may differ from those in the bottom region. By making the dielectric layer (second portion 32 or fourth portion 52) in the sidewall region thicker, stronger surface passivation can be provided, reducing surface recombination and thereby improving carrier lifetime.

[0078] In some embodiments, the thickness of the second portion 32 of the first dielectric layer 30 is greater than the thickness of the first portion 31.

[0079] Thus, making the first portion 31 thinner can improve the tunneling efficiency of charge carriers, thereby improving collection efficiency. Making the second portion 32 thicker can increase the insulation path of the surface-induced charge in the protrusion region 123. At the same time, the second portion 32 can also block the dopant elements in the first doped polysilicon layer 40, reducing the probability of them diffusing into the isolation layer 20, further reducing the risk of recombination and leakage. In addition, due to its geometry and possible crystal orientation differences, the requirements for the passivation layer on the first side 1212 of the first recessed region 121 may be different from those on the bottom surface region. By making the second portion 32 of the sidewall region thicker, stronger surface passivation can be provided, reducing surface recombination and thus improving the carrier lifetime.

[0080] Similarly, in some embodiments, the thickness of the fourth portion 52 of the second dielectric layer 50 is greater than the thickness of the third portion 51.

[0081] Thus, making the third portion 51 thinner can improve the tunneling efficiency of charge carriers, thereby improving collection efficiency. Making the fourth portion 52 thicker can increase the insulation path of the surface-induced charge in the protrusion region 123. At the same time, the fourth portion 52 can also block the dopant elements in the second doped polysilicon layer 60, reducing the probability of them diffusing into the isolation layer 20, further reducing the risk of recombination and leakage. In addition, due to its geometry and possible crystal orientation differences, the requirements for the passivation layer in the second side surface 1222 of the second recessed region 122 may be different from those in the bottom region. By making the fourth portion 52 in the sidewall region thicker, stronger surface passivation can be provided, reducing surface recombination and thus improving the carrier lifetime.

[0082] In some embodiments, the thickness of the second portion 32 may be 1.2 to 5 times the thickness of the first portion 31, such as 1.2 times, 1.5 times, 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times, 5 times, or other values ​​between 1.2 and 5 times.

[0083] Thus, setting the thickness of the second part 32 to be 1.2 to 5 times the thickness of the first part 31 can avoid the second part 32 being too thin, which would result in poor blocking effect of dopant diffusion and the insulation path being too short, which would result in poor ability to reduce recombination and leakage risks. It can also avoid the second part 32 being too thick, which would result in increased cost and an excessively large ineffective area of ​​the silicon substrate 10, which would affect the overall efficiency.

[0084] Similarly, in some embodiments, the thickness of the fourth portion 52 may be 1.2 to 5 times the thickness of the third portion 51, for example, 1.2 times, 1.5 times, 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times, 5 times, or other values ​​between 1.2 and 5 times.

[0085] Thus, setting the thickness of the fourth part 52 to be 1.2 to 5 times the thickness of the third part 51 can avoid the fourth part 52 being too thin, which would result in poor blocking effect of dopant diffusion and the insulation path being too short, which would result in poor ability to reduce recombination and leakage risks. It can also avoid the fourth part 52 being too thick, which would result in increased cost and an excessively large ineffective area of ​​the silicon substrate 10, which would affect the overall efficiency.

[0086] In some embodiments, the thickness of the first portion 31 is 0.5nm-4nm, such as 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm or other values ​​between 0.5nm and 4nm, and the thickness of the second portion 32 is 0.6nm-20nm, such as 0.6nm, 0.8nm, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm or other values ​​between 0.6nm and 20nm.

[0087] In this way, by precisely defining the thickness of the first part 31 and the second part 32, the tunneling efficiency of the charge carriers at the first part 31 can be guaranteed, while the insulating path formed by the second part 32 can be guaranteed not to be too short, and the blocking effect of the second part 32 on the doped elements in the first doped polysilicon layer 40 can also be guaranteed.

[0088] In some embodiments, the thickness of the third portion 51 is 0.5nm-4nm, such as 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, or other values ​​between 0.5nm and 4nm, and the thickness of the fourth portion 52 is 0.6nm-20nm, such as 0.6nm, 0.8nm, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, or other values ​​between 0.6nm and 20nm.

[0089] In this way, by precisely limiting the thickness of the third part 51 and the fourth part 52, the tunneling efficiency of the charge carriers at the third part 51 can be guaranteed, while the insulating path formed by the fourth part 52 can be guaranteed not to be too short, and the blocking effect of the fourth part 52 on the doped elements in the second doped polysilicon layer 60 can also be guaranteed.

[0090] Of course, it should be noted that in some possible embodiments, the thickness of the first part 31 may be greater than or equal to the thickness of the second part 32, and the thickness of the third part 51 may be greater than or equal to the thickness of the fourth part 52.

[0091] Please see Figure 4 In some embodiments, the back contact battery 100 may further include a third dielectric layer 110 disposed between the isolation layer 20 and the silicon substrate 10.

[0092] Thus, by setting the third dielectric layer 110, the surface passivation effect of the protrusion region 123 can be improved, thereby improving the efficiency of the back contact cell 100. At the same time, when there are doped elements in the isolation layer 20, the setting of the third dielectric layer 110 can also effectively block the doped elements in the isolation layer 20, reduce the probability of them entering the silicon substrate 10, and thus reduce Auger recombination loss in the bulk region.

[0093] In some embodiments, the material of the third dielectric layer 110 is different from the materials of the first dielectric layer 30 and the second dielectric layer 50. Thus, by using different materials to passivate different areas, a superior passivation effect can be achieved.

[0094] Furthermore, in such an embodiment, both the first dielectric layer 30 and the second dielectric layer 50 can be silicon oxide layers, and the third dielectric layer 110 can be a silicon nitride layer.

[0095] Thus, the first dielectric layer 30 and the second dielectric layer 50 are made of silicon oxide, which can ensure the tunneling efficiency of the charge carriers. The third dielectric layer 110 is made of silicon nitride, which can improve the hydrogen passivation effect of the protrusion region 123 and provide stronger blocking for dopants, reducing Auger recombination loss in the bulk region.

[0096] In some embodiments, the first doped polysilicon layer 40 is a p-type doped polysilicon layer, the second doped polysilicon layer 60 is an n-type doped polysilicon layer, and a plurality of first holes (not shown) are formed on the first portion 31. The third portion 51 has no holes or a plurality of second holes (not shown) are formed on the third portion 51, and the number of second holes is less than the number of first holes.

[0097] Thus, the first doped polysilicon layer 40 is doped with a Group 3 element, and the second doped polysilicon layer 60 is doped with a Group 5 element. On the one hand, since the transport speed of hole carriers is slower than that of electron carriers, by forming several first holes in the first portion 31, the first doped polysilicon layer 40 can form a connection with the silicon substrate 10 through the first holes, reducing the contact resistance of the p-region itself and improving the collection efficiency of hole carriers. On the other hand, the electron transport speed in the n-region is fast, and the n-region has higher requirements for passivation quality. The presence of holes will lead to a deterioration of passivation quality. Therefore, by not forming holes or forming several second holes in the third portion 51 of the n-region, the passivation quality of the n-region can be guaranteed without affecting the transport of electron carriers. That is to say, in this embodiment, through such differentiated design, the passivation effect of the n-region can be guaranteed while improving the transport efficiency of hole carriers in the p-region.

[0098] In some embodiments, the isolation layer 20 may also be doped with a third group element and / or a fifth group element. In such cases, the doping concentration of the third group element in the isolation layer 20 is less than the doping concentration of the third group element in the first doped polysilicon layer 40, and the doping concentration of the fifth group element in the isolation layer 20 is less than the doping concentration of the fifth group element in the second doped polysilicon layer 60.

[0099] Thus, by employing low-concentration doping of Group 3 and / or Group 5 elements in the isolation layer 20, effective surface field passivation and interfacial recombination can be achieved while ensuring electrical isolation performance. Furthermore, by introducing a low-concentration doped isolation layer 20, the field passivation effect can be further improved compared to using undoped intrinsic parts. Simultaneously, the lower doping concentration in the isolation layer 20 effectively reduces parasitic absorption of light from the back surface 12, improving the bifaciality.

[0100] Specifically, the isolation layer 20, due to its low-concentration doping, can form a built-in electric field on its surface, effectively repelling or attracting charge carriers, reducing the surface recombination rate, and especially improving performance under low irradiation. Moreover, the low-concentration doping can adjust the Fermi level position at the tunneling interface between the first dielectric layer 30 and the silicon substrate 10.

[0101] In particular, when the isolation layer 20 is simultaneously doped with both Group 3 and Group 5 elements, the net doping concentration and Fermi level position can be more precisely and stably controlled through the compensation doping effect. This not only more effectively suppresses the capture of charge carriers by interface defects and significantly reduces interface recombination, but also improves material quality due to the partial offsetting effect of the two doping elements on lattice stress, thereby further enhancing the passivation effect and the robustness of device performance.

[0102] Specifically, when the isolation layer 20 is simultaneously doped with both Group 5 and Group 3 elements, it provides better field passivation, and the doping of Group 5 elements achieves a better edge recombination reduction effect. Specifically, when the isolation layer 20 is doped with Group 5 elements (i.e., n-type), the Fermi level is raised in the conduction band direction, resulting in a high electron concentration at the interface, with most interface defect states being filled by electrons. Since these defects have a slow hole-capturing rate for the captured electrons, recombination channels through interface defects are suppressed. This is the physical reason for the superior effect of n-type doping. Group 3 elements can achieve co-doping or compensating doping of both. By simultaneously incorporating Group 5 and Group 3 elements, the net doping concentration and Fermi level position can be more finely adjusted, achieving better interface passivation and electrical properties, which is particularly useful when precise control of the absolute doping concentration is required.

[0103] In some embodiments, the width (i.e., the length dimension in the first direction) of the isolation layer 20 can be 5μm-700μm, for example, 5μm, 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 150μm, 200μm, 250μm, 300μm, 400μm, 500μm, 600μm, 700μm, or other values ​​between 5μm and 700μm. This configuration effectively ensures the electrical isolation performance of the isolation layer 20.

[0104] It should be noted that the width of the isolation layer 20 refers to the width at any position of the isolation layer 20. The width at different positions of the isolation layer 20 can be uniform and the same, or it can be different. There is no specific restriction here. That is, the width of the isolation layer 20 at any position is within the range of 5μm-700μm.

[0105] In some embodiments, the width of the isolation layer 20 is preferably 100μm-500μm, such as 100μm, 150μm, 200μm, 250μm, 300μm, 400μm, or 500μm. This setting allows the isolation performance of the isolation layer 20 to reach its optimal level, while also preventing the width of the isolation layer 20 from being too large, which would result in the width of the first doped polysilicon layer 40 and the second doped polysilicon layer 60 being too narrow and thus affecting the carrier collection efficiency.

[0106] Please see Figure 4 In some embodiments, the isolation layer 20 includes a middle portion 21, a first edge portion 22 and a second edge portion 23, the first edge portion 22 being located between the middle portion 21 and the second portion 32, the second portion 32 extending to the side surface of the first edge portion 22 near the first recessed area 121, and the second edge portion 23 being located between the middle portion 21 and the fourth portion 52, the fourth portion 52 extending to the side surface of the second edge portion 23 facing the second recessed area 122. Both the first doped polysilicon layer 40 and the first edge portion 22 are doped with a third group element, and the doping concentration of the third group element in the first edge portion 22 is less than the doping concentration of the third group element in the first doped polysilicon layer 40. Both the second doped polysilicon layer 60 and the second edge portion 23 are doped with a fifth group element, and the doping concentration of the fifth group element in the second edge portion 23 is less than the doping concentration of the fifth group element in the second doped polysilicon layer 60. The doping concentration of the third group element in the middle part 21 is less than that of the third group element in the first edge part 22, and the doping concentration of the fifth group element in the middle part 21 is less than that of the fifth group element in the second edge part 23.

[0107] Thus, by setting the doping concentration of the Group 3 elements in the first edge portion 22 to be relatively high but lower than the doping concentration in the first doped polysilicon layer 40, and setting the doping concentration of the Group 5 elements in the second edge portion 23 to be relatively high but lower than the doping concentration in the second doped polysilicon layer 60, the passivation effect of the isolation layer 20 can be improved, thereby increasing the efficiency of the battery. Conversely, by setting the doping concentration of the Group 3 and Group 5 elements in the middle portion 21 to be relatively low or even excluding them, the electrical isolation effect of the middle portion 21 can be better, thereby reducing recombination. In other words, this configuration effectively ensures the electrical isolation effect of the isolation layer 20 while improving the passivation effect.

[0108] In some embodiments, the intermediate portion 21 does not contain third-group and fifth-group elements. This allows for better electrical isolation of the intermediate portion 21.

[0109] In some embodiments, the doping concentrations of both the Group III and Group V elements in the intermediate portion 21 are less than 5E17 / cm². 3 For example, 1E13 / cm 3 5E13 / cm 3 5E14 / cm 3 1E15 / cm 3 5E15 / cm 3 1E16 / cm 3 5E16 / cm 3 1E17 / cm 3 1.5E17 / cm 3 2E17 / cm 3 2.5E17 / cm 3 3E17 / cm 3 4.5E17 / cm 3 4.8E17 / cm 3 4.9E17 / cm 3 .

[0110] In some embodiments, the doping concentration of the third group element in the intermediate portion 21 is less than or equal to 0.01 times that of the third group element in the first doped polysilicon layer 40, such as 0.01 times, 0.005 times, 0.003 times, 0.002 times, 0.001 times, or other values ​​less than 0.01, and / or, the doping concentration of the fifth group element in the intermediate portion 21 is less than or equal to 0.01 times that of the fifth group element in the second doped polysilicon layer 60, such as 0.01 times, 0.005 times, 0.003 times, 0.002 times, 0.001 times, or other values ​​less than 0.01.

[0111] Thus, by setting the doping concentration of the doped element in the intermediate portion 21 to at least 0.01 times that of the doped element in the first doped polysilicon layer 40 and the second doped polysilicon layer 60, the isolation performance of the isolation portion 40 can be further improved.

[0112] It should be noted that in this paper, the doping concentration of Group 3 and Group 5 elements can be obtained by ECV testing. The doping concentration of the region to be measured is tested by ECV testing to obtain a doping concentration curve of concentration and depth. By analyzing the doping concentration curve, the doping concentration of the corresponding position in the corresponding region can be obtained.

[0113] Thus, by specifically optimizing the doping concentration of Group 3 and Group 5 elements in the intermediate part 21, and setting the doping concentration of the doped elements in the intermediate part 21 to be low enough, the passivation effect of the region below the intermediate part 21 can be improved while ensuring the electrical isolation effect of the intermediate part 21. In other words, through such specific optimization design, the relationship between the electrical isolation effect and the passivation effect of the region below the intermediate part 21 can be balanced, thereby improving the passivation effect of the battery while ensuring the electrical isolation effect, and thus ensuring the efficiency of the battery.

[0114] Furthermore, in such an embodiment, when the intermediate portion 21 contains a third group element, the doping concentration of the third group element in the intermediate portion 21 is preferably less than 1E14 / cm³. 3 When the intermediate portion 21 contains a Group 5 element, the doping concentration of the Group 5 element in the intermediate portion 21 is preferably less than 1E14 / cm. 3 .

[0115] In some embodiments, the doping concentration of the third group element in the first doped polysilicon layer 40 is greater than 10 times the doping concentration of the third group element per unit volume in the first edge portion 22, and the doping concentration of the fifth group element per unit volume in the second doped polysilicon layer 60 is greater than 10 times the doping concentration of the fifth group element in the second edge portion 23.

[0116] With this configuration, a concentration difference of more than 10 times can create a sufficiently high carrier concentration gradient and significant band bending between the isolation layer 20 and the first doped polysilicon layer 40 and the second doped polysilicon layer 60. This is equivalent to establishing a controllable potential barrier between the first doped polysilicon layer 40 and the second doped polysilicon layer 60, which can effectively block the direct diffusion and recombination of majority carriers, achieving more reliable electrical isolation than simply having a "low concentration". In addition, the isolation layer 20 has a substantially low doping level, which enables it to effectively form field passivation, but is far from reaching the level that would form a "pn-like junction" with the highly doped region or cause parasitic leakage.

[0117] In some embodiments, the doping concentration of the third group element in the first edge portion 22 gradually decreases in the direction away from the first recessed region 121. In some possible embodiments, the doping concentration of the third group element in the first edge portion 22 may exhibit a continuously decreasing trend.

[0118] This configuration optimizes carrier transport and recombination, effectively suppressing the recombination rate between the isolation layer 20 and the first doped polysilicon layer 40.

[0119] In some embodiments, the doping concentration of the Group 5 element in the second edge portion 23 gradually decreases in the direction away from the second recessed region 122. In some possible embodiments, the doping concentration of the Group 5 element in the second edge portion 23 may exhibit a continuously decreasing trend.

[0120] This configuration optimizes carrier transport and recombination, effectively suppressing the recombination rate between the isolation layer 20 and the second doped polysilicon layer 60.

[0121] Specifically, in some embodiments, the doping concentration of the third group element in the first edge portion 22 gradually decreases in the direction away from the first recessed region 121, and the doping concentration of the fifth group element in the second edge portion 23 gradually decreases in the direction away from the second recessed region 122.

[0122] In some embodiments, the width of the first edge portion 22 (i.e., the length dimension in the first direction) may be 1μm-10μm, such as 1μm, 2μm, 4μm, 6μm, 8μm, 10μm or other values ​​between 1μm and 10μm, and no specific limitation is made here.

[0123] The width (i.e. the length dimension in the first direction) of the second edge portion 23 can be 1μm-10μm, such as 1μm, 2μm, 4μm, 6μm, 8μm, 10μm or other values ​​between 1μm and 10μm, and is not limited here.

[0124] The width of the intermediate portion 21 (i.e., the length dimension in the first direction) can be 60μm-600μm, such as 60μm, 100μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, 450μm, 500μm, 550μm, 600μm or other values ​​between 60μm and 600μm, and is not limited here.

[0125] Thus, by specifically optimizing the widths of the middle portion 21, the first edge portion 22, and the second edge portion 23, it is possible to effectively avoid the poor passivation effect caused by the first edge portion 22 and the second edge portion 23 being too short, and also to avoid the poor electrical isolation effect caused by the first edge portion 22 and the second edge portion 23 being too long and the middle portion 21 being too narrow. Simultaneously, it is also possible to avoid the passivation effect being too wide. In other words, this balances the relationship between the passivation effect and the electrical isolation effect, effectively ensuring the electrical isolation effect of the isolation layer 20 while guaranteeing the passivation effect.

[0126] In some embodiments, the width of the first edge portion 22 is greater than the width of the second edge portion 23.

[0127] Thus, by setting the width of the first edge portion 22 to be wider, the passivation effect of the area below the isolation layer 20 can be further improved.

[0128] In some embodiments, the width of the second edge portion 23 may be 0.4 to 0.8 times the width of the first edge portion 22, such as 0.4 times, 0.45 times, 0.5 times, 0.55 times, 0.6 times, 0.65 times, 0.7 times, 0.75 times, 0.8 times, or other values ​​between 0.4 and 0.8, and no specific limitation is made here.

[0129] In this way, by optimizing the width of the first edge portion 22 and the second edge portion 23, the passivation effect of the battery can be effectively improved.

[0130] In some embodiments, the width of the middle portion 21 is greater than the width of the first edge portion 22, and the width of the middle portion 21 is greater than the width of the second edge portion 23.

[0131] Therefore, by making the width of the middle part 21 wider, the electrical isolation effect of the battery can be further improved.

[0132] In some embodiments, the ratio between the width of the first edge portion 22 and the overall width of the isolation layer 20 is less than 0.2, for example, 0.18, 0.15, 0.1, or 0.05; the ratio between the width of the second edge portion 23 and the overall width of the isolation layer is less than 0.2, for example, 0.18, 0.15, 0.1, or 0.05; and the ratio between the width of the middle portion 21 and the overall width of the isolation layer is greater than 0.6, for example, 0.61, 0.65, 0.7, 0.8, 0.85, or 0.9.

[0133] Thus, by specifically optimizing the width ratio among the middle portion 21, the first edge portion 22, and the second edge portion 23, the passivation effect of the area below the isolation layer 20 can be effectively improved while ensuring the electrical isolation effect of the isolation layer 20.

[0134] In some embodiments, the isolation layer 20 is doped with at least one of oxygen, nitrogen and carbon. The oxygen doping concentration in the isolation layer 20 is 1E16 / cm³. 3 -2E22 / cm 3 For example, 1E16 / cm 3 5E16 / cm 3 1E17 / cm 3 5E17 / cm 3 1E18 / cm 3 1E19 / cm 3 1E20 / cm 3 1E21 / cm 3 1E22 / cm 3 ; and / or, the nitrogen doping concentration in the isolation layer 20 is 1E16 / cm³. 3 -2E22 / cm 3 For example, 1E16 / cm 3 5E16 / cm 3 E17 / cm 3 5E17 / cm 3 1E18 / cm 3 1E19 / cm 3 1E20 / cm 3 1E21 / cm 3 1E22 / cm 3 And / or, the carbon doping concentration in the isolation layer 20 is 1E16 / cm³. 3 -2E22 / cm 3 For example, 1E16 / cm 3 5E16 / cm 3 1E17 / cm 3 5E17 / cm 3 1E18 / cm 3 1E19 / cm 3 1E20 / cm 3 1E21 / cm 3 1E22 / cm 3 .

[0135] In other words, when oxygen is doped into the isolation layer 20, the oxygen doping concentration is 1E16 / cm³. 3 -2E22 / cm 3 When nitrogen is doped in the isolation layer 20, the nitrogen doping concentration is 1E16 / cm³. 3 -2E22 / cm 3When carbon is doped in the isolation layer 20, the carbon doping concentration is 1E16 / cm³. 3 -2E22 / cm 3 .

[0136] Thus, by doping the separator 20 with at least one of oxygen, nitrogen, and carbon elements and by specifically optimizing the content of oxygen, nitrogen, and carbon elements, the electrical isolation effect of the separator 20 can be effectively improved, further reducing battery recombination and improving battery efficiency.

[0137] Specifically, in such an embodiment, the isolation layer 20 may be doped with only oxygen, and the oxygen doping concentration may be controlled at 1E16 / cm³. 3 -2E22 / cm 3 Within this range, the isolation layer 20 can be doped with only nitrogen, and the nitrogen doping concentration can be controlled at 1E16 / cm. 3 -2E22 / cm 3 Within this range, the isolation layer 20 can also be doped with only carbon, and the nitrogen doping concentration can be controlled at 1E16 / cm. 3 -2E22 / cm 3 Within this range. Of course, in some embodiments, the isolation layer 20 may also be doped with two or three of the elements of oxygen, nitrogen and carbon, which is not limited here.

[0138] Please see Figure 5 and Figure 6 In some embodiments, the first doped polysilicon layer 40 may further include a third extension 43 extending from the first extension 42 to a portion of the surface of the isolation layer 20 away from the silicon substrate 10, and a first insulating layer 120 is provided between the third extension 43 and the isolation layer 20.

[0139] Thus, by setting the third extension 43, the passivation effect of the protruding area 123 can be further improved, while the setting of the first insulating layer 120 can achieve insulation isolation between the third extension 43 and the insulating layer 20, reducing the risk of recombination and leakage.

[0140] Specifically, the first insulating layer 120 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other film layers, and no specific limitation is made here.

[0141] In some embodiments, the thickness of the first insulating layer 120 is greater than the thickness of the first portion 31 and is 200 to 10,000 times the thickness of the first portion 31, such as 200, 300, 400, 500, 600, 700, 800, 900, 1,000, 3,000, 5,000, 8,000, 9,000, 10,000, or other values ​​between 2,000 and 10,000.

[0142] Thus, by setting the thickness of the first insulating layer 120 to be 200-10000 times the thickness of the first portion 31, the first insulating layer 120 can have sufficient thickness to ensure its insulation performance, while also avoiding excessive cost due to excessive thickness of the first insulating layer 120.

[0143] In some embodiments, the width of the third extension 43 may be 1μm-10μm, such as 1μm, 2μm, 4μm, 6μm, 8μm, 10μm or other values ​​between 1μm and 10μm, and is not limited here.

[0144] Thus, by setting the width of the third extension 43 within this reasonable range, it is possible to avoid the parasitic absorption of the protruding area 123 being too large, which would lead to a significant decrease in the bifaciality, and it is also possible to avoid the passivation effect being poorly improved if the width of the third extension 43 is too small.

[0145] In some embodiments, the ratio between the width of the portion of the isolation layer 20 covered by the third extension 43 and the overall width of the isolation layer 20 is less than or equal to 0.2, for example, 0.18, 0.15, 0.1, or 0.05.

[0146] In this way, the area covered by the third extension 43 of the isolation layer 20 times can be controlled within a small range, thereby reducing parasitic absorption at the protrusion 123 and improving the bifaciality.

[0147] Please see Figure 5 and Figure 6 In some embodiments, the second doped polysilicon layer 60 further includes a fourth extension 63 extending from the second extension 62 to a portion of the surface of the isolation layer 20 away from the silicon substrate 10, and a second insulating layer 130 is provided between the fourth extension 63 and the isolation layer 20.

[0148] Thus, by providing the fourth extension 63, the passivation effect of the protruding area 123 can be further improved, while the second insulating layer 130 can achieve insulation isolation between the fourth extension 63 and the insulating layer 20, reducing the risk of bonding and leakage.

[0149] Specifically, the second insulating layer 130 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other film layers, and no specific limitation is made here.

[0150] In some embodiments, the thickness of the second insulating layer 130 is greater than the thickness of the third portion 51 and is 200 to 10,000 times the thickness of the third portion 51, for example, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 3000, 5000, 8000, 9000, 10000, or other values ​​between 2,000 and 10,000.

[0151] Thus, by setting the thickness of the second insulating layer 130 to be 200-10000 times the thickness of the third part 51, the second insulating layer 130 can have sufficient thickness to ensure its insulation performance, while also avoiding excessive cost due to excessive thickness of the second insulating layer 130.

[0152] In some embodiments, the width of the fourth extension 63 may be 1μm-10μm, such as 1μm, 2μm, 4μm, 6μm, 8μm, 10μm or other values ​​between 1μm and 10μm, and is not limited here.

[0153] Thus, by setting the width of the fourth extension 63 within this reasonable range, it is possible to avoid the parasitic absorption of the protruding area 123 being too large, which would lead to a significant decrease in the bifaciality, and it is also possible to avoid the passivation effect being poorly improved if the width of the fourth extension 63 is too small.

[0154] In some embodiments, the ratio between the width of the portion of the isolation layer 20 covered by the fourth extension 63 and the overall width of the isolation layer 20 is less than or equal to 0.2, for example, 0.18, 0.15, 0.1, or 0.05.

[0155] In this way, the area covered by the fourth extension 63 of the isolation layer 20 times can be controlled within a small range, thereby reducing parasitic absorption at the protrusion 123 and improving the bifaciality.

[0156] Please see Figure 6In some embodiments, the back contact battery 100 further includes a third doped polysilicon layer 140 and a third insulating layer 150 located between the fourth extension 63 and the second insulating layer 130. The polarity of the third doped polysilicon layer 140 is the same as that of the first doped polysilicon layer 40. The third doped polysilicon layer 140 is stacked on the second insulating layer 130, and the third insulating layer 150 is stacked on the third doped polysilicon layer 140. The fourth extension 63 is stacked on the third insulating layer 150, and the fourth portion 52 extends to the side surface of the third doped polysilicon layer 140 facing the second recessed region 122.

[0157] Thus, by introducing a third doped polysilicon layer 140 and a third insulating layer 150 between the fourth extension 63 and the second insulating layer 130, the passivation effect of the protrusion region 123 can be further improved. The setting of the third insulating layer 150 can achieve insulation isolation between the surface of the third doped polysilicon layer 140 away from the silicon substrate 10 and the fourth extension 63. The extension of the fourth portion 52 can achieve insulation isolation between the side of the third doped polysilicon layer 140 and the second extension 62, reducing the risk of leakage.

[0158] In such an embodiment, the third insulating layer 150 may also be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other film layers, and no specific limitation is made here.

[0159] In some embodiments, the thickness of the third insulating layer 150 is greater than the thickness of the first portion 31 and is 200 to 10,000 times the thickness of the first portion 31, for example, 200, 300, 400, 500, 600, 700, 800, 900, 1,000, 3,000, 5,000, 8,000, 9,000, 10,000, or other values ​​between 2,000 and 10,000.

[0160] Thus, by setting the thickness of the third insulating layer 150 to be 200-10000 times the thickness of the first part 31, the third insulating layer 150 can have sufficient thickness to ensure its insulation performance, while also avoiding excessive cost due to excessive thickness of the third insulating layer 150.

[0161] In the description of this specification, the references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0162] Furthermore, the above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate having opposing front and back sides, the back side including a protruding region and a first recessed region and a second recessed region located on both sides of the protruding region and adjacent to the protruding region, the surface of the first recessed region being recessed into the silicon substrate relative to the surface of the protruding region, and the surface of the second recessed region also being recessed into the silicon substrate relative to the surface of the protruding region, the first recessed region including a first bottom surface and a first side surface connected to the protruding region, and the second recessed region including a second bottom surface and a second side surface connected to the protruding region; An isolation layer is disposed on the protruding area; A first dielectric layer, the first dielectric layer comprising a first portion stacked on the first bottom surface and a second portion extending from the first portion to the first side surface and the side surface of the insulating layer facing the first recessed area; A first doped polysilicon layer, the first doped polysilicon layer including a first body portion stacked on the first portion and a first extension portion stacked on the second portion, the first extension portion being separated from the isolation layer by the second portion; The second dielectric layer includes a third portion stacked on the second bottom surface and a fourth portion extending from the third portion to the second side surface and the side surface of the insulating layer facing the second recessed area. The second doped polysilicon layer includes a second body portion stacked on the third portion and a second extension portion stacked on the fourth portion, wherein the second extension portion is separated from the isolation layer by the fourth portion. and A back passivation layer is stacked on the side of the first doped polysilicon layer, the second doped polysilicon layer, and the isolation layer that is away from the silicon substrate.

2. The back contact battery according to claim 1, characterized in that, The depth of the first recessed region recessed into the silicon substrate relative to the protruding region is 2μm-20μm; The second recessed region is recessed into the silicon substrate to a depth of 2μm-20μm relative to the protruding region.

3. The back contact battery according to claim 1, characterized in that, The first doped polysilicon layer is a p-type doped polysilicon layer, and the second doped polysilicon layer is an n-type doped polysilicon layer; The depth of the first recessed region recessed into the silicon substrate relative to the protruding region is greater than the depth of the second recessed region recessed into the silicon substrate relative to the protruding region.

4. The back contact battery according to claim 1, characterized in that, The thickness of the second part is different from the thickness of the first part; and / or The thickness of the fourth part is different from the thickness of the third part.

5. The back contact battery according to claim 4, characterized in that, The thickness of the second part is greater than the thickness of the first part; and / or The thickness of the fourth part is greater than the thickness of the third part.

6. The back contact battery according to claim 5, characterized in that, The thickness of the second part is 1.2 to 5 times the thickness of the first part; and / or The thickness of the fourth part is 1.2 to 5 times the thickness of the third part.

7. The back contact battery according to claim 5, characterized in that, The thickness of the first portion is 0.5nm-4nm, and the thickness of the second portion is 0.6nm-20nm; and / or The thickness of the third part is 0.5nm-4nm, and the thickness of the fourth part is 0.6nm-20nm.

8. The back contact battery according to claim 1, characterized in that, The back contact battery also includes a third dielectric layer disposed between the isolation layer and the silicon substrate.

9. The back contact battery according to claim 8, characterized in that, The material of the third dielectric layer is different from that of the first dielectric layer and the second dielectric layer.

10. The back contact battery according to claim 9, characterized in that, The first dielectric layer and the second dielectric layer are both silicon oxide layers, and the third dielectric layer is a silicon nitride layer.

11. The back contact battery according to claim 1, characterized in that, The first doped polysilicon layer is a p-type doped polysilicon layer, the second doped polysilicon layer is an n-type doped polysilicon layer, and a plurality of first holes are formed on the first portion; Wherein, the third part does not have holes; or The third part has a number of second holes, and the number of second holes is less than the number of first holes.

12. The back contact battery according to claim 1, characterized in that, The isolation layer includes a middle portion, a first edge portion, and a second edge portion. The first edge portion is located between the middle portion and the second portion. The second portion extends to the side surface of the first edge portion near the first recessed area. The second edge portion is located between the middle portion and the fourth portion. The fourth portion extends to the side surface of the second edge portion toward the second recessed area. Both the first doped polysilicon layer and the first edge portion are doped with a third group element, and the doping concentration of the third group element in the first edge portion is less than the doping concentration of the third group element in the first doped polysilicon layer. Both the second doped polysilicon layer and the second edge portion are doped with a fifth group element, and the doping concentration of the fifth group element in the second edge portion is less than the doping concentration of the fifth group element in the second doped polysilicon layer. Wherein, the intermediate part does not contain elements of the third main group and the fifth main group; or The doping concentrations of Group 3 elements and Group 5 elements in the intermediate portion are both less than 5E17 / cm³. 3 .

13. The back contact battery according to claim 12, characterized in that, In the direction away from the first recessed region, the doping concentration of the third group element in the first edge portion gradually decreases; and / or, in the direction away from the second recessed region, the doping concentration of the fifth group element in the second edge portion gradually decreases.

14. The back contact battery according to claim 12, characterized in that, The width of the first edge portion is greater than the width of the second edge portion.

15. The back contact battery according to claim 14, characterized in that, The width of the second edge portion is 0.4 to 0.8 times the width of the first edge portion.

16. The back contact battery according to claim 12, characterized in that, The width of the middle portion is greater than the width of the first edge portion, and the width of the middle portion is greater than the width of the second edge portion.

17. The back contact battery according to claim 12, characterized in that, The width of the first edge portion is 1μm-10μm, the width of the second edge portion is 1μm-10μm, and the width of the middle portion is 60μm-600μm.

18. The back contact battery according to claim 12, characterized in that, The ratio between the width of the first edge portion and the overall width of the isolation layer is less than or equal to 0.2; The ratio between the width of the second edge portion and the overall width of the isolation layer is less than or equal to 0.2; The ratio between the width of the middle section and the overall width of the isolation layer is greater than or equal to 0.

6.

19. The back contact battery according to claim 1, characterized in that, The isolation layer is doped with at least one of oxygen, nitrogen and carbon elements; The oxygen doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 And / or the nitrogen doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 And / or the carbon doping concentration in the isolation layer is 1E16 / cm³. 3 -2E22 / cm 3 .

20. The back contact battery according to claim 1, characterized in that, The width of the isolation layer is 50μm-700μm.

21. The back contact battery according to claim 1, characterized in that, The first doped polysilicon layer further includes a third extension extending from the first extension to a portion of the surface of the isolation layer away from the silicon substrate, wherein a first insulating layer is provided between the third extension and the isolation layer.

22. The back contact battery according to claim 21, characterized in that, The thickness of the first insulating layer is greater than the thickness of the first portion and is 200 to 10,000 times the thickness of the first portion.

23. The back contact battery according to claim 21, characterized in that, The width of the third extension is 1μm-10μm.

24. The back contact battery according to claim 21, characterized in that, The ratio between the width of the portion of the isolation layer covered by the third extension and the overall width of the isolation layer is less than or equal to 0.

2.

25. The back contact battery according to claim 1, characterized in that, The second doped polysilicon layer further includes a fourth extension extending from the second extension to a portion of the surface of the isolation layer away from the silicon substrate, wherein a second insulating layer is provided between the fourth extension and the isolation layer.

26. The back contact battery according to claim 25, characterized in that, The thickness of the second insulating layer is greater than the thickness of the third part and is 200 to 10,000 times the thickness of the third part.

27. The back contact battery according to claim 25, characterized in that, The width of the fourth extension is 1μm-10μm.

28. The back contact battery according to claim 25, characterized in that, The ratio between the width of the portion of the isolation layer covered by the fourth extension and the overall width of the isolation layer is less than or equal to 0.

2.

29. The back contact battery according to claim 25, characterized in that, The back contact battery further includes a third doped polysilicon layer and a third insulating layer located between the fourth extension and the second insulating layer. The polarity of the third doped polysilicon layer is the same as that of the first doped polysilicon layer. The third doped polysilicon layer is stacked on the second insulating layer. The third insulating layer is stacked on the third doped polysilicon layer. The fourth extension is stacked on the third insulating layer. The fourth extension extends to the side surface of the third doped polysilicon layer facing the second recessed region.

30. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1-29.

31. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 30.

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