Active region pattern, storage module and preparation method thereof
By designing a corresponding pattern between the active region and the conductive plug pattern, the problems of high cost and security risks in existing chip key preparation are solved, achieving low-cost and uniquely uncontrollable key generation, thus improving chip security.
Patent Information
- Application Number
- CN202610536259.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-21
- Publication Date
- 2026-07-14
AI Technical Summary
Existing chip key preparation schemes increase manufacturing and application costs and pose security risks. Furthermore, the one-time physical design of chip identity codes increases circuit design and structural costs.
The layout design employs active area graphics, including key active area and storage active area graphic arrays, which correspond one-to-one with conductive plug graphics and are manufactured using the same layout, ensuring the uncontrollability of the contact method between the key active area and the conductive plug.
This reduces the cost of key preparation processes and improves chip security by enabling unique and uncontrollable key generation through the precision deviation of the processing equipment.
Smart Images
Figure CN122392583A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a layout of an active region pattern, a memory module, and a method for fabricating the same. Background Technology
[0002] Encryption technology generally involves two elements: an encryption algorithm and a key. The security of both the algorithm and the key is crucial to the security of the encryption. In many applications, such as radio frequency identification (RFID) and wireless sensor networks, a single chip needs to store a unique key that identifies the chip.
[0003] However, key preparation for existing chips typically includes the following methods: (1) Directly write the key into the chip's memory, but this approach not only increases the cost of manufacturing and application, but also increases the possibility of being attacked, affecting the security of chip applications.
[0004] (2) Chip identification codes are designed using one-time physical methods such as Fuse / OTP (One-Time Programmable). However, designing chips using one-time physical methods requires special block design circuits, which increases the design cost and structural cost of the circuit. Summary of the Invention
[0005] To address the aforementioned technical problems, this invention provides a layout of an active region graphic and a storage module, as well as a method for preparing the same, so as to form a unique and uncontrollable key for the storage module at a low cost.
[0006] According to a first aspect of the present invention, a layout of an active region pattern is provided, corresponding to a layout of a conductive plug, wherein the layout of the conductive plug includes a plurality of arrays of conductive plug patterns spaced apart along a first direction, each of the conductive plug pattern arrays includes a plurality of sub-arrays of conductive plug patterns spaced apart along a second direction, and each of the conductive plug pattern sub-arrays includes two conductive plug patterns. The layout of the active region graphic includes: Several rows of active region pattern arrays are spaced apart along a first direction. Each active region pattern array includes several active region patterns spaced apart along a second direction. At least one of the active region pattern arrays includes multiple key active region patterns and multiple storage active region patterns. The first direction and the second direction are perpendicular to each other. The conductive plug pattern subarray corresponds one-to-one with the active region pattern. Each storage active region pattern is in contact with two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is in contact with two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is in contact with one conductive plug pattern in the corresponding conductive plug pattern subarray.
[0007] Optionally, the layout of the active region pattern also corresponds to the layout of the gate lines. The layout of the gate lines includes several rows of gate line pattern arrays arranged at intervals along the first direction. Each gate line pattern array includes two gate line patterns arranged at intervals along the first direction, and each gate line pattern is orthogonal to several storage active region patterns of the corresponding active region pattern array.
[0008] Optionally, the projections of several key active region patterns in the active region pattern array along the second direction are all located within the projection range of the storage active region pattern along the second direction.
[0009] Optionally, the width of the key active region pattern along the second direction is equal to 1 / 4 to 1 / 3 of the width of the storage active region pattern along the second direction.
[0010] Optionally, at least one of the active region patterns in the active region pattern array is a storage active region pattern.
[0011] According to a second aspect of the present invention, a storage module is provided, the storage module comprising: A plurality of rows of active region arrays are arranged at intervals along a first direction on a substrate. Each active region array includes a plurality of active regions arranged at intervals along a second direction. At least one of the active region arrays includes a plurality of key active regions and a plurality of storage active regions. The first direction and the second direction are perpendicular to each other. A plurality of conductive plug arrays are arranged at intervals along a first direction on a plurality of active region arrays. Each conductive plug array includes a plurality of conductive plug sub-arrays arranged at intervals along a second direction. The plurality of conductive plug sub-arrays correspond one-to-one with a plurality of active region patterns. Each conductive plug pattern sub-array includes two conductive plug patterns. All storage active region patterns are in contact with the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is in contact with the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is in contact with one conductive plug pattern in the corresponding conductive plug pattern sub-array.
[0012] Optionally, a plurality of rows of gate line arrays are arranged at intervals along the first direction on a plurality of rows of active region arrays, each of the gate line arrays comprising two gate line structures arranged at intervals along the first direction, and each of the gate line structures being orthogonal to a plurality of storage active regions of the corresponding active region array.
[0013] Optionally, the projection of the key active region pattern along the second direction is located within the projection range of the storage active region pattern along the second direction.
[0014] Optionally, the width of the key active region along the second direction is between 1 / 4 and 1 / 3 of the width of the storage active region along the second direction.
[0015] According to a third aspect of the present invention, a method for manufacturing a storage module is provided, the method comprising: The layout of the active region pattern according to the first aspect and optional solution of the present invention forms a plurality of rows of active region arrays spaced apart along a first direction on a substrate, each of the active region arrays includes a plurality of active regions spaced apart along a second direction, and at least one of the active region arrays includes a plurality of key active regions and a plurality of storage active regions, wherein the first direction and the second direction are perpendicular to each other. After forming several rows of active region arrays, several rows of gate line arrays are formed on the several rows of active region arrays based on the gate line layout. Each gate line array includes two gate line structures arranged at intervals along the first direction, and each gate line structure is orthogonal to several storage active regions of the corresponding active region array. After forming several rows of gate line arrays, based on the layout of the conductive plugs described in the first aspect and optional embodiments of the present invention, several rows of conductive plug arrays spaced apart along the first direction are formed on several rows of active region arrays. Each conductive plug array includes several conductive plug sub-arrays spaced apart along the second direction. The several conductive plug sub-arrays correspond one-to-one with several active region patterns. Each conductive plug pattern sub-array includes two conductive plug patterns. All storage active region patterns are in contact with the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is in contact with the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern sub-array. At least one key active region pattern is in contact with one conductive plug pattern in the corresponding conductive plug pattern sub-array.
[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the active region pattern layout provided by the technical solution of the present invention, the active region pattern layout comprises several rows of active region pattern arrays spaced apart along a first direction. At least one of the active region pattern arrays includes multiple key active region patterns and multiple storage active region patterns. The first direction and the second direction are perpendicular to each other. Furthermore, since the active region pattern layout corresponds to the conductive plug layout, the conductive plug layout includes several rows of conductive plug pattern arrays spaced apart along the first direction. Each conductive plug pattern array includes several conductive plug pattern sub-arrays spaced apart along a second direction. Each conductive plug pattern sub-array includes two conductive plug patterns. The conductive plug pattern sub-array corresponds one-to-one with the active region pattern, and both conductive plug patterns are in contact with the corresponding storage active region pattern. Therefore, the semiconductor structure fabricated based on the mask of the above layout constitutes a memory module.
[0017] Since at least one of the key active region patterns is in contact with two of the conductive plug patterns in the corresponding conductive plug pattern subarray, at least one of the key active region patterns is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern subarray, and at least one of the key active region patterns is in contact with one of the conductive plug patterns in the corresponding conductive plug pattern subarray, theoretically, among the several key active regions made based on the layout of the active region pattern, it has been determined that some key active regions can simultaneously contact two first conductive plugs made based on the layout of the conductive plugs, some key active regions cannot contact two first conductive plugs, and another part of key active regions cannot simultaneously contact two first conductive plugs.
[0018] However, due to the mismatch between the application node of the processing equipment and the current key active area process node, the actual length of the key active area along the first direction will deviate from the designed length during the fabrication of the storage module. This may cause the key active area that could previously contact the conductive plug to become uncontactable, or it may cause the key active area that could not previously contact the conductive plug to become contactable. This makes the contact between the key active area and the conductive plug uncontrollable, resulting in a unique but uncontrollable key. Furthermore, since the key active area and the storage active area are fabricated simultaneously using the same layout, no additional fabrication process is required, thus greatly reducing the process cost of key fabrication. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 A top view combining the layout of the active region pattern, the layout of the conductive plug, and the layout of the gate line provided for embodiments of the present invention; Figure 2 A flowchart illustrating a method for preparing a storage module according to an embodiment of the present invention; Figure 3 A top view of a storage module provided for an embodiment of the present invention.
[0021] Explanation of reference numerals in the attached figures: 10-Store active area graphics; 11-Graphics of the key active region; 20-Conductive plug pattern; 30 - First grid line pattern; 31 - Second grid line pattern; 40 - Active storage area; 41-Key active area; 50-Conductive plug; 60 - First gate line structure; 61 - Second gate structure; X - First direction; Y - Second direction. Detailed Implementation
[0022] As described in the background section, key preparation for existing chips typically includes the following methods: (1) Directly write the key into the chip's memory, but this approach not only increases the cost of manufacturing and application, but also increases the possibility of being attacked, affecting the security of chip applications.
[0023] (2) Chip identification codes are designed using one-time physical methods such as Fuse / OTP (One-Time Programmable). However, designing chips using one-time physical methods requires special block design circuits, which increases the design cost and structural cost of the circuit.
[0024] In view of this, the technical solution of the present invention provides a new layout of active region patterns. The layout of the active region patterns comprises several rows of active region pattern arrays spaced apart along a first direction. At least one of the active region pattern arrays includes multiple key active region patterns and multiple storage active region patterns. The first direction and the second direction are perpendicular to each other. Furthermore, since the layout of the active region patterns corresponds to the layout of the conductive plugs, the layout of the conductive plugs includes several rows of conductive plug pattern arrays spaced apart along the first direction. Each conductive plug pattern array includes several conductive plug pattern sub-arrays spaced apart along a second direction. Each conductive plug pattern sub-array includes two conductive plug patterns. The conductive plug pattern sub-arrays correspond one-to-one with the active region patterns, and both conductive plug patterns are arranged to contact the corresponding storage active region pattern. Therefore, the semiconductor structure fabricated based on the mask of the above layout constitutes a memory module.
[0025] Since at least one of the key active region patterns is in contact with two of the conductive plug patterns in the corresponding conductive plug pattern subarray, at least one of the key active region patterns is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern subarray, and at least one of the key active region patterns is in contact with one of the conductive plug patterns in the corresponding conductive plug pattern subarray, theoretically, among the several key active regions made based on the layout of the active region pattern, it has been determined that some key active regions can simultaneously contact two first conductive plugs made based on the layout of the conductive plugs, some key active regions cannot contact two first conductive plugs, and another part of key active regions cannot simultaneously contact two first conductive plugs.
[0026] However, due to the mismatch between the application node of the processing equipment and the current key active area process node, the actual length of the key active area along the first direction will deviate from the designed length during the fabrication of the storage module. This may cause the key active area that could previously contact the conductive plug to become uncontactable, or it may cause the key active area that could not previously contact the conductive plug to become contactable. This makes the contact between the key active area and the conductive plug uncontrollable, resulting in a unique but uncontrollable key. Furthermore, since the key active area and the storage active area are fabricated simultaneously using the same layout, no additional fabrication process is required, thus greatly reducing the process cost of key fabrication.
[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0028] The terms “first,” “inner ring,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0029] The technical solution of the present invention will be described in detail below with reference to the embodiments in this example. These embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0030] Please refer to Figure 1 The layout of the active region pattern provided in this embodiment may include several rows of active region pattern arrays arranged at intervals along the first direction X. Each active region pattern array may include several active region patterns arranged at intervals along the second direction. The several rows of active region pattern arrays may include at least one row of first type active region pattern arrays. The first type of active region pattern array may include multiple key active region patterns 11 arranged at intervals along the second direction Y and multiple storage active region patterns 10 arranged at intervals along the second direction Y. The first direction X and the second direction Y are perpendicular to each other.
[0031] The layout of the active region pattern provided in this embodiment corresponds to the layout of the conductive plug. The layout of the conductive plug may include several rows of conductive plug pattern arrays arranged at intervals along the first direction X. Each row of conductive plug pattern arrays may include several conductive plug pattern sub-arrays arranged at intervals along the second direction Y. Each conductive plug pattern sub-array may include two conductive plug patterns 20.
[0032] In this embodiment, at least one row of first-type active region pattern arrays corresponds to a conductive plug pattern array, and multiple key active region patterns 11 and multiple storage active region patterns 10 in the first-type active region pattern array correspond one-to-one with several conductive plug pattern subarrays in the corresponding conductive plug pattern array.
[0033] In this embodiment, in the active storage region pattern 10 corresponding to the conductive plug pattern subarray, each active storage region pattern 10 is in contact with both conductive plug patterns 20 of the corresponding conductive plug pattern subarray.
[0034] In this embodiment, among the several key active region patterns 11 corresponding to the conductive plug pattern subarray, at least one key active region pattern 11 is in contact with two conductive plug patterns 20 in the corresponding conductive plug pattern subarray, at least one key active region pattern 11 is not in contact with either of the two conductive plug patterns 20 in the corresponding conductive plug pattern subarray, and at least one key active region pattern 11 is in contact with one conductive plug pattern 20 in the corresponding conductive plug pattern subarray.
[0035] Therefore, in the several key active regions made based on the layout of the active region pattern and the several conductive plug pattern subarrays made based on the layout of the conductive plug, it has been determined that some key active regions can contact the corresponding two first conductive plugs simultaneously, some key active regions cannot contact the corresponding two first conductive plugs, and another part of key active regions cannot contact the two first conductive plugs simultaneously. That is, the key active region only contacts one of the two first conductive plugs, while the other does not contact the other. So theoretically, when the storage module prepared based on the layout of the active region pattern and the layout of the conductive plug in this embodiment reads the information of the key active region, it will obtain a unique and definite key value. For example, the key active region that contacts the corresponding two first conductive plugs simultaneously is read as 11, the key active region that cannot contact either of the corresponding two first conductive plugs is read as 00, and the key active region that only contacts one of the two first conductive plugs is read as 10 or 01.
[0036] from Figure 1 It can be seen that the two conductive plug patterns 20 in the conductive plug pattern subarray are arranged along the first direction X. When the upper plug of the two first conductive plugs is in contact with the corresponding key active area, while the lower plug of the two first conductive plugs is not in contact with the corresponding key active area, the information of the key active area is read as 10.
[0037] When the upper plug and the corresponding active key area are not in contact, but the lower plug and the corresponding active key area are in contact, the information in the active key area is read as 01.
[0038] It should be noted that the direction from the upper plug to the lower plug is the first direction X.
[0039] In the array of several rows of active region patterns arranged at intervals along the first direction X, in addition to the first type of active region pattern array, a second type of active region pattern array may also be included. The second type of active region pattern array may include several storage active region patterns 10 arranged at intervals along the second direction Y.
[0040] In this embodiment, several conductive plug pattern arrays and several second-type active region pattern arrays correspond one-to-one, and several conductive plug pattern subarrays in each conductive plug pattern array correspond one-to-one with several storage active region patterns 10 in the corresponding second-type active region pattern array. Finally, it is set that the two conductive plug patterns 20 in each conductive plug pattern subarray are in contact with the corresponding storage active region pattern 10.
[0041] This can be understood as follows: apart from the first type of active area pattern array and conductive plug pattern array, the remaining active area pattern arrays and the remaining conductive plug pattern arrays are used to form conventional storage modules.
[0042] Please continue to refer to this. Figure 1 The layout of the active region pattern provided in this embodiment also corresponds to the layout of the gate lines. The layout of the gate lines may include several rows of gate line pattern arrays arranged at intervals along the first direction X. Among the several rows of gate line pattern arrays, there may be at least one row of first type gate line pattern arrays corresponding to the first type of active region pattern array. The first type of gate line pattern array may include two first gate line patterns 30 arranged at intervals along the first direction X, and both first gate line patterns 30 are orthogonal to the corresponding several storage active region patterns 10.
[0043] In addition, among the several rows of gate line pattern arrays arranged at intervals along the first direction X, besides the first type of gate line pattern array, there is also a second type of gate line pattern array. The several rows of the second type of gate line pattern arrays correspond one-to-one with the several rows of the second type of active region pattern arrays. Each row of the second type of gate line pattern array includes two second gate line patterns 31 arranged at intervals along the first direction X, and the two second gate line patterns 31 are orthogonal to the corresponding several storage active region patterns 10.
[0044] In a preferred embodiment, the projections of several key active region patterns in the active region pattern array along the second direction are all located within the projection range of the storage active region pattern along the second direction.
[0045] Furthermore, among the plurality of key active region patterns 11, the maximum length of the key active region pattern 11 along the first direction X can be set to be equal to the length of the storage active region pattern 10 along the first direction X, thereby ensuring that the longest key active region along the first direction X and the corresponding two first conductive plugs are in contact. The minimum length of the key active region pattern 11 along the first direction X can be set to be less than or equal to the interval between the two first gate line patterns 30 along the first direction X, thereby ensuring that the shortest key active region along the first direction X and the corresponding two first conductive plugs are not in contact.
[0046] In this embodiment, the remaining key active area patterns 11 are spaced apart along the first direction X between the maximum length and the minimum length. That is, the remaining key active area patterns 11 are spaced apart along the first direction X between the length of the storage active area pattern 10 along the first direction X and the spacing distance between the two first gate line patterns 30 along the first direction X, so that the prepared partial key active area can contact the corresponding two first conductive plugs, the prepared partial key active area only contacts one of the corresponding two first conductive plugs, and finally the prepared partial key active area does not contact the corresponding two first conductive plugs.
[0047] In this embodiment, the key active region pattern 11 can be evenly divided into multiple parts, such as 20 parts, along the first direction X from its maximum to minimum length. This division results in multiple key active region patterns 11 with successively decreasing lengths along the first direction X, which are then fabricated through a process to obtain multiple key active regions with successively decreasing lengths along the first direction X. Of course, the number of key active regions can be adjusted according to requirements and is not limited here.
[0048] In addition to the length setting, in this embodiment, the width of the key active area pattern 11 along the second direction Y is equal to 1 / 4 to 1 / 3 of the width of the storage active area pattern 10 along the second direction Y. Based on the above-mentioned length division of the key active area pattern 11 along the first direction X, the maximum to minimum width of the key active area pattern 11 along the second direction Y can also be evenly divided into multiple parts, such as 20 parts, so that the width of the multiple key active areas prepared by the process decreases sequentially along the second direction Y.
[0049] In this embodiment, the maximum width of the key active area pattern 11 along the second direction Y can be set to be equal to 1 / 3 of the width of the storage active area pattern 10 along the second direction Y, and the minimum width of the key active area pattern 11 along the second direction Y can be set to be equal to 1 / 4 of the width of the storage active area pattern 10 along the second direction Y.
[0050] It should be noted that if only one row of the first type of active region pattern array is set, then the multiple key active region patterns 11 in this embodiment are all concentrated in the single first type of active region pattern array, and there is no need to restrict the arrangement order of the multiple key active region patterns 11 in the first type of active region pattern array. Specifically, the following description uses the aforementioned 20 key active region patterns 11.
[0051] In this embodiment, if four rows of first-type active area pattern arrays are provided, the 20 key active area patterns 11 in this embodiment can be arbitrarily distributed within the four rows of first-type active area pattern arrays. For example, the 20 key active area patterns 11 can be evenly distributed within the four rows of first-type active area pattern arrays, that is, each row of the first-type active area pattern array is provided with five key active area patterns 11. Alternatively, the 20 key active area patterns 11 can be unevenly distributed within the four rows of first-type active area pattern arrays. For example, one row of the four rows of first-type active area pattern arrays is provided with 10 key active area patterns 11, the other two rows are provided with 3 key active area patterns 11 and 5 key active area patterns 11 respectively, and the last row is provided with 2 key active area patterns 11.
[0052] In another embodiment, if a twenty-row first-class active region pattern array is provided, the 20 key active region patterns 11 in this embodiment can be evenly distributed across the twenty-row first-class active region pattern array.
[0053] Therefore, the distribution of the key active area pattern 11 can be set according to actual needs, and is not limited here.
[0054] In the actual fabrication process, 1 to 4 rows of virtual structures along the first direction X are usually reserved. This can be understood as setting 1 to 4 rows of virtual conductive plug pattern arrays, active region pattern arrays, and gate line pattern arrays outside the chip. Since the conductive plug array, active region array, and gate line array fabricated based on the virtual conductive plug pattern array, active region pattern array, and gate line pattern array outside the chip do not participate in the chip's operation, the first type of conductive plug pattern array, the first type of active region pattern array, and the first type of gate line pattern array can be respectively set in the virtual conductive plug pattern array, active region pattern array, and gate line pattern array outside the chip. This effectively reduces the impact of the key active region on the storage active region, and thus reduces the impact of the key used to fabricate the storage module on storage performance.
[0055] Please refer to Figure 2 This embodiment also provides a method for preparing a storage module, which may specifically include the following steps: Step S1: Based on the layout of the active region pattern provided in this embodiment, a plurality of rows of active regions are arranged at intervals along the first direction on the substrate.
[0056] Among them, the plurality of rows of active area arrays may include at least one row of first type active area arrays. The first type of active area array may include a plurality of key active areas and a plurality of storage active areas arranged at intervals along the second direction, wherein the first direction and the second direction are perpendicular to each other.
[0057] Step S2: After forming several rows of active region arrays, based on the gate line layout provided in this embodiment, several rows of gate line arrays arranged at intervals along the first direction are formed on the several rows of active region arrays.
[0058] In this embodiment, the plurality of rows of gate line arrays may include at least one row of first type gate line arrays corresponding to the first type of active region array. The first type of gate line array may include two first gate line structures arranged at intervals along a first direction, and both first gate line structures are indirectly connected to the corresponding plurality of storage active regions.
[0059] Specifically, in practical applications, both first gate junction structures are indirectly connected through the control gate structure and the active storage region.
[0060] Step S3: After forming several rows of gate line arrays, based on the layout of the conductive plugs provided in this embodiment, several rows of conductive plug arrays are formed on several rows of active region arrays, arranged at intervals along the first direction.
[0061] In this embodiment, each conductive plug array may include a plurality of conductive plug sub-arrays arranged at intervals along the second direction. The plurality of conductive plug sub-arrays correspond one-to-one with a plurality of active regions. Each conductive plug sub-array may include two conductive plugs. All storage active regions are in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is not in contact with either of the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with one conductive plug in the corresponding conductive plug sub-array.
[0062] Because the application node of the process equipment and the current process node of the key active area are mismatched—for example, the application node of the process equipment is 40nm or above, while the design node of the key active area is 12nm or below—the actual length of multiple key active areas along the first direction during the fabrication of the memory module will deviate from the design length due to the influence of the active area etching process. This can be understood as the actual length of multiple key active areas along the first direction potentially shortening, lengthening, or even completely disconnecting from the design length. This could make key active areas that were previously able to contact the conductive plugs uncontactable, or make key active areas that were previously unable to contact the conductive plugs contactable, thus making the contact between the key active areas and the conductive plugs uncontrollable, resulting in a unique and uncontrollable key in the memory module. Furthermore, since the key active area and the memory active area are fabricated simultaneously using the same layout, no additional fabrication process is required, significantly reducing the process cost of key fabrication.
[0063] Please refer to Figure 3Based on the above-described method for fabricating a storage module, this embodiment also provides a storage module, which may include: several rows of active region arrays, several rows of gate line arrays, and several rows of conductive plug arrays.
[0064] The active region array comprises several rows located on a substrate (not shown) and arranged at intervals along a first direction X. The active region array may include at least one row of a first type of active region array, which may include several key active regions 41 arranged at intervals along a second direction Y and several storage active regions 40 arranged at intervals along the second direction Y, wherein the first direction X and the second direction Y are perpendicular to each other.
[0065] In this embodiment, several rows of gate line arrays are located on several rows of active region arrays and are arranged at intervals along the first direction X. The several rows of gate line arrays may include at least one row of first type gate line arrays corresponding to the first type of active region arrays. The first type of gate line array may include two first gate line structures 60 arranged at intervals along the first direction X, and both first gate line structures 60 are indirectly connected to the corresponding several storage active regions 40.
[0066] In this embodiment, several rows of conductive plug arrays are located on several rows of active region arrays and are arranged at intervals along the first direction X.
[0067] In this embodiment, each conductive plug array may include several conductive plug sub-arrays arranged at intervals along the second direction Y. The several conductive plug sub-arrays correspond one-to-one with several active regions. Each conductive plug sub-array may include two conductive plugs 50. All storage active regions 40 are in contact with the two conductive plugs 50 in the corresponding conductive plug sub-array. At least one key active region 41 is in contact with the two conductive plugs 50 in the corresponding conductive plug sub-array. At least one key active region 41 is not in contact with either of the two conductive plugs 50 in the corresponding conductive plug sub-array. At least one key active region 41 is in contact with one conductive plug 50 in the corresponding conductive plug sub-array.
[0068] Since the beneficial effects of setting the key active area 41 and the arrangement of the key active area 41 in this embodiment can be referred to the key active area 41, they will not be described again.
[0069] In a preferred embodiment, the projections of several key active region patterns in the active region pattern array along the second direction are all located within the projection range of the storage active region pattern along the second direction.
[0070] Furthermore, in the plurality of key active area patterns 11, the maximum length of the key active area 41 along the first direction X can be equal to the size of the storage active area 40 along the first direction X, and the minimum length of the key active area 41 along the first direction X can be less than or equal to the spacing between the two first gate lines along the first direction X. The remaining lengths of the key active areas 41 along the first direction X are spaced between the maximum length and the minimum length. Since the length setting of the key active area 41 along the first direction X can be referenced to the length setting of the key active area pattern along the first direction X, it will not be described in detail again.
[0071] In this embodiment, the width of the key active area 41 along the second direction Y can be set between 1 / 4 and 1 / 3 of the width of the storage active area 40 along the second direction Y. Since the width setting of the key active area 41 along the second direction Y can be referenced, it will not be described again.
[0072] In the array of several rows of active regions arranged at intervals along the first direction X, in addition to the first type of active region array, there is also a second type of active region array. The second type of active region array includes several storage active regions 40 arranged at intervals along the second direction Y.
[0073] Please continue to refer to this. Figure 3 In addition, among the several rows of gate line arrays arranged at intervals along the first direction X, besides the first type of gate line array, there is also a second type of gate line array. The several rows of the second type of gate line arrays correspond one-to-one with the several rows of the second type of active region arrays. Each row of the second type of gate line array includes two second gate line structures 61 arranged at intervals along the first direction X, and the two second gate line structures 61 are orthogonal to the corresponding several storage active regions 40.
[0074] In this embodiment, the storage module can be configured with a 4Mb storage specification. Therefore, the storage module includes 512 rows of active area arrays, with each row of active area arrays including 4096 active storage areas 40. In addition to the 512 rows of active area arrays, an additional 4 rows of active area arrays can be set as a virtual structure to place the key active area 41 in the 4 rows of active area arrays as virtual structures, and the arrangement format of the key active area 41 is not limited.
[0075] In summary, the storage module provided in this embodiment, during the normal preparation of the storage active area, utilizes the mismatch between the processing precision of the processing machine and the process node of the key active area to simultaneously prepare a unique and uncontrollable key, thereby greatly reducing the process cost of key preparation.
[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A layout of an active region graphic, characterized in that, Corresponding to the layout of the conductive plug, the layout of the conductive plug includes several rows of conductive plug pattern arrays arranged at intervals along a first direction, each conductive plug pattern array includes several conductive plug pattern sub-arrays arranged at intervals along a second direction, and each conductive plug pattern sub-array includes two conductive plug patterns. The layout of the active region graphic includes: Several rows of active region pattern arrays are spaced apart along a first direction. Each active region pattern array includes several active region patterns spaced apart along a second direction. At least one of the active region pattern arrays includes multiple key active region patterns and multiple storage active region patterns. The first direction and the second direction are perpendicular to each other. The conductive plug pattern subarray corresponds one-to-one with the active region pattern. Each storage active region pattern is in contact with two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is in contact with two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is not in contact with either of the two conductive plug patterns in the corresponding conductive plug pattern subarray. At least one key active region pattern is in contact with one conductive plug pattern in the corresponding conductive plug pattern subarray.
2. The layout of the active region graphic according to claim 1, characterized in that, The layout of the active region pattern also corresponds to the layout of the gate lines. The layout of the gate lines includes several rows of gate line pattern arrays arranged at intervals along the first direction. Each gate line pattern array includes two gate line patterns arranged at intervals along the first direction, and each gate line pattern is orthogonal to several storage active region patterns of the corresponding active region pattern array.
3. The layout of the active region graphic according to claim 2, characterized in that, The projections of several key active region patterns in the active region pattern array along the second direction are all located within the projection range of the storage active region pattern along the second direction.
4. The layout of the active region graphic according to claim 1, characterized in that, The width of the key active region pattern along the second direction is equal to 1 / 4 to 1 / 3 of the width of the storage active region pattern along the second direction.
5. The layout of the active region graphic according to claim 1, characterized in that, At least one of the active region pattern arrays consists of active region pattern storage.
6. A storage module, characterized in that, include: A plurality of rows of active region arrays are arranged at intervals along a first direction on a substrate. Each active region array includes a plurality of active regions arranged at intervals along a second direction. At least one of the active region arrays includes a plurality of key active regions and a plurality of storage active regions. The first direction and the second direction are perpendicular to each other. A plurality of conductive plug arrays are arranged at intervals along a first direction on a plurality of active region arrays. Each conductive plug array includes a plurality of conductive plug sub-arrays arranged at intervals along a second direction. The plurality of conductive plug sub-arrays correspond one-to-one with the plurality of active regions. Each conductive plug sub-array includes two conductive plugs. All storage active regions are in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is not in contact with either of the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with one conductive plug in the corresponding conductive plug sub-array.
7. The storage module according to claim 6, characterized in that, A plurality of rows of gate line arrays are arranged at intervals along the first direction on a plurality of rows of active region arrays. Each of the gate line arrays includes two gate line structures arranged at intervals along the first direction, and each of the gate line structures is orthogonal to a plurality of storage active regions of the corresponding active region array.
8. The storage module according to claim 7, characterized in that, The projection of the key active region along the second direction is located within the projection range of the storage active region along the second direction, and the projection of the key active region along the second direction is in contact with the projections of the corresponding two gate lines along the second direction.
9. The storage module according to claim 7, characterized in that, The width of the key active region along the second direction is between 1 / 4 and 1 / 3 of the width of the storage active region along the second direction.
10. A method for manufacturing a storage module, characterized in that, The method includes: Based on the layout of the active region according to any one of claims 1 to 5, a plurality of rows of active region arrays are formed on the substrate at intervals along a first direction, each of the active region arrays includes a plurality of active regions at intervals along a second direction, and at least one of the active region arrays includes a plurality of key active regions and a plurality of storage active regions, wherein the first direction and the second direction are perpendicular to each other. After forming several rows of active region arrays, several rows of gate line arrays are formed on the several rows of active region arrays based on the gate line layout. Each gate line array includes two gate line structures arranged at intervals along the first direction, and each gate line structure is orthogonal to several storage active regions of the corresponding active region array. After forming several rows of gate line arrays, based on the layout of the conductive plugs according to any one of claims 1 to 5, several rows of conductive plug arrays are formed on several rows of active region arrays, arranged at intervals along the first direction. Each conductive plug array includes several conductive plug sub-arrays arranged at intervals along the second direction. The several conductive plug sub-arrays correspond one-to-one with several active regions. Each conductive plug sub-array includes two conductive plugs. All storage active regions are in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is not in contact with either of the two conductive plugs in the corresponding conductive plug sub-array. At least one key active region is in contact with one conductive plug in the corresponding conductive plug sub-array.