A 1s1r type memory device and a method of manufacturing the same

Abstract

This application relates to the field of semiconductor memory technology and discloses a 1S1R type memory device and its fabrication method. The 1S1R type memory device includes, from bottom to top, a bottom electrode, a selector switch layer, a middle electrode, a resistive switching layer, an oxygen storage layer, and a top electrode. The bottom electrode, selector switch layer, and middle electrode constitute a selector unit, and the middle electrode, resistive switching layer, oxygen storage layer, and top electrode constitute a resistive switching memory unit. The middle electrode is a common electrode for both the selector unit and the resistive switching memory unit. The thickness of the selector switch layer is 10–500 Å, the thickness of the resistive switching layer is 10–200 Å, and the thickness of the oxygen storage layer is 10–500 Å. This application, through the vertical series structure of the selector unit and the resistive switching memory unit, suppresses leakage paths in the cross array while maintaining the resistive switching memory function. Furthermore, by using the oxygen storage layer to participate in the regulation of oxygen-related components in the resistive switching layer, it improves the device's read / write capability and array integration adaptability.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, specifically to a 1S1R type memory device and its fabrication method. Background Technology

[0002] Resistive random access memory (RSM) is a type of non-volatile memory that utilizes changes in the resistance state of a material to store data. A typical RSM usually consists of electrodes and a resistive switching layer located between the electrodes. Under the influence of an applied electric field, oxygen-related defects, conductive filaments, or localized conductive channels in the resistive switching layer change, causing the device to switch between a high-resistance state and a low-resistance state. Due to its simple structure, miniaturization, and non-volatile storage characteristics, RSM is suitable for applications such as high-density memory arrays and memory-class memory.

[0003] In high-density storage applications, cross-connect arrays formed by word lines and bit lines have high integration potential. In this structure, the memory cells are located at the intersection of word lines and bit lines, and the cell area can be close to the size of the interconnect intersection area. However, when a single resistive random access memory (RRAM) cell is directly connected to the cross-connect array, unselected and half-selected cells will form a leakage path together with the selected cells. When some unselected cells in the array are in a low-resistance state, the read / write current will bypass the target cell, causing the read result to deviate from the true resistance state of the target cell, and in severe cases, it can even cause false writes or false erases. Therefore, the leakage path problem in the cross-connect array is a key issue that needs to be addressed when implementing large-scale array integration of resistive random access memory (RRAM).

[0004] To suppress leakage paths, existing resistive switching memories (RSMs) often employ a 1T1R structure, consisting of a transistor and a resistive switching cell connected in series. The transistor can select and control the resistive switching cell, but it requires a certain area and needs to provide the drive current necessary for resistive switching operation. As memory cell sizes continue to shrink, the transistor area cannot shrink synchronously with the resistive switching cell, thus limiting the storage density of the 1T1R structure. For memory applications requiring high capacity and low cost per bit, the 1T1R structure cannot fully leverage the miniaturization advantages of resistive switching memory cells.

[0005] Replacing transistors with selectors and connecting them in series with resistive switching cells to form a 1S1R structure is one way to improve the adaptability of cross-arrays. The selector limits current under unselected bias and conducts under selected bias, allowing for selection control of the resistive switching cells without introducing large-area transistors. However, existing 1S1R structures still require addressing the vertical stacking relationship between the selector layer, resistive switching layer, and electrode layer, as well as the connection issues with the upper and lower metal interconnects during practical integration. Complex connection structures between the selector cells and resistive switching cells increase manufacturing complexity and cell height, and also hinder the formation of regular cylindrical memory cells.

[0006] Furthermore, the resistive-state stability of resistive switching memory cells is closely related to the distribution of oxygen-related defects in the resistive switching layer. In a single resistive switching layer structure, the migration location, quantity, and distribution of oxygen ions and oxygen vacancies are prone to change during multiple set and reset processes, leading to fluctuations in the readout window between high and low resistive states. The sidewalls of the resistive switching layer are also affected by plasma, filling media, or cleaning solutions during etching, filling, and cleaning processes, making the conductive channels in the edge regions unstable. For high-density memory cells with columnar structures, the stability of the sidewall interface directly affects the device's cycling characteristics, retention characteristics, and array consistency.

[0007] Therefore, it is necessary to provide a 1S1R type memory device suitable for cross arrays and its fabrication method, so that selector units and resistive switching memory units can be effectively connected in series in the vertical direction, and the structural integration, leakage current suppression capability and resistive state control stability can be improved by using a common electrode, oxygen storage layer and sidewall protection structure. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this application provides a 1S1R type memory device and its fabrication method, which solves the problems of leakage paths in existing resistive switching memories in cross arrays, the limitation of storage density of traditional 1T1R structures by transistor size, and the insufficient resistance state control stability of single resistive switching devices.

[0009] To achieve the above objectives, this application provides the following technical solution:

[0010] In a first aspect, this application provides a 1S1R type storage device, which adopts the following technical solution: It includes, from bottom to top, a bottom electrode, a selector switch layer, a middle electrode, a resistive switching layer, an oxygen storage layer, and a top electrode.

[0011] The bottom electrode, the selector switch layer, and the middle electrode constitute a selector unit, and the middle electrode, the resistive switching layer, the oxygen storage layer, and the top electrode constitute a resistive switching memory unit. The middle electrode is a common electrode for the selector unit and the resistive switching memory unit.

[0012] The thickness of the selector switching layer is 10–500 Å, the thickness of the resistive switching layer is 10–200 Å, and the thickness of the oxygen storage layer is 10–500 Å.

[0013] By adopting the above technical solution, the selector unit and the resistive switching memory unit are connected in series in the vertical direction, and the middle electrode serves as the connecting electrode for both units, enabling the device to form a 1S1R structure within a relatively small lateral area. The selector switching layer limits the current under the unselected bias voltage and conducts under the selected bias voltage, thereby reducing the impact of leakage paths in the cross array. The resistive switching layer forms high-resistance and low-resistance states under the action of an applied electric field, and the oxygen storage layer is arranged adjacent to the resistive switching layer to participate in the regulation of oxygen-related components during the resistive switching process. Thus, the device can simultaneously perform gating control and resistive switching memory functions.

[0014] Preferably, the material of the selector switching layer is selected from GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, Vox, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO. One or more; the material of the resistive switching layer is selected from one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO; the material of the oxygen storage layer is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON.

[0015] By adopting the above technical solutions, the selector switching layer adopts a chalcogenide material system, which can form a nonlinear conductive layer; the resistive switching layer adopts an oxide material system, which can provide the oxygen vacancy regulation environment required for resistive switching; the oxygen storage layer adopts a metal, metal oxide, metal nitride or metal nitride material system, which can cooperate with the resistive switching layer to regulate the resistive switching state.

[0016] Preferably, the 1S1R type memory device further includes a bottom metal layer, a bottom electrode-bottom metal layer inter-insulating layer, and a via filling layer. The bottom electrode-bottom metal layer inter-insulating layer is disposed between the bottom metal layer and the bottom electrode, and the via filling layer is disposed in the bottom electrode-bottom metal layer inter-insulating layer and is electrically connected to the bottom metal layer and the bottom electrode, respectively.

[0017] By adopting the above technical solution, the bottom metal layer forms a local connection with the bottom electrode through the via filling layer, and the insulating layer between the bottom electrode and the bottom metal layer provides isolation in the non-via area, enabling the core function stack to be connected to the lower interconnect structure.

[0018] Preferably, the 1S1R type memory device further includes an etch stop layer, a sidewall protection layer, an inter-device fill layer, an inter-metal insulating layer, and a top metal layer. The etch stop layer is disposed on the top electrode, the sidewall protection layer is disposed on the sidewalls of the bottom electrode, the selector switch layer, the middle electrode, the resistive switching layer, the oxygen storage layer, the top electrode, and the etch stop layer, the inter-device fill layer is disposed between adjacent sidewall protection layers, the inter-metal insulating layer is disposed above the inter-device fill layer, and the top metal layer is disposed in the inter-metal insulating layer and electrically connected to the top electrode.

[0019] By employing the above technical solution, the etching barrier layer is used for process protection of the top region, the sidewall protection layer is used to cover the sidewalls of the core functional stack, the inter-device fill layer is used to isolate adjacent columnar device structures, and the inter-metal insulating layer is used to isolate the area surrounding the top metal layer. After the top metal layer is electrically connected to the top electrode, the device forms a current path from the bottom metal layer to the top metal layer.

[0020] Secondly, this application provides a method for fabricating a 1S1R type memory device, which adopts the following technical solution: A method for fabricating a 1S1R type memory device includes the following steps: A selector switch layer is deposited on the bottom electrode, the thickness of which is 10–500 Å. A central electrode is deposited on the selector switch layer; A resistive switching layer is deposited on the central electrode, and the thickness of the resistive switching layer is 10–200 Å. An oxygen storage layer is deposited on the resistive switching layer, and the thickness of the oxygen storage layer is 10–500 Å. A top electrode is deposited on the oxygen storage layer; The bottom electrode, the selector switch layer, and the middle electrode constitute a selector unit, and the middle electrode, the resistive switching layer, the oxygen storage layer, and the top electrode constitute a resistive switching memory unit. The middle electrode is a common electrode for the selector unit and the resistive switching memory unit.

[0021] By employing the above technical solution, the functional layers of the selector unit and the resistive switching memory unit are deposited sequentially, forming a vertically connected 1S1R core functional stack. The central electrode achieves the electrical connection between the selector unit and the resistive switching memory unit in the same film layer, reducing additional connection structures.

[0022] Preferably, before depositing the selector switch layer, a bottom metal layer, a bottom electrode-bottom metal layer interlayer insulating layer, a via filling layer, and a bottom electrode are formed.

[0023] By adopting the above technical solution, the bottom metal layer is connected to the bottom electrode through the via filling layer, enabling the 1S1R core function stack to be integrated with the lower interconnect structure.

[0024] Preferably, after depositing the top electrode, an etch barrier layer is formed, and the etch barrier layer, the top electrode, the oxygen storage layer, the resistive switching layer, the middle electrode, the selector switching layer, and the bottom electrode are etched to form a columnar device structure; a sidewall protection layer is formed on the sidewall of the columnar device structure.

[0025] By adopting the above technical solution, the core functional stack can be patterned and etched to form a columnar device structure. The sidewall protective layer covers the sidewall of the columnar device structure, reducing the impact of subsequent filling, etch-back and cleaning processes on the sidewall of the functional film layer.

[0026] Preferably, after forming the sidewall protective layer, an inter-device fill layer is formed, and the inter-device fill layer and the sidewall protective layer are etched back to expose the connection area of ​​the top electrode; an inter-metal insulating layer is formed above the inter-device fill layer, and a top metal layer electrically connected to the top electrode is formed in the inter-metal insulating layer.

[0027] By adopting the above technical solution, adjacent columnar device structures are isolated by inter-device filling layers, the top electrode is led out through the top metal layer, and the inter-metal insulating layer is used for insulation isolation of the top interconnect area, thereby completing the integration of the 1S1R type memory device with the upper interconnect structure.

[0028] This application provides a 1S1R type memory device and its fabrication method. It has the following beneficial effects: 1. This application adopts a structure in which the bottom electrode, selector switch layer, middle electrode, resistive switching layer, oxygen storage layer and top electrode are stacked in sequence, so that the selector unit and resistive switching memory unit are connected in series in the vertical direction. The selector switch layer limits the current under non-selected or half-selected bias voltage and conducts under selected bias voltage, thus reducing the impact of leakage path in cross array on read and write judgment and reducing dependence on transistor selection structure.

[0029] 2. This application sets the middle electrode as a shared electrode for the selector unit and the resistive switching memory unit, reducing the additional connection structure between the selector unit and the resistive switching memory unit. This setting is beneficial for forming 1S1R columnar memory cells with smaller lateral dimensions, and establishes a clear top-to-bottom electrical connection relationship between the bottom metal layer, via filling layer, core function stack, and top metal layer, making it easy to apply to cross-array and multi-layer stacked memory structures.

[0030] 3. This application incorporates an oxygen storage layer on the resistive switching layer, and the sidewalls of the columnar device structure can be covered by a sidewall protection layer. The oxygen storage layer participates in the migration and containment of oxygen-related components during resistive switching, which is beneficial for the resistive switching layer to form readable high-resistivity and low-resistivity states. The sidewall protection layer separates the sidewalls of the selector switching layer, resistive switching layer, and oxygen storage layer from the inter-device filler layer, which helps to reduce the impact of subsequent filling, etch-back, and cleaning processes on the sidewalls of the functional film layer. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the memory hierarchy provided in an embodiment of this application; Figure 2 A schematic diagram provided for an embodiment of this application; Figure 3 A schematic diagram provided for an embodiment of this application; Figure 4 Test diagram of the switching characteristics of the selector unit provided in the embodiments of this application; Figure 5 This is a test diagram of the resistive switching characteristics of the resistive switching memory cell provided in the embodiments of this application; Figure 6 This application provides a diagram of the 1S1R overall device read / write and half-select leakage current test in an embodiment of the present application. Figure 7 The diagram shows a comparison test of the structural composition and storage stability provided in the embodiments of this application.

[0032] The components are: 1. Bottom metal layer; 2. Insulating layer between bottom electrode and bottom metal layer; 3. Via fill layer; 4. Bottom electrode; 5. Selector switch layer; 6. Middle electrode; 7. Resistive switching layer; 8. Oxygen storage layer; 9. Top electrode; 10. Etch barrier layer; 11. Sidewall protection layer; 12. Inter-device fill layer; 13. Insulating layer between metal layers; 14. Top metal layer; 15. Word line; 16. Bit line; 17. 1S1R device. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Please see the appendix Figure 1 -Appendix Figure 7 This application provides a 1S1R type storage device and its manufacturing method, including...

[0035] In this application, a 1S1R type memory device refers to a memory device formed by connecting a selector unit and a resistive variable memory unit in series. The selector unit corresponds to "1S" in 1S1R, and the resistive variable memory unit corresponds to "1R" in 1S1R. The selector unit is used to turn on under the selected voltage and limit the current flow in the unselected state; the resistive variable memory unit is used to form different resistance states under the action of an external electric field, thereby realizing data storage.

[0036] For ease of description, in this application, "up" and "down" are based on the stacking direction of the storage device, that is, the direction from the bottom metal layer 1 to the top metal layer 14 is the upward direction, and the opposite direction is the downward direction. "Lateral" refers to the direction parallel to the main surface of the substrate or the plane parallel to the extension direction of the bottom metal layer 1.

[0037] Please see the appendix Figure 1 -Appendix Figure 3 The 1S1R type memory device includes, from bottom to top, a bottom metal layer 1, a bottom electrode-bottom metal layer interlayer insulating layer 2, a bottom electrode 4, a selector switch layer 5, a middle electrode 6, a resistive switching layer 7, an oxygen storage layer 8, a top electrode 9, an etch barrier layer 10, an interlayer insulating layer 13, and a top metal layer 14. A via filling layer 3 is disposed within the bottom electrode-bottom metal layer interlayer insulating layer 2, a sidewall protection layer 11 is disposed on the sidewall of the columnar device structure formed from the bottom electrode 4 to the etch barrier layer 10, and an inter-device filling layer 12 is disposed between adjacent columnar device structures.

[0038] The bottom metal layer 1 is located at the bottom of the memory device, serving as the lower-layer interconnect structure. The bottom metal layer 1 and the bottom electrode 4 do not have direct, large-area contact; they are separated by a bottom electrode-bottom metal layer interlayer insulating layer 2. Through-holes are formed in the bottom electrode-bottom metal layer interlayer insulating layer 2, and these through-holes are filled with conductive material to form a through-hole filling layer 3. The lower end of the through-hole filling layer 3 is electrically connected to the bottom metal layer 1, and the upper end of the through-hole filling layer 3 is electrically connected to the bottom electrode 4. This achieves partial conductivity between the bottom metal layer 1 and the bottom electrode 4 while maintaining the isolation function of the bottom electrode-bottom metal layer interlayer insulating layer 2.

[0039] The bottom electrode 4 is disposed above the bottom electrode-bottom metal interlayer insulating layer 2 and the via filling layer 3. The bottom electrode 4 covers the top connection area of ​​the via filling layer 3 and serves as the lower electrode of the selector unit. The bottom electrode 4 is in contact with the selector switch layer 5, allowing external electrical signals to be transmitted to the selector switch layer 5 via the bottom metal layer 1 and the via filling layer 3.

[0040] The selector switching layer 5 is disposed on the bottom electrode 4. The selector switching layer 5 is a switching layer with non-linear conductivity, exhibiting a low conduction state under low voltage or unselected voltage, and allowing current to flow when the selection condition is met. The thickness of the selector switching layer 5 is 10–500 Å. This thickness range corresponds to the thickness of a continuous film layer capable of forming a thin-film switching layer, and is also suitable for forming a vertical series structure with the bottom electrode 4 and the middle electrode 6.

[0041] The middle electrode 6 is disposed on the selector switching layer 5. The lower surface of the middle electrode 6 is in contact with the selector switching layer 5, and the upper surface of the middle electrode 6 is in contact with the resistive switching layer 7. Thus, the bottom electrode 4, the selector switching layer 5, and the middle electrode 6 together constitute the selector unit; the middle electrode 6 also serves as the upper electrode of the selector unit and the lower electrode of the resistive switching memory unit. This middle electrode 6 is not two separate electrode layers, but rather simultaneously undertakes the electrical connection and interface cooperation between the two units within the same conductive film layer.

[0042] A resistive switching layer 7 is disposed on the middle electrode 6. The resistive switching layer 7 is a functional layer that changes the resistance state, and its thickness is 10–200 Å. Under the influence of an electric field, the resistive switching layer 7 forms different resistance states through changes in the internal defect state, oxygen vacancy distribution, or conductive channel state. The resistive switching layer 7 is in contact with the middle electrode 6, facilitating the formation of a vertical current path from the middle electrode 6 to the top electrode 9 in the resistive switching memory cell.

[0043] An oxygen storage layer 8 is disposed on the resistive switching layer 7. The thickness of the oxygen storage layer 8 is 10–500 Å. The oxygen storage layer 8 is disposed adjacent to the resistive switching layer 7 and is used to exchange or contain oxygen-related components with the resistive switching layer 7 when the resistive state switches, thereby participating in the regulation of the conductivity state within the resistive switching layer 7. The oxygen storage layer 8 can be a metal layer, a metal oxide layer, a metal nitride layer, a metal nitride layer, or a composite layer formed of one or more of the above materials.

[0044] The top electrode 9 is disposed on the oxygen storage layer 8. The top electrode 9 serves as the upper electrode of the resistive switching memory cell, and together with the middle electrode 6, the resistive switching layer 7, and the oxygen storage layer 8, forms a resistive switching memory cell in the vertical direction. Thus, the selector unit and the resistive switching memory cell are connected in series in the same vertical direction, and the two are connected through the middle electrode 6 to form a 1S1R type memory cell.

[0045] An etching barrier layer 10 is disposed on the top electrode 9. The etching barrier layer 10 is used to cover the upper surface of the top electrode 9 during the forming of the columnar device structure and subsequent processing of the top connection area, reducing unexpected losses of the top electrode 9 during etching or etch-back processes. The etching barrier layer 10 and the top electrode 9 are located together in the top region of the columnar device structure.

[0046] Bottom electrode 4, selector switch layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8, top electrode 9, and etch barrier layer 10 are patterned and etched to form a columnar device structure. A columnar device structure refers to a structure in which the above layers are stacked vertically within the same memory cell region and separated laterally from adjacent memory cells. The cross-sectional shape of the columnar device structure can be circular, elliptical, polygonal, or other closed patterns formed by photolithography and etching processes.

[0047] A sidewall protective layer 11 is disposed on the sidewall of the columnar device structure. The sidewall protective layer 11 covers the sidewall regions of the bottom electrode 4, selector switching layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8, top electrode 9, and etching barrier layer 10. The sidewall protective layer 11 also covers the upper surface of the bottom electrode-bottom metal interlayer insulation layer 2 exposed between adjacent columnar device structures. Through this arrangement, the functional film layer sidewalls of the columnar device structure are separated from the subsequent filling material, and the sidewall interfaces of the selector switching layer 5, resistive switching layer 7, and oxygen storage layer 8 can be covered by the sidewall protective layer 11.

[0048] Inter-device filler layer 12 is disposed between adjacent columnar device structures and between adjacent sidewall protective layers 11. Inter-device filler layer 12 fills the gap between adjacent memory cells, thereby forming a dielectric isolation between adjacent columnar device structures. The upper surface of inter-device filler layer 12, after being etched back or polished, provides a bearing surface for the formation of inter-metal insulating layer 13.

[0049] An intermetallic insulating layer 13 is disposed above the inter-device fill layer 12 and surrounding the top metal layer 14. The intermetallic insulating layer 13 isolates the top metal layer 14 from the columnar device structure of the underlying non-connected area and isolates adjacent top metal layers 14. In areas where the top electrode 9 needs to be connected to the top metal layer 14, the intermetallic insulating layer 13 has connection openings or trenches to allow the top metal layer 14 to form an electrical connection with the top electrode 9.

[0050] The top metal layer 14 is disposed within or above the inter-metal insulating layer 13. The top metal layer 14 is electrically connected to the top electrode 9 and is used to apply a top electrical signal to the resistive switching memory cell. The bottom metal layer 1 and the top metal layer 14 are located below and above the 1S1R type memory device, respectively, and together they form a vertical addressing path for a single columnar device structure. In the array structure, the bottom metal layer 1 and the top metal layer 14 can each serve as two sets of interconnects arranged in a cross configuration.

[0051] In the above structure, the selector unit is located below the resistive switching memory unit, and the resistive switching memory unit is located above the selector unit. When an external electrical signal is input from the bottom metal layer 1, it enters the bottom electrode 4 through the via filling layer 3, and then sequentially passes through the selector switching layer 5, the middle electrode 6, the resistive switching layer 7, the oxygen storage layer 8, and the top electrode 9 before being transmitted to the top metal layer 14. This current path allows the selector unit and the resistive switching memory unit to form a series connection within a single memory cell.

[0052] In this application, the bottom electrode 4, selector switch layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8, and top electrode 9 constitute the core functional stack of a 1S1R type memory device. The etch stop layer 10, sidewall protection layer 11, inter-device fill layer 12, inter-metal insulating layer 13, bottom metal layer 1, via fill layer 3, and top metal layer 14 cooperate with the core functional stack to enable integration with the upper and lower interconnect structures and to maintain electrical isolation between adjacent memory cells.

[0053] The via-filling layer 3 in the bottom electrode-bottom metal interlayer insulating layer 2 is not limited to a filling structure formed by a single conductive material, but also includes a composite filling structure formed by a metal layer, a metal nitride layer, or a metal oxide nitride layer. The sidewall protective layer 11 is not limited to a single dielectric layer, but also includes a composite protective structure formed by an oxide layer, a nitride layer, or a TEOS-deposited silicon oxide layer. The inter-device filling layer 12 is not limited to a single filling dielectric, but also includes a composite filling structure formed by TEOS-deposited silicon oxide and OSG.

[0054] The 1S1R type memory device can be used as a memory cell in a single-layer memory array or as a single-layer memory cell in a multi-layer stacked memory array. When multiple columnar device structures are spaced apart laterally, adjacent columnar device structures are separated by a sidewall protective layer 11 and an inter-device filling layer 12. When multiple memory layers are stacked vertically, the bottom metal layer 1, the core functional stack, and the top metal layer 14 in each layer are arranged according to corresponding interconnection relationships.

[0055] In the above structure, the material selection and formation method of each functional film layer need to match the stacking relationship of the 1S1R type memory device. The bottom metal layer 1 and the top metal layer 14 serve as interconnects between the upper and lower layers. The bottom electrode 4, selector switch layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8, and top electrode 9 constitute the core functional stack. The bottom electrode-bottom metal layer insulating layer 2, via filling layer 3, etching barrier layer 10, sidewall protection layer 11, inter-device filling layer 12, and metal layer insulating layer 13 work together to complete isolation, connection, protection, and filling. Therefore, in specific fabrication, it is necessary to select appropriate raw materials, precursors, targets, reactive gases, and process equipment according to the position and function of each layer in the device.

[0056] All raw materials and equipment used in this application are configured around the aforementioned layered structure. The following raw material description clarifies the material sources and formation methods that can be used for each structural layer, and the following equipment description clarifies the basic process conditions required for each film deposition, patterning, etching, filling, planarization, cleaning, and testing process.

[0057] The raw materials and equipment used in the embodiments of this application are all suitable for semiconductor back-end processes. Unless otherwise stated, the metal targets, dielectric deposition precursors, reactive gases, cleaning reagents, and photolithography materials used can all be commercially available semiconductor process-grade materials, or prepared using conventional methods in the art. Before use, each material is stored, transported, and purified according to semiconductor wafer process requirements to reduce the impact of particles, moisture, and metal impurities on the film interface.

[0058] The metal materials used in the bottom metal layer 1 and the top metal layer 14 include one or more of Cu and Al. Cu and Al can be used in the form of sputtering targets, electroplating materials, vapor deposition materials, or chemical vapor deposition precursors. When Cu interconnects are used, one or more of Ta, TaN, Ti, TiN, and Ru can be used as barrier layer or seed layer materials. These barrier layers or seed layers are part of the interconnect process of the bottom metal layer 1 or the top metal layer 14 and are not structural layers separately numbered in this application.

[0059] The materials used for the bottom electrode-bottom metal interlayer insulating layer 2 include one or more of SiO2, NDC, and PEOX. SiO2 and PEOX can be deposited using PECVD processes; NDC can be deposited under plasma conditions using silicon-containing precursors, carbon-containing precursors, and nitrogen-containing gases. Here, NDC refers to nitrogen-doped silicon carbide dielectric films, and PEOX refers to plasma-enhanced silicon oxide dielectric films; both are dielectric film layers that can be formed in the back-end processes of semiconductor fabrication.

[0060] The conductive materials used for the via filling layer 3, bottom electrode 4, middle electrode 6, and top electrode 9 include metals, metal nitrides, and metal nitrides. Metals include one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, and W; metal nitrides include one or more of TiN, TaN, AlN, WN, and MoN; and metal nitrides include one or more of TiON, TaON, and AlON. These materials can be formed using corresponding metal targets, alloy targets, ceramic targets, or reactive sputtering, or, where suitable for filling vias, using a CVD process.

[0061] The materials used in the selector switching layer 5 include one or more of the following: GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO. These materials can be deposited using chalcogenide sputtering targets with corresponding compositions, or they can be formed using multi-target co-sputtering. When using multi-target co-sputtering, different targets provide the elemental sources required for the selector switching layer 5, and the corresponding film composition is obtained by adjusting the power of each target and the deposition time. When using a single composite target, the composition of the composite target corresponds to the material of the selector switching layer 5 to be deposited.

[0062] The resistive switching layer 7 is made of one or more of the following materials: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO. The resistive switching layer 7 can be formed by ALD, PVD, or PECVD deposition. When using ALD deposition, the metal precursor and oxygen source are alternately introduced into the reaction chamber to form a corresponding oxide film on the surface of the central electrode 6. When using PVD deposition, an oxide target can be used, or a metal target can be used in conjunction with oxygen-containing gas for reactive sputtering.

[0063] The oxygen storage layer 8 is made of one or more of the following materials: Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON. The oxygen storage layer 8 can be formed by PVD deposition. For metal oxygen storage layers, sputtering with the corresponding metal target can be used; for metal oxide, metal nitride, and metal nitride oxygen storage layers, ceramic target deposition or reactive sputtering can be used. TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, and NiOx represent the oxide materials of the corresponding metals, where x represents the different oxidation states formed by variations in oxygen content in the metal oxide under different deposition conditions.

[0064] The etching barrier layer 10 is made of one or more of SiON, Si3N4, and PEOX. SiON and Si3N4 can be deposited using a PECVD process. SiON can be formed under plasma conditions using silicon-containing gas, oxygen-containing gas, and nitrogen-containing gas; Si3N4 can be formed under plasma conditions using silicon-containing gas and nitrogen-containing gas; and PEOX can be formed under plasma conditions using silicon-containing gas and oxygen-containing gas.

[0065] The sidewall protective layer 11 is made of one or more of the following materials: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and TEOS. The sidewall protective layer 11 can be formed by ALD or PECVD deposition. When depositing HfO2, Ta2O5, TiO2, ZrO2, or Al2O3 using ALD, the precursor used is the corresponding metal-organic precursor or inorganic precursor, and the oxygen source is one of H2O, O3, O2 plasma, or N2O plasma. In this application, TEOS refers to a silicon oxide dielectric film deposited using tetraethoxysilane as a silicon source, and is not used as a polymer material.

[0066] The inter-device filling layer 12 is made of one or more materials, including TEOS and OSG. The TEOS filling layer can be formed as a silicon oxide dielectric film by PECVD deposition of tetraethoxysilane. OSG refers to organosilicon glass or carbon-doped silicon oxide low-dielectric-constant dielectric film, which can be formed by deposition of organosilicon precursors under plasma conditions. The inter-device filling layer 12 can be a monolayer structure formed by TEOS deposition of silicon oxide, a monolayer structure formed by OSG, or a composite filling structure formed by sequential deposition of TEOS-deposited silicon oxide and OSG.

[0067] The material used for the intermetallic insulating layer 13 is OSG. OSG can be formed by PECVD deposition and is used for the intermetallic insulating structure surrounding the top metal layer 14. The intermetallic insulating layer 13 can also be integrated with a dielectric film for blocking, covering or planarizing on the basis of the OSG main film layer. The dielectric film used does not change the structural relationship of the intermetallic insulating layer 13 with OSG as the main insulating medium.

[0068] The materials used in photolithography include positive photoresist, negative photoresist, bottom anti-reflective coating, developer, resist stripper, and cleaning solution. Photoresist is used to define the patterns of vias, pillar-like device structures, top metal connection openings, or trenches. The developer can be a tetramethylammonium hydroxide aqueous solution. The resist stripper can be oxygen plasma stripping, wet stripping, or a combination of both. All of the above photolithography materials are commonly used in semiconductor photolithography processes.

[0069] The gases used in the etching process include fluorine-containing etching gases, chlorine-containing etching gases, hydrogen bromide, oxygen, argon, nitrogen, and other auxiliary gases. Fluorine-containing etching gases include one or more of CF4, CHF3, and C4F8, mainly used for etching oxides, oxynitrides, or some dielectric layers. Chlorine-containing etching gases include one or more of Cl2 and BCl3, mainly used for etching metals, metal nitrides, metal oxynitrides, and some chalcogenide films. Ar is used for plasma-assisted bombardment and atmosphere dilution, O2 is used for removing organic residues or conditioning the etching atmosphere, and N2 is used for atmosphere conditioning and plasma stabilization.

[0070] The cleaning process uses reagents including deionized water, diluted hydrofluoric acid, ammonia-hydrogen peroxide cleaning solution, hydrochloric acid-hydrogen peroxide cleaning solution, and a cleaning solution for removing organic residues. Diluted hydrofluoric acid is used to remove some oxide residues or surface contaminants after etching. Ammonia-hydrogen peroxide cleaning solution can be used for cleaning particles and organic residues, while hydrochloric acid-hydrogen peroxide cleaning solution can be used for cleaning metal ion contaminants. Cleaning conditions are selected according to the material of the film being cleaned to ensure that the cleaning process does not damage the sidewall structure of the already formed selector switching layer 5, resistive switching layer 7, and oxygen storage layer 8.

[0071] The deposition equipment used in the embodiments of this application includes a PVD equipment, an ALD equipment, a PECVD equipment, and a CVD equipment. The PVD equipment is used to deposit metal, metal nitrides, metal oxide nitrides, a selector switching layer 5, an oxygen storage layer 8, and a portion of the top electrode 9. The ALD equipment is used to deposit the resistive switching layer 7 and the oxide film layer in the sidewall protective layer 11. The PECVD equipment is used to deposit the bottom electrode-bottom metal interlayer insulating layer 2, the etching barrier layer 10, the inter-device filling layer 12, and the metal interlayer insulating layer 13. The CVD equipment is used to form a portion of the metal material in the via filling layer 3, and is particularly suitable for filling high aspect ratio vias.

[0072] The patterning equipment used in this application includes a photoresist coating and developing device, an exposure device, and a dry etching device. The photoresist coating and developing device is used to form photoresist patterns on the wafer surface. The exposure device is used to define via patterns, columnar device patterns, and top metal connection patterns. The dry etching device can be a RIE device or an ICP-RIE device, used to etch the bottom electrode-bottom metal interlayer insulating layer 2, vias, core function stacks, and top metal connection openings.

[0073] The planarization equipment used in the embodiments of this application includes CMP equipment or hard pad polishing equipment. CMP equipment is used for planarization after the via filling layer 3 is deposited, and also for surface planarization after the top metal layer 14 is formed. The slurry used in the polishing process is selected according to the material being polished. When the via filling layer 3 is metal or metal nitride, a slurry adapted to a conductive material is used. When the inter-device filling layer 12 or the inter-metal insulating layer 13 is a dielectric material, a slurry adapted to an oxide or a low dielectric constant material is used.

[0074] The characterization equipment used in this application includes a scanning electron microscope (SEM), a transmission electron microscope (TEM), an ellipsometer, an X-ray reflectance testing device, a four-probe testing device, and an electrical testing instrument. The SEM and TEM are used to observe the columnar device structure, the coverage of the sidewall protective layer 11, the filling of the inter-device filling layer 12, and the connection of the top metal layer 14. The ellipsometer and X-ray reflectance testing device are used to measure the thin film thickness. The four-probe testing device is used to test the sheet resistance of the conductive film layer. The electrical testing instrument is used to test the current-voltage characteristics of the selector unit, the resistive switching memory unit, and the 1S1R type memory device.

[0075] Unless otherwise specified, the raw materials and equipment used in the embodiments of this application are not limited to specific manufacturers or models. Any equipment and materials that can form the corresponding material film layer, achieve the corresponding patterning process, complete the corresponding planarization and cleaning steps, and obtain the laminated structure of this application are applicable to the implementation of this application.

[0076] Preparation Examples 1-3: Based on the aforementioned raw materials and equipment, the metals, oxides, nitrides, oxynitrides, and dielectric films involved in this application can be obtained using commercial targets, commercial precursors, or conventional semiconductor deposition processes. For the chalcogenide material used in the selector switching layer 5, the composite oxide material used in the resistive switching layer 7, and the composite dielectric film used in the bottom electrode-bottom metal interlayer insulating layer 2 and the device interlayer filling layer 12, their formation methods are further illustrated below through preparation examples. The following preparation examples are used to illustrate the methods of obtaining the corresponding materials or films and do not imply that all materials in this application need to be prepared in-house.

[0077] Preparation Example 1: This preparation example provides a method for preparing a selector switching layer target, including the following steps: According to the target composition of the selector switch layer target material to be prepared, weigh the corresponding elemental raw materials from In, Sn, Sb, Ge, Si, As, Te, Se, Nb, V, Ti, Ga, Zr, Hf, Ta, and Al. The target composition corresponds to any one of GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO. Each elemental raw material should be a semiconductor or electronic-grade material with a purity of not less than 99.9%.

[0078] The weighed elemental raw material is placed in a quartz tube, quartz ampoule, or vacuum melting container. The quartz tube, quartz ampoule, or vacuum melting container is then evacuated, or purged with an inert gas. The inert gas is one of Ar, N2, or He. When using a sealed-tube melting method, the quartz tube or quartz ampoule containing the elemental raw material is sealed.

[0079] The sealed quartz tube or quartz ampoule is placed in a heating furnace, or a vacuum melting vessel containing the elemental raw material is placed in a vacuum melting apparatus for melting reaction under vacuum or inert atmosphere. The melting temperature is 500–1100℃, and the holding time is 1–24 h. For raw material systems containing Se, As, or Te, the heating process is carried out in stages or slowly, with a heating rate of 0.5–10℃ / min.

[0080] After the heat treatment is completed, the molten material is cooled to obtain sulfide ingots. The cooling method is one of furnace cooling, air cooling, water cooling, or quenching. The obtained sulfide ingots are then annealed at a temperature of 100–500℃ for 1–48 hours in a vacuum or inert atmosphere.

[0081] The annealed chalcogenide ingots are crushed, ground, and sieved to obtain chalcogenide powder. The chalcogenide powder is then loaded into a molding die and formed by cold pressing, hot pressing, or sintering to obtain the selector switch layer target material. When hot pressing is used, the hot pressing temperature is 100–500℃, the pressure is 10–80 MPa, and the holding time is 1–8 h.

[0082] The obtained selector switching layer target is used to form selector switching layer 5 by PVD deposition. The material of selector switching layer 5 is selected from one or more of GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO, and the deposition thickness is 10–500 Å.

[0083] Preparation Example 2: This preparation example provides a method for preparing a composite resistive switching layer thin film, including the following steps: A wafer with a central electrode 6 is provided and placed in an ALD reaction chamber. The ALD reaction chamber is evacuated and purged with an inert gas. The inert gas is one or more of N2, Ar, or He.

[0084] The wafer temperature is controlled between 50 and 400°C, and the pressure in the ALD reaction chamber is controlled between 0.01 and 10 Torr. A first metal precursor is pulsed into the ALD reaction chamber for 0.01 to 10 s; then, an inert gas is introduced for purging for 0.1 to 60 s; next, an oxygen source is introduced into the ALD reaction chamber for 0.01 to 10 s; then, an inert gas is introduced again for purging for 0.1 to 60 s, forming the first metal oxide deposition cycle.

[0085] After completing the first metal oxide deposition cycle, a second metal precursor is pulsed into the ALD reaction chamber for 0.01–10 s; then, inert gas is introduced for purging for 0.1–60 s; then, an oxygen source is introduced into the ALD reaction chamber for 0.01–10 s; then, inert gas is introduced again for purging for 0.1–60 s, thus forming the second metal oxide deposition cycle.

[0086] Alternating first and second metal oxide deposition cycles are performed to form a composite resistive switching layer thin film on the central electrode 6. The thickness of the composite resistive switching layer thin film is 10–200 Å.

[0087] The first and second metal precursors are each independently selected from one of the following: Hf precursor, Ta precursor, Si precursor, Zr precursor, and Al precursor. The oxygen source is selected from one or more of H2O, O3, O2 plasma, and N2O plasma.

[0088] When the first metal precursor is an Hf precursor and the second metal precursor is a Ta precursor, an HfTaO composite resistive switching layer film is formed; when the second metal precursor is replaced by a Si precursor, a Zr precursor or an Al precursor, an HfSiO, HfZrO or HfAlO composite resistive switching layer film is formed accordingly.

[0089] In this application, HfSiO, HfTaO, HfZrO, and HfAlO comprise composite oxide films formed by alternating deposition of the corresponding metal oxides. The composite resistive switching layer thin film is used as resistive switching layer 7.

[0090] Preparation Example 3: This preparation example provides a method for preparing a composite dielectric film, including the following steps: A wafer with a bottom metal layer 1 is provided and placed in a PECVD reaction chamber. The PECVD reaction chamber is evacuated, and the wafer temperature is controlled at 100–400°C, while the chamber pressure is controlled at 0.1–10 Torr.

[0091] A silicon-containing precursor, a carbon-containing precursor, and a nitrogen-containing gas are introduced into the PECVD reaction chamber, and an NDC layer is deposited on the bottom metal layer 1 under plasma conditions. During deposition, the RF power is 10–2000 W. The silicon-containing precursor is one of silane, disilane, or an organosilicon precursor; the carbon-containing precursor is one of a carbon-silicon source, a hydrocarbon gas, or an organosilicon precursor; and the nitrogen-containing gas is NH3, N2, or a combination of both.

[0092] After the NDC layer is formed, a PEOX layer is deposited on top of the NDC layer. During the deposition of the PEOX layer, a silicon-containing precursor and an oxygen-containing gas are introduced into the PECVD reaction chamber to form a plasma-enhanced silicon oxide dielectric film under plasma conditions. The oxygen-containing gas is O2, N2O, or a combination of both. The NDC layer and the PEOX layer together constitute the bottom electrode-bottom metal interlayer insulating layer 2, and the total thickness of the bottom electrode-bottom metal interlayer insulating layer 2 is 150–2000 Å.

[0093] After forming the columnar device structure and sidewall protective layer 11, the wafer is placed in a PECVD reaction chamber, and a TEOS silicon oxide dielectric layer is deposited using TEOS as the silicon source. During the deposition process, the wafer temperature is 100–400°C, the chamber pressure is 0.1–10 Torr, and the RF power is 10–2000 W. TEOS refers to tetraethoxysilane, and the film obtained by depositing TEOS is a silicon oxide dielectric film.

[0094] After the TEOS silicon oxide dielectric layer is formed, an organosilicon precursor and an auxiliary reaction gas are introduced into the PECVD reaction chamber, and an OSG dielectric layer is deposited under plasma conditions. The organosilicon precursor is an organosilicon precursor for semiconductor low dielectric deposition, and the auxiliary reaction gas is selected from one or more of O2, N2O, CO2, He, N2, and Ar.

[0095] The TEOS silicon oxide dielectric layer and the OSG dielectric layer together constitute the inter-device filler layer 12, and the total thickness of the inter-device filler layer 12 is 10 to 10000 Å. The inter-device filler layer 12 can also be formed into a single-layer structure using either the TEOS silicon oxide dielectric layer or the OSG dielectric layer.

[0096] Examples 1-5: Example 1: This embodiment provides a method for fabricating a 1S1R type memory device, including the following steps: A wafer with a completed lower interconnect structure is provided. Cu is deposited on the wafer using PVD to form a bottom metal layer 1 with a thickness of 1000 Å.

[0097] A bottom electrode-bottom metal interlayer insulating layer 2 is deposited on the bottom metal layer 1 using PECVD. The bottom electrode-bottom metal interlayer insulating layer 2 is an NDC / PEOX composite dielectric layer, wherein the NDC layer is disposed close to the bottom metal layer 1, and the PEOX layer is disposed on the NDC layer. The thickness of the NDC layer is 600 Å, the thickness of the PEOX layer is 900 Å, and the total thickness of the bottom electrode-bottom metal interlayer insulating layer 2 is 1500 Å.

[0098] A via photolithography pattern is formed on the bottom electrode-bottom metal interlayer insulating layer 2, and the vias are formed by dry etching, exposing the connection area of ​​the bottom metal layer 1. After removing the photoresist, a via-hole filling layer 3 is deposited in the vias. The via-hole filling layer 3 includes a Ti layer and a TiN layer, wherein the Ti layer is deposited as a contact layer on the inner wall and bottom of the via, and the TiN layer is deposited on the Ti layer and fills the via. The total deposition thickness of the via-hole filling layer 3 is 1500 Å. After deposition, the via-hole filling layer 3 is polished so that the top of the via-hole filling layer 3 is flush with the top of the bottom electrode-bottom metal interlayer insulating layer 2.

[0099] TaN was deposited by PVD on the bottom electrode-bottom metal interlayer insulating layer 2 and the via filling layer 3 to form the bottom electrode 4, which has a thickness of 100 Å.

[0100] A selector switch layer 5 with a thickness of 80 Å was formed by PVD deposition of a GeSe chalcogenide material on the bottom electrode 4. The selector switch layer 5 was formed by deposition of the selector switch layer target material obtained in Preparation Example 1.

[0101] TiN is deposited by PVD on the selector switch layer 5 to form the central electrode 6, which has a thickness of 100 Å.

[0102] HfO2 was deposited on the middle electrode 6 by ALD to form a resistive switching layer 7 with a thickness of 50 Å.

[0103] Ti was deposited on the resistive switching layer 7 by PVD to form an oxygen storage layer 8 with a thickness of 100 Å.

[0104] TiN was deposited on oxygen storage layer 8 by PVD to form top electrode 9, which has a thickness of 300 Å.

[0105] SiON is deposited on the top electrode 9 by PECVD to form an etch barrier layer 10 with a thickness of 500 Å.

[0106] A photolithographic pattern of a columnar device structure is formed on the etch barrier layer 10, and the etch barrier layer 10, top electrode 9, oxygen storage layer 8, resistive switching layer 7, middle electrode 6, selector switching layer 5, and bottom electrode 4 are sequentially etched using dry etching to form the columnar device structure. The columnar device structure includes, from bottom to top, the bottom electrode 4, selector switching layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8, top electrode 9, and etch barrier layer 10.

[0107] After the columnar device structure is formed, the wafer is etched and cleaned to remove photoresist and etching residues. Al2O3 is deposited by ALD on the sidewalls of the columnar device structure and on the exposed bottom electrode-bottom metal interlayer insulating layer 2 to form a sidewall protective layer 11 with a thickness of 50 Å.

[0108] A TEOS silicon oxide dielectric film is deposited by PECVD between adjacent columnar device structures and on top of the columnar device structures to form an inter-device filling layer 12 with a thickness of 2000 Å.

[0109] The inter-device filler layer 12 and the sidewall protective layer 11 are etched back to remove part of the inter-device filler layer 12 and part of the sidewall protective layer 11 at the top of the columnar device structure, thereby opening the top region corresponding to the connection region of the top electrode 9. In the connection region, the etch barrier layer 10 is completely or partially removed so that the subsequently formed top metal layer 14 can form an electrical connection with the top electrode 9.

[0110] OSG is deposited by PECVD over the inter-device filling layer 12 and the top region of the columnar device structure to form an inter-metal insulating layer 13 with a thickness of 20,000 Å.

[0111] A top metal connection opening is formed in the inter-metal insulating layer 13 to expose the connection area of ​​the top electrode 9. Cu is formed in the top metal connection opening to obtain a top metal layer 14. In this embodiment, a Cu seed layer is deposited by PVD followed by Cu electroplating to form the top metal layer 14, and the thickness of the top metal layer 14 is 1000 Å. The structure with the top metal layer 14 is then polished and cleaned to obtain a 1S1R type memory device.

[0112] Example 2: This embodiment provides a method for fabricating a 1S1R type memory device, including the following steps: A wafer with a completed lower interconnect structure is provided, and a bottom metal layer 1, a bottom electrode-bottom metal layer interlayer insulating layer 2, a via filling layer 3, and a bottom electrode 4 are formed according to the method of Example 1. The bottom metal layer 1 is a Cu layer with a thickness of 1000 Å; the bottom electrode-bottom metal layer interlayer insulating layer 2 is an NDC / PEOX composite dielectric layer with a total thickness of 1500 Å; the via filling layer 3 is a Ti / TiN composite conductive layer with a total deposition thickness of 1500 Å; and the bottom electrode 4 is a TaN layer with a thickness of 100 Å.

[0113] A GeAsTe chalcogenide material was deposited on the bottom electrode 4 by PVD to form a selector switch layer 5 with a thickness of 150 Å. The selector switch layer 5 was formed by deposition of the corresponding selector switch layer target material prepared by the method in Preparation Example 1.

[0114] TiN is deposited by PVD on the selector switch layer 5 to form the central electrode 6, which has a thickness of 100 Å.

[0115] HfO2 was deposited on the middle electrode 6 by ALD to form a resistive switching layer 7 with a thickness of 50 Å.

[0116] Ti was deposited on the resistive switching layer 7 by PVD to form an oxygen storage layer 8 with a thickness of 100 Å.

[0117] TiN was deposited on the oxygen storage layer 8 by PVD to form a top electrode 9 with a thickness of 300 Å. SiON was deposited on the top electrode 9 by PECVD to form an etch barrier layer 10 with a thickness of 500 Å.

[0118] The etching barrier layer 10, top electrode 9, oxygen storage layer 8, resistive switching layer 7, middle electrode 6, selector switch layer 5 and bottom electrode 4 are patterned and etched to form a columnar device structure.

[0119] Al2O3 is deposited by ALD on the sidewalls of the columnar device structure to form a sidewall protective layer 11 with a thickness of 50 Å. A TEOS silicon oxide dielectric film is deposited by PECVD between adjacent columnar device structures to form an inter-device filling layer 12 with a thickness of 2000 Å.

[0120] The inter-device fill layer 12 and the sidewall protection layer 11 are etched back to open the top region corresponding to the connection region of the top electrode 9. An OSG is deposited on top of the inter-device fill layer 12 using PECVD to form an inter-metal insulating layer 13 with a thickness of 20,000 Å.

[0121] A top metal connection opening is formed in the interlayer insulating layer 13 to expose the connection area of ​​the top electrode 9. A Cu seed layer is deposited in the top metal connection opening using PVD followed by Cu electroplating to form a top metal layer 14 with a thickness of 1000 Å. The structure with the top metal layer 14 is then ground and cleaned to obtain a 1S1R type memory device.

[0122] Example 3: This embodiment provides a method for fabricating a 1S1R type memory device, including the following steps: A wafer with a completed lower interconnect structure is provided, and a bottom metal layer 1, a bottom electrode-bottom metal layer interlayer insulating layer 2, a via filling layer 3, a bottom electrode 4, a selector switch layer 5, and a middle electrode 6 are formed according to the method of Example 1. The selector switch layer 5 is a GeSe-based chalcogenide layer with a thickness of 80 Å; the middle electrode 6 is a TiN layer with a thickness of 100 Å.

[0123] An HfTaO composite resistive switching layer 7 with a thickness of 120 Å was formed on the central electrode 6 by alternating ALD deposition cycles of Hf oxide and Ta oxide.

[0124] Ti was deposited on the resistive switching layer 7 by PVD to form an oxygen storage layer 8 with a thickness of 100 Å.

[0125] TiN was deposited on the oxygen storage layer 8 by PVD to form a top electrode 9 with a thickness of 300 Å. SiON was deposited on the top electrode 9 by PECVD to form an etch barrier layer 10 with a thickness of 500 Å.

[0126] The etching barrier layer 10, top electrode 9, oxygen storage layer 8, resistive switching layer 7, middle electrode 6, selector switch layer 5 and bottom electrode 4 are patterned and etched to form a columnar device structure.

[0127] Al2O3 is deposited by ALD on the sidewalls of the columnar device structure to form a sidewall protective layer 11 with a thickness of 50 Å. A TEOS silicon oxide dielectric film is deposited by PECVD between adjacent columnar device structures to form an inter-device filling layer 12 with a thickness of 2000 Å.

[0128] The inter-device fill layer 12 and the sidewall protection layer 11 are etched back to open the top region corresponding to the connection region of the top electrode 9. An OSG is deposited on top of the inter-device fill layer 12 using PECVD to form an inter-metal insulating layer 13 with a thickness of 20,000 Å.

[0129] A top metal connection opening is formed in the interlayer insulating layer 13 to expose the connection area of ​​the top electrode 9. A Cu seed layer is deposited in the top metal connection opening using PVD followed by Cu electroplating to form a top metal layer 14 with a thickness of 1000 Å. The structure with the top metal layer 14 is then ground and cleaned to obtain a 1S1R type memory device.

[0130] Example 4: This embodiment provides a method for fabricating a 1S1R type memory device, including the following steps: A wafer with a completed lower interconnect structure is provided, and a bottom metal layer 1, a bottom electrode-bottom metal layer interlayer insulating layer 2, a via filling layer 3, a bottom electrode 4, a selector switching layer 5, a middle electrode 6, and a resistive switching layer 7 are formed according to the method of Example 1. The selector switching layer 5 is a GeSe-based chalcogenide layer with a thickness of 80 Å; the resistive switching layer 7 is an HfO2 layer with a thickness of 50 Å.

[0131] TiOx was deposited on the resistive switching layer 7 using reactive PVD to form an oxygen storage layer 8 with a thickness of 300 Å. A Ti target was used during the deposition process, and Ar and O2 were introduced to create a reactive sputtering atmosphere. TiOx represents the titanium oxide film formed by oxygen-containing reactive sputtering.

[0132] TiN was deposited on the oxygen storage layer 8 by PVD to form a top electrode 9 with a thickness of 300 Å. SiON was deposited on the top electrode 9 by PECVD to form an etch barrier layer 10 with a thickness of 500 Å.

[0133] The etching barrier layer 10, top electrode 9, oxygen storage layer 8, resistive switching layer 7, middle electrode 6, selector switch layer 5 and bottom electrode 4 are patterned and etched to form a columnar device structure.

[0134] Al2O3 is deposited by ALD on the sidewalls of the columnar device structure to form a sidewall protective layer 11 with a thickness of 50 Å. A TEOS silicon oxide dielectric film is deposited by PECVD between adjacent columnar device structures to form an inter-device filling layer 12 with a thickness of 2000 Å.

[0135] The inter-device fill layer 12 and the sidewall protection layer 11 are etched back to open the top region corresponding to the connection region of the top electrode 9. An OSG is deposited on top of the inter-device fill layer 12 using PECVD to form an inter-metal insulating layer 13 with a thickness of 20,000 Å.

[0136] A top metal connection opening is formed in the interlayer insulating layer 13 to expose the connection area of ​​the top electrode 9. A Cu seed layer is deposited in the top metal connection opening using PVD followed by Cu electroplating to form a top metal layer 14 with a thickness of 1000 Å. The structure with the top metal layer 14 is then ground and cleaned to obtain a 1S1R type memory device.

[0137] Example 5: This embodiment provides a method for fabricating a 1S1R type memory device, including the following steps: A wafer with a completed lower interconnect structure is provided, and a bottom metal layer 1, a bottom electrode-bottom metal layer interlayer insulating layer 2, a via filling layer 3, a bottom electrode 4, a selector switching layer 5, a middle electrode 6, a resistive switching layer 7, an oxygen storage layer 8, a top electrode 9, and an etch barrier layer 10 are formed according to the method of Example 1. Specifically, the selector switching layer 5 is a GeSe-based chalcogenide layer with a thickness of 80 Å; the resistive switching layer 7 is an HfO2 layer with a thickness of 50 Å; the oxygen storage layer 8 is a Ti layer with a thickness of 100 Å; and the etch barrier layer 10 is a SiON layer with a thickness of 500 Å.

[0138] The etching barrier layer 10, top electrode 9, oxygen storage layer 8, resistive switching layer 7, middle electrode 6, selector switch layer 5 and bottom electrode 4 are patterned and etched to form a columnar device structure.

[0139] HfO2 was deposited by ALD on the sidewalls of the columnar device structure and the exposed bottom electrode-bottom metal interlayer insulation layer 2 to form a sidewall protective layer 11 with a thickness of 80 Å.

[0140] OSG is deposited by PECVD between adjacent columnar device structures and on top of the columnar device structures to form an inter-device filling layer 12 with a thickness of 3000 Å.

[0141] The inter-device fill layer 12 and the sidewall protection layer 11 are etched back to open the top region corresponding to the connection region of the top electrode 9. An OSG is deposited on top of the inter-device fill layer 12 using PECVD to form an inter-metal insulating layer 13 with a thickness of 20,000 Å.

[0142] A top metal connection opening is formed in the interlayer insulating layer 13 to expose the connection area of ​​the top electrode 9. A Cu seed layer is deposited in the top metal connection opening using PVD followed by Cu electroplating to form a top metal layer 14 with a thickness of 1000 Å. The structure with the top metal layer 14 is then ground and cleaned to obtain a 1S1R type memory device.

[0143] Comparative Examples 1-4: Comparative Example 1: Compared with Example 1, the difference is that: the selector switch layer 5 is not formed, and the middle electrode 6 is directly formed on the bottom electrode 4, while the rest are the same.

[0144] Comparative Example 2: Compared with Example 1, the difference is that the oxygen storage layer 8 is not formed, and the top electrode 9 is directly formed on the resistive switching layer 7, while the rest are the same.

[0145] Comparative Example 3: Compared with Example 1, the difference is that: no sidewall protective layer 11 is formed, and the inter-device filling layer 12 is directly filled between adjacent columnar device structures and contacts the sidewall of the columnar device structure; otherwise, they are the same.

[0146] Comparative Example 4: Compared with Example 1, the difference is that instead of using the 1S1R structure formed by stacking the bottom electrode 4, selector switch layer 5, middle electrode 6, resistive switching layer 7, oxygen storage layer 8 and top electrode 9 in sequence, a single resistive switching storage device structure is formed by stacking the bottom electrode, resistive switching layer, oxygen storage layer and top electrode in sequence. The remaining interconnection, insulation, sidewall protection and filling structures are set as in Example 1.

[0147] Test Examples 1-4: Test Example 1: Test steps: 1. Fix the wafer to be tested onto the probe stage. The probes contact the lower electrode test terminal led out from the bottom electrode 4 and the upper electrode test terminal led out from the middle electrode 6, respectively. The test environment temperature is controlled at room temperature. Before the test, the probe contact status is checked for open circuit and short circuit to eliminate test deviations caused by abnormal probe contact.

[0148] 2. A semiconductor parameter analyzer was used to apply a voltage scan to the selector unit. The scan mode was 0V, maximum positive voltage, 0V, maximum negative voltage, 0V. The voltage step was set to 0.01~0.05V, the maximum positive voltage was set to 1.5V, and the maximum negative voltage was set to -1.5V. A current limit of 50~100μA was set during the test to prevent the selector switch layer 5 from experiencing excessive current after being turned on.

[0149] 3. Record the current versus voltage curve during the forward scan. When the current moves from the low current region to the high current region, record the corresponding voltage as the turn-on voltage. Turn off the current. Select the current value at a readout voltage of 0.2V, and turn on the current. Select the current value under a 1.2V bias voltage. Select the value according to... calculate.

[0150] 4. For each type of selector switch layer 5 material, select multiple test units for repeated testing. Perform multiple voltage scans on each test unit continuously, and record the turn-on voltage, turn-off current, turn-on current, and selectivity. If no irreversible short circuit or open circuit occurs during the continuous scan, record that the test unit has repeatable selection behavior.

[0151] 5. Statistical analysis was performed on the test data obtained in Examples 1 and 2. In Example 1, the selector switching layer 5 was a GeSe chalcogenide layer with a thickness of 80 Å; in Example 2, the selector switching layer 5 was a GeAsTe chalcogenide layer with a thickness of 150 Å. Both were located between the bottom electrode 4 and the middle electrode 6, used to verify the selection feasibility of different chalcogenide selector switching layers 5 in the 1S1R structure.

[0152] Table 1 Test data of selector unit switching characteristics

[0153] in conclusion: Figure 4 In (a), the horizontal axis represents the voltage applied across the selector unit, and the vertical axis represents the current flowing through the selector unit. The vertical axis uses a logarithmic scale to simultaneously display the turn-off current under low bias and the turn-on current. Figure 4 (a) It can be seen that both Example 1 and Example 2 maintain a low current state in the low bias region and enter the conduction region after the voltage rises to near the corresponding turn-on voltage, which is consistent with the test results of turn-on voltage and turn-on current in Table 1.

[0154] Figure 4 (b) It can be seen that each test unit has 10 4The selectivity ratio of the order of magnitude indicates that the selector switch layer 5 can limit the current under low voltage conditions and provide the conduction current under turn-on conditions, which meets the requirements of the selector cell of the 1S1R type memory device for low leakage current and turn-on.

[0155] According to the data in Table 1, the selector units in Examples 1 and 2 both exhibit nonlinear conductivity characteristics of low voltage and low current, with high voltage conduction. At a readout voltage of 0.2V, the turn-off current of Example 1 is 0.38–0.56 nA, and the turn-off current of Example 2 is 0.29–0.44 nA, indicating that both GeSe and GeAsTe chalcogenide materials can limit current flow under low bias conditions.

[0156] At a bias voltage of 1.2V, the turn-on current of Example 1 is 32.8–41.9 μA, and the turn-on current of Example 2 is 22.5–28.9 μA; the corresponding selectivity ratios are 5.86 × 10⁻⁶. 4 ~1.10×10 5 and 5.11×10 4 ~9.52×10 4 The results show that the selector switch layer 5 can provide a vertical conduction path after reaching the turn-on voltage, while maintaining a low current state at low voltage, which meets the nonlinear gating requirements of 1S1R type memory devices.

[0157] In Example 1, the turn-on voltage of the switching layer 5 of the GeSe system chalcogenide selector is 0.76–0.85 V, and in Example 2, the turn-on voltage of the switching layer 5 of the GeAsTe system chalcogenide selector is 0.89–0.99 V. Both sets of data are within the range that can be triggered by an applied voltage, indicating that different material systems affect the turn-on voltage window, but do not change the basic switching behavior of the selector unit.

[0158] Since the middle electrode 6 serves as both the upper electrode of the selector unit and the lower electrode of the resistive switching memory unit, the low-voltage current-limiting characteristic of the selector unit can be applied to the subsequently connected resistive switching memory units. In the unselected or half-selected bias state, the selector switch layer 5 can limit leakage current; in the selected operation state, its turn-on current can support read and write operations of the resistive switching memory unit. Therefore, the results shown in Table 1 demonstrate the electrical feasibility of the selector unit structure design of this application.

[0159] In summary, within the thickness range of the selector switch layer 5 defined in this application, the chalcogenide selector switch layer 5 can achieve significant current nonlinear modulation between the bottom electrode 4 and the middle electrode 6. This nonlinear modulation is the basis for suppressing leakage paths when the 1S1R type memory device is used in a cross-array. The selector switch layer 5 is directly integrated inside the memory cell and forms a series stack with the resistive switching layer 7, the oxygen storage layer 8, and the top electrode 9 in the vertical direction. The test results in Table 1 correspond to this structural design.

[0160] Test Example 2: Test steps: 1. Fix the wafer to be tested onto the probe stage, ensuring that the test leads from the middle electrode 6 and the top electrode 9 are in contact with the probes. Before testing, confirm the absence of open or short circuits at the test leads using a low-voltage scan. Set the readout voltage to 0.2V, which is lower than the voltages used in subsequent Set and Reset operations.

[0161] 2. Perform initial electrical checks on the resistive switching memory cell using a semiconductor parameter analyzer. The initial scan voltage is gradually increased from 0V to a preset positive voltage, and the current limit is set to 50–100μA. If the device enters a low-resistance state during the initial scan, the initial scan is stopped, and subsequent cyclic testing begins.

[0162] 3. Apply a Set operation voltage to the resistive switching memory cell to switch it from a high-resistance state to a low-resistance state. The Set operation uses a forward voltage scan or a forward pulse, with a scan voltage range of 0–1.6V and a current limit of 50–100μA. Record the voltage corresponding to a significant increase in current as the Set voltage. .

[0163] 4. After the Set operation, read the low-resistance resistance RLRS of the resistive variable memory cell with a readout voltage of 0.2V. The readout process uses a small-signal test, and the readout current does not exceed the current limit in the Set operation to avoid changes in resistance state caused by the readout process.

[0164] 5. Apply a Reset operation voltage to the resistive variable memory cell to switch it from a low-resistance state to a high-resistance state. The Reset operation uses a negative voltage scan or a negative pulse, with a scan voltage range of 0 to -1.5V. Record the voltage corresponding to the current decrease and entry into the high-resistance state as the Reset voltage. .

[0165] 6. After the Reset operation, read the high-resistivity resistance RHRS of the resistive variable memory cell using a readout voltage of 0.2V. Calculate the resistance window according to RHRS / RLRS. Select multiple test cells for each embodiment and perform tests, and statistically analyze the results. , Low-resistivity resistance, high-resistivity resistance, and resistance window.

[0166] 7. In Example 1, the resistive switching layer 7 is an HfO2 layer and the oxygen storage layer 8 is a Ti layer; in Example 3, the resistive switching layer 7 is an HfTaO composite resistive switching layer and the oxygen storage layer 8 is a Ti layer; in Example 4, the resistive switching layer 7 is an HfO2 layer and the oxygen storage layer 8 is a TiOx layer. The feasibility of resistive switching under different combinations of resistive switching layer 7 and oxygen storage layer 8 was evaluated through testing of the above three sets of samples.

[0167] Table 2 Test data of resistive switching characteristics of resistive switching memory cells

[0168] in conclusion: Figure 5 In (a), the positive voltage scan corresponds to the Set process, and the negative voltage scan corresponds to the Reset process. From Figure 5 (a) As can be seen, all three embodiments showed an increase in current during the forward scan and a decrease in current during the negative scan, consistent with Table 2. and The test data are consistent, indicating that different combinations of resistive switching layer 7 and oxygen storage layer 8 can all form reversible resistive switching behavior.

[0169] Figure 5 In (b), the Reset voltage is expressed as an absolute value. The Set and Reset voltages of Example 3 are generally higher than those of Example 1, while the Set and Reset voltages of Example 4 are generally lower than those of Example 1, indicating that the material combination of the resistive switching layer 7 and the oxygen storage layer 8 affects the resistive switching voltage.

[0170] Figure 5 (c) The resistance state window is calculated according to RHRS / RLRS. Examples 1, 3 and 4 all have distinguishable high resistance state and low resistance state, and the resistance state window is within the readable range, indicating that the resistive variable memory cell can provide stable resistance state differentiation under 0.2V readout conditions.

[0171] According to the data in Table 2, Examples 1, 3, and 4 can all switch from a high-resistance state to a low-resistance state under a positive voltage, and from a low-resistance state to a high-resistance state under a negative voltage. Among them, Example 1... The voltage range is 1.02–1.19V. The voltage range is -0.79 to -0.97V; Example 3 The voltage range is 1.18–1.31V. The voltage range is -0.96 to -1.10V; Example 4 The voltage ranges from 0.93 to 1.11V. The voltage range is -0.69 to -0.88V. This result indicates that the above-mentioned resistive switching memory cell has measurable bidirectional resistance switching behavior.

[0172] At a readout voltage of 0.2V, the low-resistivity state resistance RLRS of Example 1 is 7.9–10.8kΩ, the high-resistivity state resistance RHRS is 0.88–1.21MΩ, and the resistance window is 81.5–153.2 mm; the low-resistivity state resistance RLRS of Example 3 is 9.2–12.7kΩ, the high-resistivity state resistance RHRS is 1.27–1.89MΩ, and the resistance window is 119.8–148.8 mm; the low-resistivity state resistance RLRS of Example 4 is 6.2–8.4kΩ, the high-resistivity state resistance RHRS is 0.68–1.02MΩ, and the resistance window is 109.7–121.4 mm. These results indicate that different combinations of resistive switching layer 7 and oxygen storage layer 8 can form distinguishable high and low resistance states, meeting the state differentiation requirements of the resistive switching memory unit.

[0173] Example 3 uses HfTaO composite resistive switching layer 7. and Compared to Example 1, the resistance is increased, and the overall high-resistivity state resistance is higher, indicating that the composite oxide resistive switching layer affects the defect distribution and conductive channel formation conditions in the resistive switching layer 7, but it can still cooperate with the Ti oxygen storage layer 8 to form reversible resistive switching behavior. Example 4, after using the TiOx oxygen storage layer 8, and The overall performance is lower than that of Examples 1 and 3, while still maintaining a readable resistive state window, indicating that the metal oxide oxygen storage layer can also participate in the oxygen-related defect regulation in the resistive switching layer 7 and form a resistive switching storage function.

[0174] In summary, the resistive switching memory cells in Examples 1, 3, and 4 all exhibit repeatable Set / Reset behavior. The resistive switching layer 7 is located between the middle electrode 6 and the oxygen storage layer 8, and the oxygen storage layer 8 is located between the resistive switching layer 7 and the top electrode 9. When an external electric field is applied between the middle electrode 6 and the top electrode 9, the resistive switching layer 7 can form different resistance states in conjunction with the oxygen storage layer 8. This test example demonstrates the basic working mechanism of the resistive switching memory cell of this application, and together with the selection mechanism of the selector unit in Test Example 1, constitutes the electrical basis of the 1S1R type memory device.

[0175] Test Example 3: Test steps: 1. Fix the wafer to be tested onto the probe stage, ensuring that the test terminals of the bottom metal layer 1 and the top metal layer 14 are in contact with the probes. Before testing, use a low-voltage scan to check the connection status of the test terminals, eliminating test units with open circuits, short circuits, or unstable probe contact.

[0176] 2. Apply a Set pulse to each test unit to bring the device into a low-resistance state. The Set pulse is applied to the top metal layer 14 and the bottom metal layer 1 is grounded. The Set pulse amplitude is set to 1.1–1.7V according to the response of different samples, the pulse width is set to 1μs, and the current limit is set to 100μA.

[0177] 3. After the Set operation, apply a readout voltage to read the low-resistance current. Set the readout voltage to 1.2V and the readout pulse width to 10μs. Record the selected low-resistance readout current under these conditions. LRS. This readout voltage is used to put the selector switch layer 5 in embodiments 1-5 into a conduction state and to read the low-resistance response of the series resistive variable memory cell.

[0178] 4. Apply a Reset pulse to the same test unit to bring the device into a high-impedance state. The Reset pulse is applied to the top metal layer 14, and the bottom metal layer 1 is grounded. The Reset pulse amplitude is set to -0.9 to -1.4V according to the response of different samples, and the pulse width is set to 1μs.

[0179] 5. After the Reset operation, use a 1.2V readout voltage to read the high-impedance current. HRS. Low-resistance readout current and high-resistance readout current are used to evaluate the readout window of a complete 1S1R type memory device.

[0180] 6. After rewriting the test unit to the low-impedance state, apply a half-select voltage to perform a leakage current test. The half-select voltage is set to 0.6V, and the pulse width is set to 10μs. Half-select leakage current... Measured under low-resistance conditions, it is used to characterize the leakage risk when unselected or half-selected cells in a cross array are in a low-resistance state.

[0181] 7. According to LRS / Calculate the ratio of the selected readout current to the half-select leakage current. The LRS uses the low-resistance readout current measured at a readout voltage of 1.2V as the standard. The leakage current measured at a half-selection voltage of 0.6V is used as the standard.

[0182] 8. Multiple test units were selected for each sample group for repeated testing. Examples 1-5 were used to evaluate the complete device read / write characteristics under different combinations of selector switching layer 5, resistive switching layer 7, oxygen storage layer 8, sidewall protection layer 11 and inter-device filling layer 12; Comparative Example 1 was used to evaluate the half-select leakage current when the selector switching layer 5 was not provided.

[0183] Table 3. Overall device read / write and half-select leakage current test data for 1S1R

[0184] in conclusion: Figure 6 (a) The readout current in the low-to-medium impedance state is displayed in nA, calculated from the μA-level readout current in Table 3. Figure 6 (a) It can be seen that there is a distinguishable current difference between the low-resistance readout current and the high-resistance readout current in Examples 1 to 5, indicating that the selector unit and the resistive variable storage unit can still complete the resistive readout after being connected in series. Although Comparative Example 1 also has high and low resistance state differences, it cannot reflect the half-select leakage current suppression capability.

[0185] Figure 6 (b) The half-selection leakage current of Examples 1 to 5 is below nA to about 1nA, while the half-selection leakage current of Comparative Example 1 is in the range of several thousand nA. This shows that after setting the selector switch layer 5, the complete 1S1R type memory device has a significant current limiting effect under half-selection conditions.

[0186] Figure 6 (c) In Examples 1-5, the Iread,LRS / Ihalf ratio is 10 4 Magnitude, compared to Example 1 LRS / A ratio of less than 10 indicates that Examples 1-5 have a clear current distinction between the selected and half-selected states; while Comparative Example 1, which does not have a selector switch layer 5, still generates a large current in the low-resistivity state under the half-selected voltage.

[0187] According to the data in Table 3, Examples 1-5 can all achieve switching between low-resistance and high-resistance states of the complete device through Set and Reset pulses. At a readout voltage of 1.2V, the low-resistance readout current of Examples 1-5 is 18.9-31.5μA, and the high-resistance readout current is 54-112nA. There is a distinguishable current window between the two, indicating that the resistance state of the resistive switching memory cell can be read through the top metal layer 14 and the bottom metal layer 1.

[0188] At a half-select voltage of 0.6V, the half-select leakage current of Examples 1-5 is 0.38-1.02nA. This half-select voltage is lower than the turn-on voltage range of the selector switch layer 5 in Test Example 1. Therefore, the current of the complete 1S1R device in the half-select state is mainly limited by the selector switch layer 5. Among them, Examples 1 and 2 use different chalcogenide selector switch layers 5, and the half-select leakage currents are 0.54-0.62nA and 0.38-0.46nA, respectively. This shows that the material of the selector switch layer 5 affects the half-select leakage current level, but both can achieve half-select current limiting.

[0189] Comparative Example 1, which lacks a selector switch layer 5, exhibits a 0.6V half-select leakage current of 5200–6700 nA, significantly higher than Examples 1–5. Although Comparative Example 1 shows a low-resistivity readout current of 43.2–46.8 μA, indicating that the resistive switching structure alone can achieve a conducting state, it lacks a nonlinear current-limiting layer connected in series with the resistive switching memory cell under half-select conditions. Consequently, the low-resistivity cell is prone to generating a large leakage current at relatively low bias voltages.

[0190] Examples 1-5 LRS / The ratio is 2.66 × 10 4 ~5.71×10 4 Compared to Comparative Example 1, the current is only 6.45 to 9.00. It can be seen that Examples 1 to 5 can provide a readout current in the selected readout state and limit the leakage current to the nA level in the half-selection state, so that there is a large distinction between the selected readout current and the half-selection leakage current; while without the selector switch layer 5, the half-selection leakage current suppression capability is significantly reduced.

[0191] In Example 3, after using the HfTaO composite resistive switching layer 7, the Set pulse amplitude and Reset pulse amplitude were improved compared to Example 1. The low-resistivity readout current was slightly lower, but the half-select leakage current remained below 1nA. This indicates that the material change of the resistive switching layer 7 mainly affects the switching voltage and readout current of the resistive switching memory cell. The selector switch layer 5 can still limit the current of the series device under the half-select voltage.

[0192] In Example 4, after using the TiOx oxygen storage layer 8, the low-resistivity readout current was 28.2–31.5 μA, the high-resistivity readout current was 105–112 nA, and the half-select leakage current was 0.83–1.02 nA. This indicates that when the oxygen storage layer 8 is a metal oxide film, the complete 1S1R device can still achieve read and write operations and maintain the half-select current limiting characteristics.

[0193] In Example 5, after replacing the sidewall protection layer 11 and the inter-device filler layer 12, the low-resistivity readout current, high-resistivity readout current, and half-select leakage current remained at the same level as in Example 1. This indicates that the material changes of the sidewall protection layer 11 and the inter-device filler layer 12 did not disrupt the core vertical series path. Their main function is to protect the sidewalls of the columnar device structure and isolate adjacent devices.

[0194] In summary, under selected read conditions, the selector switch layer 5 of the complete 1S1R type memory device of this application is in the on state, and the high and low resistance states of the resistive variable memory cell can be read; under half-select conditions, the selector switch layer 5 is in the current-limiting state, and the leakage current of the series device is limited. This result proves that by integrating the selector cell and the resistive variable memory cell in the vertical direction and using the middle electrode 6 as a common electrode, it is possible to achieve read / write and half-select leakage current control of the complete 1S1R device.

[0195] Test Example 4: Test steps: 1. Fix the wafer to be tested onto the probe stage, ensuring that the test terminals of the bottom metal layer 1 and the top metal layer 14 are in contact with the probes. Before testing, use a low-voltage scan to check for open or short circuit abnormalities in the test units, and discard test units with abnormal initial readout current.

[0196] 2. Perform Set / Reset cycle tests on each test unit. The amplitudes of the Set and Reset pulses are set according to the voltage window of the corresponding sample, enabling the test unit to switch between high-resistance and low-resistance states. Each Set operation and Reset operation is counted as one cycle. The readout voltage is set to 0.2V, and the high-resistance resistance RHRS and low-resistance resistance RLRS are read after a fixed number of cycles.

[0197] 3. Test units that have an RHRS / RLRS ratio less than 10, or that fail to complete a Set / Reset switch three times consecutively, are considered failures. Record the number of cycles completed by each test unit before reaching the failure criterion; this number serves as a cycle stability evaluation indicator.

[0198] 4. After completing 1000 Set / Reset cycles, read the RHRS and RLRS of each test unit and compare them with the RHRS and RLRS in the initial cycle to calculate the high-resistivity drift rate and low-resistivity drift rate. The high-resistivity drift rate is calculated based on the change in RHRS after the cycle relative to the initial RHRS, and the low-resistivity drift rate is calculated based on the change in RLRS after the cycle relative to the initial RLRS.

[0199] 5. Perform a hold test on the test unit that has completed 1000 cycles without failure. Write the test unit into the high-resistivity state and the low-resistivity state respectively, and hold it at 85°C for 24 hours. Then read RHRS and RLRS at a readout voltage of 0.2V, and calculate the resistance window RHRS / RLRS after the hold test.

[0200] 6. Perform read disturbance tests on the test units written to high-resistivity and low-resistivity states. Set the read disturbance voltage to 0.2V and apply 1000 read pulses continuously, then count the number of times a resistance state is misjudged during the read disturbance process.

[0201] 7. Perform a write perturbation test on the test unit. Set the write perturbation voltage to a half-select perturbation voltage lower than the Set or Reset threshold, apply 1000 perturbation pulses continuously, and count the number of times the test unit experiences unexpected resistive state switching.

[0202] 8. For each sample group, select multiple test units for testing and record the number of cycles, resistance drift rate, resistance window after holding test, number of read disturbance misjudgments, and number of write disturbance abnormal flips.

[0203] Table 4 Comparative test data on the impact of structural composition on storage stability

[0204] in conclusion: Figure 7 (a) The number of cycles in Examples 1, 3, 4 and 5 is 10. 5 More than 10 to nearly 10 6 The second range was significantly higher than that of Comparative Examples 2, 3 and 4, indicating that the complete 1S1R structure, oxygen storage layer 8 and sidewall protection layer 11 all contribute to improving cycle stability.

[0205] Figure 7 (b) The high-resistivity drift rate and low-resistivity drift rate of the example group are both lower than those of the comparative example group, indicating that the oxygen storage layer 8, the sidewall protection layer 11 and the 1S1R stacking method can reduce the resistance drift during the cycling process.

[0206] Figure 7 (c) The resistivity window of the embodiment group remains within the distinguishable range, while the resistivity windows of Comparative Examples 2 and 4 are significantly reduced, and Comparative Example 3 is also lower than that of the embodiment group. This result shows that the adjacent arrangement of the oxygen storage layer 8 and the resistivity switching layer 7 helps to maintain the difference between high and low resistivity states, and the sidewall protection layer 11, after covering the sidewall of the columnar device structure, helps to reduce the influence of the sidewall interface on the retention characteristics.

[0207] Figure 7 (d) The number of anomalies in the example group during 1000 read disturbances and 1000 write disturbances was low, while the number of anomalies in Comparative Examples 2, 3 and 4 increased significantly, indicating that the 1S1R type memory device of this application can maintain a relatively stable resistance state discrimination result under disturbance conditions.

[0208] According to the data in Table 4, the number of cycles before failure for Examples 1, 3, 4, and 5 was 6.7 × 10⁻⁶. 5 ~9.4×10 5 Comparative Example 2 is 1.6 × 10⁻⁶. 5 ~1.9×10 5 The second example, Comparative Example 3, is 2.4 × 10⁻⁶. 5 ~2.8×10 5 Next, Comparative Example 4 is 7.5 × 10 4 ~9.2×10 4This result demonstrates that the complete 1S1R stack structure can maintain a relatively long operational cycle range during cyclic switching.

[0209] After 1000 cycles, the high-resistivity drift rate of the example group was 4.7%–7.6%, and the low-resistivity drift rate was 3.8%–6.2%; while the resistance drift rates of Comparative Examples 2, 3, and 4 were significantly increased. These results indicate that the adjacent arrangement of the oxygen storage layer 8 and the resistive switching layer 7 is beneficial for regulating the migration of oxygen-related defects during the resistive switching process; and that the sidewall protection layer 11, after covering the sidewall of the columnar device structure, prevents the sidewall interfaces of the selector switching layer 5, the resistive switching layer 7, and the oxygen storage layer 8 from being directly exposed to the filling medium, thereby reducing resistance drift during cycling.

[0210] After being held at 85°C for 24 hours, the resistance window of the first example group was 79.5–126.9 mm, that of Comparative Example 2 was 11.8–14.6 mm, that of Comparative Example 3 was 31.5–38.7 mm, and that of Comparative Example 4 was 7.9–8.6 mm. These results demonstrate that the resistive switching memory cell of this application can still retain readable high and low resistance state differences under holding conditions; without the oxygen storage layer 8 or the sidewall protective layer 11, the resistance window after holding is significantly reduced.

[0211] In the disturbance test, the number of read disturbance misjudgments in the example group was 0-2 times per 1000 times, and the number of write disturbance abnormal flips was 1-3 times per 1000 times, both significantly lower than those in the comparative example group. This result indicates that when the selector switch layer 5 is connected in series with the resistive switching memory cell, it can limit the current passing through the resistive switching memory cell under low voltage disturbances; the oxygen storage layer 8 and the sidewall protection layer 11 also help reduce resistive drift and abnormal flips under disturbance conditions.

[0212] In Example 3, when the HfTaO composite resistive switching layer 7 is used, the number of cycles and the resistive state window after holding are at a relatively high level in the example group, indicating that the composite oxide resistive switching layer 7 can be used as an optional implementation method for the resistive switching memory cell of this application. In Example 4, when the TiOx oxygen storage layer 8 is used, its stability is still significantly better than that of Comparative Example 2 without the oxygen storage layer 8, indicating that the metal oxide oxygen storage layer can also participate in the regulation of the resistive switching state. In Example 5, after replacing the sidewall protection layer 11 and the inter-device filler layer 12, the cycle stability and disturbance test results are still within the range of the example group, indicating that different sidewall protection and filler materials can be stacked in conjunction with the core 1S1R function.

[0213] In summary, the storage stability of this application's solution stems from the synergistic effect of multiple structural layers: the selector switching layer 5 provides series current limiting, the resistive switching layer 7 provides resistance state switching, the oxygen storage layer 8 participates in oxygen-related regulation, the sidewall protection layer 11 covers the sidewalls of the columnar device structure, and the inter-device filling layer 12 achieves isolation between adjacent devices. Comparative Examples 2, 3, and 4, which removed key structures, showed lower cycle counts, resistance drift, hold window, and perturbation results compared to the example group, indicating that the 1S1R type storage device of this application can improve storage stability through the synergistic arrangement of the selector unit, resistive switching storage unit, and sidewall protection structure.

Claims

1. A 1S1R type storage device, characterized in that, It includes a bottom electrode (4), a selector switch layer (5), a middle electrode (6), a resistive switching layer (7), an oxygen storage layer (8), and a top electrode (9) arranged sequentially from bottom to top. The bottom electrode (4), the selector switch layer (5) and the middle electrode (6) constitute a selector unit, and the middle electrode (6), the resistive switching layer (7), the oxygen storage layer (8) and the top electrode (9) constitute a resistive switching memory unit. The middle electrode (6) is a common electrode of the selector unit and the resistive switching memory unit. The thickness of the selector switching layer (5) is 10–500 Å, the thickness of the resistive switching layer (7) is 10–200 Å, and the thickness of the oxygen storage layer (8) is 10–500 Å.

2. The 1S1R type storage device according to claim 1, characterized in that, The material of the selector switch layer (5) is selected from one or more of GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO. The resistive switching layer (7) is made of one or more of the following materials: HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, WO3, HfSiO, HfTaO, HfZrO, and HfAlO. The material of the oxygen storage layer (8) is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON.

3. The 1S1R type storage device according to claim 1, characterized in that, The material of the bottom electrode (4) is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON, and the thickness of the bottom electrode (4) is 10 to 1500 Å. The material of the middle electrode (6) is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON, and the thickness of the middle electrode (6) is 10 to 1500 Å. The material of the top electrode (9) is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiOx, TaOx, HfOx, ZrOx, AlOx, WOx, NiOx, TiN, TaN, AlN, TiON, TaON, and AlON, and the thickness of the top electrode (9) is 10 to 500 Å.

4. A 1S1R type storage device according to claim 1, characterized in that, It also includes a bottom metal layer (1), a bottom electrode-bottom metal layer interlayer insulating layer (2), and a via filling layer (3). The bottom electrode-bottom metal interlayer insulating layer (2) is disposed between the bottom metal layer (1) and the bottom electrode (4), and the through hole filling layer (3) is disposed in the bottom electrode-bottom metal interlayer insulating layer (2) and is electrically connected to the bottom metal layer (1) and the bottom electrode (4) respectively. The material of the bottom electrode-bottom metal interlayer insulation layer (2) is selected from one or more of SiO2, NDC, and PEOX, and the thickness of the bottom electrode-bottom metal interlayer insulation layer (2) is 150 to 2000 Å. The material of the via filling layer (3) is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, TiN, TaN, AlN, TiON, TaON, and AlON, and the thickness of the via filling layer (3) is 150 to 2000 Å.

5. A 1S1R type storage device according to claim 1, characterized in that, It also includes an etching barrier layer (10), a sidewall protection layer (11), an inter-device filling layer (12), an inter-metal insulating layer (13), and a top metal layer (14). The etching barrier layer (10) is disposed on the top electrode (9), the sidewall protection layer (11) is disposed on the sidewalls of the bottom electrode (4), the selector switch layer (5), the middle electrode (6), the resistive switching layer (7), the oxygen storage layer (8), the top electrode (9) and the etching barrier layer (10), the inter-device filling layer (12) is disposed between adjacent sidewall protection layers (11), the inter-metal insulating layer (13) is disposed above the inter-device filling layer (12), and the top metal layer (14) is disposed in the inter-metal insulating layer (13) and electrically connected to the top electrode (9); The material of the etching barrier layer (10) is selected from one or more of SiON, Si3N4, and PEOX, and the thickness of the etching barrier layer (10) is 100 to 5000 Å. The material of the sidewall protective layer (11) is selected from one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and TEOS, and the thickness of the sidewall protective layer (11) is 10 to 500 Å. The material of the inter-device filling layer (12) is selected from one or more of TEOS and OSG, and the thickness of the inter-device filling layer (12) is 10 to 10000 Å. The material of the metal interlayer insulation layer (13) is OSG, and the thickness of the metal interlayer insulation layer (13) is 100 to 50,000 Å.

6. A method for fabricating a 1S1R type memory device, characterized in that, The preparation of a 1S1R type memory device as described in any one of claims 1-5 includes the following steps: Deposit a selector switch layer (5) on the bottom electrode (4); A central electrode (6) is deposited on the selector switch layer (5); A resistive switching layer (7) is deposited on the central electrode (6); An oxygen storage layer (8) is deposited on the resistive switching layer (7); A top electrode (9) is deposited on the oxygen storage layer (8).

7. The preparation method according to claim 6, characterized in that, The selector switch layer (5) is deposited using ALD, PVD or PECVD. The resistive switching layer (7) is deposited using ALD, PVD or PECVD; The oxygen storage layer (8) is deposited using PVD.

8. The preparation method according to claim 6, characterized in that, Before depositing the selector switch layer (5), a bottom metal layer (1) is formed, and a bottom electrode-bottom metal layer interlayer insulating layer (2) is deposited on the bottom metal layer (1) by PECVD. A through hole is formed in the bottom electrode-bottom metal interlayer insulating layer (2), a through hole filling layer (3) is deposited in the through hole, and the through hole filling layer (3) is ground so that the top of the through hole filling layer (3) is flush with the top of the bottom electrode-bottom metal interlayer insulating layer (2); The bottom electrode (4) is deposited by PVD on the bottom electrode-bottom metal interlayer insulating layer (2) and the via filling layer (3).

9. The preparation method according to claim 6, characterized in that, After depositing the top electrode (9), an etch barrier layer (10) is deposited using PECVD. The etching barrier layer (10), the top electrode (9), the oxygen storage layer (8), the resistive switching layer (7), the middle electrode (6), the selector switch layer (5) and the bottom electrode (4) are etched to form a columnar device structure; A protective layer (11) is deposited on the sidewall of the columnar device structure using ALD or PECVD.

10. The preparation method according to claim 9, characterized in that, After the sidewall protective layer (11) is formed, an inter-device fill layer (12) is deposited between adjacent columnar device structures using PECVD. The inter-device filling layer (12) and the sidewall protective layer (11) are etched back to expose the connection area of ​​the top electrode (9); A metal interlayer insulating layer (13) is deposited by PECVD above the inter-device filling layer (12). A top metal layer (14) is formed in the inter-metal insulating layer (13) to electrically connect the top metal layer (14) to the top electrode (9).

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