Integrated mask circuit generation and detection method and platform

Abstract

This invention belongs to the field of integrated mask circuit generation technology, and provides a method and platform for generating and detecting integrated mask circuits. The method involves obtaining an S-box configuration file, parsing it, extracting the S-box, generating hardware circuits from the extracted S-box, and obtaining an S-box file. A test environment is constructed based on the S-box file, and corresponding test stimulus files are generated. Behavioral-level simulation is performed in the test environment, and simulation logs are recorded. The simulation logs are parsed to determine whether the S-box design is functionally correct. The RTL-level design of the S-box file is converted into a gate-level netlist based on the target technology library, generating a netlist file and an area report. Timing verification and power estimation are performed under preset timing and load constraints, generating timing and power reports respectively. Multiple reports are synthesized, key performance indicators are extracted, structured, and a comprehensive evaluation report is generated. This invention can improve the design efficiency, reliability, and overall performance of mask circuits.

Description

Technical Field

[0001] This invention belongs to the field of integrated mask circuit generation technology, specifically relating to an integrated mask circuit generation and detection method and platform. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] With the rapid development of IoT technology, a large number of connectable devices have been widely used in daily life. Due to their easy accessibility, these devices are facing various physical attacks, especially side-channel attacks. These attacks extract sensitive data from within the device by analyzing its power consumption, electromagnetic radiation, temperature, and other physical information during operation. To defend against side-channel attacks, researchers have proposed various protective measures, among which masking schemes have gained widespread application due to their provable theoretical basis. Masking schemes sever the correlation between secret data and device energy consumption by making the intermediate values ​​of the algorithm independent of the secret variables. Threshold implementation was the first masking strategy applicable to hardware platforms. Subsequently, to reduce random number and area overhead while resisting attacks, various efficient masking schemes, such as unified masking schemes and domain-oriented masks, have been proposed. Following this, to further characterize physical effects in actual hardware (such as glitches, signal flips, and coupling), robust detection models were introduced, providing more practical theoretical guidance for the design and implementation of masking schemes.

[0004] However, designing secure and efficient masking schemes for complex, large-scale circuits remains a significant challenge, as the process is highly dependent on expertise and consumes substantial computational resources. To address this, the concept of PINA security was proposed. Based on a divide-and-conquer strategy, small PINA components can be easily combined into large-scale secure circuits. Currently, most PINA components only support two-input multiplication (such as HPC1, HPC2, etc.). While they can be combined to implement complex circuits, they often introduce multi-cycle delays, limiting their application in low-latency scenarios. To solve the latency problem, GHPCLL was proposed, becoming the first first-order PINA secure component capable of constructing arbitrary single-cycle circuits. Building upon this, Time-Shared Masking (CMS) further improves the hardware's efficiency in terms of randomness and area while maintaining low latency. To further optimize performance, the academic community has recently proposed a novel method for constructing low-latency first-order PINA components—Mirror Circuit Masking (MCM). While maintaining low latency, this scheme demonstrates significant advantages in key metrics such as random number consumption and circuit area, and can be extended to arbitrary Boolean functions, providing a more efficient implementation path for the practical application of masking technology.

[0005] However, existing advanced masking technologies (such as MCM) face an engineering gap in their transition from theoretical methods to engineering practice. Their design concepts currently remain largely at the theoretical description level, lacking an automated and standardized implementation process covering component description to the final hardware solution, and also lacking corresponding toolchain support. This makes it difficult to quickly and reliably translate their high-efficiency and secure characteristics into actual circuits. Simultaneously, how to conduct complete and reliable functional verification and performance evaluation of masked protection circuits remains a complex and critical problem that urgently needs to be solved. Currently, the verification and evaluation processes for such hardware security circuits typically suffer from the following shortcomings: fragmented processes that heavily rely on manual labor, are cumbersome, error-prone, and inefficient; functional verification and performance evaluation heavily depend on specific commercial EDA tools, with high costs and compliance barriers hindering the technology's widespread adoption and application; furthermore, the functional verification, logic synthesis, and physical performance analysis stages are disconnected from each other, failing to form a collaborative closed loop, making it difficult for designers to comprehensively and in real-time weigh performance and resource consumption, thus limiting the system's overall optimization capabilities. Summary of the Invention

[0006] To address the aforementioned problems, this invention proposes an integrated mask circuit generation and detection method and platform. This invention can automate the entire process from algorithm description to secure hardware implementation and performance evaluation, providing support for systematically improving the design efficiency, reliability, and overall performance of mask circuits.

[0007] According to some embodiments, the present invention adopts the following technical solution: A method for generating and detecting integrated mask circuits includes the following steps: Obtain the S-box configuration file, parse it, extract the S-box, generate hardware circuits for the extracted S-box, and obtain the masked S-box file. A test environment is built for the S-box file, and a corresponding test stimulus file is generated. Behavioral-level simulation is performed in the test environment, and simulation logs are recorded. Analyze the simulation logs to determine if the S-box design is functionally correct. The RTL-level design of the S-box file is converted into a gate-level netlist based on the target technology library, generating a netlist file and an area report. Based on the generated netlist file, timing verification and power consumption estimation are performed under preset timing and load constraints, generating timing reports and power consumption reports respectively. Based on the area report, timing report, and power consumption report, key performance indicators are extracted, structured, and a comprehensive evaluation report is generated.

[0008] As an alternative implementation, the process of obtaining and parsing the S-box configuration file includes reading the S-boxes from the S-box configuration file and storing them in a list.

[0009] As an alternative implementation, the process of generating hardware circuits for the extracted S-box includes generating hardware circuits for the S-box using a mirror circuit masking algorithm.

[0010] As an alternative implementation, the process of building a test environment for the S-box file includes: calling a testbench template to fill in the script, filling in the parameters of the S-box module name, port list, and stimulus file path into the testbench template, generating a complete testbench file, and using the command-line interface of the simulation tool Iverilog to call the script to compile the design file and start the simulation.

[0011] As an optional implementation method, the process of parsing the simulation log and determining whether the S-box design is functionally correct includes: reading the log file, counting the number of failed stimuli, and if the number of failures is 0, the function is determined to be correct, the verification is passed, and the process proceeds to the next stage; otherwise, an error report is output, listing the detailed information of all failed stimuli, indicating that the masking scheme is functionally incorrect, and the process is terminated.

[0012] As an alternative implementation, the process of converting the RTL-level design of the S-box file into a gate-level netlist based on the target technology library and generating a netlist file and area report includes: filling the technology library file and the masked S-box file path into the synthesis analysis script template to generate a corresponding synthesis script; using the synthesis script to read the S-box file and analyze the hierarchical structure of the design modules; then performing general logic synthesis to convert the RTL-level design into a gate-level netlist based on the target technology library; using the ABC tool to perform combinational logic optimization and mapping to standard cells, and simultaneously outputting the netlist file and area report.

[0013] As an alternative implementation, based on the generated netlist file, timing verification and power estimation are performed under preset timing and load constraints, generating timing reports and power reports respectively. Based on the generated netlist file, the static timing analysis tool OpenSTA is called to perform timing verification and power estimation under preset timing and load constraints, generating timing reports and power reports respectively, thus completing a multi-dimensional automated evaluation of the mask circuit performance.

[0014] As an alternative implementation, the process of extracting key performance indicators based on the area report, timing report, and power consumption report includes reading the chip area, worst-case setup time margin, and total power consumption from the three reports respectively as key performance indicators.

[0015] As an alternative implementation method, the process of performing structured processing to generate a comprehensive evaluation report includes: integrating the extracted key performance indicators with information such as design name, process library, and constraints to generate a comprehensive evaluation report containing this information.

[0016] An integrated mask circuit generation and detection platform, comprising: The mask protection module is configured to obtain the S-box configuration file, parse it, extract the S-box, generate hardware circuits from the extracted S-box, and obtain the masked S-box file. The functional simulation module is configured to build a test environment for the S-box file, generate a corresponding test stimulus file, perform behavioral-level simulation in the test environment, and record simulation logs. The logic synthesis and analysis module is configured to parse simulation logs and determine whether the S-box design is functionally correct; convert the RTL-level design of the S-box file into a gate-level netlist based on the target technology library, generate a netlist file and an area report; and perform timing verification and power estimation under preset timing and load constraints based on the generated netlist file, generating timing reports and power reports respectively. The data integration module is configured to extract key performance indicators based on the area report, timing report, and power consumption report, perform structured processing, and generate a comprehensive evaluation report.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention provides an integrated automated platform for mask circuit generation, functional verification, and performance evaluation, realizing an automated process from high-level security description to physical implementation. It has significant engineering practical value and technical advantages. Based on cutting-edge mask theory, this invention transforms the traditional design process that relies on professional experience and manual operation into a standardized and repeatable automated process. By integrating open-source toolchains, it builds a complete mask circuit implementation and evaluation system.

[0018] This invention can automatically complete the entire process in a unified environment, from S-box input, MCM mask generation, functional simulation verification to comprehensive performance evaluation in multiple dimensions such as timing, area, and power consumption, and output a structured and quantifiable comprehensive report, which greatly improves design efficiency, reliability, and evaluation comprehensiveness.

[0019] This invention significantly reduces reliance on expensive commercial EDA tools and deep professional experience through open-source tool integration and process automation, effectively promoting the engineering implementation and widespread application of masking protection technology in a wider range of scenarios, and providing an efficient, reliable, and low-cost system-level solution for cryptographic hardware security design.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0022] Figure 1 This is a schematic diagram of an integrated mask circuit generation and detection process according to one embodiment; Figure 2 This is a schematic diagram of the mask protection stage process in one embodiment; Figure 3 This is a schematic diagram of the functional simulation stage of one embodiment; Figure 4 This is a schematic diagram of the logic synthesis and analysis phase of one embodiment; Figure 5 This is a schematic diagram of the data integration phase process in one embodiment. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] Where there is no conflict, the embodiments and features described in this application may be combined with each other.

[0027] Example 1 An integrated mask circuit generation and detection method, such as Figure 1As shown, the process comprises four stages: mask protection, functional simulation, logic synthesis and analysis, and data integration. First, in the mask protection stage, a standard configuration file is read, the S-box is automatically extracted, and the MCM masking algorithm is executed to generate a masked S-box design file. Second, in the functional simulation stage, testing and simulation are automatically performed, with a critical checkpoint—the process is only allowed to proceed to the next stage if the functional verification is completely correct. Subsequently, in the logic synthesis and performance analysis stage, open-source tools are used to sequentially complete logic synthesis (generating a netlist and area report) and static timing and power analysis (generating timing and power reports). Finally, in the data integration stage, various reports are automatically parsed, key indicators are extracted, and synthesized into a unified and comprehensive integrated performance evaluation report. Finally, the S-box mask circuit and the integrated performance evaluation report are output. This process achieves a fully automated closed-loop from mask design implementation to comprehensive evaluation.

[0028] The following is a detailed introduction.

[0029] Phase 1: Masking Protection Phase like Figure 2 As shown, this stage takes the S-box as input, processes it through the MCM protection algorithm, and outputs the protected S-box. The specific implementation process includes the following steps: S-Box Configuration File Parsing: First, the S-Box configuration file Sbox.swcfg, conforming to a custom format, is read. The platform uses regular expressions to match the file content, extracting the hexadecimal numerical strings and bit width values ​​within square brackets. Then, the numerical strings are split by commas, and each hexadecimal string is converted into an integer, which is then stored sequentially in a list as the S-Box lookup table. Simultaneously, the length of the list is checked to ensure it is a power of 2 (the bit width). If a mismatch is found, an error is reported and the process terminates to ensure data accuracy.

[0030] Hardware Circuit Generation: The built-in Mirror Circuit Masking (MCM) algorithm is used to generate the hardware circuit for the S-box. This algorithm first determines the number of mask bits based on the S-box input bit width and adds a random mask layer to each input / output signal. Then, based on the S-box lookup table, it generates a masked S-box logic expression that conforms to the PINI characteristics through algebraic transformation or lookup table reconstruction methods. Finally, the logic expression is described using Verilog, and the mask register and random number generation interface are instantiated. The output is a masked S-box file, Sbox_ANF_PINI.v, that conforms to design specifications, thus completing the automated conversion from algorithm description to secure hardware design.

[0031] Phase Two: Functional Simulation Phase like Figure 3As shown, this stage performs functional verification on the masked S-box design to determine whether to proceed to the next stage. The specific implementation steps of the platform are as follows: Automatic test environment construction: Based on the generated Sbox_ANF_PINI.v, the platform calls the test template engine. This engine pre-stores standard testbench templates (including modules for clock generation, reset control, stimulus reading, and result comparison). By replacing the module names, port lists, and stimulus file paths in the template, the corresponding test stimulus file Sbox_ANF_PINI_tb.v is generated.

[0032] Test stimulus generation: Based on the S-box input bit width, the platform automatically generates an ergodic test vector (if bit width ≤ 8) or a random test vector (if bit width > 8). For masked S-boxes, the stimulus generation module randomly generates a mask value for each plaintext input, calculates the masked input, and generates the desired output according to the masking algorithm rules (e.g., the output should be the XOR of the original S-box output and the mask value). All stimuli and desired outputs are written to a stimulus file in text format.

[0033] Behavioral simulation and logging: The platform calls the open-source simulation tool Iverilog, compiles the design file and testbench via command line, and executes behavioral simulation. During the simulation, the testbench reads the stimulus file, applies stimuli one by one, records the comparison results between the actual output and the expected output, and writes the input, expected output, actual output, and comparison status of each stimulus to the simulation log sim.log.

[0034] Functionality Correctness Verification: The platform's built-in log parsing script reads sim.log and counts the number of failed incentives. If the failure count is 0, the function is considered correct, verification passes, and the process proceeds to the next stage; otherwise, an error report is output, listing detailed information on all failed incentives and displaying the message "Mask scheme functionality error," terminating the process.

[0035] Phase Three: Logical Synthesis and Analysis like Figure 4 As shown, this stage takes a masked S-box file and a synthesis and analysis script automatically generated by the platform as input. After logic synthesis and performance analysis, it finally outputs three key performance reports: area, timing, and power consumption. The specific implementation steps are as follows: Automatic synthesis script generation: The platform automatically generates the synthesis script synth.tcl based on preset parameters such as the target technology library path, clock cycle constraints (e.g., 2ns), and input / output loads. The script content includes: reading the design file, specifying the top-level module, setting timing constraints, performing logic synthesis, and outputting the gate-level netlist and area report.

[0036] Logic Synthesis: The open-source synthesis tool Yosys is invoked, and the `synth.tcl` script is executed. Yosys first reads the RTL-level design `Sbox_ANF_PINI.v` and then uses the built-in command (`synth -top`) to synthesize the code. <top>The high-level synthesis is performed, then mapped to the target process library cell, and finally the gate-level netlist Sbox_ANF_PINI_synthesis.v is output, and the area report area.rpt is generated simultaneously.

[0037] Timing Verification and Power Estimation: Based on the generated netlist file, the platform calls the open-source static timing analysis tool OpenSTA. First, an STA script is automatically generated, setting the same clock constraints, input / output delays, and environmental conditions (such as operating voltage and temperature). Then, static timing analysis is performed to extract the setup time slack of the worst path, generating a timing report (timing.rpt). Next, using OpenSTA's power estimation function, based on the netlist and switch activity rate (which can assume the default toggle rate or be obtained from simulation), dynamic power consumption and leakage power consumption are calculated, generating a power report (power.rpt). This completes the multi-dimensional automated evaluation of the mask circuit performance.

[0038] Phase Four: Data Integration Phase like Figure 5 As shown, this stage takes three analysis reports—area, timing, and power consumption—as input. The platform's built-in report parsing engine automatically extracts key performance indicators (KPIs), integrates and structures them, and finally outputs a complete comprehensive evaluation report, Mask.rpt. The specific implementation steps are as follows: "Chip area," "slack," and "Total Power" are read from the three reports as KPIs. Then, the extracted KPIs are integrated with information such as design name, process library, and constraints to generate a comprehensive evaluation report containing this information.

[0039] Example 2 An integrated mask circuit generation and detection platform, comprising: The mask protection module is configured to obtain the S-box configuration file, parse it, extract the S-box, generate hardware circuits from the extracted S-box, and obtain the masked S-box file. The functional simulation module is configured to build a test environment for the S-box file, generate a corresponding test stimulus file, perform behavioral-level simulation in the test environment, and record simulation logs. The logic synthesis and analysis module is configured to parse simulation logs and determine whether the S-box design is functionally correct; convert the RTL-level design of the S-box file into a gate-level netlist based on the target technology library, generate a netlist file and an area report; and perform timing verification and power estimation under preset timing and load constraints based on the generated netlist file, generating timing reports and power reports respectively. The data integration module is configured to extract key performance indicators based on the area report, timing report, and power consumption report, perform structured processing, and generate a comprehensive evaluation report.

[0040] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of one or more computer-usable storage media (including, but not limited to, disk storage, etc.) containing computer-usable program code. CD - ROM It takes the form of a computer program product implemented on (such as optical memory, etc.).

[0041] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0042] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0043] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made by those skilled in the art without creative effort within the spirit and principles of the present invention should be included within the scope of protection of the present invention.< / top>

Claims

1. A method for generating and detecting integrated mask circuits, characterized in that, Includes the following steps: Obtain the S-box configuration file, parse it, extract the S-box, generate hardware circuits for the extracted S-box, and obtain the masked S-box file. A test environment is built for the S-box file, and a corresponding test stimulus file is generated. Behavioral-level simulation is performed in the test environment, and simulation logs are recorded. Analyze the simulation logs to determine if the S-box design is functionally correct. The RTL-level design of the S-box file is converted into a gate-level netlist based on the target technology library, generating a netlist file and an area report. Based on the generated netlist file, timing verification and power consumption estimation are performed under preset timing and load constraints, generating timing reports and power consumption reports respectively. Based on the area report, timing report, and power consumption report, key performance indicators are extracted, structured, and a comprehensive evaluation report is generated.

2. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of obtaining and parsing the S-box configuration file involves reading the S-boxes from the configuration file and storing them in a list.

3. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of generating hardware circuits for the extracted S-box includes generating hardware circuits for the S-box using a mirror circuit masking algorithm.

4. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of building a test environment for the S-box file includes: calling the testbench template to fill in the script, filling in the parameters of S-box module name, port list, and stimulus file path into the testbench template, generating a complete testbench file, and using the command-line interface of the simulation tool Iverilog to call the script to compile the design file and start the simulation.

5. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of parsing simulation logs to determine whether the S-box design is functionally correct includes: reading the log file, counting the number of failed stimuli; if the number of failures is 0, the function is considered correct, the verification is passed, and the process proceeds to the next stage; otherwise, an error report is output, listing detailed information of all failed stimuli, indicating that the masking scheme is functionally incorrect, and the process is terminated.

6. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of converting the RTL-level design of the S-box file into a gate-level netlist based on the target technology library and generating a netlist file and area report includes: filling the technology library file and the masked S-box file path into the synthesis analysis script template to generate the corresponding synthesis script; using the synthesis script to read the S-box file and analyze the hierarchical structure of the design modules; then performing general logic synthesis to convert the RTL-level design into a gate-level netlist based on the target technology library; using the ABC tool to perform combinational logic optimization and mapping to standard cells, and simultaneously outputting the netlist file and area report.

7. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, Based on the generated netlist file, timing verification and power estimation are performed under preset timing and load constraints, generating timing reports and power reports respectively. Based on the generated netlist file, the static timing analysis tool OpenSTA is called to perform timing verification and power estimation under preset timing and load constraints, generating timing reports and power reports respectively, completing a multi-dimensional automated evaluation of the mask circuit performance.

8. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of extracting key performance indicators based on the area report, timing report, and power consumption report includes reading the chip area, worst-case setup time margin, and total power consumption from the three reports as key performance indicators.

9. The method for generating and detecting integrated mask circuits as described in claim 1, characterized in that, The process of structuring and generating a comprehensive evaluation report includes: integrating the extracted key performance indicators with information such as design name, process library, and constraints to generate a comprehensive evaluation report containing this information.

10. An integrated mask circuit generation and detection platform, characterized in that, include: The mask protection module is configured to obtain the S-box configuration file, parse it, extract the S-box, generate hardware circuits from the extracted S-box, and obtain the masked S-box file. The functional simulation module is configured to build a test environment for the S-box file, generate a corresponding test stimulus file, perform behavioral-level simulation in the test environment, and record simulation logs. The logic synthesis and analysis module is configured to parse simulation logs and determine whether the S-box design is functionally correct. The RTL-level design of the S-box file is converted into a gate-level netlist based on the target technology library, generating a netlist file and an area report. Based on the generated netlist file, timing verification and power consumption estimation are performed under preset timing and load constraints, generating timing reports and power consumption reports respectively. The data integration module is configured to extract key performance indicators based on the area report, timing report, and power consumption report, perform structured processing, and generate a comprehensive evaluation report.

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