Chip and method for manufacturing a chip

Abstract

The application provides a chip and a preparation method of the chip. The chip comprises a substrate and a transistor. The transistor comprises a channel structure, a first electrode, a second electrode, a first doped layer and a gate. At least part of the first electrode is located on one side of the channel structure, and the first electrode is a source electrode or a drain electrode. At least part of the second electrode is located on one side of the channel structure, and the second electrode is a source electrode or a drain electrode. At least part of the first doped layer is located on one side of the channel structure, away from the first electrode and the second electrode. The gate is located on at least one side of the channel structure. By arranging at least part of the first doped layer and at least part of the electrode (the first electrode and the second electrode) on two sides of the channel structure respectively, the doped layer can more effectively dope the channel structure, the contact barrier of the channel structure is thinned, the contact resistance between the electrode and the channel structure is reduced without introducing additional parasitic effects, and the performance of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to a chip and a method for fabricating the chip. Background Technology

[0002] Channel structures have characteristics such as high carrier mobility, ultra-thin body, and ballistic transport. They have natural advantages in reducing the power consumption of silicon-based semiconductor devices and reducing parasitic effects on silicon-based semiconductor devices, and are one of the important directions for the future development and evolution of chip technology.

[0003] In chips containing channel structures, the channel structure is relatively thin (approximately 1–2 nm), making it more fragile than the bulk material and prone to Fermi level pinning (FLP). This prevents the use of ion implantation for heavy doping in the contact region, a common practice in silicon-based devices. Therefore, the contact resistance of the channel structure and the parasitic resistance of the extension region (the area between the gate and electrode) become limiting factors for the device performance of the channel structure (e.g., I0). on One of the key bottlenecks (such as variation).

[0004] Typically, doping the contact region of a channel structure can reduce its contact resistance. For example, localized solid-state doping involves depositing a dielectric material as a dopant layer on the channel structure, utilizing the fixed charge within the dielectric material itself or charge transfer at the interface with the channel structure to achieve doping. One related technique places the doped layer between the electrode and the channel structure; however, this introduces parasitic resistance, leading to a decrease in transistor operating voltage and thus affecting chip performance. Another related technique places the doped layer in the extension region, but this method has two drawbacks: first, the doped layer can only dop to the area where it contacts the electrode in the channel structure; within the transfer length (current does not only exist at the metal boundary but also has a current distribution length on the electrode), the area below the contact electrode cannot be effectively doped. Second, the contact region of the channel structure requires a higher doping level, while the extension region does not, creating a contradiction that affects chip performance.

[0005] Therefore, how to reduce the contact resistance between the electrodes and the channel structure without introducing additional parasitic effects and improve chip performance has become an urgent technical problem to be solved. Summary of the Invention

[0006] This application provides a chip and a method for fabricating the chip, which can effectively doping the channel structure in the contact area between the channel structure and the electrode, thinning the contact barrier of the channel structure, reducing the contact resistance between the electrode and the channel structure without introducing additional parasitic effects, thereby improving the performance of the chip.

[0007] In a first aspect, a chip is provided, comprising: a substrate; a transistor; the transistor comprising: a channel structure; a first electrode, at least a portion of which is located on one side of the channel structure, the first electrode being a source or a drain; a second electrode, at least a portion of which is located on one side of the channel structure, the second electrode being a source or a drain; a first doped layer, at least a portion of which is located on the side of the channel structure away from the first electrode and the second electrode; and a gate, the gate being located on at least one side of the channel structure.

[0008] In the above technical solution, by placing at least a portion of the electrode and at least a portion of the doped layer on both sides of the channel structure, special electron transport channels can be formed when the doped layer and the end face (or side face) of the channel structure come into contact. These channels have superior electron transport properties, which can significantly improve the mobility of charge carriers in the doped layer to the channel structure. This allows the doped layer to more effectively doping the channel structure, reducing the contact barrier of the channel structure. Thus, while reducing the contact resistance between the electrode and the channel structure, no additional parasitic effects are introduced. This accelerates the charge accumulation and release speed of the transistor during the switching process, improves the switching speed of the transistor, and thus improves the working efficiency of the transistor.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the first doped layer is in direct contact with the channel structure.

[0010] In conjunction with the first aspect, some implementations of the first aspect further include: a buffer layer located between the first doped layer and the channel structure.

[0011] In the above technical solution, by setting a buffer layer between the first doped layer and the channel structure, the first doped layer contacts the channel structure through the buffer layer, thereby controlling the doping concentration of the first doped layer in the region of the channel structure in contact with the electrode through the buffer layer.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the gate is located on the side of the channel structure away from the substrate; or the gate is located on both the side of the channel structure away from the substrate and the side of the channel structure close to the substrate.

[0013] In conjunction with the first aspect, some implementations of the first aspect further include: a second doped layer located on the side of the channel structure away from the gate.

[0014] In the above technical solution, the region in the channel structure that is in contact with the gate can also be doped by the second doping layer. Since the concentration of the doping material in the second doping layer is different from that in the first doping layer, the second doping layer can meet the doping requirements of the region in the channel structure that is in contact with the gate.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the position of the second doped layer is opposite to the position of the gate.

[0016] In conjunction with the first aspect, some implementations of the first aspect further include: a third doped layer located between the first doped layer and the second doped layer, or located between the first doped layer and the gate.

[0017] In conjunction with the first aspect, some implementations of the first aspect further include: a stop layer, at least a portion of which is located on the side of the channel structure away from the substrate.

[0018] In the above technical solution, by adding a stop layer on the side of the channel structure away from the substrate, the channel structure can be covered and protected.

[0019] In a second aspect, a method for fabricating a chip is provided, comprising: forming a channel structure on a substrate; forming a first electrode on one side of the channel structure, at least a portion of the first electrode being in contact with one side of the channel structure, the first electrode being a source or a drain; forming a second electrode on one side of the channel structure, at least a portion of the second electrode being in contact with one side of the channel structure, the second electrode being a source or a drain; forming a first doped layer on the side of the channel structure away from the first and second electrodes, at least a portion of the first doped layer being in contact with the side of the channel structure away from the first and second electrodes; and forming a gate on at least one side of the channel structure.

[0020] In conjunction with the second aspect, in some implementations of the second aspect, a first doped layer is formed directly on the surface of the channel structure away from the first electrode and the second electrode, such that at least a portion of the first doped layer is in direct contact with the channel structure.

[0021] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: depositing a buffer material between the first doped layer and the channel structure to form a buffer layer, such that at least a portion of the first doped layer contacts the channel structure through the buffer layer.

[0022] In conjunction with the second aspect, in some implementations of the second aspect, a channel material is deposited on the substrate to form the channel structure.

[0023] In conjunction with the second aspect, in some implementations of the second aspect, a first region for placing the first electrode is formed on the side of the channel structure away from the substrate; electrode material is deposited in the first region to form the first electrode; a second region for placing the second electrode is formed on the side of the channel structure away from the substrate; electrode material is deposited in the second region to form the second electrode; the substrate is etched to form a third region for placing the first doped layer; and doped material is deposited in the third region to form the first doped layer.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, the substrate is etched to form a first region where the first electrode is placed; electrode material is deposited in the first region to form the first electrode; the substrate is etched to form a second region where the second electrode is placed; electrode material is deposited in the second region to form the second electrode; a third region where the first doped layer is placed is formed on the side of the channel structure away from the substrate; and doped material is deposited in the third region to form the first doped layer.

[0025] In conjunction with the second aspect, in some implementations of the second aspect, a stop material is deposited across the entire side of the channel structure away from the substrate to form a stop layer, at least a portion of which contacts the side of the channel structure away from the substrate; the stop layer is etched to form the first region; and the stop layer is etched to form the second region.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: depositing a mask material over the entire surface of the stop layer to form a mask layer; etching the mask layer and the stop layer to form the first region; and etching the mask layer and the stop layer to form the second region.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, a fourth region for placing the gate is formed on the side of the channel structure away from the substrate; gate material is deposited in the fourth region to form the gate.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, a stop material is deposited across the entire side of the channel structure away from the substrate to form a stop layer; the stop layer formed on the side of the channel structure away from the substrate is etched to form the fourth region.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, a mask layer and a stop layer formed on the side of the channel structure away from the substrate are etched to form the fourth region.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: etching the substrate to form a fifth region in which the gate is placed; and depositing the gate material in the fifth region to form the gate.

[0031] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes forming a second doped layer on the side of the channel structure away from the gate.

[0032] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: forming a third doped layer between the first doped layer and the second doped layer; or forming the third doped layer between the first doped layer and the gate.

[0033] It should be understood that for the beneficial effects of the second aspect and its various implementations, please refer to the first aspect and its various implementations; they will not be repeated here.

[0034] Thirdly, a packaging structure is provided, the packaging structure including a substrate and a chip in the first aspect and any implementation thereof, or a chip prepared according to the second aspect and any implementation thereof.

[0035] Fourthly, an electronic device is provided, including a circuit board and the chip of the third aspect, the chip being disposed on the circuit board and electrically connected to the circuit board. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a related technical solution.

[0037] Figure 2 This is a schematic diagram of another related technical solution.

[0038] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0039] Figure 4 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0040] Figure 5 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0041] Figure 6 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0042] Figure 7 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0043] Figure 8This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0044] Figure 9 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0045] Figure 10 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0046] Figure 11 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0047] Figure 12 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0048] Figure 13 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0049] Figure 14 This is a schematic diagram of another chip structure provided in an embodiment of this application.

[0050] Figure 15 This is a schematic flowchart illustrating a chip fabrication method provided in an embodiment of this application.

[0051] Figures 16-17 This is a schematic flowchart illustrating a chip fabrication method provided in an embodiment of this application.

[0052] Figure 18 This is a schematic diagram of an electronic device 2000 provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0054] This application will present various aspects, embodiments, or features relating to systems comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0055] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0056] In the embodiments of this application, "corresponding" and "corresponding" can sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, their intended meanings are consistent.

[0057] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0058] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0059] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0060] The miniaturization gains of silicon-based semiconductor devices have reached their limits in terms of advanced process node narrowing and size reduction. The short-channel effect has a significant impact, making power consumption the most significant problem for silicon-based semiconductor devices. Channel structures, with their characteristics of high carrier mobility, ultra-thin body, and ballistic transport, have a natural advantage in reducing the power consumption and parasitic effects of silicon-based semiconductor devices, and represent one of the important directions for the future development and evolution of chip technology.

[0061] In chips containing channel structures, the channel structure is relatively thin (approximately 1–2 nm), making it more fragile than the bulk material and prone to Fermi level pinning (FLP). This prevents the use of ion implantation for heavy doping in the contact region, a common practice in silicon-based devices. Therefore, the contact resistance of the channel structure and the parasitic resistance of the extension region become limiting factors for the device performance of the channel structure (e.g., IL). on One of the key bottlenecks (such as variation).

[0062] It should be understood that the extension region refers to the area between the gate and the electrode.

[0063] Contact resistivity can be measured by the contact barrier (including the Schottky barrier height and tunneling barrier width). A higher Schottky barrier or a wider tunneling barrier makes carrier injection more difficult, resulting in a higher contact resistivity. Ideally, given a channel structure, the barrier height is primarily determined by the contact metal work function, while the barrier width is mainly determined by the doping of the channel structure. However, in actual manufacturing processes, channel structures inevitably suffer damage, especially since material damage is more easily introduced. Furthermore, metals with low work functions in n-type devices are often unstable, resulting in the presence of interface states at the metal-semiconductor (MS) interface, which limits the influence of the metal work function on the contact barrier. Therefore, the doping of the contact region of the channel structure is crucial for reducing contact resistivity.

[0064] It should be understood that the contact area of ​​the channel structure refers to the area in the channel structure that contacts the electrode.

[0065] Currently, the common doping strategy for channel structures is localized solid-state doping. This involves depositing a dielectric material as a doping layer on the channel structure, utilizing the fixed charge within the dielectric material itself or the charge transfer at the interface with the channel structure to achieve doping of the channel structure.

[0066] A related technical solution is as follows Figure 1 As shown, this scheme places the doped layer between the electrode and the channel structure. This method introduces a parasitic resistance, which causes a drop in the transistor's operating voltage, making the transistor malfunction or unstable, thus affecting the chip's performance.

[0067] Another related technical solution is as follows Figure 2As shown, this scheme places the doped layer in the extension region between the gate and the electrode. On one hand, in this doping method, the doped layer can only doping to the region in the channel structure that contacts the electrode boundary. The region below the contact electrode within the transfer length (current doesn't only exist at the metal boundary; there's actually a current distribution length on the electrode, called the transfer length) cannot be effectively doped. On the other hand, the contact region of the channel structure requires a higher doping level, while the extension region does not necessarily require a higher doping level. This contradiction affects the chip's performance.

[0068] In view of this, embodiments of this application provide a chip that can effectively doping the channel structure in the contact area of ​​the channel structure, thinning the contact barrier, reducing the contact resistance between the electrode and the channel structure without introducing additional parasitic effects, thereby improving the chip performance.

[0069] For example, the chip provided in this application embodiment may include a substrate and a transistor, wherein the transistor includes a channel structure, a first electrode, a second electrode, a first doped layer, and a gate. The various parts included in the transistor are described in detail below.

[0070] 1. Channel structure

[0071] The channel structure is located on one side of the substrate. For example, such as Figure 3 As shown, the channel structure 301 is located above the substrate 305.

[0072] 2. First electrode

[0073] At least a portion of the first electrode is located on one side of the channel structure, as described below. Figures 3-6 The location of the first electrode is described in detail.

[0074] In one example, a portion of the first electrode is located on one side of the channel structure. For example, as... Figure 3 As shown, a portion of the first electrode 303 is located above the channel structure 301. For example, as... Figure 5 As shown, a portion of the first electrode 303 is located below the channel structure 301.

[0075] In another example, the entire first electrode is located on one side of the channel structure. For example, as... Figure 4 As shown, the entire first electrode 303 is located above the channel structure 301. For example, as... Figure 6 As shown, the entire first electrode 303 is located below the channel structure 301.

[0076] The first electrode mentioned above can be either the source electrode or the drain electrode; this application does not specifically limit this in the embodiments.

[0077] 3. Second electrode

[0078] At least a portion of the second electrode is located on one side of the channel structure. (See below for details.) Figures 3-6 The location of the second electrode is described in detail.

[0079] In one example, a portion of the second electrode is located on one side of the channel structure. For example, as... Figure 3 As shown, a portion of the second electrode 317 is located above the channel structure 301. For example, as... Figure 5 As shown, a portion of the second electrode 317 is located below the channel structure 301.

[0080] In another example, the entire second electrode is located on one side of the channel structure. For example, as... Figure 4 As shown, the entire second electrode 317 is located above the channel structure 301. For example, as... Figure 6 As shown, the entire second electrode 317 is located below the channel structure 301.

[0081] The second electrode mentioned above can be either a source electrode or a drain electrode; this application does not specifically limit this in its embodiments.

[0082] 4. First doped layer

[0083] At least a portion of the first doped layer is located on the side of the channel structure away from the first and second electrodes, allowing the end face (side face) of the channel structure to contact the first doped layer.

[0084] In the above technical solution, by contacting the first doped layer with the end face (side face) of the channel structure, the ohmic contact resistance can be reduced, thereby improving the performance of the transistor. On the other hand, when the doped layer and the side face of the channel structure are in contact, special electron transport channels (e.g., two-dimensional electron gas, 2DEG) can be formed. The electron transport properties in these channels are excellent, and there is no effect of impurity scattering affecting the mobility degradation. This can significantly improve the carrier mobility of the first doped layer, thereby improving the operating speed and efficiency of the transistor.

[0085] For example, the following will be combined with Figures 3-6 The location of the first doped layer is described in detail.

[0086] In one example, a portion of the first doped layer is located on the side of the channel structure away from the first and second electrodes. For example, as... Figure 3 As shown, taking the example where a portion of the first electrode 303 is located above the channel structure 301, a portion of the first doped layer 302 is located below the channel structure 301. For example, as... Figure 5As shown, taking the first electrode 303 partly located below the channel structure 301 as an example, the first doped layer 302 partly located above the channel structure 301.

[0087] In another example, the entire first doped layer is located on the side of the channel structure away from the first and second electrodes. For example, as... Figure 4 As shown, taking the example where the entire first electrode 303 is located above the channel structure 301, the entire first doped layer 302 is located below the channel structure 301. For example, as... Figure 6 As shown, taking the case where the entire first electrode 303 is located below the channel structure 301, the entire first doped layer 302 is located above the channel structure 301.

[0088] In this embodiment, the portion of the first doped layer 302 that contacts the channel structure 301 is opposite to the portion of the first electrode 303 that contacts the channel structure 301. That is, the first doped layer 302 can doping the region of the channel structure 301 that contacts the first electrode 303.

[0089] In this embodiment, the portion of the first doped layer 302 that contacts the channel structure 301 is opposite to the portion of the first electrode 303 that contacts the channel structure 301. That is, the first doped layer 302 can also doping the region of the channel structure 301 that contacts the second electrode 317.

[0090] 5. Gate

[0091] The gate is located on at least one side of the channel structure. (See below for details.) Figure 3 and Figure 7 The location of the gate is described in detail.

[0092] In one example, the gate is located on the side of the channel structure furthest from the substrate. For example, as... Figure 3 As shown, the substrate 305 is located below the channel structure 301, and the gate 307 is located above the channel structure 301.

[0093] Another example is where the gate is located on the side of the channel structure furthest from the substrate and on the side of the channel structure closest to the substrate. For example, as... Figure 7 As shown, the substrate 305 is located below the channel structure 301, and the gate 307 is located above and below the channel structure 301.

[0094] The above Figure 7 The chip shown is a gate all around (GAA) structure. This structure allows the gate 307 to more effectively control the current in the channel, improving the transistor's performance and power efficiency, thereby improving the chip's performance.

[0095] It should be noted that, Figure 7 Therefore Figure 3 For example, in Figure 3 Based on this, a gate 307 is added below the channel structure 301. Similarly, see also... Figure 7 , can Figures 4-6 Based on the existing channel structure 301, a gate 307 is added below it, which will not be described in detail here.

[0096] In this embodiment, the contact method between the first doped layer and the channel structure is not specifically limited. The different contact methods between the first doped layer and the channel structure are described in detail below.

[0097] In one example, the first doped layer is in direct contact with the channel structure. For example, as... Figures 3-7 The first doped layer 302 is in direct contact with the channel structure 301.

[0098] In another example, the first doped layer contacts the channel structure via a buffer layer; that is, the transistor described above also includes a buffer layer located between the first doped layer and the channel structure. For example, as... Figure 8 As shown, taking the first doped layer 302 partially located below the channel structure 301 as an example, the buffer layer 301 is located above the channel structure 301. The upper surface of the first doped layer 302 partially contacts the lower surface of the buffer layer 301, and the lower surface of the channel structure 301 contacts the upper surface of the buffer layer 301.

[0099] In the chip described above, the buffer layer 301 is placed between the first doped layer 302 and the channel structure 301. On the one hand, the carrier concentration of the channel structure 301 can be controlled, and on the other hand, the interface scattering of the first doped layer 302 to the carriers can be reduced.

[0100] It should be noted that, Figure 8 Therefore Figure 3 For example, in Figure 3 A buffer layer 301 was added between the first doped layer 302 and the channel structure 301. Similarly, see also... Figure 8 , can Figures 4-6 Based on this, a buffer layer 301 is added between the first doped layer 302 and the channel structure 301, which will not be described in detail here.

[0101] Optionally, in some embodiments, the chip may further include a second doped layer located on the side of the channel structure away from the gate.

[0102] It should be understood that the concentration of the second doped layer is different from the concentration of the first doped layer. For example, the concentration of the second doped layer is less than the concentration of the first doped layer.

[0103] As an example, with gate 307 located above channel structure 301, such as... Figure 9 As shown, the second doped layer 319 is located below the channel structure 301.

[0104] In this embodiment, the portion of the second doped layer 319 that contacts the channel structure 301 is opposite to the portion of the gate 307 that contacts the channel structure 301. That is, the second doped layer 319 can doping the region of the channel structure 301 that contacts the gate 307.

[0105] It should be noted that, Figure 9 Therefore Figure 3 For example, in Figure 3 A second doped layer, 319, was added to the existing structure. Similarly, refer to... Figure 9 In this way, Figures 4-6 , Figure 8 Based on this, a second doped layer 319 is added below the channel structure 301.

[0106] Optionally, in some embodiments, the chip may further include a third doped layer, as described below. Figures 10-11 An example is given to illustrate the location of the third doped layer.

[0107] It should be understood that the concentrations of the third doped layer, the second doped layer, and the first doped layer are different. For example, the concentration of the third doped layer is less than the concentration of the second doped layer, and the concentration of the second doped layer is less than the concentration of the first doped layer.

[0108] In one example, the third doped layer is located between the first and second doped layers. For example, as... Figure 10 As shown, the third doped layer 320 is located between the first doped layer 302 and the second doped layer 319.

[0109] In this embodiment, the third doped layer 320 can doping the region in the channel structure 301 that is not in contact with the gate 307, the first electrode 303, and the second electrode 317.

[0110] It should be noted that, Figure 10 Therefore Figure 9 For example, in Figure 9 A third doped layer, 320, was added to the existing structure.

[0111] In another example, the third doped layer is located between the first doped layer and the gate. For example, as shown below. Figure 11 As shown, the third doped layer 320 is located between the first doped layer 302 and the gate 307.

[0112] It should be noted that, Figure 11 Therefore Figure 7 For example, in Figure 7 A third doped layer, 320, was added to the existing structure.

[0113] Optionally, in some embodiments, the chip may further include a stop layer, at least a portion of which is located on the side of the channel structure away from the substrate.

[0114] In this embodiment, the stop layer added on the side of the channel structure away from the substrate can be used to cover and protect the channel structure.

[0115] An example, such as Figure 12 As shown, the channel structure 301 is located above the substrate, and at least a portion of the stop layer 304 is located above the channel structure 301.

[0116] It should be noted that, Figure 12 Therefore Figure 3 For example, in Figure 3 A stop layer 304 was added above the channel structure 301. Similarly, see [reference needed]. Figure 12 , can Figures 4-11 Based on this, a stop layer 304 is added above the channel structure 301, which will not be described in detail here.

[0117] Optionally, in some embodiments, a mask layer may also be placed above the stop layer 304.

[0118] An example, such as Figure 13 As shown, the channel structure 301 is located above the substrate, at least a portion of the stop layer 304 is located above the channel structure 301, and the mask layer 306 is located above the stop layer 304.

[0119] It should be noted that, Figure 13 Therefore Figure 12 For example, in Figure 12 A mask layer 306 was added above the stop layer 304. Similarly, see [reference needed]. Figure 13 ,exist Figures 3-11 The mask layer 306 is added on top of the existing one, which will not be elaborated here.

[0120] Optionally, in some embodiments, a high-k dielectric material (high-K, HK) may be deposited around the gate 307.

[0121] An example, such as Figure 14 As shown, HK308 is deposited around gate 307.

[0122] It should be noted that, Figure 14 Therefore Figure 13 For example, in Figure 3HK308 was deposited around gate 307. Similarly, see also... Figure 14 HK308 is added to other figures that include gate 307, which will not be described in detail here.

[0123] The following is combined with Figure 15 The method for fabricating the chip provided in the embodiments of this application will be described in detail.

[0124] like Figure 15 As shown, the chip fabrication method may include steps 1510-1550, which are described in detail below.

[0125] Step 1510: Form a channel structure on the substrate.

[0126] As an example, channel material can be deposited on a substrate to form a channel structure.

[0127] The aforementioned substrate can also be referred to as an insulating substrate. In this application embodiment, the material of the insulating substrate is not specifically limited. The material of the insulating substrate includes, but is not limited to, any one or more combinations of the following materials: silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), etc.

[0128] This application does not specifically limit the channel material described above, and the channel material may include, but is not limited to, 2D materials and carbon nanotubes (CNTs). 2D materials include, but are not limited to, molybdenum disulfide (MoS2), tungsten diselenide (WSe2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), indium selenide (InSe), and black phosphorus (BP); CNTs include, but are not limited to, arrayed CNTs (Align-CNTs) and network CNTs.

[0129] Step 1520: Form a first electrode on one side of the channel structure.

[0130] In this embodiment, a first electrode may be formed on one side of the channel structure, and at least a portion of the first electrode is in contact with one side of the channel structure.

[0131] In implementation method 1, taking the first electrode located above the channel structure as an example, a first region for placing the first electrode can be formed on the side of the channel structure away from the substrate, and electrode material can be deposited in the first region to form the first electrode.

[0132] The embodiments of this application do not specifically limit the electrode materials mentioned above. The electrode materials include, but are not limited to, any one or more combinations of the following materials: palladium (Pd), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), titanium nitride (TiN), aluminum scandium (AlSc), etc.

[0133] As an example, a stop material can be deposited across the entire side of the channel structure away from the substrate to form a stop layer (at least a portion of the stop layer contacts the side of the channel structure away from the substrate), and the stop layer can be etched to form a first region where a first electrode is placed.

[0134] This application does not specifically limit the method of etching the stop layer. For example, the stop layer can be etched by atomic layer etching (ALE) until the channel structure is exposed. Alternatively, the stop layer can be etched by wet etching until the channel structure is exposed.

[0135] This application does not specifically limit the stop material mentioned above, and the stop material may include, but is not limited to: aluminum oxide (Al2O3), yttrium oxide (YO2). x )wait.

[0136] Another example is that a mask material can be deposited over the entire surface of the stop layer to form a mask layer, and then the mask layer and the stop layer can be etched to form a first region where the first electrode is placed. For example, the mask layer can be etched by dry etching until the stop layer is exposed, and then the stop layer can be etched to form the first region where the first electrode is placed.

[0137] The embodiments of this application do not specifically limit the mask material mentioned above. The mask material may include, but is not limited to, silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0138] In implementation method 2, taking the first electrode located below the channel structure as an example, the substrate can be etched to form a first region where the first electrode is placed, and electrode material can be deposited in the first region to form the first electrode.

[0139] Specifically, a first region (also known as a groove for placing the first electrode) can be etched on the substrate using dry etching.

[0140] Step 1530: Form a second electrode on one side of the channel structure.

[0141] In this embodiment, a second electrode can be formed on one side of the channel structure, and at least a portion of the second electrode is in contact with one side of the channel structure.

[0142] It should be understood that the method of forming the second electrode on one side of the channel structure is similar to the method of forming the first electrode on one side of the channel structure. For details, please refer to the relevant description of forming the first electrode on one side of the channel structure in step 1520, which will not be repeated here.

[0143] Step 1540: Form a first doped layer on the side of the channel structure away from the first electrode and the second electrode.

[0144] In this embodiment, a first doped layer may be formed on the side of the channel structure away from the first electrode and the second electrode, and at least a portion of the first doped layer is in contact with the side of the channel structure away from the first electrode and the second electrode.

[0145] In implementation method 1, taking the first doped layer located below the channel structure as an example, the substrate can be etched to form a third region where the first doped layer is placed, and doped material can be deposited in the third region to form the first doped layer.

[0146] Specifically, a third region (also known as a groove for placing the first doped layer) can be etched on the substrate using dry etching.

[0147] This application does not specifically limit the doping materials described above, and the doping materials include, but are not limited to, any one or more combinations of the following materials: silicon-based oxides (SiO2). x Silicon nitride (SiN) x Aluminum nitride (AlN) x Alumina (AlO) x ), molybdenum oxide (MoO) x ), tungsten oxide (WO3) x ).

[0148] In implementation method 2, taking the first doped layer located above the channel structure as an example, a third region for placing the first doped layer can be formed on the side of the channel structure away from the substrate, and doped material can be deposited in the third region to form the first doped layer.

[0149] As an example, a stop material can be deposited across the entire side of the channel structure away from the substrate to form a stop layer (at least a portion of the stop layer contacts the side of the channel structure away from the substrate), and the stop layer can be etched to form a third region where the first doped layer is placed.

[0150] This application does not specifically limit the method of etching the stop layer. For example, the stop layer can be etched by atomic layer etching (ALE) until the channel structure is exposed. Alternatively, the stop layer can be etched by wet etching until the channel structure is exposed.

[0151] Another example is to deposit mask material over the entire surface of the stop layer to form a mask layer, and then etch the mask layer and the stop layer to form a third region where the first doped layer is placed. For example, the mask layer can be etched by dry etching until the stop layer is exposed, and then the stop layer can be etched to form the third region where the first doped layer is placed.

[0152] Optionally, in some embodiments, a buffer material may be deposited between the first doped layer and the channel structure to form a buffer layer, such that at least a portion of the first doped layer contacts the channel structure through the buffer layer.

[0153] Step 1550: Form a gate on at least one side of the channel structure.

[0154] In this embodiment, a fourth region for placing the gate can be formed on the side of the channel structure away from the substrate, and gate material can be deposited in the fourth region to form the gate.

[0155] The embodiments of this application do not specifically limit the gate material described above. The gate material may include, but is not limited to, any one or more combinations of the following materials: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), titanium aluminum alloy (TiAl), etc.

[0156] For example, the stop layer formed on the channel structure can be etched to form the fourth region.

[0157] In some embodiments, the substrate may be etched to form a fifth region for placing the gate, and gate material may be deposited in the fifth region to form the gate.

[0158] Optionally, in some embodiments, HK308 may also be deposited around the gate 307. For example, HK308 may be deposited on the inner wall of the formed fourth and / or fifth regions.

[0159] It should be understood that K in HK 308 refers to the dielectric constant, which generally refers to the material's ability to concentrate an electric field. In insulators with a high dielectric constant, the material can store more charge for the same thickness.

[0160] The embodiments of this application do not specifically limit the HK 308 mentioned above, which may include, but is not limited to, hafnium dioxide (HfO2).

[0161] Optionally, in some embodiments, a second doped layer may also be formed on the side of the channel structure away from the gate. It should be understood that the implementation of forming the second doped layer is similar to that of forming the first doped layer; for details, please refer to the description of forming the first doped layer above, which will not be repeated here.

[0162] Optionally, in some embodiments, a third doped layer may be formed between the first doped layer and the second doped layer, or between the first doped layer and the gate. It should be understood that the implementation of forming the third doped layer is similar to that of forming the first doped layer; please refer to the above description of forming the first doped layer for details, which will not be repeated here.

[0163] For example, the following describes the preparation of... Figure 14 Taking the chip shown as an example, combined with Figures 16-17 This application provides a detailed description of a chip fabrication method according to an embodiment.

[0164] For example, Figure 16 Including steps 1601-1605, Figure 17 This includes steps 1606-1609.

[0165] Step 1601: Define the position of the first doped layer 302 on the substrate 305, and etch a groove 309 of depth h on the substrate 305 according to the position of the first doped layer 302.

[0166] It should be understood that the groove 309 here can correspond to the third region mentioned above for placing the first doped layer 302.

[0167] As an example, the location of the first doped layer 302 can be graphically defined on the substrate 305.

[0168] The embodiments of this application do not specifically limit the etching method described above, and the etching method may include, but is not limited to, dry etching.

[0169] For example, the depth h of the groove 309 described above can be 100 nm.

[0170] Step 1602: A doped layer material is deposited on the entire surface of the substrate 305 to form the first doped layer 302.

[0171] In this embodiment, the surface of the first doped layer 302 deposited on the substrate 305 can also be smoothed by chemical mechanical polishing (CMP), with the substrate 305 serving as the stop layer for CMP.

[0172] For example, the thickness h1 of the first doped layer 302 is greater than the depth h of the groove 309. For example, the thickness d1 of the first doped layer 302 is 200 nm.

[0173] Step 1603: A channel material is deposited on the entire surface of the substrate 305 to form the channel structure 301.

[0174] In this embodiment of the application, the active region can also be graphically defined on the channel structure 301.

[0175] Step 1604: A stop material is deposited on the entire surface of the channel structure 301 to form a stop layer 304, in order to cover and protect the area where the channel structure 301 is deposited.

[0176] For example, the thickness d2 of the stop layer 304 described above can be 15 nm.

[0177] Step 1605: Deposit a mask layer 306 over the entire surface of the stop layer 304.

[0178] For example, the thickness d3 of the mask layer 306 is 100 nm.

[0179] Step 1606: First, the gate trench 310 is patterned and defined on the mask layer 306. Then, the pattern of the gate trench 310 to be etched is formed on the mask layer 306 by photolithography and left on the mask layer 306. Then, the stop layer 304 is removed by atomic layer etching (ALE) or wet process using the mask layer 306 as a mask to expose the channel structure 301.

[0180] It should be understood that the gate trench 310 refers to a groove with a specific shape and size formed by a specific process (e.g., etching), which is used as the contact area of ​​the gate 307.

[0181] It should be noted that the shape and size of the gate trench 310 are not specifically limited in the embodiments of this application.

[0182] Step 1607: Atomic layer deposition (ALD) is performed on the inner wall of the gate trench 310 to deposit a high-k, HK material 308. Then, a gate 307 is deposited in the gate trench 310. Finally, the surface of the deposited gate 307 is smoothed by CMP, with the mask layer 306 as the stop layer for CMP.

[0183] It should be understood that K in HK 308 refers to the dielectric constant, which generally refers to the material's ability to concentrate an electric field. In insulators with a high dielectric constant, the material can store more charge for the same thickness.

[0184] For example, the thickness d4 of the HK 308 mentioned above is 10nm.

[0185] For example, the thickness d5 of the deposited gate 307 is 150 nm.

[0186] Step 1608: First, two electrode trenches 311 are patterned and defined on the mask layer 306. Then, the pattern of the two electrode trenches 311 to be etched is formed on the mask layer 306 by photolithography and left on the mask layer 306. Then, the stop layer 304 is removed by atomic layer etching (ALE) or wet process using the mask layer 306 as a mask to expose the channel structure 301.

[0187] Step 1609: Deposit electrode 303 in one electrode trench 311 and electrode 317 in the other electrode trench 311. Finally, smooth the surfaces of the deposited electrodes 303 and 317 by CMP, with mask layer 306 as the stop layer for CMP.

[0188] For example, the thickness d6 of the deposited electrodes 303 and 317 is 150 nm.

[0189] For example, electrode 303 is the source and electrode 317 is the drain; or, electrode 303 is the drain and electrode 317 is the source. This application does not specifically limit this.

[0190] Figure 18 This is a schematic diagram of an electronic device 2000 provided in an embodiment of this application. The electronic device 2000 includes a chip 2010 and a circuit board 2020, with the chip 2010 disposed on the circuit board 2020. Electronic devices 2030 may also be disposed on the circuit board 2020, and the electronic devices 2030 can be electrically or communicatively connected to the chip 2010. For example, the electronic device 2030 may be a camera module, a radio frequency module, an audio module, etc. The electronic device 2000 provided in this embodiment of the application can be, but is not limited to, terminal devices (e.g., mobile terminals, wearable terminals, etc.), communication devices (e.g., servers, network products, etc.), home appliances, vehicle-mounted devices, energy storage devices, etc.

[0191] In some possible implementations, chip 2010 can be fixed to circuit board 2020 by solder balls, or chip 2010 can be assembled on the surface of circuit board 2020 using surface mounted technology (SMT). Chip 2010 and other circuits or electronic components on circuit board 2020 can be electrically connected. For example, chip 2010 can be electrically connected to other circuits or electronic components on circuit board 2020 by wire bonding, or chip 2010 can be electrically connected to other circuits or electronic components on circuit board 2020 through structures such as solder pads.

[0192] It should be noted that, in the embodiments of this application, when one device is "connected" to another device, it can be a direct connection to the other device, or there can be an intermediate device between them. "Connection" can be "electrical connection," "coupling," etc., and this application does not limit the terminology.

[0193] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

[0194] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: Substrate; transistor; The transistor includes: Channel structure; A first electrode, at least a portion of which is located on one side of the channel structure, wherein the first electrode is a source or a drain. The second electrode, at least a portion of which is located on one side of the channel structure, is a source or a drain. A first doped layer, at least a portion of which is located on the side of the channel structure away from the first electrode and the second electrode; A gate, the gate being located on at least one side of the channel structure.

2. The chip according to claim 1, characterized in that, The first doped layer is in direct contact with the channel structure.

3. The chip according to claim 1, characterized in that, Also includes: A buffer layer is located between the first doped layer and the channel structure.

4. The chip according to any one of claims 1 to 3, characterized in that, The gate is located on the side of the channel structure away from the substrate; or The gate is located on the side of the channel structure away from the substrate and on the side of the channel structure closer to the substrate.

5. The chip according to claim 4, characterized in that, Also includes: A second doped layer is located on the side of the channel structure away from the gate.

6. The chip according to any one of claims 1 to 5, characterized in that, Also includes: A third doped layer is located between the first and second doped layers, or between the first doped layer and the gate.

7. The chip according to any one of claims 1 to 6, characterized in that, Also includes: A stop layer, at least a portion of which is located on the side of the channel structure away from the substrate.

8. A method for fabricating a chip, characterized in that, include: A channel structure is formed on the substrate; A first electrode is formed on one side of the channel structure, at least a portion of the first electrode is in contact with one side of the channel structure, and the first electrode is a source or a drain. A second electrode is formed on one side of the channel structure, at least a portion of the second electrode is in contact with one side of the channel structure, and the second electrode is a source or a drain. A first doped layer is formed on the side of the channel structure away from the first electrode and the second electrode, and at least a portion of the first doped layer is in contact with the side of the channel structure away from the first electrode and the second electrode. A gate is formed on at least one side of the channel structure.

9. The method according to claim 8, characterized in that, The formation of the first doped layer on the side of the channel structure away from the first electrode and the second electrode includes: A first doped layer is formed directly on the surface of the channel structure away from the first and second electrodes, such that at least a portion of the first doped layer is in direct contact with the channel structure.

10. The method according to claim 8, characterized in that, The method further includes: A buffer material is deposited between the first doped layer and the channel structure to form a buffer layer, such that at least a portion of the first doped layer contacts the channel structure through the buffer layer.

11. The method according to any one of claims 8 to 10, characterized in that, The formation of the channel structure on the substrate includes: Channel material is deposited on the substrate to form the channel structure.

12. The method according to any one of claims 8 to 11, characterized in that, The formation of a first electrode on one side of the channel structure includes: A first region for placing the first electrode is formed on the side of the channel structure away from the substrate; Electrode material is deposited in the first region to form the first electrode; The formation of a second electrode on one side of the channel structure includes: A second region for placing the second electrode is formed on the side of the channel structure away from the substrate; Electrode material is deposited in the second region to form the second electrode; The formation of a first doped layer on the side of the channel structure away from the first and second electrodes includes: The substrate is etched to form a third region where the first doped layer is placed; A doped material is deposited in the third region to form the first doped layer.

13. The method according to any one of claims 8 to 11, characterized in that, The formation of a first electrode on one side of the channel structure includes: The substrate is etched to form a first region where the first electrode is placed; Electrode material is deposited in the first region to form the first electrode; The formation of a second electrode on one side of the channel structure includes: The substrate is etched to form a second region where the second electrode is placed; Electrode material is deposited in the second region to form the second electrode; The formation of a first doped layer on the side of the channel structure away from the first and second electrodes includes: A third region is formed on the side of the channel structure away from the substrate, where the first doped layer is placed; A doped material is deposited in the third region to form the first doped layer.

14. The method according to claim 12, characterized in that, The formation of a first region for placing the first electrode on the side of the channel structure away from the substrate includes: A stop material is deposited across the entire side of the channel structure away from the substrate to form a stop layer, at least a portion of which contacts the side of the channel structure away from the substrate. The stop layer is etched to form the first region; The formation of a second region for placing the second electrode on the side of the channel structure away from the substrate includes: The stop layer is etched to form the second region.

15. The method according to claim 14, characterized in that, The method further includes: A masking material is deposited over the entire surface of the stop layer to form a masking layer; The etching of the stop layer to form the first region includes: The mask layer and the stop layer are etched to form the first region; The etching of the stop layer forms the second region, including: The mask layer and the stop layer are etched to form the second region.

16. The method according to any one of claims 8 to 15, characterized in that, The formation of a gate on at least one side of the channel structure includes: A fourth region for placing the gate is formed on the side of the channel structure away from the substrate; A gate material is deposited in the fourth region to form the gate.

17. The method according to claim 16, characterized in that, The formation of a fourth region for placing the gate on the side of the channel structure away from the substrate includes: A stop material is deposited across the entire side of the channel structure away from the substrate to form a stop layer; A stop layer is etched on the side of the channel structure away from the substrate to form the fourth region.

18. The method according to claim 17, characterized in that, The stop layer formed on the side of the etched channel structure away from the substrate forms the fourth region, including: The mask layer and stop layer formed on the side of the channel structure away from the substrate are etched to form the fourth region.

19. The method according to any one of claims 16 to 18, characterized in that, The method further includes: The substrate is etched to form a fifth region where the gate is placed; The gate material is deposited in the fifth region to form the gate.

20. The method according to any one of claims 8 to 19, characterized in that, The method further includes: A second doped layer is formed on the side of the channel structure away from the gate.

21. The method according to any one of claims 8 to 20, characterized in that, The method further includes: A third doped layer is formed between the first and second doped layers; or The third doped layer is formed between the first doped layer and the gate.

22. A packaging structure, characterized in that, The packaging structure includes a substrate and a chip as described in any one of claims 1 to 7 or a chip prepared according to any one of claims 8 to 21.

23. An electronic device, characterized in that, It includes a circuit board and the chip of claim 22, wherein the chip is disposed on the circuit board and electrically connected to the circuit board.

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