Error amplifier circuit with adaptive adjustable transconductance, boost converter, power supply chip and electronic device

Abstract

The application belongs to the field of electronic circuits and provides an error amplifier circuit capable of self-adapting to adjust transconductance, a boost converter, a power supply chip and an electronic device. The error amplifier circuit comprises an input module, an output module, a first current module and a second current module. The first end of the input module is connected with a feedback node, the second end of the input module receives a reference voltage, the first end of the first current module is connected with the third end of the input module, the first end of the output module and the first end of the second current module respectively, the second end of the first current module is connected with the fourth end of the input module, the second end of the output module and the second end of the second current module respectively, the third end of the output module, the third end of the first current module and the third end of the second current module are connected with a first node, and the fourth end of the first current module and the fourth end of the second current module are connected with a second node. The error amplifier circuit of the application solves the problem of slow loop transient response speed of the traditional boost circuit.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an error amplifier circuit, a boost converter, a power chip, and an electronic device with adaptively adjustable transconductance. Background Technology

[0002] Backlight-driven electronic devices, especially those powered by batteries, experience significant voltage variations, ranging from 3V to 48V. Furthermore, due to the diverse applications of backlight systems, the number of LED strings varies considerably, from 3 to 14 strings, resulting in a correspondingly large output voltage range of 8V to 45V. Current power supply systems primarily utilize boost architectures. For conditions where both input and output voltages fluctuate significantly, phase compensation needs to be designed based on the maximum voltage conversion ratio to ensure stable operation across the entire output voltage range. The loop bandwidth must be lower than the frequency corresponding to the RHP (Right-Half-Plane) zero point. This necessitates the use of large-capacity capacitors for phase compensation to reduce the loop bandwidth, which leads to a decrease in transient response speed and a longer response time during load transitions. Therefore, there is an urgent need to design a new transient response acceleration circuit. Summary of the Invention

[0003] This application provides an error amplifier circuit, boost converter, power chip, and electronic device with adaptively adjustable transconductance, which can solve the problem of slow transient response speed of traditional boost circuit loops.

[0004] In a first aspect, embodiments of this application provide an error amplifier circuit with adaptively adjustable transconductance, including an input module, an output module, a first current module, and a second current module. A first terminal of the input module is connected to the feedback node of a boost circuit to receive a feedback voltage. A second terminal of the input module is used to receive a reference voltage. A first terminal of the first current module is connected to a third terminal of the input module, a first terminal of the output module, and a first terminal of the second current module. A second terminal of the first current module is connected to a fourth terminal of the input module, a second terminal of the output module, and a second terminal of the second current module. A third terminal of the output module, a third terminal of the first current module, and a third terminal of the second current module are all connected to a first node of the boost circuit. A fourth terminal of the first current module and a fourth terminal of the second current module are both connected to a second node of the boost circuit. When the load current of the boost circuit decreases and the difference between the feedback voltage and the reference voltage is greater than a set value, the input module outputs a first current and a second current; the output module outputs a third current based on the first current and the second current; the first current module outputs a fourth current and a fifth current based on the first current and the second current; the third current and the fourth current discharge the first node together, causing the voltage at the first node to drop rapidly, and the fifth current discharges the second node, causing the voltage at the second node to drop rapidly; the second current module stops outputting based on the first current and the second current. When the load current increases and the difference between the reference voltage and the feedback voltage is greater than a set value, the input module outputs a sixth current and a seventh current; the output module outputs an eighth current based on the sixth current and the seventh current; the second current module outputs a ninth current and a tenth current based on the sixth current and the seventh current; the eighth current and the ninth current jointly charge the first node, causing the voltage at the first node to rise rapidly, and the tenth current charges the second node, causing the voltage at the second node to rise rapidly; the first current module stops outputting based on the sixth current and the seventh current.

[0005] In one possible implementation of the first aspect, the input module includes an input unit and a feedback unit. A first end of the input unit is connected to the feedback node, a second end of the input unit is used to receive a reference voltage, a third end of the input unit is connected to the first end of the feedback unit, a fourth end of the input unit is connected to the second end of the feedback unit, a fifth end of the input unit is connected to the third end of the feedback unit, a sixth end of the input unit is connected to the fourth end of the feedback unit, the fifth end of the feedback unit is connected to the first end of the output module, the first end of the first current module, and the first end of the second current module, respectively, and the sixth end of the feedback unit is connected to the second end of the output module, the second end of the first current module, and the second end of the second current module, respectively. When the load current of the boost circuit decreases and the difference between the feedback voltage and the reference voltage is greater than a set value, the input unit is used to output a first voltage and a second voltage; the feedback unit is used to output a first current and a second current according to the first voltage and the second voltage, and to feed back a first signal and a second signal to the input unit to improve the linearity of the input unit. When the load current increases from small to large and the difference between the reference voltage and the feedback voltage is greater than a set value, the input unit is used to output a third voltage and a fourth voltage; the feedback unit is used to output a sixth current and a seventh current according to the third voltage and the fourth voltage, and to feed back the third signal and the fourth signal to the input unit to improve the linearity of the input unit.

[0006] In one possible implementation of the first aspect, the input unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a transconductance resistor. The gate of the first transistor is connected to the feedback node, the drain of the first transistor is connected to a first terminal of the feedback unit, and the source of the first transistor is connected to a first terminal of the transconductance resistor, the drain of the fifth transistor, and a third terminal of the feedback unit. The gate of the second transistor is used to receive a reference voltage, the drain of the second transistor is connected to a second terminal of the feedback unit, and the source of the second transistor is connected to a second terminal of the transconductance resistor, the drain of the sixth transistor, and a fourth terminal of the feedback unit. The source of the fifth transistor is connected to the drain of the third transistor, and the source of the sixth transistor is connected to the drain of the fourth transistor. Both the source of the third transistor and the source of the fourth transistor receive a power supply voltage. Both the gate of the third transistor and the gate of the fourth transistor receive a first bias voltage, and both the gate of the fifth transistor and the gate of the sixth transistor receive a second bias voltage.

[0007] In one possible implementation of the first aspect, the feedback unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The source of the seventh transistor, the source of the ninth transistor, and the source of the twenty-fourth transistor all receive a power supply voltage. The gates of the body transistor and the ninth transistor both receive a first bias voltage. The drain of the seventh transistor is connected to the source of the eighth transistor, and the drain of the ninth transistor is connected to the source of the tenth transistor. The gates of the eighth transistor, the tenth transistor, and the twenty-third transistor all receive a second bias voltage. The drain of the tenth transistor is connected to the gate of the fifteenth transistor, the first terminal of the first resistor, the first terminal of the third resistor, and the drain of the eleventh transistor. The source of the eleventh transistor is connected to the third terminal of the input unit and the drain of the nineteenth transistor. The source of the nineteenth transistor is connected to the twentyth transistor. The drains of the transistors are connected, and the gates of the nineteenth transistor, the twentieth transistor, the thirteenth transistor, and the fourteenth transistor all receive a third bias voltage. The drain of the fourteenth transistor is connected to the source of the thirteenth transistor. The drain of the thirteenth transistor is connected to the source of the twelfth transistor and the fourth terminal of the input unit, respectively. The drain of the twelfth transistor is connected to the drain of the eighth transistor, the gate of the seventeenth transistor, the first terminal of the second resistor, and the first terminal of the fourth resistor, respectively. The second terminal of the first resistor is connected to the first terminal of the first capacitor, and the second terminal of the second resistor is connected to the first terminal of the second capacitor. The drain of the fifteenth transistor is connected to the source of the sixteenth transistor. The gates of the sixteenth transistor, the twenty-second transistor, the eleventh transistor, the twelfth transistor, and the eighteenth transistor all receive a fourth bias voltage. The drain of the sixteenth transistor is connected to the fifth terminal of the input unit. The drain of the seventeenth transistor is connected to the source of the eighteenth transistor. The drain of the eighteenth transistor is connected to the sixth terminal of the input unit. The second terminal of the third resistor is connected to the first terminal of the third capacitor and the gate of the twenty-first transistor. The drain of the twenty-first transistor is connected to the source of the twenty-second transistor.The drain of the 22nd transistor is connected to the drain of the 23rd transistor, the gate of the 24th transistor, the first terminal of the output module, the first terminal of the first current module, and the first terminal of the second current module, respectively. The source of the 23rd transistor is connected to the drain of the 20th transistor. The second terminal of the fourth resistor is connected to the first terminal of the fourth capacitor, the second terminal of the output module, the second terminal of the first current module, and the second terminal of the second current module, respectively. The source of the 21st transistor, the second terminal of the third capacitor, the second terminal of the first capacitor, the source of the 15th transistor, the source of the 20th transistor, the source of the 14th transistor, the second terminal of the second capacitor, the source of the 17th transistor, and the second terminal of the fourth capacitor are all grounded.

[0008] In one possible implementation of the first aspect, the first current module includes a 25th transistor, a 26th transistor, a 27th transistor, a 28th transistor, a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, a 37th transistor, a 38th transistor, a 39th transistor, and a 40th transistor. The gate of the 26th transistor is connected to the second terminal of the output module, the fourth terminal of the input module, and the second terminal of the second current module. The drain of the 26th transistor is connected to the source of the 25th transistor. The gates of the 25th transistor, the 38th transistor, the 35th transistor, and the 40th transistor all receive a fourth bias voltage. The drain of the 25th transistor is connected to the drains of the 28th transistor, the 30th transistor, the 31st transistor, the 32nd transistor, and the 33rd transistor. The gates of the 28th transistor, the 30th transistor, the 31st transistor, and the 34th transistor all receive a second bias voltage. The source of the 28th transistor is connected to the drain of the 27th transistor. The gate of the 27th transistor is connected to the gate of the 29th transistor, the first terminal of the output module, the first terminal of the second current module, and the third terminal of the input module. The source of the 30th transistor is connected to the drain of the 29th transistor. The source of the 31st transistor is connected to the drain of the 32nd transistor. The source of the 34th transistor is connected to the drain of the 33rd transistor. The sources of the 27th, 29th, 32nd, and 33rd transistors all receive a power supply voltage. The drain of the 34th transistor is connected to the gate of the 35th transistor. The drain of the body transistor, the gate of the thirty-sixth transistor, the gate of the thirty-seventh transistor, and the gate of the thirty-ninth transistor are connected. The drain of the thirty-ninth transistor is connected to the source of the fortieth transistor. The drain of the fortieth transistor is used to connect to the second node. The source of the thirty-fifth transistor is connected to the drain of the thirty-sixth transistor. The drain of the thirty-seventh transistor is connected to the source of the thirty-eighth transistor. The drain of the thirty-eighth transistor is used to connect to the first node. The sources of the twenty-sixth transistor, the thirty-seventh transistor, the thirty-sixth transistor, and the thirty-ninth transistor are all grounded.

[0009] In one possible implementation of the first aspect, the second current module includes transistors forty-first, forty-second, forty-third, forty-fourth, forty-fifth, forty-sixth, forty-seventh, forty-eighth, forty-ninth, fiftieth, fifty-first, fifty-second, fifty-third, fifty-fourth, fifty-fifth, and fifty-sixth. The gate of transistor forty-first is connected to a first terminal of the first current module, a first terminal of the output module, and a third terminal of the input module. The source of transistor forty-first and transistor forty-third are connected to the first terminal of the first current module, a first terminal of the output module, and a third terminal of the input module. The source of the 41st transistor, the source of the 55th transistor, and the source of the 52nd transistor all receive a power supply voltage. The drain of the 41st transistor is connected to the source of the 42nd transistor. The gates of the 42nd transistor, the 54th transistor, the 56th transistor, and the 51st transistor all receive a second bias voltage. The drain of the 42nd transistor is connected to the drains of the 43rd transistor, the 46th transistor, the 47th transistor, the gate of the 48th transistor, and the gate of the 49th transistor. The gate of the 43rd transistor and the 56th transistor... The gates of the transistor, the forty-seventh transistor, and the fiftieth transistor all receive a fourth bias voltage. The source of the forty-third transistor is connected to the drain of the forty-fourth transistor, and the source of the forty-sixth transistor is connected to the drain of the forty-fifth transistor. The gate of the forty-fourth transistor is connected to the gate of the forty-fifth transistor, the second terminal of the output module, the fourth terminal of the input module, and the second terminal of the first current module. The source of the forty-seventh transistor is connected to the drain of the forty-eighth transistor, and the source of the fiftieth transistor is connected to the drain of the forty-ninth transistor. The drains of the fiftieth transistor are respectively... The source of the 51st transistor is connected to the drain of the 52nd transistor, the drain of the 55th transistor is connected to the source of the 56th transistor, the drain of the 56th transistor is connected to the second node, the drain of the 53rd transistor is connected to the source of the 54th transistor, the drain of the 54th transistor is connected to the first node, and the sources of the 44th transistor, the 45th transistor, the 48th transistor, and the 49th transistor are all grounded.

[0010] In one possible implementation of the first aspect, the output module includes a 57th transistor, a 58th transistor, a 59th transistor, and a 60th transistor. The gate of the 60th transistor is connected to the third terminal of the input module, the first terminal of the first current module, and the first terminal of the second current module, respectively. The source of the 60th transistor receives a power supply voltage. The drain of the 60th transistor is connected to the source of the 59th transistor. The drain of the 59th transistor is connected to the drain of the 57th transistor and the first node, respectively. The source of the 57th transistor is connected to the drain of the 58th transistor. The gate of the 58th transistor is connected to the fourth terminal of the input module, the second terminal of the first current module, and the second terminal of the second current module, respectively. The source of the 58th transistor is grounded.

[0011] Secondly, embodiments of this application provide a boost converter, including a boost circuit and an error amplifier circuit with adaptively adjustable transconductance as described in any of the first aspects. The first terminal of the input module in the error amplifier circuit with adaptively adjustable transconductance is connected to the feedback node of the boost circuit. The first node of the boost circuit is connected to the third terminal of the output module, the third terminal of the first current module, and the third terminal of the second current module in the error amplifier circuit with adaptively adjustable transconductance, respectively. The second node of the boost circuit is connected to the fourth terminal of the first current module and the fourth terminal of the second current module, respectively.

[0012] Thirdly, embodiments of this application provide a power supply chip, including the boost converter described in any one of the second aspects.

[0013] Fourthly, embodiments of this application provide an electronic device including the power chip described in any one of the third aspects.

[0014] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides an error amplifier circuit with adaptively adjustable transconductance, including an input module, an output module, a first current module, and a second current module. The first terminal of the input module is connected to the feedback node of the boost circuit to receive feedback voltage. The second terminal of the input module is used to receive a reference voltage. The first terminal of the first current module is connected to the third terminal of the input module, the first terminal of the output module, and the first terminal of the second current module. The second terminal of the first current module is connected to the fourth terminal of the input module, the second terminal of the output module, and the second terminal of the second current module. The third terminals of the output module, the first current module, and the second current module are all connected to the first node of the boost circuit. The fourth terminals of the first current module and the second current module are all connected to the second node of the boost circuit.

[0015] When the load current of the boost circuit decreases from high to low, i.e., when the load switches from heavy to light, the output voltage of the boost circuit overshoots, causing the feedback voltage to rise accordingly and increasing the difference between the feedback voltage and the reference voltage. When the difference between the feedback voltage and the reference voltage exceeds a set value, the input module outputs a first current and a second current; the output module outputs a third current based on the first and second currents; the first current module outputs a fourth and a fifth current based on the first and second currents; the third and fourth currents together discharge the first node, causing the voltage at the first node to drop rapidly. Simultaneously, the fifth current discharges the second node, causing the voltage at the second node to drop rapidly. After the voltage at the first node drops, the duty cycle of the boost circuit decreases, accelerating the transient response speed during load changes. At this point, the second current module stops outputting based on the first and second currents.

[0016] When the load current increases from a small to a large value, i.e., when the load switches from a light load to a heavy load, the output voltage of the boost circuit undershoots, the feedback voltage decreases accordingly, and the difference between the reference voltage and the feedback voltage increases. When the difference between the reference voltage and the feedback voltage exceeds the set value, the input module outputs the sixth and seventh currents; the output module outputs the eighth current based on the sixth and seventh currents; the second current module outputs the ninth and tenth currents based on the sixth and seventh currents. The eighth and ninth currents together charge the first node, causing the voltage at the first node to rise rapidly; simultaneously, the tenth current charges the second node, causing the voltage at the second node to rise rapidly. After the voltage at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed during load changes. At this point, the first current module stops outputting based on the sixth and seventh currents.

[0017] In summary, when the load switches from heavy load to light load, the output voltage overshoots. When the difference between the feedback voltage and the reference voltage exceeds a set value, the first node is discharged, causing its voltage to drop rapidly. Simultaneously, the second node is discharged, causing its voltage to drop rapidly, thus accelerating the voltage change at the first node. After the voltage at the first node drops, the duty cycle of the boost circuit decreases, accelerating the transient response speed during load transitions. When the load switches from light load to heavy load, the output voltage undershoots. When the difference between the reference voltage and the feedback voltage exceeds a set value, the first node is charged, causing its voltage to rise rapidly. Simultaneously, the second node is charged, causing its voltage to rise rapidly, thus accelerating the voltage change at the first node. After the voltage at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed during load transitions.

[0018] Therefore, the adaptively adjustable transconductance error amplifier circuit provided in this application solves the problem of slow transient response speed of traditional boost circuit loops.

[0019] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a traditional boost circuit; Figure 2 This is a schematic diagram of an error amplifier circuit with adaptively adjustable transconductance provided in an embodiment of this application; Figure 3 This is a schematic diagram of an error amplifier circuit with adaptively adjustable transconductance provided in another embodiment of this application; Figure 4 This is a circuit connection diagram of an error amplifier circuit with adaptively adjustable transconductance provided in an embodiment of this application.

[0022] In the diagram: 10, error amplifier circuit; 11, input module; 111, input unit; 112, feedback unit; 12, output module; 13, first current module; 14, second current module. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Figure 1 The structure of a conventional boost circuit is shown, such as Figure 1 As shown, the error amplifier EA, the PWM comparator, and the compensation resistor R C The common terminal is the first node, and the compensation resistor R C With compensation capacitor C C The common terminal is the second node E2, and the first feedback resistor R f1 Second feedback resistor R f2 The common terminal of the error amplifier EA is the feedback node. Its working principle is as follows: Output voltage V OUT via the first feedback resistor R f1 With the second feedback resistor R f2 The sampling network forms the feedback voltage VFB; the error amplifier EA differentially amplifies the feedback voltage VFB and the reference voltage VREF and outputs the error current, which is then compensated by the resistor R. C With compensation capacitor C CThe compensation network consists of a voltage VE1 at the first node and a current sampling signal V. sense Slope compensation signal V SLOPE The superimposed signal is processed by a PWM comparator to generate a PWM comparison signal. The PWM comparison signal and the clock signal CLK are processed sequentially by an RS flip-flop, a level shift and dead time module, and a drive module to output a drive signal, which controls the on and off states of the power transistor MN.

[0030] Since the loop bandwidth of the boost circuit needs to be lower than the frequency value corresponding to the zero point of RHP, a compensation capacitor C is required. C Large-capacity capacitors are required for phase compensation to reduce loop bandwidth, which leads to a decrease in loop transient response speed and a corresponding increase in response time during load changes. Therefore, there is an urgent need to design a new transient response acceleration circuit.

[0031] To address the aforementioned problems, this application provides an error amplifier circuit with adaptively adjustable transconductance. When the load switches from heavy load to light load, the output voltage overshoots. When the difference between the feedback voltage and the reference voltage exceeds a set value, the first node is discharged, causing its voltage to drop rapidly. Simultaneously, the second node is discharged, causing its voltage to drop rapidly, thus accelerating the voltage change at the first node. After the voltage at the first node drops, the duty cycle of the boost circuit decreases, accelerating the transient response speed during load transitions. When the load switches from light load to heavy load, the output voltage undershoots. When the difference between the reference voltage and the feedback voltage exceeds a set value, the first node is charged, causing its voltage to rise rapidly. Simultaneously, the second node is charged, causing its voltage to rise rapidly, thus accelerating the voltage change at the first node. After the voltage at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed during load transitions.

[0032] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0033] Figure 2 A schematic diagram of an adaptively adjustable transconductance error amplifier circuit according to an embodiment of this application is shown. Figure 2As shown, the error amplifier circuit 10 includes an input module 11, an output module 12, a first current module 13, and a second current module 14. The first terminal of the input module 11 is connected to the feedback node of the boost circuit to receive the feedback voltage. The second terminal of the input module 11 is used to receive the reference voltage VREF. The first terminal of the first current module 13 is connected to the third terminal of the input module 11, the first terminal of the output module 12, and the first terminal of the second current module 14, respectively. The second terminal of the first current module 13 is connected to the fourth terminal of the input module 11, the second terminal of the output module 12, and the second terminal of the second current module 14, respectively. The third terminals of the output module 12, the first current module 13, and the second current module 14 are all connected to the first node of the boost circuit. The fourth terminals of the first current module 13 and the second current module 14 are all connected to the second node of the boost circuit.

[0034] Specifically, when the load current of the boost circuit changes from large to small, that is, when the load switches from heavy load to light load, the output voltage V of the boost circuit... OUT When overshoot occurs, the feedback voltage VFB increases, and the difference between the feedback voltage VFB and the reference voltage VREF increases. When the difference between the feedback voltage VFB and the reference voltage VREF exceeds a set value, the input module 11 outputs a first current and a second current; the output module 12 outputs a third current based on the first and second currents; and the first current module 13 outputs a fourth current and a fifth current based on the first and second currents. The fourth and fifth currents are related to the output voltage VFB. OUT The changes are proportional. The third and fourth currents discharge the first node together, causing the voltage VE1 at the first node to drop rapidly. At the same time, the fifth current discharges the second node, causing the voltage VE2 at the second node to drop rapidly. After the voltage VE1 at the first node drops, the duty cycle of the boost circuit decreases, accelerating the transient response speed during load switching. At this time, the second current module 14 stops outputting according to the first and second currents.

[0035] When the load current increases from small to large, that is, when the load changes from light load to heavy load, the output voltage V of the boost circuit increases. OUT When an undershoot occurs, the feedback voltage VFB decreases, and the difference between the reference voltage VREF and the feedback voltage VFB increases. When the difference between the reference voltage VREF and the feedback voltage VFB exceeds a set value, input module 11 outputs the sixth and seventh currents; output module 12 outputs the eighth current based on the sixth and seventh currents; and second current module 14 outputs the ninth and tenth currents based on the sixth and seventh currents. The ninth and tenth currents are related to the output voltage VFB. OUTThe changes are proportional. The eighth and ninth currents charge the first node together, causing the voltage VE1 at the first node to rise rapidly; simultaneously, the tenth current charges the second node, causing the voltage VE2 at the second node to rise rapidly. After the voltage VE1 at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed when the load changes. At this time, the first current module 13 stops outputting according to the sixth and seventh currents.

[0036] In summary, when the load changes from heavy load to light load, the output voltage V OUT Overshoot occurs when the difference between the feedback voltage VFB and the reference voltage VREF exceeds a set value. This discharges the first node, causing a rapid decrease in its voltage VE1. Simultaneously, the second node is discharged, causing a rapid decrease in its voltage VE2, thus accelerating the change in VE1 at the first node. After VE1 decreases, the duty cycle of the boost circuit decreases, accelerating the transient response during load changes. When the load switches from light to heavy load, the output voltage V... OUT When an undershoot occurs, if the difference between the reference voltage VREF and the feedback voltage VFB exceeds a set value, the first node is charged, causing the voltage VE1 at the first node to rise rapidly. Simultaneously, the second node is charged, causing the voltage VE2 at the second node to rise rapidly, thus accelerating the change in voltage VE1 at the first node. After the voltage VE1 at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed during load switching.

[0037] Therefore, the adaptively adjustable transconductance error amplifier circuit 10 provided in this application solves the problem of slow transient response speed of traditional boost circuit loops.

[0038] In one embodiment of this application, such as Figure 3 As shown, the input module 11 includes an input unit 111 and a feedback unit 112. The first end of the input unit 111 is used to connect to the feedback node, the second end of the input unit 111 is used to receive the reference voltage VREF, the third end of the input unit 111 is connected to the first end of the feedback unit 112, the fourth end of the input unit 111 is connected to the second end of the feedback unit 112, the fifth end of the input unit 111 is connected to the third end of the feedback unit 112, the sixth end of the input unit 111 is connected to the fourth end of the feedback unit 112, the fifth end of the feedback unit 112 is connected to the first end of the output module 12, the first end of the first current module 13, and the first end of the second current module 14, respectively, and the sixth end of the feedback unit 112 is connected to the second end of the output module 12, the second end of the first current module 13, and the second end of the second current module 14, respectively.

[0039] Specifically, when the load current decreases and the difference between the feedback voltage VFB and the reference voltage VREF is greater than a set value, the input unit 111 outputs a first voltage and a second voltage; the feedback unit 112 outputs a first current and a second current based on the first voltage and the second voltage, and feeds back a first signal and a second signal to the input unit 111 to improve the linearity of the input unit 111, thereby ensuring the accuracy of the voltage-to-current conversion. The first signal and the second signal are current signals.

[0040] When the load current increases and the difference between the reference voltage VREF and the feedback voltage VFB exceeds a set value, the input unit 111 outputs a third voltage and a fourth voltage; the feedback unit 112 outputs a sixth current and a seventh current based on the third and fourth voltages, and feeds back the third and fourth signals to the input unit 111 to improve the linearity of the input unit 111, thereby ensuring the accuracy of the voltage-to-current conversion. The third and fourth signals are current signals.

[0041] In one embodiment of this application, such as Figure 4 As shown, the input unit 111 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a transconductance resistor R. GM The gate of the first transistor M1 is connected to the feedback node, the drain of the first transistor M1 is connected to the first terminal of the feedback unit 112, and the source of the first transistor M1 is connected to the transconductance resistor R. GM The first terminal of the second transistor M2, the drain of the fifth transistor M5, and the third terminal of the feedback unit 112 are connected. The gate of the second transistor M2 is used to receive the reference voltage VREF. The drain of the second transistor M2 is connected to the second terminal of the feedback unit 112. The source of the second transistor M2 is connected to the transconductance resistor R. GM The second terminal of the transistor, the drain of the sixth transistor M6, and the fourth terminal of the feedback unit 112 are connected. The source of the fifth transistor M5 is connected to the drain of the third transistor M3. The source of the sixth transistor M6 is connected to the drain of the fourth transistor M4. The sources of the third transistor M3 and the fourth transistor M4 both receive the power supply voltage VCC. The gates of the third transistor M3 and the fourth transistor M4 both receive the first bias voltage VB1. The gates of the fifth transistor M5 and the sixth transistor M6 both receive the second bias voltage VB2.

[0042] Specifically, the first transistor M1 and the second transistor M2 constitute an input pair. When the load current decreases and the difference between the feedback voltage VFB and the reference voltage VREF is greater than a set value, the first transistor M1 and the second transistor M2 are used to convert the input difference (i.e., the difference between the feedback voltage VFB and the reference voltage VREF) into a differential voltage, namely the first voltage and the second voltage.

[0043] When the load current increases and the difference between the reference voltage VREF and the feedback voltage VFB is greater than the set value, the first transistor M1 and the second transistor M2 are used to convert the input difference (i.e., the difference between the reference voltage VREF and the feedback voltage VFB) into differential voltages, namely the third voltage and the fourth voltage.

[0044] In one embodiment of this application, such as Figure 4As shown, the feedback unit 112 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24; a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4; a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The sources of transistors M7, M9, and M24 all receive the power supply voltage VCC. The gates of both transistors M7 and M9 receive the first bias voltage VB1. The drain of transistor M7 is connected to the source of transistor M8. The drain of transistor M9 is connected to the source of transistor M10. The gates of transistors M8, M10, and M23 all receive the second bias voltage VB2. The drain of transistor M10 is connected to the gate of transistor M15, the first terminal of resistor R1, the first terminal of resistor R3, and the drain of transistor M11. The source of transistor 1 is connected to the third terminal of input unit 111 and the drain of the nineteenth transistor M19. The source of the nineteenth transistor M19 is connected to the drain of the twentieth transistor M20. The gates of the nineteenth transistor M19, the twentieth transistor M20, the thirteenth transistor M13, and the fourteenth transistor M14 all receive the third bias voltage VB3. The drain of the fourteenth transistor M14 is connected to the source of the thirteenth transistor M13. The drain of the thirteenth transistor M13 is connected to the source of the twelfth transistor M12 and the fourth terminal of input unit 111. The drain of the twelfth transistor M12 is connected to the drain of the eighth transistor M8, the gate of the seventeenth transistor M17, the first terminal of the second resistor R2, and the... The first terminal of resistor R4 is connected; the second terminal of resistor R1 is connected to the first terminal of capacitor C1; the second terminal of resistor R2 is connected to the first terminal of capacitor C2; the drain of transistor M15 is connected to the source of transistor M16; the gates of transistors M16, M22, M11, M12, and M18 all receive the fourth bias voltage VB4; the drain of transistor M16 is connected to the fifth terminal of input unit 111; the drain of transistor M17 is connected to the source of transistor M18; and the drain of transistor M18 is connected to the sixth terminal of input unit 111.The second terminal of the third resistor R3 is connected to the first terminal of the third capacitor C3 and the gate of the twenty-first transistor M21. The drain of the twenty-first transistor M21 is connected to the source of the twenty-second transistor M22. The drain of the twenty-second transistor M22 is connected to the drain of the twenty-third transistor M23, the gate of the twenty-fourth transistor M24, the first terminal of the output module 12, the first terminal of the first current module 13, and the first terminal of the second current module 14. The source of the twenty-third transistor M23 is connected to the drain of the twentieth transistor M24. The second terminal of the fourth resistor R4 is connected to the first terminal of the fourth capacitor C4, the second terminal of the output module 12, the second terminal of the first current module 13, and the second terminal of the second current module 14. The source of the twenty-first transistor M21, the second terminal of the third capacitor C3, the second terminal of the first capacitor C1, the source of the fifteenth transistor M15, the source of the twentieth transistor M20, the source of the fourteenth transistor M14, the second terminal of the second capacitor C2, the source of the seventeenth transistor M17, and the second terminal of the fourth capacitor C4 are all grounded.

[0045] Specifically, the fifteenth transistor M15 and the seventeenth transistor M17 form a negative feedback loop. These transistors detect the differential voltage output from the first transistor M1 and the second transistor M2, convert it into current, and feed a certain proportion of this current back to the sources of the first transistor M1 and the second transistor M2. This feedback from the drain to the source of the first transistor M1 and the second transistor M2 ensures that the first transistor M1 and the second transistor M2 have constant gate-source voltages, further linearizing them. The input difference of input unit 111 is entirely applied to the transconductance resistor R. GM Above, the transconductance resistance R flows GM Provided by the fifteenth transistor M15 and the seventeenth transistor M17, the current flowing through the fifteenth transistor M15 is replicated to the twenty-first transistor M21 at a 1:1 ratio, and then output to the first terminal of the output module 12, the first terminal of the first current module 13, and the first terminal of the second current module 14. The current flowing through the seventeenth transistor M17 is output to the second terminal of the output module 12, the second terminal of the first current module 13, and the second terminal of the second current module 14.

[0046] The functions of the first resistor R1 and the first capacitor C1 are compensation. The functions of the second resistor R2 and the second capacitor C2 are compensation. The functions of the third resistor R3 and the third capacitor C3 are compensation. The functions of the fourth resistor R4 and the fourth capacitor C4 are compensation.

[0047] In one embodiment of this application, such as Figure 4As shown, the first current module 13 includes the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the thirtieth transistor M30, the thirty-first transistor M31, the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34, the thirty-fifth transistor M35, the thirty-sixth transistor M36, the thirty-seventh transistor M37, the thirty-eighth transistor M38, the thirty-ninth transistor M39, and the fortieth transistor M40. The gate of the twenty-sixth transistor M26 is connected to the second terminal of the output module 12, the fourth terminal of the input module 11, and the second terminal of the second current module 14. The drain of the 26th transistor M26 is connected to the source of the 25th transistor M25. The gates of the 25th transistor M25, the 38th transistor M38, the 35th transistor M35, and the 40th transistor M40 all receive the fourth bias voltage VB4. The drain of the 25th transistor M25 is connected to the drains of the 28th transistor M28, the 30th transistor M30, the 31st transistor M31, the gate of the 32nd transistor M32, and the gate of the 33rd transistor M33. The gates of the 28th transistor M28, the 30th transistor M30, the 31st transistor M31, and the 34th transistor M34 are connected to the source of the 25th transistor M25. The gates of all transistors receive the second bias voltage VB2. The source of the twenty-eighth transistor M28 is connected to the drain of the twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is connected to the gate of the twenty-ninth transistor M29, the first terminal of the output module 12, the first terminal of the second current module 14, and the third terminal of the input module 11, respectively. The source of the thirtieth transistor M30 is connected to the drain of the twenty-ninth transistor M29. The source of the thirty-first transistor M31 is connected to the drain of the thirty-second transistor M32. The source of the thirty-fourth transistor M34 is connected to the drain of the thirty-third transistor M33. The sources of the twenty-seventh transistor M27, the twenty-ninth transistor M29, and the thirty-second transistor M27 are connected to the drain of the input module 11. The sources of transistors M32 and M33 both receive the power supply voltage VCC. The drain of transistor M34 is connected to the drain of transistor M35, the gate of transistor M36, the gate of transistor M37, and the gate of transistor M39, respectively. The drain of transistor M39 is connected to the source of transistor M40, which is used to connect to the second node. The source of transistor M35 is connected to the drain of transistor M36, and the drain of transistor M37 is connected to the source of transistor M38, which is used to connect to the first node.The sources of transistors M26 (26th), M37 (37th), M36 (36th), and M39 (39th) are all grounded.

[0048] Specifically, when the load current changes from large to small, that is, when the load switches from heavy load to light load, the output voltage V of the boost circuit... OUT When overshoot occurs, the feedback voltage VFB increases, and the difference between VFB and the reference voltage VREF increases. The input pair transistors M1 and M2 output differential voltages, namely the first voltage and the second voltage. Because the feedback voltage VFB increases, the first voltage is less than the second voltage, meaning the source voltage of the eleventh transistor M11 decreases, which in turn lowers the gate voltage of the fifteenth transistor M15. Consequently, the current flowing through the fifteenth transistor M15 decreases, becoming the first current. The seventeenth transistor M17 outputs a second current based on the second voltage, and the first current is less than the second current. The first current is mirrored 1:1 to the twenty-first transistor M21, and then mirrored to the first terminal of the first current module 13, i.e., mirrored to the twenty-seventh transistor M27. The second current is mirrored 1:1 to the second terminal of the first current module 13, i.e., mirrored to the twenty-sixth transistor M26. The ratio of the twenty-seventh transistor M27 to the twenty-ninth transistor M29 is 1:k, where 0 < k < 1; therefore, the first current is mirrored k times to the twenty-ninth transistor M29. When the difference between the feedback voltage VFB and the reference voltage VREF is greater than the set value, the current flowing through the 26th transistor M26 is greater than the sum of the currents flowing through the 27th transistor M27 and the 29th transistor M29. That is, the second current is greater than the sum of the first current and k times the first current. At this time, the 32nd transistor M32 turns on, and the current flowing through it is mirrored 1:1 to the 33rd transistor M33, and then mirrored to the 39th transistor M39 and the 37th transistor M37 respectively. The current flowing through the 37th transistor M37 is the fourth current. This fourth current is related to the output voltage VFB. OUT The change in voltage is directly proportional to the change in current. The current flowing through the thirty-ninth transistor M39 is the fifth current. The fifth current is related to the output voltage V. OUT The change in voltage is proportional to the change in voltage. The fourth current and the third current output by the output module 12 discharge the first node together, causing the voltage VE1 at the first node to drop rapidly. The fifth current discharges the second node, causing the voltage VE2 at the second node to drop rapidly, thereby accelerating the change in voltage VE1 at the first node. After the voltage VE1 at the first node drops, the duty cycle of the boost circuit decreases, accelerating the transient response speed when the load changes.

[0049] In one embodiment of this application, such as Figure 4As shown, the second current module 14 includes transistors M41 (41st), M42 (42nd), M43 (43rd), M44 (44th), M45 (45th), M46 (46th), M47 (47th), M48 (48th), M49 (49th), M50 (50th), M51 (51st), M52 (52nd), M53 (53rd), M54 (54th), M55 (55th), and M56 (56th). The gate of transistor M41 is connected to the first terminal of the first current module 13, the first terminal of the output module 12, and the third terminal of the input module 11. The sources of transistors M1, M53, M55, and M52 all receive the power supply voltage VCC. The drain of transistor M41 is connected to the source of transistor M42. The gates of transistor M42, M54, M56, and M51 all receive the second bias voltage VB2. The drain of transistor M42 is connected to the drains of transistors M43, M46, M47, M48, and M49, respectively. The gates of transistors M43, M46, M47, and M50 all receive the fourth bias voltage VB4. The source of transistor M43 is connected to the drain of transistor M44. The source of transistor M46 is connected to the drain of transistor M45. The gate of transistor M44 is connected to the gate of transistor M45, the second terminal of output module 12, the fourth terminal of input module 11, and the second terminal of first current module 13. The source of transistor M47 is connected to the drain of transistor M48. The source of transistor M50 is connected to the drain of transistor M49. The drain of transistor M50 is connected to the drain of transistor M51 (51), the gate of transistor M55 (55), and the gate of transistor M52 (52), respectively. The source of transistor M51 is connected to the drain of transistor M52 (52), the drain of transistor M55 is connected to the source of transistor M56 (56), and the drain of transistor M56 is used to connect to the second node. The drain of transistor M53 (53) is connected to the source of transistor M54 (54), and the drain of transistor M54 is used to connect to the first node. The sources of transistors M44 (44), M45 (45), M48 (48), and M49 (49) are all grounded.

[0050] Specifically, when the load current increases from small to large, i.e. when the load switches from light load to heavy load, the output voltage V of the boost circuit... OUT When an undershoot occurs, the feedback voltage VFB decreases, increasing the difference between the reference voltage VREF and the feedback voltage VFB. This causes the first transistor M1 and the second transistor M2 in the input pair to output differential voltages, namely the third and fourth voltages. Because the feedback voltage VFB decreases, the third voltage is greater than the fourth voltage, meaning the source voltage of the eleventh transistor M11 increases, which in turn increases the gate voltage of the fifteenth transistor M15. Consequently, the current flowing through the fifteenth transistor M15 increases, becoming the sixth current. The seventeenth transistor M17 outputs a seventh current based on the fourth voltage. The sixth current is greater than the seventh current. The sixth current is mirrored 1:1 to the twenty-first transistor M21, and then mirrored to the first terminal of the second current module 14, i.e., mirrored to the forty-first transistor M41. The seventh current is mirrored 1:1 to the second terminal of the second current module 14, i.e., mirrored to the forty-fourth transistor M44. The ratio of the forty-fourth transistor M44 to the forty-fifth transistor M45 is 1:k; therefore, the seventh current is mirrored k times to the forty-fifth transistor M45. When the difference between the reference voltage VREF and the feedback voltage VFB is greater than the set value, the current flowing through the 41st transistor M41 is greater than the current flowing through the 44th transistor M44 and the 45th transistor M45. That is, the sixth current is greater than the sum of the seventh current and k times the seventh current. At this time, the 48th transistor M48 turns on, and the current flowing through it is mirrored 1:1 to the 49th transistor M49, and then mirrored to the 55th transistor M55 and the 53rd transistor M53 respectively. The current flowing through the 53rd transistor M53 is the ninth current. The ninth current and the output voltage VFB... OUT The change in voltage is directly proportional to the change in current. The current flowing through the fifty-fifth transistor M55 is the tenth current. The tenth current is related to the output voltage V. OUT The change in voltage is directly proportional to the change in voltage. The ninth current and the eighth current output by the output module 12 charge the first node, causing the voltage VE1 at the first node to rise rapidly. The tenth current charges the second node, causing the voltage VE2 at the second node to rise rapidly, thereby accelerating the change in voltage VE1 at the first node. After the voltage VE1 at the first node rises, the duty cycle of the boost circuit increases, accelerating the transient response speed when the load changes.

[0051] transconductance G M Due to transconductance resistance R GM The reciprocal of the current and the ratio by which the currents flowing through the fifteenth transistor M15 and the seventeenth transistor M17 are mirrored to the twenty-first transistor M21 and the fifty-eighth transistor M58, respectively, determine the transconductance resistance R. GMOnce the current mirror ratio is determined, the transconductance G can be determined. M The value of transconductance G. M The principle of adaptive adjustment is that the current flowing through the forty-first transistor M41 and the forty-fourth transistor M44 contains the same DC current I. DC The value of a small-signal current ΔI, which is the same in magnitude but opposite in direction, is (V). P –V N ) / R GM , (V P –V N The input voltage difference of input module 11 is used to mirror the current flowing through the forty-fourth transistor M44 to the forty-fifth transistor M45 by a factor of k. When the current flowing through the forty-first transistor M41 is greater than the sum of the currents flowing through the forty-fourth transistor M44 and the forty-fifth transistor M45, the forty-eighth transistor M48 is turned on. The difference between the current flowing through the forty-first transistor M41 and the sum of the currents flowing through the forty-fourth transistor M44 and the forty-fifth transistor M45 is amplified to the first node and the second node respectively, thus increasing the transconductance G of the circuit. M Increase. When the current flowing through the forty-first transistor M41 equals the sum of the current flowing through the forty-fourth transistor M44 and the current flowing through the forty-fifth transistor M45, the following formula can be written: , Among them, (V) P –V N ) th This is a set value. The transconductance G can be derived from the above formula. M When the value changes from a fixed value to an adaptively increasing value, (V) P –V N ) th The expression is When (V) P –V N ) exceeding (V P –V N ) th At that time, transconductance G M This achieves adaptive amplification. The error amplifier circuit 10 will ultimately output a voltage equal to the output voltage V. OUT Current whose change in magnitude is directly proportional to the output voltage V OUT If overshoot occurs, the output discharge current (i.e., the fourth and fifth currents) will be proportional to it, and the output voltage V will increase. OUT If an undershoot occurs, a charging current proportional to it (i.e., the ninth and tenth currents) is output and applied to the first and second nodes respectively, causing the transconductance G to... M Based on the output voltage V OUT The degree of deviation from the target value is adaptively increased, thereby improving the transient response speed when the load changes.

[0052] It should be noted that, considering the operating characteristics of the boost circuit at different operating frequencies, the current ratio of the thirty-sixth transistor M36 to the thirty-ninth transistor M39, and the current ratio of the fifty-second transistor M52 to the fifty-fifth transistor M55, can be configured according to different frequencies. This will improve the transient response speed while meeting the circuit stability requirements at different frequencies.

[0053] In one embodiment of this application, such as Figure 4 As shown, the output module 12 includes a 57th transistor M57, a 58th transistor M58, a 59th transistor M59, and a 60th transistor M60. The gate of the 60th transistor M60 is connected to the third terminal of the input module 11, the first terminal of the first current module 13, and the first terminal of the second current module 14, respectively. The source of the 60th transistor M60 receives the power supply voltage VCC. The drain of the 60th transistor M60 is connected to the source of the 59th transistor M59. The drain of the 59th transistor M59 is connected to the drain of the 57th transistor M57 and the first node, respectively. The source of the 57th transistor M57 is connected to the drain of the 58th transistor M58. The gate of the 58th transistor M58 is connected to the fourth terminal of the input module 11, the second terminal of the first current module 13, and the second terminal of the second current module 14, respectively. The source of the 58th transistor M58 is grounded.

[0054] Specifically, the fifteenth transistor M15 and the seventeenth transistor M17 form a negative feedback loop. These transistors detect the differential voltage output from the first transistor M1 and the second transistor M2, convert it into current, and feed a certain proportion of this current back to the sources of the first transistor M1 and the second transistor M2. This feedback from the drain to the source of the first transistor M1 and the second transistor M2 ensures that the first transistor M1 and the second transistor M2 have constant gate-source voltages, further linearizing them. The input difference of input unit 111 is entirely applied to the transconductance resistor R. GM Above, the transconductance resistance R flows GM Provided by the fifteenth transistor M15 and the seventeenth transistor M17, the current flowing through the fifteenth transistor M15 is replicated to the twenty-first transistor M21 in a 1:1 ratio, and then mirrored to the sixtieth transistor M60. The current flowing through the seventeenth transistor M17 is mirrored to the fifty-eighth transistor M58, and then output to the first node in a single-ended manner.

[0055] When the difference between the feedback voltage VFB and the reference voltage VREF is greater than the set value, the current flowing through the sixtieth transistor M60 is less than the current flowing through the fifty-eighth transistor M58, and a third current is output to the first node. The third current is the discharge current.

[0056] When the difference between the reference voltage VREF and the feedback voltage VFB is greater than the set value, the current flowing through the sixtieth transistor M60 is greater than the current flowing through the fifty-eighth transistor M58, and the eighth current is output to the first node. The eighth current is the charging current.

[0057] In summary, the adaptively adjustable transconductance error amplifier circuit 10 provided in this application can output an output voltage V. OUT Current whose change in magnitude is directly proportional to the output voltage V OUT If overshoot occurs, the output discharge current (i.e., the fourth and fifth currents) will be proportional to it, and the output voltage V will increase. OUT If an undershoot occurs, a charging current proportional to it (i.e., the ninth and tenth currents) is output and applied to the first and second nodes respectively, causing the transconductance G to... M Based on the output voltage V OUT The degree of deviation from the target value is adaptively increased, thereby improving the transient response speed when the load changes.

[0058] This application embodiment also provides a boost converter, including a boost circuit and the aforementioned adaptively adjustable transconductance error amplifier circuit 10. The first terminal of the input module 11 in the adaptively adjustable transconductance error amplifier circuit 10 is connected to the feedback node of the boost circuit. The first node of the boost circuit is connected to the third terminal of the output module 12, the third terminal of the first current module 13, and the third terminal of the second current module 14 in the adaptively adjustable transconductance error amplifier circuit 10, respectively. The second node of the boost circuit is connected to the fourth terminal of the first current module 13 and the fourth terminal of the second current module 14, respectively.

[0059] Specifically, the output voltage V OUT via the first feedback resistor R f1 With the second feedback resistor R f2 The sampling network forms a feedback voltage VFB. The error amplifier circuit 10 differentially amplifies the feedback voltage VFB and the reference voltage VREF, and outputs the feedback voltage VFB and the reference voltage VREF. OUT Current whose change in magnitude is directly proportional to the output voltage V OUT If overshoot occurs, the output discharge current, which is proportional to the overshoot, will be the fourth and fifth currents, and the output voltage V will increase. OUT If an undershoot occurs, the output charging current is proportional to it, namely the ninth and tenth currents; when the output voltage V... OUTWhen the voltage fluctuation is large, the current output by the error amplifier circuit 10 will act on the first node and the second node respectively, rapidly charging or discharging them to quickly change the voltage VE1 at the first node and the voltage VE2 at the second node, thereby improving the transient response speed during load transitions. At this time, the transconductance G... m It will vary with the output voltage V OUT The change amplitude increases. The voltage VE1 at the first node and the current sampling signal V... sense Slope compensation signal V SLOPE The superimposed signal is processed by a PWM comparator to generate a PWM comparison signal. The PWM comparison signal and the clock signal CLK are processed sequentially by an RS flip-flop, a level shift and dead time module, and a drive module to output a drive signal, which controls the on and off states of the power transistor MN.

[0060] This application also provides a power supply chip, including the boost converter described above. Since the power supply chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0061] This application also provides an electronic device including the power chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0062] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0063] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An error amplifier circuit with adaptively adjustable transconductance, applied to a boost circuit, the boost circuit comprising an input capacitor, an inductor, a diode, a power transistor, an output capacitor, an equivalent series resistance, a first feedback resistor, a second feedback resistor, a load, a drive module, a current sampling module, a level shift and dead-time module, an RS flip-flop, an OSC, a PWM comparator, an adder, a compensation resistor, and a compensation capacitor; the first terminal of the input capacitor and the first terminal of the inductor both receive the input voltage; the second terminal of the inductor is connected to the drain of the power transistor, the anode of the diode, and the input terminal of the current sampling module, respectively; the cathode of the diode is connected to the first terminal of the output capacitor, the first terminal of the load, and the first terminal of the first feedback resistor, respectively; the second terminal of the output capacitor is connected to the first terminal of the equivalent series resistance; the second terminal of the first feedback resistor is connected to the first terminal of the second feedback resistor; their common terminal is called the feedback node; the second terminal of the input capacitor, the source of the power transistor, and the equivalent series resistance... The second end of the series resistor, the second end of the load, and the second end of the second feedback resistor are all grounded. The output of the current sampling module is connected to the first input of the adder. The second input of the adder is connected to the first output of the OSC. The output of the adder is connected to the positive input of the PWM comparator. The negative input of the PWM comparator is connected to the first end of the compensation resistor. Their common terminal is called the first node. The second end of the compensation resistor is connected to the first end of the compensation capacitor. Their common terminal is called the second node. The second end of the compensation capacitor is grounded. The second output of the OSC is connected to the S terminal of the RS flip-flop. The output of the PWM comparator is connected to the R terminal of the RS flip-flop. The Q terminal of the RS flip-flop is connected to the input of the level shift and dead time module. The output of the level shift and dead time module is connected to the input of the drive module. The output of the drive module is connected to the gate of the power transistor. The characteristic of this configuration is that... The system includes an input module, an output module, a first current module, and a second current module. The first terminal of the input module is connected to the feedback node of the boost circuit to receive a feedback voltage. The second terminal of the input module is used to receive a reference voltage. The first terminal of the first current module is connected to the third terminal of the input module, the first terminal of the output module, and the first terminal of the second current module. The second terminal of the first current module is connected to the fourth terminal of the input module, the second terminal of the output module, and the second terminal of the second current module. The third terminals of the output module, the first current module, and the second current module are all connected to the first node of the boost circuit. The fourth terminals of the first current module and the second current module are both connected to the second node of the boost circuit. When the load current of the boost circuit decreases and the difference between the feedback voltage and the reference voltage is greater than a set value, the input module is used to output a first current and a second current based on the feedback voltage and the reference voltage, wherein the first current is less than the second current; the output module is used to output a third current based on the first current and the second current. The first current module is used to output a fourth current and a fifth current based on the first current and the second current, wherein the fourth current and the fifth current are discharge currents that are proportional to the amplitude of the output voltage change. The third current and the fourth current together discharge the first node, causing the voltage at the first node to drop rapidly; the fifth current discharges the second node, causing the voltage at the second node to drop rapidly. The second current module is used to stop outputting based on the first current and the second current; When the load current increases and the difference between the reference voltage and the feedback voltage is greater than a set value, the input module outputs a sixth current and a seventh current based on the feedback voltage and the reference voltage, wherein the sixth current is greater than the seventh current; the output module outputs an eighth current based on the sixth current and the seventh current; the second current module outputs a ninth current and a tenth current based on the sixth current and the seventh current, wherein the ninth current and the tenth current are charging currents that are proportional to the amplitude of the output voltage change. The eighth current and the ninth current together charge the first node, causing the voltage at the first node to rise rapidly; the tenth current charges the second node, causing the voltage at the second node to rise rapidly. The first current module is used to stop outputting based on the sixth current and the seventh current.

2. The error amplifier circuit with adaptively adjustable transconductance according to claim 1, characterized in that, The input module includes an input unit and a feedback unit. The first end of the input unit is used to connect to the feedback node, the second end of the input unit is used to receive a reference voltage, the third end of the input unit is connected to the first end of the feedback unit, the fourth end of the input unit is connected to the second end of the feedback unit, the fifth end of the input unit is connected to the third end of the feedback unit, and the sixth end of the input unit is connected to the fourth end of the feedback unit. The fifth end of the feedback unit is connected to the first end of the output module, the first end of the first current module, and the first end of the second current module, respectively. The sixth end of the feedback unit is connected to the second end of the output module, the second end of the first current module, and the second end of the second current module, respectively. When the load current of the boost circuit decreases and the difference between the feedback voltage and the reference voltage is greater than a set value, the input unit is used to output a first voltage and a second voltage; the feedback unit is used to output a first current and a second current according to the first voltage and the second voltage, and to feed back a first signal and a second signal to the input unit to improve the linearity of the input unit. When the load current increases from small to large and the difference between the reference voltage and the feedback voltage is greater than a set value, the input unit is used to output a third voltage and a fourth voltage; the feedback unit is used to output a sixth current and a seventh current according to the third voltage and the fourth voltage, and to feed back the third signal and the fourth signal to the input unit to improve the linearity of the input unit.

3. The error amplifier circuit with adaptively adjustable transconductance according to claim 2, characterized in that, The input unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a transconductance resistor. The gate of the first transistor is connected to the feedback node, and the drain of the first transistor is connected to a first terminal of the feedback unit. The source of the first transistor is connected to a first terminal of the transconductance resistor, the drain of the fifth transistor, and a third terminal of the feedback unit. The gate of the second transistor is used to receive a reference voltage, and the drain of the second transistor is connected to a second terminal of the feedback unit. The source of the second transistor is connected to a second terminal of the transconductance resistor, the drain of the sixth transistor, and a fourth terminal of the feedback unit. The source of the fifth transistor is connected to the drain of the third transistor, and the source of the sixth transistor is connected to the drain of the fourth transistor. Both the source of the third transistor and the source of the fourth transistor receive a power supply voltage. Both the gate of the third transistor and the gate of the fourth transistor receive a first bias voltage, and both the gate of the fifth transistor and the gate of the sixth transistor receive a second bias voltage.

4. The error amplifier circuit with adaptively adjustable transconductance according to claim 2, characterized in that, The feedback unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The sources of the seventh transistor, the ninth transistor, and the twenty-fourth transistor all receive a power supply voltage. The gate of the seventh transistor and the ninth transistor... The gates of all transistors receive a first bias voltage. The drain of the seventh transistor is connected to the source of the eighth transistor, and the drain of the ninth transistor is connected to the source of the tenth transistor. The gates of the eighth transistor, the tenth transistor, and the twenty-third transistor all receive a second bias voltage. The drain of the tenth transistor is connected to the gate of the fifteenth transistor, the first terminal of the first resistor, the first terminal of the third resistor, and the drain of the eleventh transistor. The source of the eleventh transistor is connected to the third terminal of the input unit and the drain of the nineteenth transistor. The source of the nineteenth transistor is connected to the drain of the twentieth transistor. The gates of the nineteenth transistor, the twentieth transistor, the thirteenth transistor, and the fourteenth transistor all receive a third bias voltage. The drain of the fourteenth transistor is connected to the source of the thirteenth transistor. The drain of the thirteenth transistor is connected to the source of the twelfth transistor and the fourth terminal of the input unit. The drain of the twelfth transistor is connected to the drain of the eighth transistor, the gate of the seventeenth transistor, the first terminal of the second resistor, and the first terminal of the fourth resistor. The second terminal of the first resistor is connected to the first terminal of the first capacitor, and the second terminal of the second resistor is connected to the first terminal of the second capacitor. The fifteenth transistor... The drain of the transistor is connected to the source of the sixteenth transistor. The gates of the sixteenth transistor, the twenty-second transistor, the eleventh transistor, the twelfth transistor, and the eighteenth transistor all receive a fourth bias voltage. The drain of the sixteenth transistor is connected to the fifth terminal of the input unit. The drain of the seventeenth transistor is connected to the source of the eighteenth transistor. The drain of the eighteenth transistor is connected to the sixth terminal of the input unit. The second terminal of the third resistor is connected to the first terminal of the third capacitor and the gate of the twenty-first transistor. The drain of the twenty-first transistor is connected to the source of the twenty-second transistor.The drain of the 22nd transistor is connected to the drain of the 23rd transistor, the gate of the 24th transistor, the first terminal of the output module, the first terminal of the first current module, and the first terminal of the second current module, respectively. The source of the 23rd transistor is connected to the drain of the 24th transistor. The second terminal of the fourth resistor is connected to the first terminal of the fourth capacitor, the second terminal of the output module, the second terminal of the first current module, and the second terminal of the second current module, respectively. The source of the 21st transistor, the second terminal of the third capacitor, the second terminal of the first capacitor, the source of the 15th transistor, the source of the 20th transistor, the source of the 14th transistor, the second terminal of the second capacitor, the source of the 17th transistor, and the second terminal of the fourth capacitor are all grounded.

5. The error amplifier circuit with adaptively adjustable transconductance according to any one of claims 1-4, characterized in that, The first current module includes transistors 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, and 40. The gate of transistor 26 is connected to the second terminal of the output module, the fourth terminal of the input module, and the second terminal of the second current module. The drain of transistor 26 is connected to the source of transistor 25. The gates of transistors 25, 38, 35, and 40 all receive a fourth bias voltage. The drain of transistor 25 is connected to the drains of transistors 28, 30, 31, 32, and 33. The gates of transistors 28, 30, 31, and 34 all receive a second bias voltage. The source of transistor 28 is connected to the drain of transistor 27. The gate of the transistor is connected to the gate of the 29th transistor, the first terminal of the output module, the first terminal of the second current module, and the third terminal of the input module, respectively. The source of the 30th transistor is connected to the drain of the 29th transistor, the source of the 31st transistor is connected to the drain of the 32nd transistor, and the source of the 34th transistor is connected to the drain of the 33rd transistor. The sources of the 27th, 29th, 32nd, and 33rd transistors all receive power supply voltage. The drain of the 34th transistor is connected to the drain of the 35th transistor. The gates of the thirty-sixth transistor, the thirty-seventh transistor, and the thirty-ninth transistor are connected. The drain of the thirty-ninth transistor is connected to the source of the fortieth transistor. The drain of the fortieth transistor is used to connect to the second node. The source of the thirty-fifth transistor is connected to the drain of the thirty-sixth transistor. The drain of the thirty-seventh transistor is connected to the source of the thirty-eighth transistor. The drain of the thirty-eighth transistor is used to connect to the first node. The sources of the twenty-sixth transistor, the thirty-seventh transistor, the thirty-sixth transistor, and the thirty-ninth transistor are all grounded.

6. The error amplifier circuit with adaptively adjustable transconductance according to any one of claims 1-4, characterized in that, The second current module includes transistors forty-first, forty-second, forty-third, forty-fourth, forty-fifth, forty-sixth, forty-seventh, forty-eighth, forty-ninth, fiftieth, fifty-first, fifty-second, fifty-third, fifty-fourth, fifty-fifth, and fifty-sixth. The gate of transistor forty-first is connected to the first terminal of the first current module, the first terminal of the output module, and the third terminal of the input module. The sources of transistors forty-first, fifty-third, and fifty-fifth are also connected. The source of the 41st transistor and the source of the 52nd transistor both receive a power supply voltage. The drain of the 41st transistor is connected to the source of the 42nd transistor. The gates of the 42nd transistor, the 54th transistor, the 56th transistor, and the 51st transistor all receive a second bias voltage. The drain of the 42nd transistor is connected to the drains of the 43rd transistor, the 46th transistor, the 47th transistor, the 48th transistor, and the 49th transistor, respectively. The gates of the 43rd transistor, the 46th transistor, and the 51st transistor all receive a second bias voltage. The gates of the 47th transistor and the 50th transistor both receive a fourth bias voltage. The source of the 43rd transistor is connected to the drain of the 44th transistor. The source of the 46th transistor is connected to the drain of the 45th transistor. The gate of the 44th transistor is connected to the gate of the 45th transistor, the second terminal of the output module, the fourth terminal of the input module, and the second terminal of the first current module. The source of the 47th transistor is connected to the drain of the 48th transistor. The source of the 50th transistor is connected to the drain of the 49th transistor. The drain of the 50th transistor is connected to the gate of the 45th transistor. The drain of transistor 51, the gate of transistor 55, and the gate of transistor 52 are connected. The source of transistor 51 is connected to the drain of transistor 52. The drain of transistor 55 is connected to the source of transistor 56. The drain of transistor 56 is used to connect to the second node. The drain of transistor 53 is connected to the source of transistor 54. The drain of transistor 54 is used to connect to the first node. The sources of transistors 44, 45, 48, and 49 are all grounded.

7. The error amplifier circuit with adaptively adjustable transconductance according to any one of claims 1-4, characterized in that, The output module includes a 57th transistor, a 58th transistor, a 59th transistor, and a 60th transistor. The gate of the 60th transistor is connected to the third terminal of the input module, the first terminal of the first current module, and the first terminal of the second current module, respectively. The source of the 60th transistor receives the power supply voltage. The drain of the 60th transistor is connected to the source of the 59th transistor. The drain of the 59th transistor is connected to the drain of the 57th transistor and the first node, respectively. The source of the 57th transistor is connected to the drain of the 58th transistor. The gate of the 58th transistor is connected to the fourth terminal of the input module, the second terminal of the first current module, and the second terminal of the second current module, respectively. The source of the 58th transistor is grounded.

8. A boost converter, characterized in that, The circuit includes a boost circuit and an error amplifier circuit with adaptively adjustable transconductance as described in any one of claims 1-7. The first terminal of the input module in the error amplifier circuit with adaptively adjustable transconductance is connected to the feedback node of the boost circuit. The first node of the boost circuit is connected to the third terminal of the output module, the third terminal of the first current module, and the third terminal of the second current module in the error amplifier circuit with adaptively adjustable transconductance, respectively. The second node of the boost circuit is connected to the fourth terminal of the first current module and the fourth terminal of the second current module, respectively.

9. A power supply chip, characterized in that, Includes the boost converter as described in claim 8.

10. An electronic device, characterized in that, Includes the power chip as described in claim 9.

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