A distributed communication method based on a double plane architecture and adaptive erasure code

Abstract

This invention relates to the field of data communication and provides a distributed communication method based on a dual-plane architecture and adaptive erasure coding. The method includes constructing a global scheduler, creating logical mailboxes within the global scheduler, and establishing exchange links; processing received data by embedding data length and padding with zeros to obtain encoded data; performing target sandbox delivery on the encoded data according to a data block threshold to obtain decoded data; enqueuing the data and promoting it from the lower network plane to the upper application plane; calculating sequence number differences; accumulating these sequence number differences to calculate packet loss assessment parameters; updating the data block threshold based on the packet loss assessment parameters to obtain an iterative data block threshold; writing the iterative data block threshold to a pending configuration buffer; obtaining indicator parameters; retrieving the iterative data block threshold from the pending configuration buffer; and updating the parameters using the iterative data block threshold. This invention can complete data communication.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a distributed communication method based on a dual-plane architecture and adaptive erasure coding. Background Technology

[0002] With the continuous evolution of distributed computing and IoT technologies, mission-critical distributed systems, such as intelligent vehicle-road cooperation and centralized industrial control, are undergoing a profound evolution from traditional local area networks (LANs) to cross-regional wide area network (WAN) interconnection. In WAN hybrid network environments, due to long physical links and complex routing nodes, network transmission inevitably suffers from high latency jitter and sudden cluster packet loss phenomena.

[0003] Meanwhile, the data flows carried within mission-critical systems exhibit stringent heterogeneous constraints: for example, continuous real-time data has extremely high timeliness, requiring microsecond-level end-to-end latency, and retransmission after expiration is meaningless; while discrete control commands are highly transactional data, with an absolute "zero packet loss" requirement for data integrity and order preservation. Faced with the inherent contradiction between wide area network environments and heterogeneous business needs, existing communication middleware suffers from the following significant objective technical deficiencies in its underlying architecture, error correction algorithms, and concurrency optimization mechanisms: 1. The failure of traditional transmission protocols and conventional hybrid architectures in complex WANs: Existing distributed communication largely relies on a single transport layer protocol. If TCP is used, its underlying mechanism relies on automatic retransmission requests. When facing packet loss in a WAN cluster, high-frequency timeout retransmissions can cause severe "head-of-line congestion," leading to a large backlog of subsequent continuous real-time data that expires and completely loses its timeliness. If native UDP is used, although head-of-line congestion is eliminated, the lack of basic reliability management makes it highly susceptible to irreversible loss of discrete control commands. Even when some existing systems attempt to use a hybrid approach of TCP and UDP, it is often only a business split at the application layer. This approach has flaws: when WAN congestion occurs, commands using TCP will still be delayed due to head-of-line congestion, causing critical transactions to stall.

[0004] 2. Computational Bottlenecks and Adaptation Challenges for Variable-Length Streams in Existing Forward Error Correction Algorithms: To compensate for network packet loss, current application-layer algorithms often employ forward error correction schemes based on Reed-Solomon coding. However, Reed-Solomon coding heavily relies on polynomial multiplication over the Galois field for encoding and decoding, requiring frequent memory lookup operations in pure software implementations. This easily leads to CPU cache misses, resulting in significant computational overhead and microsecond-level latency jitter, making it difficult to meet the extreme latency requirements of continuous real-time data. On the other hand, while array codes based on pure bitwise operations have extremely low CPU overhead, their native mathematical model is designed for disk storage, requiring absolutely consistent memory block lengths for computation. Since the length of application-layer network packets is often highly random, directly introducing native array codes can cause memory step size calculation errors and memory overflow crashes. Existing technologies struggle to achieve perfect compatibility of array codes with variable-length network packet streams with extremely low computational overhead.

[0005] 3. Lack of closed-loop network awareness and security mechanisms for multi-threaded concurrent parameter tuning: Existing technologies mostly use static redundant parameters, which either result in excessive redundancy and wasted bandwidth in time-varying channels, or insufficient fault tolerance leading to decoding failures. Even if some systems attempt to introduce dynamic parameter adjustment, they still face serious security risks in multi-threaded concurrent environments: In high-throughput scenarios with concurrent transmission and reception, if the control thread attempts to directly modify the erasure parameters being used by the data thread based on the network situation, without locking, it will instantly destroy the dimension of the two-dimensional data matrix being assembled, causing the program to crash; if traditional mutex locks are used for cross-thread state synchronization, frequent lock contention will cause threads to be suspended and context switched frequently, resulting in a precipitous drop in the system's network throughput. Summary of the Invention

[0006] This invention aims to at least solve one of the technical problems existing in related technologies. To this end, this invention provides a distributed communication method based on a dual-plane architecture and adaptive erasure coding, achieving lossless transmission of data with low latency and stable throughput.

[0007] This invention provides a distributed communication method based on a dual-plane architecture and adaptive erasure coding, comprising: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0008] According to the distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the present invention, step S1 further includes: S11: Construct a global scheduler, instantiate a UDP socket and configure a TCP listener in the global scheduler, construct the pull-up data plane through the UDP socket, and construct the pull-up control plane through the TCP listener; S12: Create a mailbox logical identifier in the global scheduler, and create the logical mailbox according to the mailbox logical identifier; S13: The data plane is pulled up to obtain the handshake signal. The handshake signal is verified through the data plane and the logical mailbox. If the verification is successful, the switching link is established.

[0009] According to the distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the present invention, step S2 further includes: S21: After the switching link obtains the received data, it determines the actual data length of the received data, converts the actual data length into a little-endian length, and embeds the little-endian length into the starting physical memory address of the received data to obtain the length-embedded data. S22: Determine the maximum load threshold, and pad the length embedded data with zeros according to the maximum load threshold to obtain the processed data; S23: Determine the continuous memory step size constraint, and under the constraint of the continuous memory step size constraint, perform row diagonal parity check encoding on the processed data through in-place XOR operation to obtain parity check encoded data, and perform data encoding on the parity check encoded data to obtain the encoded data.

[0010] According to the distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the present invention, step S3 further includes: S31: By demultiplexing the physical link of the global scheduler, the encoded data is delivered to the target sandbox, the data block threshold is determined, and the encoded data is received in batches in the target sandbox according to the data block threshold. S32: Determine the data integrity of the encoded data in the target sandbox, select the target recovery logic from the recovery logic including single packet loss recovery and double packet loss recovery according to the data integrity, and recover the lost data of the encoded data through the target recovery logic; S33: Perform length metadata parsing and data segmentation on the encoded data to obtain the decoded data.

[0011] According to the distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the present invention, step S4 further includes: S41: Acquire a mutex lock, enqueue the decoded data using the mutex lock and send a single-point wake-up signal, and promote the decoded data from the underlying network plane to the upper application plane according to the single-point wake-up signal; S42: In the upper application plane, obtain the data sequence number and historical sequence number of the decoded data, calculate the sequence number difference through the data sequence number and historical sequence number, and determine the data status based on the sequence number difference; S43: Initialize the global state counter, and increment the global state counter according to the data state to obtain the counter parameter; S44: Calculate the packet loss evaluation parameters, including the steady-state packet loss rate and the expected average length, based on the counter parameters; select a threshold calculation strategy based on the expected average length; determine the constraint boundary through the steady-state packet loss rate; and update the data block threshold according to the threshold calculation strategy under the constraint of the constraint boundary to obtain the iterative data block threshold.

[0012] According to the distributed communication method based on dual-plane architecture and adaptive erasure coding provided by the present invention, in step S5, the initial value of the indicator parameter is 1, the number of the write data row group of the exchange link is obtained, when the number of the write data row group is 0, the indicator parameter is set to 0, and when the indicator parameter is 0, the parameter is updated by iterating the data block threshold to complete the configuration overwrite and memory reallocation.

[0013] This invention also provides a distributed communication system based on a dual-plane architecture and adaptive erasure coding, comprising: Switching Link Module: Used to build a global scheduler that includes raising the control plane and raising the data plane, create logical mailboxes in the global scheduler, and establish switching links by raising the data plane and logical mailboxes; Encoded data module: Used to acquire received data through the switching link, perform data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and perform row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; Data receiving and decoding module: used to determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and recover and decode lost data to obtain decoded data; Iterative data block threshold module: It is used to enqueue decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, the sequence number difference is calculated, the global state counter is initialized, the sequence number difference is accumulated to obtain the counter parameter, the packet loss evaluation parameter is calculated using the counter parameter, and the data block threshold is updated based on the packet loss evaluation parameter to obtain the iterative data block threshold. Configuration update module: Used to initiate the control plane to write the iterative data block threshold into the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described above.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described above.

[0016] The present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, and when the program instructions are executed by a computer, the computer is able to perform the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described above.

[0017] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects: This invention provides a distributed communication method based on a dual-plane architecture and adaptive erasure coding. It achieves high-concurrency isolation and low-latency routing for multiple endpoints under a single node through a global scheduler. By delivering encoded data to a target sandbox, receiving it in batches, and recovering and decoding lost data, it transforms matrix algebra operations into bitwise XOR and linear loop operations natively supported by the central processing unit. This improves the instruction cache hit rate, reduces the computational latency for reconstructing variable-length business data, and, from the processing architecture perspective, eliminates the impact of network long-tail effects on decoding real-time performance. Simultaneously, in the cross-thread delivery stage, the system uses mutexes and condition variables to enable on-demand suspension and single-point wake-up of consumers, avoiding empty polling of application worker threads and reducing unnecessary resource consumption. Dynamically adjusting the data block threshold based on data loss assessment parameters achieves automated adjustment of error correction redundancy for different priority business flows without generating additional probe traffic.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the present invention.

[0021] Figure 2 This is a schematic diagram of the structure of a distributed communication system based on a dual-plane architecture and adaptive erasure coding provided by the present invention.

[0022] Figure 3 This is a schematic diagram of the structure of a distributed communication device based on a dual-plane architecture and adaptive erasure coding provided by the present invention.

[0023] Figure label: 100. Switching link module; 200. Encoded data module; 300. Data receiving and decoding module; 400. Iterative data block threshold module; 500. Configuration update module; 810. Processor; 820. Communication interface; 830. Memory; 840. Communication bus. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The following embodiments are used to illustrate this invention but cannot be used to limit the scope of this invention.

[0025] In the description of the embodiments of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0027] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0028] The following is combined with Figures 1 to 3 Specific embodiments of the present invention are described below. Figure 1 A flowchart illustrating a distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by this invention includes: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; Furthermore, the objective of this stage is to construct a global scheduler and create logical mailboxes, thereby establishing a switching link. Specifically, step S1 further includes: S11: Construct a global scheduler, instantiate a UDP socket and configure a TCP listener in the global scheduler, construct the pull-up data plane through the UDP socket, and construct the pull-up control plane through the TCP listener; S12: Create a mailbox logical identifier in the global scheduler, and create the logical mailbox according to the mailbox logical identifier; S13: The data plane is pulled up to obtain the handshake signal. The handshake signal is verified through the data plane and the logical mailbox. If the verification is successful, the switching link is established.

[0029] The specific implementation method for the above steps in this embodiment is as follows: First, a global scheduler needs to be built to uniformly manage all network I / O resources and endpoint lifecycles within a node. Upon system startup, the underlying asynchronous event-driven engine is initialized first, and an independent worker thread is allocated to it to ensure that all subsequent network send / receive operations are executed efficiently in non-blocking mode. Then, a globally unique and shared UDP socket is instantiated and bound in the global scheduler. This socket serves as the unified foreground channel for all data entering and leaving the current physical node. After the UDP socket binding is complete, the data plane is established, and the system immediately starts a resident low-level asynchronous receive loop, bringing the data plane into a full-duplex, high-speed send / receive ready state. In addition, a control plane also needs to be built. This involves the system instantiating a TCP listener and binding it to a specified physical port according to preset configuration parameters. Once started, this listener immediately enters a background asynchronous receive state, dedicated to waiting for connection requests from other distributed nodes. The control plane is dedicated to a highly reliable physical channel for independent signaling interaction and network status parameter feedback.

[0030] Next, a logical mailbox identifier needs to be created in the global scheduler. This involves the global scheduler generating a globally unique logical mailbox identifier in memory based on the request, thereby synchronously allocating and instantiating a logical mailbox. Subsequently, the global scheduler binds the business name of this logical mailbox to the logical mailbox identifier and stores it in a concurrent hash mapping dictionary in system memory. This mechanism achieves complete decoupling between application-layer logical addressing and the underlying physical topology, giving the system extremely high location transparency.

[0031] Subsequently, the initiator of the communication constructs and sends a handshake signal containing multi-dimensional routing characteristics. This signal carries not only the name and logical identifier of the initiator's logical mailbox, but also the global UDP port number that the initiator's data plane is listening on, and the name of the logical mailbox to be sent. If the data plane can match the global UDP port number that the initiator's data plane is listening on, it extracts the name of the logical mailbox to be sent and performs verification in its local concurrent hash mapping dictionary. If the logical mailbox to be sent exists, the global scheduler constructs a switching link and sends the acknowledgment signal back along the original path; if it does not exist, it actively closes the connection, rejecting the establishment of illegal data. The network 5-tuple of the switching link is strongly bound to the mailbox logical identifier and has a dedicated array-coded transmitter and receiver, ensuring that it does not interfere with other switching links.

[0032] S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; Furthermore, the purpose of this stage is to acquire the received data. This involves embedding the data length, padding with zeros to align the received data, and then encoding the data to obtain the encoded data. Specifically, step S2 further includes: S21: After the switching link obtains the received data, it determines the actual data length of the received data, converts the actual data length into a little-endian length, and embeds the little-endian length into the starting physical memory address of the received data to obtain the length-embedded data. S22: Determine the maximum load threshold, and pad the length embedded data with zeros according to the maximum load threshold to obtain the processed data; S23: Determine the continuous memory step size constraint, and under the constraint of the continuous memory step size constraint, perform row diagonal parity check encoding on the processed data through in-place XOR operation to obtain parity check encoded data, and perform data encoding on the parity check encoded data to obtain the encoded data.

[0033] The specific implementation method for the above steps in this embodiment is as follows: First, the switching link needs to acquire the received data. Then, the actual data length is determined. To prevent byte order parsing errors due to cross-platform compatibility, the system forcibly converts the actual data length to a fixed two-byte little-endian value, thus obtaining the little-endian length. This little-endian length is then embedded into the starting physical memory address of the received data, resulting in the length embedding data. This step adds hard-coded length metadata to the header of the received data, specifically for accurately defining the physical boundaries of the actual business data after array decoding at the receiving end.

[0034] When the system inputs length-embedded data into the buffer area, for the remaining memory area where the actual copy length is less than the preset maximum load threshold, the system performs forced zero padding to obtain the processed data. This step constructs a two-dimensional encoding space with strictly aligned lengths, completely eliminating the risk of pointer out-of-bounds errors during matrix operations.

[0035] Subsequently, a continuous memory step size constraint is determined. In this embodiment, the total length of the load slots is required to be perfectly divisible by a preset prime number parameter. This constraint ensures that no byte truncation will occur when the underlying pointer slides according to the preset calculated memory step size. Under the constraint of the continuous memory step size, row-by-row diagonal parity check encoding is performed on the processed data through in-place XOR operation to obtain parity check encoded data. That is, using the bitwise XOR instruction natively supported by the CPU, the encoding module directly performs double traversal in-place on the continuous physical memory address where the original business data is located: horizontal vectorized XOR is performed using continuous memory offsets to generate row parity data; diagonal XOR is performed using modulo operation to calculate the physical span to generate diagonal parity data. Thus, row-by-row diagonal parity check encoding is completed without any data copying. In addition, priority identifiers, globally unique incrementing sequence numbers used for situational awareness, identifiers of the current operation batch, group sequence numbers, and currently effective redundant configuration parameters need to be written into the parity check encoded data, and then injected into the physical network instantly using the underlying asynchronous non-blocking interface to obtain the encoded data. Then, the current two-dimensional buffer matrix is ​​cleared, the row pointers are reset, and preparations are made for the assembly of the next batch of data.

[0036] S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; Furthermore, the objective of this stage is to perform calculations on the encoded data based on the data block threshold to obtain the decoded data. Specifically, step S3 further includes: S31: By demultiplexing the physical link of the global scheduler, the encoded data is delivered to the target sandbox, the data block threshold is determined, and the encoded data is received in batches in the target sandbox according to the data block threshold. S32: Determine the data integrity of the encoded data in the target sandbox, select the target recovery logic from the recovery logic including single packet loss recovery and double packet loss recovery according to the data integrity, and recover the lost data of the encoded data through the target recovery logic; S33: Perform length metadata parsing and data segmentation on the encoded data to obtain the decoded data.

[0037] The specific implementation method for the above steps in this embodiment is as follows: First, the physical links of the global scheduler need to be demultiplexed to deliver the encoded data to the target sandbox. This involves uniformly capturing the data stream via UDP sockets and using an asynchronous receive callback function to instantly intervene, stripping the fixed-length communication protocol header from the packets and extracting the mailbox logical identifier. The system uses this mailbox logical identifier as the routing anchor point to demultiplex the highly multiplexed physical link stream, directly delivering the encoded data to the target sandbox of the link bound to the logical mailbox. This mechanism completely decouples the logical addressing of upper-layer services from the underlying physical network topology, achieving massive endpoint concurrency isolation under a single physical port.

[0038] Subsequently, a data block threshold K is determined. The receiver array engine built into the switching link collects out-of-order encoded data in groups according to batch identifiers. To reduce latency, the receiver engine does not wait for all the encoded data in the current batch to arrive; once it detects that the number of successfully collected encoded data in the same batch has reached the data block threshold, the engine immediately interrupts the collection process and sends the encoded data out for data integrity verification. This mechanism eliminates the impact of the network long tail effect on decoding real-time performance at the architectural level.

[0039] The system then checks the integrity of the encoded data in the target sandbox to determine its completeness. If incomplete, lost data recovery is required. This involves determining whether the recovery logic is for a single packet loss or a double packet loss. If it's a single packet loss, single-packet recovery is performed, directly executing a basic one-dimensional vectorized XOR operation along the row or diagonal check path to recover the lost data. If it's a double packet loss, double-packet recovery is performed, completely abandoning the time-consuming matrix inversion process relying on finite field multiplication and Gaussian elimination found in traditional Reed-Solomon coding. The system pre-allocates a lightweight state marker array in memory. Based on the location of the lost encoded data, the algorithm records the horizontal and diagonal intersection maps using the state array. Subsequently, the engine calculates the physical span using simple modulo operations and performs iterative pure XOR calculations along the Zig-Zag broken line path to recover the lost data.

[0040] The lossless encoded data is then parsed using length metadata, which involves taking the first two little-endian bytes at the starting physical memory address and restoring them to the actual data length from little-endian. The engine then uses this data length as a hard benchmark to precisely truncate and discard the trailing zero-padding bytes, obtaining the decoded data.

[0041] S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. Furthermore, the objective of this stage is to enqueue the decoded data and obtain packet loss assessment parameters, thereby updating the data block threshold based on the packet loss assessment parameters to obtain the iterative data block threshold. Specifically, step S4 further includes: S41: Acquire a mutex lock, enqueue the decoded data using the mutex lock and send a single-point wake-up signal, and promote the decoded data from the underlying network plane to the upper application plane according to the single-point wake-up signal; S42: In the upper application plane, obtain the data sequence number and historical sequence number of the decoded data, calculate the sequence number difference through the data sequence number and historical sequence number, and determine the data status based on the sequence number difference; S43: Initialize the global state counter, and increment the global state counter according to the data state to obtain the counter parameter; S44: Calculate the packet loss evaluation parameters, including the steady-state packet loss rate and the expected average length, based on the counter parameters; select a threshold calculation strategy based on the expected average length; determine the constraint boundary through the steady-state packet loss rate; and update the data block threshold according to the threshold calculation strategy under the constraint of the constraint boundary to obtain the iterative data block threshold.

[0042] The specific implementation method for the above steps in this embodiment is as follows: First, the network worker thread needs to acquire the mutex lock within the logical mailbox. After successfully acquiring the mutex lock, the network worker thread pushes the decoded data as an independent node into the asynchronous concurrent buffer queue built into the logical mailbox. Once the data enqueue operation is complete, the network worker thread immediately sends a single-point wake-up signal via a condition variable, then releases the mutex lock and returns to the underlying network listening state to continue receiving subsequent decoded data. When the application worker thread is in a suspended state, once it captures the single-point wake-up signal, it wakes up from the operating system scheduler and reacquires the mutex lock for the logical mailbox. After acquiring the mutex lock, the application worker thread extracts the decoded data, then releases the mutex lock and transfers it to the upper-layer time-consuming business computation pipeline, thus elevating the decoded data from the underlying network plane to the upper-layer application plane. If a client actively queries the data, the application worker thread first checks the status of the buffer queue. If the buffer queue is empty, the application worker thread does not execute an infinite loop check that consumes computational resources, but instead suspends itself to conserve computing resources.

[0043] Subsequently, in the upper-layer application plane, the system parses the communication protocol header of the decoded data and extracts the globally incrementing sequence number, which is the data sequence number. It also needs to obtain the sequence number of the last successfully received legitimate message maintained in memory, i.e., the historical sequence number, and calculate the difference between the current sequence number and the historical sequence number. The calculation logic for the difference is: subtract the historical sequence number from the current sequence number, and then subtract 1 to obtain the data difference. If the data difference is equal to zero, it indicates that the decoded data has arrived continuously; if the data difference is greater than zero, it indicates that the network has experienced a continuous number of packet loss events equal to the difference, thus completing the confirmation of the data status.

[0044] Subsequently, global state counters are initialized, including good-to-good, good-to-poor, poor-to-good, and poor-to-poor counters. Furthermore, the system needs to evaluate the communication quality of the switching links and classify it as good or poor. When the data status indicates that no continuous packet loss has occurred, if the current channel status is good and the previous status was good, the good-to-good counter is incremented once; if the current channel status is good and the previous status was poor, the poor-to-good counter is incremented once. When the data status indicates a continuous packet loss event, for the first decoded data packet that is lost, if the channel status was good at the previous moment, a transition from good to bad occurs, and the good-to-bad counter is incremented once. If the channel status was already bad at the previous moment, the bad-to-bad counter is incremented once. The number of subsequent lost decoded data packets is used to increment the bad-to-bad counter as many times as possible. Finally, since the current decoded data has successfully arrived, the system determines that the switching link has been restored, generating a transition from bad to good, and incrementing the bad-to-good counter once. This yields the values ​​of each counter within a statistical time window, which are the counter parameters.

[0045] At the end of the preset statistical time window, the system extracts the accumulated values ​​of the four counters mentioned above. Then, it calculates the actual probability p of transitioning from good to poor: in, The value of the counter from good to poor quality. The value of the good-to-good counter is given. Then, the actual probability r of a defective product transitioning to a good product is calculated: in, The value of the counter is from poor to good. This is the value of the poor-to-poor counter. This allows us to calculate the steady-state packet loss rate. : We can also use the reciprocal of the actual probability of transferring from poor to good data loss as the expected average length, thus obtaining the packet loss evaluation parameters. Subsequently, to calculate the iterative data block threshold... First, it is necessary to determine the threshold calculation strategy, which includes both high-priority discrete control command strategy and mid-priority continuous real-time data strategy. The system introduces a safety margin coefficient γ and, based on the steady-state packet loss rate, determines the constraint boundaries: When the decoded data is high-priority data or the expected average length exceeds the system safety threshold, the system selects a high-priority discrete control command strategy, which forces the iterative data block threshold to be set to a preset lower limit, thus obtaining the iterative data block threshold. When the decoded data is not high-priority data and the expected average length is lower than the system safety threshold, the system selects a medium-priority continuous real-time data strategy, and the iterative data block threshold is calculated in this case: In this way, the threshold of the iterative data block can be obtained when the threshold of the iterative data block is less than or equal to the preset prime number parameter.

[0046] S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0047] Furthermore, the purpose of this stage is to obtain the indication parameter and update the parameter by iterating through the data block threshold to complete the data communication. Specifically, in step S5, the initial value of the indication parameter is 1, the write data row group number of the switching link is obtained, when the write data row group number is 0, the indication parameter is set to 0, and when the indication parameter is 0, the parameter is updated by iterating through the data block threshold to complete the configuration overwrite and memory reallocation.

[0048] The specific implementation method for the above steps in this embodiment is as follows: Here, the iterative data block threshold is sent to the pending configuration buffer of the control plane via a pre-established transmission control protocol. Then, the indicator parameter is checked; its initial value is 1. During data encoding, a status probe is inserted. When the status probe detects that the data row group number is 0, meaning the previous batch of data has been encoded and sent, but the next batch has not yet been encoded, the indicator parameter is set to 0. At this point, the parameters are updated using the iterative data block threshold. This means the current data block threshold is overwritten with the iterative data block threshold, becoming the new threshold. Simultaneously, the physical row count and memory span of the encoded data buffer are recalculated based on the new threshold. The old buffer space is released from the memory pool, and a new buffer space that meets the new parameter step size requirements is allocated, thus completing memory reallocation. This completes the parameter update, preparing for the next data communication and completing one data communication cycle.

[0049] The following describes a distributed communication device based on a dual-plane architecture and adaptive erasure coding provided by the present invention. The distributed communication device based on a dual-plane architecture and adaptive erasure coding described below and the distributed communication method based on a dual-plane architecture and adaptive erasure coding described above can be referred to and correspond to each other.

[0050] Figure 2 An example is provided: a schematic diagram of a distributed communication system based on a dual-plane architecture and adaptive erasure coding, as shown below. Figure 2 As shown, a distributed communication method based on a dual-plane architecture and adaptive erasure coding, as described above, includes: Switching link module 100: Used to build a global scheduler that includes raising the control plane and raising the data plane, create logical mailboxes in the global scheduler, and establish switching links by raising the data plane and logical mailboxes; Encoding data module 200: Used to acquire received data through the switching link, perform data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and perform row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; Data receiving and decoding module 300: used to determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain decoded data; Iterative data block threshold module 400: It is used to enqueue decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, the sequence number difference is calculated, the global state counter is initialized, the sequence number difference is accumulated to obtain the counter parameter, the packet loss evaluation parameter is calculated using the counter parameter, and the data block threshold is updated based on the packet loss evaluation parameter to obtain the iterative data block threshold. Configuration update module 500: It is used to pull up the control plane to write the iterative data block threshold into the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0051] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830, and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other via the communication bus 840. The processor 810 can call a computer program in the memory 830 to execute a distributed communication method based on a dual-plane architecture and adaptive erasure coding, the method including: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0052] Furthermore, when the computer program in the aforementioned memory 830 can be implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0053] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute a distributed communication method based on a dual-plane architecture and adaptive erasure coding provided by the above methods, the method comprising: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0054] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the aforementioned distributed communication method based on a dual-plane architecture and adaptive erasure coding, the method comprising: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

[0055] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0056] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A distributed communication method based on a dual-plane architecture and adaptive erasure coding, characterized in that, include: S1: Construct a global scheduler that includes raising the control plane and raising the data plane, create a logical mailbox in the global scheduler, and establish a switching link by raising the data plane and the logical mailbox; S2: The switching link acquires the received data, performs data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and performs row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; S3: Determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and perform lost data recovery and decoding to obtain the decoded data; S4: Enqueue the decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, calculate the sequence number difference, initialize the global state counter, accumulate the sequence number difference to obtain the counter parameter, use the counter parameter to calculate the packet loss evaluation parameter, update the data block threshold based on the packet loss evaluation parameter, and obtain the iterative data block threshold. S5: Raise the control plane to write the iterative data block threshold to the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

2. The distributed communication method based on a dual-plane architecture and adaptive erasure coding according to claim 1, characterized in that, Step S1 further includes: S11: Construct a global scheduler, instantiate a UDP socket and configure a TCP listener in the global scheduler, construct the pull-up data plane through the UDP socket, and construct the pull-up control plane through the TCP listener; S12: Create a mailbox logical identifier in the global scheduler, and create the logical mailbox according to the mailbox logical identifier; S13: The data plane is pulled up to obtain the handshake signal. The handshake signal is verified through the data plane and the logical mailbox. If the verification is successful, the switching link is established.

3. The distributed communication method based on a dual-plane architecture and adaptive erasure coding according to claim 1, characterized in that, Step S2 further includes: S21: After the switching link obtains the received data, it determines the actual data length of the received data, converts the actual data length into a little-endian length, and embeds the little-endian length into the starting physical memory address of the received data to obtain the length-embedded data. S22: Determine the maximum load threshold, and pad the length embedded data with zeros according to the maximum load threshold to obtain the processed data; S23: Determine the continuous memory step size constraint, and under the constraint of the continuous memory step size constraint, perform row diagonal parity check encoding on the processed data through in-place XOR operation to obtain parity check encoded data, and perform data encoding on the parity check encoded data to obtain the encoded data.

4. The distributed communication method based on a dual-plane architecture and adaptive erasure coding according to claim 1, characterized in that, Step S3 further includes: S31: By demultiplexing the physical link of the global scheduler, the encoded data is delivered to the target sandbox, the data block threshold is determined, and the encoded data is received in batches in the target sandbox according to the data block threshold. S32: Determine the data integrity of the encoded data in the target sandbox, select the target recovery logic from the recovery logic including single packet loss recovery and double packet loss recovery according to the data integrity, and recover the lost data of the encoded data through the target recovery logic; S33: Perform length metadata parsing and data segmentation on the encoded data to obtain the decoded data.

5. A distributed communication method based on a dual-plane architecture and adaptive erasure coding as described in claim 1, characterized in that, Step S4 further includes: S41: Acquire a mutex lock, enqueue the decoded data using the mutex lock and send a single-point wake-up signal, and promote the decoded data from the underlying network plane to the upper application plane according to the single-point wake-up signal; S42: In the upper application plane, obtain the data sequence number and historical sequence number of the decoded data, calculate the sequence number difference through the data sequence number and historical sequence number, and determine the data status based on the sequence number difference; S43: Initialize the global state counter, and increment the global state counter according to the data state to obtain the counter parameter; S44: Calculate the packet loss evaluation parameters, including the steady-state packet loss rate and the expected average length, based on the counter parameters; select a threshold calculation strategy based on the expected average length; determine the constraint boundary through the steady-state packet loss rate; and update the data block threshold according to the threshold calculation strategy under the constraint of the constraint boundary to obtain the iterative data block threshold.

6. The distributed communication method based on a dual-plane architecture and adaptive erasure coding according to claim 1, characterized in that, In step S5, the initial value of the indicator parameter is 1. The number of the write data row group of the switching link is obtained. When the number of the write data row group is 0, the indicator parameter is set to 0. When the indicator parameter is 0, the parameter is updated by iterating the data block threshold to complete the configuration overwrite and memory reallocation.

7. A distributed communication system based on a dual-plane architecture and adaptive erasure coding, used to execute a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described in any one of claims 1 to 6, characterized in that, include: Switching Link Module: Used to build a global scheduler that includes raising the control plane and raising the data plane, create logical mailboxes in the global scheduler, and establish switching links by raising the data plane and logical mailboxes; Encoded data module: Used to acquire received data through the switching link, perform data length embedding and fixed-length zero padding alignment on the received data to obtain processed data, and perform row diagonal parity check encoding and data encoding on the processed data to obtain encoded data; Data receiving and decoding module: used to determine the data block threshold, deliver the encoded data to the target sandbox and receive it in batches according to the data block threshold, and recover and decode lost data to obtain decoded data; Iterative data block threshold module: It is used to enqueue decoded data and promote it from the underlying network plane to the upper application plane. In the upper application plane, the sequence number difference is calculated, the global state counter is initialized, the sequence number difference is accumulated to obtain the counter parameter, the packet loss evaluation parameter is calculated using the counter parameter, and the data block threshold is updated based on the packet loss evaluation parameter to obtain the iterative data block threshold. Configuration update module: Used to initiate the control plane to write the iterative data block threshold into the configuration buffer to be effective, obtain the indication parameter, retrieve the iterative data block threshold from the configuration buffer to be effective according to the indication parameter, and update the parameters through the iterative data block threshold to complete the data communication.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described in any one of claims 1 to 6.

10. A computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, characterized in that, When the program instructions are executed by the computer, the computer is able to perform the steps of a distributed communication method based on a dual-plane architecture and adaptive erasure coding as described in any one of claims 1 to 6.

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