Thermal interface material
By employing a sandwich structure of graphite and metal layers in the thermal interface material, the problem of poor heat dissipation performance is solved, the heat dissipation efficiency of the chip stack structure is improved, and high-frequency operation of high-performance components is supported.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 宋健民
- Filing Date
- 2025-01-21
- Publication Date
- 2026-07-24
Smart Images
Figure CN122443033A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a thermal interface material, and more particularly to a composite thermal interface material of metal and graphite. Background Technology
[0002] With the miniaturization of transistors within integrated circuits, 4-nanometer processes are now in mass production, and 2-nanometer technology is under active development. Due to the increasing demands for high-performance computing from artificial intelligence (AI), advanced packaging technologies are gradually moving towards stacking high-bandwidth memory (HBM) and integrating system-on-a-chip (SoC) devices such as GPUs. Therefore, chips require larger metal covers for packaging, and circuitry is shunt to the circuit board (PCB) through a silicon interposer; this is known as CoWoS (Chip on Wafer on Substrate) technology.
[0003] The extremely high density of transistors, reaching hundreds of billions, makes it difficult to eliminate hotspots within the chip in a timely manner, thus limiting the computing speed of AI or other high-performance components (such as autonomous driving systems). Traditional chip packaging (such as SoC) involves horizontal packaging on a circuit board (PCB), which results in larger transistor areas and potential signal delays between chips. However, with the rapid growth in computing power demands, especially driven by the rapid development of AI, planar transistors can no longer meet the requirements. Therefore, three-dimensional (3D IC) packaging with stacked chips is gradually becoming mainstream. For example, CoWoS technology has been widely used in systems such as robotics, autonomous driving, big data analytics, and cloud storage.
[0004] However, as chip clock speeds increase, so does the amount of heat generated. Since 2005, the processing speed of silicon-based transistors has been approaching the physical limit of 4 GHz. Currently, the total number of multi-core transistors exceeds hundreds of billions (such as in NVIDIA's B200 graphics card). However, due to hotspot issues, overall processing speed cannot be improved; instead, the increased density makes it more difficult to maintain system reliability. Summary of the Invention
[0005] The main objective of this invention is to solve the problem of poor heat dissipation performance of known thermal interface materials.
[0006] To address the aforementioned problems, the present invention provides a thermal interface material for contacting a heat source and conducting heat generated by the heat source. The thermal interface material includes at least one graphite layer and at least one metal layer, wherein the graphite layer and the metal layer are stacked on top of each other, and the metal layer has a non-planar structure that is at least partially inserted into the graphite layer along the thickness direction.
[0007] In one embodiment, the metal layer is copper or aluminum.
[0008] In one embodiment, the thermal interface material has a thermal conductivity of at least 100 W / mK in the thickness direction.
[0009] In one embodiment, the non-planar structure is a mesh structure or a needle-like structure.
[0010] In one embodiment, the graphite layer is manufactured using a polyimide as a precursor.
[0011] In one embodiment, the graphite layer is a recrystallized graphite film or a graphene stacked film.
[0012] In one embodiment, a thermal interface material is used in a chip stack structure.
[0013] In one embodiment, the thermal interface material serves as an intermediary layer in the chip stack structure.
[0014] In one embodiment, a thermal interface material is used in a chip packaging structure.
[0015] In one embodiment, a single graphite layer has a first thickness t1 before being stacked, a single metal layer has a second thickness t2 before being stacked, and a single metal layer sandwiched between two graphite layers with a total thickness t3 after compression, which conforms to the following relationship to expel gas between the graphite and metal layers:
[0016] . Attached Figure Description
[0017] Figure 1 This is a side view schematic diagram of an embodiment of the present disclosure.
[0018] Figure 2A and Figure 2B This is a schematic diagram of another embodiment of the present disclosure.
[0019] Figure 3 This is a schematic diagram of yet another embodiment of the present disclosure.
[0020] Figure 4 This is a schematic diagram of a chip packaging structure according to an embodiment of the present disclosure.
[0021] Figure 5 This is a schematic diagram of a chip packaging structure according to another embodiment of the present disclosure.
[0022] Figure 6 This is a schematic diagram of a chip module according to an embodiment of the present disclosure.
[0023] Figure 7 This is a schematic diagram of a chip module according to another embodiment of the present disclosure. Detailed Implementation
[0024] The terminology used herein is for the purpose of illustrating particular embodiments only and is not intended to limit the invention. Unless the context otherwise indicates, the singular forms “a” and “the” used herein may also include the plural forms.
[0025] The directional terms used herein, such as up, down, left, right, front, back, and their derivatives or synonyms, refer to the orientation of elements in the accompanying drawings and are not intended to limit the invention, unless the context clearly states otherwise.
[0026] This disclosure relates to a thermal interface material, which is mainly used to relieve interfacial stress between the heat dissipation surface of a high thermal expansion metal (such as copper) and the heat-generating surface of a chip made of a low thermal expansion material. According to one aspect of this disclosure, the thermal interface material includes one or more graphite layers and one or more metal layers, the graphite layers and metal layers being stacked on top of each other, the metal layers having a non-planar structure, the non-planar structure being at least partially inserted into the graphite layers along the thickness direction.
[0027] Figure 1 In one embodiment of this disclosure, the graphite layer includes a lower graphite layer 10 and an upper graphite layer 20, with a metal layer 30 sandwiched between the lower graphite layer 10 and the upper graphite layer 20.
[0028] The non-planar structure described in this disclosure refers to a structure in which the metal layer 30 is not a completely flat surface, that is, neither the top surface 31 nor the bottom surface 32 of the metal layer 30 is flat, particularly along the planar direction ( Figure 1 In the XY plane direction), having in the thickness direction ( Figure 1 In some aspects, the metal layer 30 may include a planar portion and a longitudinal portion, wherein the planar portion is a structure extending along the planar direction, and the longitudinal portion is a structure extending along the thickness direction, and particularly protrudes beyond the planar portion in the thickness direction. The longitudinal portion serves as a structure in which the lower graphite layer 10 and the upper graphite layer 20 can be inserted, while the planar portion is sandwiched between the lower graphite layer 10 and the upper graphite layer 20, serving as a pathway for heat conduction or temperature equalization in the planar direction.
[0029] Figure 2A and Figure 2B An embodiment of this disclosure is shown, wherein the metal layer 30 includes a plurality of metal wires 30a, which may be arranged in only a single direction, such as... Figure 2AThe Y direction is shown; alternatively, the metal wire 30a may include a plurality of first metal wires 30b and a plurality of second metal wires 30c, the extension directions of the first metal wires 30b and the second metal wires 30c being staggered and intersecting at an angle between 45 degrees and 90 degrees, the first metal wires 30b and the second metal wires 30c overlapping each other, and adjacent first metal wires 30b and adjacent second metal wires 30c may be arranged at equal or unequal intervals according to a predetermined spacing. It should be understood that this disclosure is not limited thereto, and the metal layer 30 may also include other groups of multiple metal wires arranged along other directions, these metal wires overlapping each other to form a mesh structure.
[0030] In one embodiment, the thickness of the metal layer 30 is 50% of the thickness of the graphite layer, that is, in Figure 2A or Figure 2B In one embodiment, the outer diameter of the metal wire 30a is approximately 50% of the thickness of either the lower graphite layer 10 or the upper graphite layer 20.
[0031] In another embodiment, a single graphite layer (lower graphite layer 10 or upper graphite layer 20) has a first thickness t1 before being stacked, and a single metal layer 30 has a second thickness t2 before being stacked (see...). Figure 3 A single metal layer 30 is sandwiched between the lower graphite layer 10 and the upper graphite layer 20, and the total thickness t3 after compression conforms to the following relationship, thereby eliminating the gas between the graphite layer and the metal layer 30:
[0032]
[0033] It should be understood that the thickness of the lower graphite layer 10 or the upper graphite layer 20 can be the same or different. If they are different, and if the lower graphite layer 10 has a first thickness t1 and the upper graphite layer 20 has a first thickness t1', then the above formula can be rewritten as:
[0034]
[0035] Figure 3 In another embodiment of this disclosure, the metal layer 30 includes a planar portion 33 and a longitudinal portion 34, the planar portion 33 being along the planar direction ( Figure 3 Extending in the XY plane direction, the longitudinal portion 34 includes a plurality of cone-shaped protrusions that pierce into the upper graphite layer 20.
[0036] The following describes an embodiment for preparing a thermal interface material. In one embodiment, a graphite film obtained from polyimide (PI) after high-temperature coking (carbonization) is used as the graphite layer. A graphite film with a thickness between 20 and 30 micrometers (referred to as the first graphite film), for example, about 25 micrometers, is first taken. A second graphite film is then stacked on the first graphite film. The second graphite film is thicker than the first graphite film, for example, about 100 micrometers. The second graphite film can be obtained by rolling expanded graphite or graphene sheets.
[0037] A copper foil, with a thickness between 15 and 25 micrometers (e.g., approximately 20 micrometers), is used as the metal layer. The surface of the copper foil is processed using a brush, for example, by scraping away portions of the surface with a steel brush, creating a needle-like structure, thus forming a metallic needle-like blanket. The copper foil is then placed between a first graphite film and a second graphite film, allowing the needle-like structure of the copper foil to penetrate the thicker second graphite film, thereby forming a sandwich structure. Approximately 10 tons of pressure is applied to the thermal interface material using a roller, rolling it back and forth until the total thickness of the sandwich structure is less than 100 micrometers.
[0038] In another embodiment, an aluminum foil with a thickness of approximately 20 micrometers can be selected. The top and bottom surfaces of the aluminum foil are stamped using a steel die to form a honeycomb-like, staggered grid structure. This grid structure has multiple perforations, the geometry of which can be triangular, quadrilateral, pentagonal, hexagonal, or other shapes. The periphery of the grid structure forms a blade-like edge due to the stamping process. Next, the aluminum foil is placed between two graphite films, each approximately 80 micrometers thick, and the grid-structured aluminum foil is embedded and bonded to the upper and lower graphite films by applying pressure and rolling back and forth, ultimately forming a thermal interface material with compressibility in the thickness direction.
[0039] Alternatively, a copper foil with a thickness of approximately 40 micrometers can be selected and stamped using a die to form a grid structure with a wall thickness of only about 10 micrometers, in the form of triangles, quadrilaterals, pentagons, hexagons, or other shapes. Next, an aluminum foil is placed between two graphite films, each approximately 80 micrometers thick, and the grid-structured aluminum foil is embedded and bonded to the upper and lower graphite films by applying pressure and rolling back and forth, ultimately forming a thermal interface material with compressibility in the thickness direction.
[0040] Thermal interface materials can be used Figures 4 to 7 In the embodiments described above.
[0041] Figure 4This disclosure shows a chip package structure 40 according to an embodiment of the present disclosure. The chip package structure 40 is disposed on a printed circuit board 50 and connected to the printed circuit board 50 by a solder ball array 51. The chip package structure 40 includes a diamond interposer 41, a processor chip 42, a plurality of memory chips 43, a first thermal interface material 44, a second thermal interface material 45, a cover plate 46, and a third thermal interface material 47. In this embodiment, the processor chip 42 is a graphics processing unit (GPU), and the memory chips 43 include a plurality of high-bandwidth memory (HBM) chips 43a, 43b, and 43c.
[0042] Figure 5 This disclosure shows a chip package structure 60 according to another embodiment of the present disclosure. The chip package structure 60 is disposed on a printed circuit board 70, and the chip package structure 60 and the printed circuit board 70 are connected by a solder ball array 71. The chip package structure 60 includes a diamond interposer 61, a plurality of processor chips 62, a plurality of memory chips 63, a first thermal interface material 64, a second thermal interface material 65, a cover plate 66, and a third thermal interface material 67. In this embodiment, the processor chips 62 include a plurality of graphics processing units (GPUs) 62a and 62b, and the memory chips 63 include a plurality of high bandwidth memory (HBM) 63a, 63b, 63c, 63d, 63e, and 63f.
[0043] Figure 6 A chip module 80, representing another embodiment of this disclosure, includes one or more chips 81, one or more heat dissipation substrates 82, and a heat dissipation module 83. The chips 81 are connected by one or more wires 84. The chips 81 are disposed on the heat dissipation substrate 82, which may be gold or silver with a high thermal conductivity of 2500 W / mK or higher. The heat dissipation module 83 contacts the heat dissipation substrate 82 through a thermal interface material 85. The heat dissipation module 83 includes a metal cover plate 831 and a polycrystalline diamond sintered body 832. The metal cover plate 831 may include a first metal layer 831a and a second metal layer 831b, which may be copper or aluminum, respectively. Copper may be a large single crystal material. The metal cover plate 831 has a recess 831c, in which the polycrystalline diamond sintered body 832 is disposed. An hBN coating 833 is disposed between the metal cover plate 831 and the polycrystalline diamond sintered body 832. In one embodiment, the metal cover 831 may be a vapor chamber lid.
[0044] Figure 7This disclosure shows a chip module 90 according to another embodiment. The chip module 90 is a CoWoS (Chip on Waferon Substrate with silicon interposer) package structure, including a substrate 91 and a chip package 92. The chip package 92 is disposed on the substrate 91 and includes an interposer 920, one or more redistribution layers (RDLs) 921, one or more chips 922, one or more liquid molding compound (LMC) layers 923, one or more underfill layers 924, a thermal interface material 925, and a metal cover plate 926. The substrate 91 is disposed on a circuit board or other substrate via a solder ball array 93.
[0045] Symbol Explanation
[0046] 10: Lower graphite layer
[0047] 20: Upper graphite layer
[0048] 30: Metal layer
[0049] 30a: Metal wire
[0050] 30b: First metal wire
[0051] 30c: Second metal wire
[0052] 31: Top surface
[0053] 32: Bottom
[0054] 33: Planar Part
[0055] 34: Vertical section
[0056] 40: Chip Packaging Structure
[0057] 41: Diamond Intermediate Layer
[0058] 42: Processor chip
[0059] 43: Memory chip
[0060] 43a, 43b, 43c: High-bandwidth memory
[0061] 44: First thermal interface material
[0062] 45: Second thermal interface material
[0063] 46: Cover plate
[0064] 47: Third thermal interface material
[0065] 50: Printed Circuit Board
[0066] 51: Solder ball array
[0067] 60: Chip Packaging Structure
[0068] 61: Diamond Intermediate Layer
[0069] 62: Processor chip
[0070] 62a, 62b: Graphics Processor
[0071] 63: Memory chip
[0072] 63a, 63b, 63c, 63d, 63e, 63f: High-bandwidth memory
[0073] 64: First thermal interface material
[0074] 65: Second thermal interface material
[0075] 66: Cover plate
[0076] 67: Third thermal interface material
[0077] 70: Printed Circuit Board
[0078] 71: Solder ball array
[0079] 80: Chip Module
[0080] 81: Chip
[0081] 82: Heat dissipation substrate
[0082] 83: Heat dissipation module
[0083] 831: Metal cover plate
[0084] 831a: First metal layer
[0085] 831b: Second metal layer
[0086] 831c: Depression
[0087] 832: Polycrystalline diamond sintered body
[0088] 833: hBN coating
[0089] 84: Wire
[0090] 85: Thermal interface materials
[0091] 90: Chip Module
[0092] 91: Substrate
[0093] 92: Chip Packaging
[0094] 93: Solder ball array
[0095] 920: Intermediary layer
[0096] 921: Redistribution Line Layer
[0097] 922: Chip
[0098] 923: Liquid encapsulation material layer
[0099] 924: Filler adhesive layer
[0100] 925: Thermal interface material
[0101] 926: Metal cover plate
[0102] t1: First thickness
[0103] t1': First thickness
[0104] t2: Second thickness
[0105] t3: Total thickness.
Claims
1. A thermal interface material, characterized in that, For contacting and conducting heat generated by a heat source, including: At least one graphite layer; and At least one metal layer, wherein the graphite layer and the metal layer are stacked on top of each other, the metal layer having a non-planar structure that is at least partially inserted into the graphite layer along the thickness direction.
2. The thermal interface material according to claim 1, characterized in that, The metal layer is copper or aluminum.
3. The thermal interface material according to claim 1, characterized in that, The thermal interface material has a thermal conductivity of at least 100 W / mK in the thickness direction.
4. The thermal interface material according to claim 1, characterized in that, The non-planar structure is a mesh structure or a needle-like structure.
5. The thermal interface material according to claim 1, characterized in that, The graphite layer is manufactured using a polyimide as a precursor.
6. The thermal interface material according to claim 1, characterized in that, The graphite layer is a recrystallized graphite film or a graphene stacked film.
7. The thermal interface material according to claim 1, characterized in that, The thermal interface material is used in a chip stacking structure.
8. The thermal interface material according to claim 7, characterized in that, The thermal interface material serves as an intermediary layer in the chip stacking structure.
9. The thermal interface material according to claim 1, characterized in that, The thermal interface material is used in a chip packaging structure.
10. The thermal interface material according to claim 1, characterized in that, Before being stacked, each graphite layer has a first thickness t1, and each metal layer has a second thickness t2. The total thickness t3 of the metal layer sandwiched between two graphite layers and compressed conforms to the following relationship, thereby excluding the gas between the graphite layers and the metal layers: 。