Cross interconnection anti-radiation charge pump circuit and layout structure based on SOI process

Abstract

The present application relates to the technical field of analog integrated circuit, and particularly provides a cross interconnection anti-radiation charge pump circuit and layout structure based on SOI process, which comprises: four current mirrors adopting cross interconnection structure are used to copy the current generated by a bias circuit, and then four switch circuits are used to control the charging and discharging of the charge pump according to the output signal of a phase discriminator, and finally a selection control circuit is used to control the conduction of the charge pump to a low-pass filter current path.The setting of the multiple cross interconnection structure current mirrors ensures that when a certain current mirror is subjected to single particle bombardment, the other current mirrors can still normally copy the current, thereby reducing the influence of single particle effect on current copying.Meanwhile, the charging and discharging control circuit controls the charging and discharging of the charge pump according to the output signal of the phase discriminator, and the selection control circuit controls the conduction of the output current path according to the locking state of the phase-locked loop, further reducing the influence of radiation on the output current of the charge pump.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit technology, and in particular to a cross-interconnect radiation-resistant charge pump circuit and its layout structure based on SOI technology. Background Technology

[0002] With the rapid development of electronic systems in aerospace, satellite communications, and deep space exploration, electronic devices face increasingly harsh operating environments. Due to the significant radiation present in these environments, high requirements are placed on the radiation resistance of electronic devices. The effects of external radiation on integrated circuits mainly include total dose effect, single-event effect, and single-event latch-up effect. These effects severely impact spaceflight missions, satellite operation, and can even have catastrophic consequences for analog integrated circuits. To ensure that these electronic devices maintain normal function under specific radiation environments, radiation hardening must be implemented at every stage.

[0003] As a core module of phase-locked loops (PLLs), charge pumps are widely used in clock synchronization, frequency synthesis, and communication systems. They achieve phase locking by converting the phase error signal output from a phase-frequency discriminator into current pulses, which drive a voltage-controlled oscillator (VCO) to adjust its output frequency.

[0004] Current layout hardening primarily employs common-center hardening and closed-layout transistor hardening. However, common-center hardening layout design is very complex and occupies a large area, mainly applicable to specific analog cells, and lacks versatility. Closed-layout transistor hardening design rules are even more complex, increasing the difficulty of placement and routing.

[0005] Therefore, there is an urgent need for a charge pump circuit structure that can improve the charge pump's resistance to single-event effects while reducing the charge pump's current mismatch, and whose layout design meets the requirement of not significantly increasing the layout area and the difficulty of layout and routing. Summary of the Invention

[0006] To address the aforementioned issues, this application provides a cross-interconnect radiation-resistant charge pump circuit and its layout structure based on SOI technology.

[0007] To achieve the objectives of this application, the following technical solution is provided: On the one hand, this application provides a cross-interconnect radiation-resistant charge pump circuit based on SOI technology, wherein the charge pump includes a bias circuit, a current replication circuit, a charge / discharge control circuit, and a selection control circuit; The input terminal of the bias circuit is connected to the power supply, and the output terminal is connected to the current replication circuit. The input terminal of the charge / discharge control circuit is connected to the output terminal of the current replication circuit and the output signal of the frequency and phase detector, and the output terminal is connected to the selection control circuit. The input terminal of the selection control circuit is connected to the output signal, and the output terminal is connected to the input terminal of the low-pass filter. The bias circuit is used to generate the first current; The current replication circuit includes four cross-interconnected current mirrors for replicating the first current to obtain the second current. The charge-discharge control circuit includes four switching circuits, which are used to control the second current to charge and discharge the charge pump based on the output signal; The selection control circuit is used to control the conduction of the output path of the current between the charge / discharge control circuit and the low-pass filter based on the output signal. By adjusting the body bias voltage of the transistors in the charge pump circuit, all transistors in the charge pump are brought into a preset operating region.

[0008] On the other hand, this application also provides a layout structure for the cross-interconnect radiation-resistant charge pump circuit based on SOI technology, the layout structure including a bias circuit layout area, four current mirror layout areas, four switch layout areas and a selection control circuit layout area; The bias circuit layout area is the layout structure of the bias circuit; One of the current mirror layout areas is the layout structure of the current mirror; One of the switch layout areas is the layout structure of one of the switch circuits; The selection control circuit layout area is the layout structure of the selection control circuit; A first switch layout area, a second switch layout area, a third switch layout area, and a fourth switch layout area are sequentially arranged around the bias circuit layout area; The second current mirror layout area, the first current mirror layout area, the third current mirror layout area, and the fourth current mirror layout area are respectively disposed on the side of the first switch layout area, the second switch layout area, the third switch layout area, and the fourth switch layout area away from the bias circuit layout area; The selection control circuit layout area is located on the side of the third switch layout area away from the second switch layout area.

[0009] As a preferred embodiment of the present invention, the first switch layout area and the third switch layout area are symmetrical about the center of the bias circuit layout area; The second switch layout area and the fourth switch layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the fourth current mirror layout area are symmetrical about the center of the bias circuit layout area; The second current mirror layout area and the third current mirror layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the third current mirror layout area are arranged in parallel; The second current mirror layout area and the fourth current mirror layout area are arranged in parallel; The first switch layout area and the fourth switch layout area are arranged in parallel. The second switch layout area and the third switch layout area are arranged in parallel.

[0010] As a preferred embodiment of the present invention, a buried oxide layer is introduced into the active layer and substrate of the MOS transistor in the charge pump circuit based on SOI process.

[0011] As a preferred embodiment of the present invention, the MOS transistors in the charge pump circuit are all H-type gate devices.

[0012] Beneficial effects: 1. The arrangement of multiple cross-interconnected current mirrors in this invention ensures that when one current mirror is bombarded by a single event, the other current mirrors can still reproduce current normally, thereby reducing the impact of the single event effect on current reproduction. Simultaneously, the charge / discharge control circuit controls the charging and discharging of the charge pump based on the output signal of the frequency and phase detector, and the selection control circuit controls the conduction of the output current path based on the locked state of the phase-locked loop, further reducing the impact of radiation on the output current of the charge pump.

[0013] 2. In the layout of this invention, the layout of the four current mirrors is arranged in four different directions, which increases the physical distance between sensitive nodes, reduces the probability of single-particle bombardment, and thus further enhances the radiation resistance. Attached Figure Description

[0014] The accompanying drawings are provided to further understand this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. Figure 1 A schematic diagram of the composition structure of a cross-interconnect radiation-resistant charge pump circuit based on SOI technology provided in an embodiment of this application; Figure 2 A schematic diagram of the partial circuit structure of a cross-interconnect radiation-resistant charge pump circuit based on SOI technology provided for an embodiment of this application; Figure 3 A schematic diagram of the composition structure of a selection control circuit for a cross-interconnect radiation-resistant charge pump circuit based on SOI technology, provided for an embodiment of this application; Figure 4 A schematic diagram of the layout structure of a cross-interconnect radiation-resistant charge pump circuit based on SOI technology provided in an embodiment of this application; Figure 5A schematic diagram of the composition of a portion of the layout area of ​​a cross-interconnect radiation-resistant charge pump circuit based on SOI technology, provided for an embodiment of this application. Figure 6 A schematic diagram of the layout structure of the selection control circuit layout area for a cross-interconnect radiation-resistant charge pump circuit based on SOI technology, provided in an embodiment of this application. Figure 7 This is a schematic diagram of the simulation results of a single-particle bombardment simulation of a cross-interconnected radiation-resistant charge pump circuit based on SOI technology, provided for an embodiment of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this application, unless otherwise stated, "multiple" means two or more.

[0017] Example 1: like Figure 1 As shown, a cross-interconnect radiation-resistant charge pump circuit based on SOI technology includes a bias circuit 11, a current replication circuit 12, a charge / discharge control circuit 13, and a selection control circuit 14. The input terminal of the bias circuit 11 is connected to the power supply, and the output terminal is connected to the current replication circuit 12. The input terminal of the charge / discharge control circuit 13 is connected to the output terminal of the current replication circuit 12 and the output signal of the frequency and phase detector, and the output terminal is connected to the selection control circuit 14. The input terminal of the selection control circuit 14 is connected to the output signal, and the output terminal is connected to the input terminal of the low-pass filter. The bias circuit 11 is used to generate a first current; The current replication circuit 12 includes four cross-interconnected current mirrors for replicating the first current to obtain the second current. The charge / discharge control circuit 13 includes four switching circuits, which are used to control the second current to charge and discharge the charge pump based on the output signal. The selection control circuit 14 is used to control the conduction of the current output path between the charge / discharge control circuit 13 and the low-pass filter based on the output signal; By adjusting the bias voltage of the transistors in the charge pump circuit, all transistors in the charge pump are brought into a preset operating area.

[0018] Understandably, traditional charge pump structures typically replicate multiple currents using only one current mirror. If this current mirror is bombarded by a single-event event, all other current mirrors will be contaminated, leading to abnormal currents. The current replication circuit in this embodiment includes four cross-connected current mirrors. Each current mirror replicates the current from the bias circuit. Because the current mirrors are cross-connected, when one current mirror is bombarded by a single event, the remaining three current mirrors can still replicate the current normally. This significantly reduces the impact of single-event effects on the charge pump and improves its radiation resistance.

[0019] Since the secondary effect of MOS transistors can affect the threshold voltage and thus change the current magnitude, this embodiment adjusts the body voltage of all MOS transistors to change the threshold voltage of the MOS transistors, so that all MOS transistors can enter the correct operating region, thereby ensuring that no current abnormality occurs during current replication and reducing current mismatch.

[0020] In a preferred embodiment, both the bias circuit and the current replication circuit include multiple stacked transistors.

[0021] It is understood that the current replication circuit in this embodiment adopts a stacked transistor structure. In a stack of transistors, one MOSFET is in the saturation region and the other MOSFET is in the linear region. When a high-energy particle is incident on one of the transistors in this stack, the voltage applied between the drain and source of the transistor will decrease. Subsequently, the voltage will be transferred to another transistor in this stack. This process will only cause a very small amount of charge displacement, thereby effectively reducing the single-event effect of the circuit.

[0022] As a preferred embodiment, the bias circuit includes a standard current source, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4; One end of the standard current source is connected to a power supply; The drain of the first NMOS transistor N1 is connected to the other end of the standard current source and the gate of the fourth NMOS transistor N4. The source is connected to the drain of the second NMOS transistor N2. The gate is connected to the gate of the second NMOS transistor N2 and the output terminal of the bias circuit. The source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3; The source of the third NMOS transistor N3 is connected to the drain of the fourth NMOS transistor N4, and the gate is connected together with the gate of the fourth NMOS transistor N4 and the output terminal of the bias circuit. The source of the fourth NMOS transistor N4 is grounded.

[0023] In a preferred embodiment, the current replication circuit includes a first current mirror, a second current mirror, a third current mirror, and a fourth current mirror; each current mirror includes a PMOS current mirror unit and an NMOS current mirror unit, and both the PMOS current mirror unit and the NMOS current mirror unit adopt a common-source common-gate stacked transistor structure and a gate cross-coupling structure; The PMOS current mirror unit is connected between the power supply terminal and the corresponding current mirror output terminal, and the NMOS current mirror unit is connected between the ground terminal and the corresponding current mirror output terminal. The bias control terminal of the NMOS current mirror unit in each current mirror is connected to the first and second output terminals of the bias circuit to receive the bias voltage. The output terminals of the first, second, third, and fourth current mirrors are respectively connected to the first to eighth input terminals of the charge and discharge control circuit to provide charge and discharge current to each switching circuit. It is understandable that, such as Figure 2As shown, each current mirror consists of an NMOS current mirror unit and a PMOS current mirror unit. The first current mirror consists of a first PMOS current mirror unit and a first NMOS current mirror unit. The first PMOS current mirror unit consists of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, and a sixteenth PMOS transistor P16. The first NMOS current mirror unit consists of a fifth NMOS transistor N5, a sixth NMOS transistor P16, a seventh NMOS transistor P17, a thirteenth PMOS transistor P18, a thirteenth PMOS transistor P19, a thirteenth PMOS transistor P10, a fifteenth PMOS transistor P11, and a sixteenth PMOS transistor P11. The NMOS transistors N6, N7, N8, N21, N22, N23, and N24 are used; the second current mirror is composed of a second PMOS current mirror unit and a second NMOS current mirror unit. The second PMOS current mirror unit is composed of a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, and a nineteenth PMOS transistor P24. The first current mirror consists of MOSFET P19 and the twentieth PMOS transistor P20. The second NMOS current mirror unit is composed of the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, the twenty-fifth NMOS transistor N25, the twenty-sixth NMOS transistor N26, the twenty-seventh NMOS transistor N27, and the twenty-eighth NMOS transistor N28. The third current mirror is composed of a third PMOS current mirror unit and a third NMOS current mirror unit. The third PMOS current mirror unit is composed of the ninth PMOS transistor P9 and the tenth PMOS transistor P20. The P10, eleventh PMOS transistor P11, twelfth PMOS transistor P12, twenty-first PMOS transistor P21, twenty-second PMOS transistor P22, twenty-third PMOS transistor P23, and twenty-fourth PMOS transistor P24 are composed of the thirteenth NMOS transistor N13, fourteenth NMOS transistor N14, fifteenth NMOS transistor N15, sixteenth NMOS transistor N16, forty-fifth NMOS transistor N45, forty-sixth NMOS transistor N46, forty-seventh NMOS transistor N47, and forty-eighth NMOS transistor N48.The fourth current mirror consists of a fourth PMOS current mirror unit and a fourth NMOS current mirror unit. The fourth PMOS current mirror unit consists of the thirty-seventh PMOS transistor P37, the thirty-eighth PMOS transistor P38, the thirty-ninth PMOS transistor P39, the fortieth PMOS transistor P40, the forty-first PMOS transistor P41, the forty-second PMOS transistor P42, the forty-third PMOS transistor P43, and the forty-fourth PMOS transistor P44. The fourth NMOS current mirror unit consists of the forty-first NMOS transistor N41, the forty-second NMOS transistor N42, the forty-third NMOS transistor N43, the forty-fourth NMOS transistor N44, the seventeenth NMOS transistor N17, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, and the twentieth NMOS transistor N20. Specifically, the gate of the fifth NMOS transistor N5 is connected to the gates of the sixth NMOS transistor N6 and the first NMOS transistor N1, the drain is connected to the drain of the fourth PMOS transistor P4, and the source is connected to the drain of the sixth NMOS transistor N6. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7; The gate of the seventh NMOS transistor N7 is connected to the gates of the eighth NMOS transistor N8 and the third NMOS transistor N3, and the source is connected to the drain of the eighth NMOS transistor N8. The gate of the ninth NMOS transistor N9 is connected to the gates of the tenth NMOS transistor N10 and the first NMOS transistor N1, the drain is connected to the drain of the eighth PMOS transistor P8, and the source is connected to the drain of the tenth NMOS transistor N10. The source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11; The gate of the eleventh NMOS transistor N11 is connected to the gates of the twelfth NMOS transistor N12 and the third NMOS transistor N3, and the source is connected to the drain of the twelfth NMOS transistor N12. The gate of the thirteenth NMOS transistor N13 is connected to the gates of the fourteenth NMOS transistor N14 and the first NMOS transistor N1, the drain is connected to the drain of the twelfth PMOS transistor P12, and the source is connected to the drain of the fourteenth NMOS transistor N14. The source of the fourteenth NMOS transistor N14 is connected to the drain of the fifteenth NMOS transistor N15; The gate of the fifteenth NMOS transistor N15 is connected to the gates of the sixteenth NMOS transistor N16 and the third NMOS transistor N3, and the source is connected to the drain of the sixteenth NMOS transistor N16. The gate of the forty-first NMOS transistor N41 is connected to the gates of the forty-second NMOS transistor N42 and the first NMOS transistor N1. The drain is connected to the drain of the forty PMOS transistor P40, and the source is connected to the drain of the forty-second NMOS transistor N42. The source of the forty-second NMOS transistor N42 is connected to the drain of the forty-third NMOS transistor N43; The gate of the forty-third NMOS transistor N43 is connected to the gates of the forty-fourth NMOS transistor N44 and the third NMOS transistor N3, and the source is connected to the drain of the forty-fourth NMOS transistor N44. The gate of the seventeenth NMOS transistor N17 is connected together with the gates of the eighteenth NMOS transistor N18 and the forty-first NMOS transistor N41. The drain of the seventeenth NMOS transistor N17 is the output terminal of the fourth NMOS current mirror unit, which is connected to the first input terminal of the charge and discharge control circuit. The source is connected to the drain of the eighteenth NMOS transistor N18. The source of the eighteenth NMOS transistor N18 is connected to the drain of the nineteenth NMOS transistor N19; The gate of the nineteenth NMOS transistor N19 is connected to the gates of the twentieth NMOS transistor N20 and the forty-third NMOS transistor N43, and the source of the nineteenth NMOS transistor N19 is connected to the drain of the twentieth NMOS transistor N20. The gate of the 21st NMOS transistor N21 is connected to the gates of the 5th NMOS transistor N5 and the 22nd NMOS transistor N22. The drain of the 21st NMOS transistor N21 is the output terminal of the first NMOS current mirror unit, which is connected to the second input terminal of the charge and discharge control circuit. The source is connected to the drain of the 22nd NMOS transistor N22. The source of the twentieth NMOS transistor N22 is connected to the drain of the twentieth NMOS transistor N23; The gate of the 23rd NMOS transistor N23 is connected to the gates of the 24th NMOS transistor N24 and the 7th NMOS transistor N7, and the source is connected to the drain of the 24th NMOS transistor N24. The gate of the 25th NMOS transistor N25 is connected to the gates of the 9th NMOS transistor N9 and the 26th NMOS transistor N26. The drain of the 25th NMOS transistor N25 is the output terminal of the second NMOS current mirror unit, which is connected to the third input terminal of the charge and discharge control circuit. The source is connected to the drain of the 26th NMOS transistor N26. The source of the 26th NMOS transistor N26 is connected to the drain of the 27th NMOS transistor N27; The gate of the 27th NMOS transistor N27 is connected to the gates of the 28th NMOS transistor N28 and the 11th NMOS transistor N11, and the source is connected to the drain of the 28th NMOS transistor N28. The gate of the forty-fifth NMOS transistor N45 is connected together with the gates of the thirteenth NMOS transistor N13 and the forty-sixth NMOS transistor N46. The drain of the forty-fifth NMOS transistor N45 is the output terminal of the third NMOS current mirror unit, which is connected to the fourth input terminal of the charge and discharge control circuit. The source is connected to the drain of the forty-sixth NMOS transistor N46. The source of the forty-sixth NMOS transistor N46 is connected to the drain of the forty-seventh NMOS transistor N47; The gate of the forty-seventh NMOS transistor N47 is connected to the gates of the fifteenth NMOS transistor N15 and the forty-eighth NMOS transistor N48, and the source is connected to the drain of the forty-eighth NMOS transistor N48. The sources of the eighth NMOS transistor N8, the twelfth NMOS transistor N12, the sixteenth NMOS transistor N16, the twentieth NMOS transistor N20, the twenty-fourth NMOS transistor N24, the twenty-eighth NMOS transistor N28, the forty-fourth NMOS transistor N44, and the forty-eighth NMOS transistor N48 are all grounded; The gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2 and the drain of the fourth PMOS transistor P4, and the drain is connected to the source of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3; The gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, and the drain is connected to the source of the fourth PMOS transistor P4. The gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6 and the drain of the eighth PMOS transistor P8, and the drain is connected to the source of the sixth PMOS transistor P6. The drain of the sixth PMOS transistor P6 is connected to the source of the seventh PMOS transistor P7. The gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8, and the drain of the seventh PMOS transistor P7 is connected to the source of the eighth PMOS transistor P8. The gate of the ninth PMOS transistor P9 is connected to the gate of the tenth PMOS transistor P10 and the drain of the twelfth PMOS transistor P12, and the drain is connected to the source of the tenth PMOS transistor P10. The drain of the tenth PMOS transistor P10 is connected to the source of the eleventh PMOS transistor P11; The gate of the eleventh PMOS transistor P11 is connected to the gate of the twelfth PMOS transistor P12, and the drain is connected to the source of the twelfth PMOS transistor P12. The gate of the thirty-seventh PMOS transistor P37 is connected to the gate of the thirty-eighth PMOS transistor P38 and the drain of the fortieth PMOS transistor P40, and the drain is connected to the source of the thirty-eighth PMOS transistor P38. The drain of the thirty-eighth PMOS transistor P38 is connected to the source of the thirty-ninth PMOS transistor P39. The gate of the thirty-ninth PMOS transistor P39 is connected to the gate of the fortieth PMOS transistor P40, and the drain is connected to the source of the fortieth PMOS transistor P40. The gate of the thirteenth PMOS transistor P13 is connected to the gates of the fourteenth PMOS transistor P14 and the first PMOS transistor P1, and the drain is connected to the source of the fourteenth PMOS transistor P14. The drain of the fourteenth PMOS transistor P14 is connected to the source of the fifteenth PMOS transistor P15. The gate of the fifteenth PMOS transistor P15 is connected to the gate of the sixteenth PMOS transistor P16 and the gate of the third PMOS transistor P3, and the drain is connected to the source of the sixteenth PMOS transistor P16. The drain of the sixteenth PMOS transistor P16 is the output terminal of the first PMOS current mirror unit, which is connected to the fifth input terminal of the charge and discharge control circuit. The gate of the seventeenth PMOS transistor P17 is connected to the gates of the eighteenth PMOS transistor P18 and the fifth PMOS transistor P5, and the drain is connected to the source of the eighteenth PMOS transistor P18. The drain of the eighteenth PMOS transistor P18 is connected to the source of the nineteenth PMOS transistor P19. The gate of the nineteenth PMOS transistor P19 is connected to the gates of the twentieth PMOS transistor P20 and the seventh PMOS transistor P7, and the drain is connected to the source of the twentieth PMOS transistor P20. The drain of the twentieth PMOS transistor P20 is the output terminal of the second PMOS current mirror unit, which is connected to the sixth input terminal of the charge and discharge control circuit. The gate of the 21st PMOS transistor P21 is connected to the gates of the 22nd PMOS transistor P22 and the 10th PMOS transistor P10, and the drain is connected to the source of the 22nd PMOS transistor P22. The drain of the 22nd PMOS transistor P22 is connected to the source of the 23rd PMOS transistor P23; The gate of the 23rd PMOS transistor P23 is connected to the gates of the 24th PMOS transistor P24 and the 11th PMOS transistor P11, and the drain of the 23rd PMOS transistor P23 is connected to the source of the 24th PMOS transistor P24. The drain of the 24th PMOS transistor P24 is the output terminal of the third PMOS current mirror unit, which is connected to the seventh input terminal of the charge and discharge control circuit. The gate of the forty-first PMOS transistor P41 is connected to the gates of the forty-second PMOS transistor P42 and the thirty-seventh PMOS transistor P37, and the drain is connected to the source of the forty-second PMOS transistor P42. The drain of the forty-second PMOS transistor P42 is connected to the source of the forty-third PMOS transistor P43. The gate of the forty-third PMOS transistor P43 is connected to the gates of the forty-fourth PMOS transistor P44 and the thirty-ninth PMOS transistor P39, and the drain of the forty-third PMOS transistor P43 is connected to the source of the forty-fourth PMOS transistor P44. The drain of the forty-fourth PMOS transistor P44 is the output terminal of the fourth PMOS current mirror unit, which is connected to the eighth input terminal of the charge and discharge control circuit. The sources of the first PMOS transistor P1, the fifth PMOS transistor P5, the ninth PMOS transistor P9, the thirteenth PMOS transistor P13, the seventeenth PMOS transistor P17, the twenty-first PMOS transistor P21, the thirty-seventh PMOS transistor P37, and the forty-first PMOS transistor P41 are all connected to a power supply.

[0024] On the other hand, through Figure 2 As can be seen, in this embodiment, while the current mirrors are interconnected, the transistors within the charge pump also satisfy a stacked transistor structure, with two transistors stacked together. For example, the first PMOS transistor P1 and the second PMOS transistor P2 form one stacked transistor, and the fifth NMOS transistor N5 and the sixth NMOS transistor N6 form another stacked transistor. This embodiment includes a total of eight stacked transistor layers. By applying a body bias voltage to each NMOS and PMOS transistor, all eight transistor layers can enter the correct operating region, thereby improving radiation resistance while reducing current mismatch.

[0025] As a preferred embodiment, the charge and discharge control circuit includes a first switching circuit comprising a first amplifier A1, a 25th PMOS transistor P25, a 26th PMOS transistor P26, a 27th PMOS transistor P27, a 28th PMOS transistor P28, a 29th NMOS transistor N29, a 30th NMOS transistor N30, a 31st NMOS transistor N31, and a 32nd NMOS transistor N32. The source of the 25th PMOS transistor P25 is connected to the drain of the 29th NMOS transistor N29, the 31st NMOS transistor N31, and the source of the 27th PMOS transistor P27, and serves as the charging terminal of the switching circuit. The gate of the 25th PMOS transistor P25 is connected to the first signal UPB1, and its drain is connected to the source of the 29th NMOS transistor N29, the source of the 30th NMOS transistor N30, the output terminal of the first amplifier, and the drain of the 26th PMOS transistor P26. The gate of the 29th NMOS transistor N29 is connected to the second signal UP1; The drain of the thirtieth NMOS transistor N30 is connected to the source of the twenty-sixth PMOS transistor P26, the drain of the thirty-second NMOS transistor N32, and the source of the twenty-eighth PMOS transistor P28, and serves as the discharge terminal of the switching circuit. The gate of the thirtieth NMOS transistor N30 is connected to the third signal DN1. The gate of the twenty-sixth PMOS transistor P26 is connected to the fourth signal DNB1. The drain of the twenty-seventh PMOS transistor P27 is connected to the source of the thirty-first NMOS transistor N31, the source of the thirty-second NMOS transistor N32, the drain of the twenty-eighth PMOS transistor P28, and the inverting input terminal of the first amplifier, and serves as the output terminal of the charge / discharge control circuit. The gate of the twenty-seventh PMOS transistor P27 is connected to the second signal. The gates of the thirty-first NMOS transistor N31 and the thirty-second NMOS transistor N32 are respectively connected to the first signal UPB1 and the fourth signal DNB1. The gate of the 28th PMOS transistor is connected to the third signal DN1; The non-inverting input terminal of the first amplifier A1 is connected to the output terminal of the first amplifier A1; The inverting input terminal of the first amplifier A1 is connected to the output terminal of the charge / discharge control circuit; The charging and discharging terminals of the first to fourth switching circuits are respectively connected to the output terminals of the PMOS current mirror units and the NMOS current mirror units of the four current mirrors, so as to form the first to eighth input terminals at the input terminal of the charging and discharging control circuit. Among them, the first signal UPB1, the second signal UP1, the third signal DN1 and the fourth signal DNB1 are all output signals of the frequency and phase detector. The first signal UPB1 and the second signal UP1 are a pair of complementary signals, and the third signal DN1 and the fourth signal DNB1 are a pair of complementary signals, which are used to control each switching circuit to charge or discharge the charge pump respectively.

[0026] Understandably, when the transistors connected to the PMOS current mirror section in the switching circuit are turned on, the PMOS current mirror section charges the charge pump. For example, when the 29th PMOS transistor P29, the 33rd NMOS transistor N33, the 31st PMOS transistor P31, and the 35th NMOS transistor N35 connected to the first PMOS current mirror section are turned on, the first PMOS current mirror section charges the charge pump. When the transistors connected to the NMOS current mirror section in the switching circuit are turned on, the NMOS current mirror section discharges the charge pump. For example, when the 30th NMOS transistor N30, the 26th PMOS transistor P26, the 32nd NMOS transistor N32, and the 28th PMOS transistor P28 connected to the first NMOS current mirror section are turned on, the first NMOS current mirror discharges the charge pump. The output terminal of the switching circuit is the output terminal CPOUT of the charge pump, which is also the input terminal of the selection control circuit.

[0027] Furthermore, the step of controlling the current replication circuit to charge and discharge the radiation-resistant charge pump based on the output signal includes: When the first signal and the second signal are valid, the charge-discharge control circuit controls the current replication circuit to charge the charge pump; When the third signal and the fourth signal are valid, the charge-discharge control circuit controls the current replication circuit to discharge the charge pump.

[0028] Understandably, when the rising signals UP1 and UPB1 of the frequency and phase detector are valid, the transistor connected to the PMOS current mirror in the switching circuit is turned on, and the PMOS current mirror charges the charge pump. Similarly, when the falling signals of the frequency and phase detector, i.e., the DN1 and DNB1 signals, are valid, the transistor connected to the NMOS current mirror in the switching circuit is turned on, and the NMOS current mirror discharges the charge pump. When both the rising and falling signals of the frequency and phase detector are invalid, the current replication circuit neither charges nor discharges.

[0029] In this embodiment, as Figure 3 As shown, the selection control circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a first transmission gate TG1, a second transmission gate TG2, and a third transmission gate TG3; The input terminal of the first inverter INV1 is connected to the first control terminal a of the first transmission gate TG1, the second control terminal d of the second transmission gate TG2, and the second signal UP1. The output terminal is connected to the second control terminal b of the first transmission gate TG1 and the first control terminal c of the second transmission gate TG2. The output of the second inverter INV2 is connected to both the input of the first transmission gate TG1 and the input of the second transmission gate TG2, and its input is connected to the third signal DN1. The input terminal of the third inverter INV3 is connected to the output terminal of the first transmission gate TG1 and the output terminal of the second transmission gate TG2. The second control terminal f of the third transmission gate TG3 is connected to the output terminal of the third inverter, the first control terminal e is connected to the output terminal of the first transmission gate TG1, the input terminal is connected to the output terminal of the charge and discharge control circuit, and the output terminal is connected to the low-pass filter.

[0030] Understandable Figure 3 middle, I CP This indicates the output current of the charge pump CP (CP output CPOUT), CONT indicates the control circuit portion of the selection control circuit, SEL indicates the selection circuit portion of the selection control circuit, and I... CP1 This indicates the output current of the final selection control circuit. The selection control circuit determines the operating state of the phase-locked loop (PLL) and transmits the determination signal to the selection circuit. When the PLL is in a locked state, the selection circuit SEL is turned off, i.e., the current output path is closed, thereby preventing radiated current interference pulses from affecting the subsequent low-pass filter circuit and ensuring that the PLL stably maintains the locked state. Specifically, the two input ports of the selection control circuit are connected to the output control signals UP1 and DN1 of the phase-frequency detector (PFD), respectively. That is, the input terminal of the first inverter INV1, the control port a of the first transmission gate TG1, and the control port d of the second transmission gate TG2 are connected to UP1; the input terminal of the second inverter INV2 is connected to DN1; the control terminal e of the third transmission gate TG3 is connected to the output signal UPS of the first transmission gate TG1; and the control terminal f of the third transmission gate TG3 is connected to the signal DNS obtained by inverting the output signal of the second transmission gate TG2 through the third inverter INV3. Thus, the conduction of the third transmission gate TG3 is controlled by the control signals UPS and DNS. Thus, the working state of the phase-locked loop (PLL) can be determined by the output signal of the PFD. When the PLL is locked, the third transmission gate TG3 in the selection control circuit is in the off state. When the PLL is not locked, the third transmission gate TG3 is in the on state.

[0031] Specifically, when the phase-locked loop (PLL) is in the locked state, the PFD output signals UP1=0 and DN1=0, the charge pump CP neither charges nor discharges, UPS=1, DNS=0, and the third transmission gate TG3 is not conducting. This means the path of the output current from the charge / discharge control circuit to the low-pass filter is closed. Therefore, when single-event radiation is present, the selection control circuit will prevent the radiation current interference pulse from affecting the subsequent low-pass filter circuit, ensuring that the PLL remains locked.

[0032] Example 2: like Figure 4 As shown, a layout structure is applied to the SOI-based cross-interconnect radiation-resistant charge pump circuit of Embodiment 1. The layout structure includes a bias circuit layout area, four current mirror layout areas, four switch layout areas, and a selection control circuit layout area. The bias circuit layout area is the layout structure of the bias circuit; One of the current mirror layout areas is the layout structure of the current mirror; One of the switch layout areas is the layout structure of one of the switch circuits; The selection control circuit layout area is the layout structure of the selection control circuit; A first switch layout area, a second switch layout area, a third switch layout area, and a fourth switch layout area are sequentially arranged around the bias circuit layout area. The second current mirror layout area, the first current mirror layout area, the third current mirror layout area, and the fourth current mirror layout area are respectively arranged on the side of the first switch layout area, the second switch layout area, the third switch layout area, and the fourth switch layout area away from the bias circuit layout area. The selection control circuit layout area is located on the side of the third switch layout area away from the second switch layout area.

[0033] It is understood that in the layout of this embodiment, the four current mirrors are arranged in four different directions, and the four-way switch layout area is set between the bias circuit and the four current mirror layout area. Without occupying more chip area, the physical distance between sensitive nodes is increased as much as possible, reducing the probability of single-particle bombardment. At the same time, the proposed selection control circuit is composed only of inverters and transmission gates, which has a simple structure, does not occupy more chip area, does not bring more power consumption, and is more conducive to integration.

[0034] In a preferred embodiment, the first switch layout area and the third switch layout area are symmetrical about the center of the bias circuit layout area; The second switch layout area and the fourth switch layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the fourth current mirror layout area are symmetrical about the center of the bias circuit layout area; The second current mirror layout area and the third current mirror layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the third current mirror layout area are arranged in parallel; The second current mirror layout area and the fourth current mirror layout area are arranged in parallel; The first switch layout area and the fourth switch layout area are arranged in parallel. The second switch layout area and the third switch layout area are arranged in parallel.

[0035] It is understood that the layout of this embodiment adopts a symmetrical structure. The symmetrical layout can ensure that the circuit module has a uniformly distributed charge collection path in the radiation environment. When high-energy particles hit the chip, the symmetrical structure will reduce the asymmetry of local charge accumulation, thereby reducing the probability of triggering single-event upset.

[0036] As a preferred embodiment, a buried oxide layer is introduced into the active layer and substrate of the MOS transistor in the charge pump circuit based on the SOI process.

[0037] It is understood that the present invention uses SOI technology, which introduces buried oxide layer in the active layer and the substrate to isolate the channel and the substrate. This isolation can prevent charge carriers generated by radiation from entering the active region, thereby reducing the impact of radiation on circuit performance and providing better robustness and reliability of the circuit in a radiation environment.

[0038] As a preferred embodiment, the MOS transistors in the charge pump circuit are all H-type gate devices.

[0039] It is understandable that, such as Figure 5 and Figure 6 As shown, the MOS transistor in the charge pump of this embodiment uses an "H"-gate device. The H-gate can effectively lead out the body, blocking the leakage current path between the source and drain, avoiding the turn-on of parasitic transistors, and simultaneously blocking the leakage current path at the device edge, reducing leakage current and enhancing the resistance to total radiation dose. At the same time, the layout structure adopts a shared active area approach, reducing the layout area. This embodiment strengthens the layout structure through SOI technology and the application of H-gate devices, thereby further improving the radiation resistance of the charge pump.

[0040] Simulation experiments were conducted based on the cross-interconnect radiation-resistant charge pump circuit based on SOI technology provided by this invention: The simulation experimental components of this invention are manufactured using SMIC 180nm CMOS technology, and the simulation circuit of this invention is built on the Cadence IC618 simulation experimental platform.

[0041] The circuit of this invention was simulated using the ADE Explorer simulation tool, with a given power supply voltage VDD of 1.8V and an operating temperature of 27 degrees Celsius.

[0042] Simulation 1: Under the above working conditions, a single-particle bombardment simulation of the present invention under locked conditions was performed, and the results are as follows. Figure 7 As shown, the horizontal axis represents time, the vertical axis represents current magnitude, and "locked" indicates that the circuit is in a locked state. CP I represents the output current of an unreinforced charge pump. CP_RHBD The output current of the reinforced radiation-resistant charge pump in this embodiment is shown. The current of the unreinforced charge pump structure fluctuates greatly after being bombarded. Compared with the unreinforced charge pump structure, the current of the radiation-resistant charge pump proposed in this embodiment remains normal, thereby ensuring that the phase-locked loop can continue to maintain a normal locking state.

[0043] It should be noted that, in this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0044] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. This application is not limited to the exact structures described above and illustrated in the accompanying drawings, and it should not be considered that the specific implementation of this application is limited to these descriptions. For those skilled in the art, various changes and modifications made without departing from the concept of this application should be considered to fall within the protection scope of this application.

Claims

1. A cross-interconnect radiation-resistant charge pump circuit based on SOI technology, characterized in that, The charge pump includes a bias circuit, a current replication circuit, a charge / discharge control circuit, and a selection control circuit. The input terminal of the bias circuit is connected to the power supply, and the output terminal is connected to the current replication circuit. The input terminal of the charge / discharge control circuit is connected to the output terminal of the current replication circuit and the output signal of the frequency and phase detector, and the output terminal is connected to the selection control circuit. The input terminal of the selection control circuit is connected to the output signal, and the output terminal is connected to the input terminal of the low-pass filter. The bias circuit is used to generate the first current; The current replication circuit includes four cross-interconnected current mirrors for replicating the first current to obtain the second current. The charge-discharge control circuit includes four switching circuits, which are used to control the second current to charge and discharge the charge pump based on the output signal; The selection control circuit is used to control the conduction of the output path of the current between the charge / discharge control circuit and the low-pass filter based on the output signal. By adjusting the body bias voltage of the transistors in the charge pump circuit, all transistors in the charge pump are brought into a preset operating region.

2. The cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to claim 1, characterized in that, Both the bias circuit and the current replication circuit include multiple stacked transistors.

3. The cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to claim 1, characterized in that, The bias circuit includes a standard current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; One end of the standard current source is connected to a power supply; The drain of the first NMOS transistor is connected to the other end of the standard current source and the gate of the fourth NMOS transistor. The source is connected to the drain of the second NMOS transistor. The gate is connected to the gate of the second NMOS transistor and the first output terminal of the bias circuit. The source of the second NMOS transistor is connected to the drain of the third NMOS transistor; The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and the second output terminal of the bias circuit. The source of the fourth NMOS transistor is grounded.

4. The cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to claim 3, characterized in that, The current replication circuit includes a first current mirror, a second current mirror, a third current mirror, and a fourth current mirror; Each current mirror includes a PMOS current mirror unit and an NMOS current mirror unit, and both the PMOS current mirror unit and the NMOS current mirror unit adopt a common source common gate stacked transistor structure and a gate cross-coupling structure; The PMOS current mirror unit is connected between the power supply terminal and the corresponding current mirror output terminal, and the NMOS current mirror unit is connected between the ground terminal and the corresponding current mirror output terminal. The bias control terminal of the NMOS current mirror unit in each current mirror is connected to the first output terminal and the second output terminal of the bias circuit to receive the bias voltage. The output terminals of the first current mirror, the second current mirror, the third current mirror, and the fourth current mirror are respectively connected to the first to the eighth input terminals of the charge and discharge control circuit to provide charge and discharge current to each switching circuit.

5. The cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to claim 4, characterized in that, The charging and discharging control circuit includes a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit. The first switching circuit, the second switching circuit, the third switching circuit, and the fourth switching circuit all include a first amplifier, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth PMOS transistor, a twenty-ninth NMOS transistor, a thirtieth NMOS transistor, a thirty-first NMOS transistor, and a thirty-second NMOS transistor; The source of the 25th PMOS transistor is connected to the drain of the 29th NMOS transistor, the 31st NMOS transistor, and the source of the 27th PMOS transistor, and serves as the charging terminal for each switching circuit. The gate of the 25th PMOS transistor is connected to the first signal, and its drain is connected to the source of the 29th NMOS transistor, the source of the 30th NMOS transistor, the output terminal of the first amplifier, and the drain of the 26th PMOS transistor. The gate of the 29th NMOS transistor is connected to the second signal; The drain of the thirtieth NMOS transistor is connected to the source of the twenty-sixth PMOS transistor, the drain of the thirty-second NMOS transistor, and the source of the twenty-eighth PMOS transistor, and serves as the discharge terminal of each switching circuit. The gate of the thirtieth NMOS transistor is connected to the third signal; the gate of the twenty-sixth PMOS transistor is connected to the fourth signal; the drain of the twenty-seventh PMOS transistor is connected to the source of the thirty-first NMOS transistor, the source of the thirty-second NMOS transistor, the drain of the twenty-eighth PMOS transistor, and the inverting input terminal of the first amplifier, and serves as the output terminal of the charge / discharge control circuit. The gate of the twenty-seventh PMOS transistor is connected to the second signal; the gates of the thirty-first NMOS transistor and the thirty-second NMOS transistor are respectively connected to the first signal and the fourth signal. The gate of the 28th PMOS transistor is connected to the third signal; The non-inverting input terminal of the first amplifier is connected to the output terminal of the first amplifier; The inverting input terminal of the first amplifier is connected to the output terminal of the charge / discharge control circuit; The charging and discharging terminals of the first to fourth switching circuits are respectively connected to the output terminals of the PMOS current mirror units and the NMOS current mirror units of the four current mirrors, so as to form the first to eighth input terminals at the input terminal of the charging and discharging control circuit. The first signal, the second signal, the third signal, and the fourth signal are the output signals of the frequency and phase detector. The first signal and the second signal are a pair of complementary signals, and the third signal and the fourth signal are a pair of complementary signals, which are used to control each switching circuit to charge or discharge the charge pump respectively.

6. The cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to claim 5, characterized in that, The selection control circuit includes a first inverter, a second inverter, a third inverter, a first transmission gate, a second transmission gate, and a third transmission gate; The input terminal of the first inverter is connected to the first control terminal of the first transmission gate, the second control terminal of the second transmission gate, and the second signal, and the output terminal is connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate. The output of the second inverter is connected to both the input of the first transmission gate and the input of the second transmission gate, and the input is connected to the third signal. The input terminal of the third inverter is connected to the output terminals of the first transmission gate and the second transmission gate. The second control terminal of the third transmission gate is connected to the output terminal of the third inverter, the first control terminal is connected to the output terminal of the first transmission gate, the input terminal is connected to the output terminal of the charge / discharge control circuit, and the output terminal is connected to the low-pass filter.

7. A layout structure applied to the cross-interconnect radiation-resistant charge pump circuit based on SOI technology according to any one of claims 1-6, characterized in that, The layout structure includes a bias circuit layout area, four current mirror layout areas, four switch layout areas, and a selection control circuit layout area. The bias circuit layout area is the layout structure of the bias circuit; One of the current mirror layout areas is the layout structure of the current mirror; One of the switch layout areas is the layout structure of one of the switch circuits; The selection control circuit layout area is the layout structure of the selection control circuit; A first switch layout area, a second switch layout area, a third switch layout area, and a fourth switch layout area are sequentially arranged around the bias circuit layout area; The second current mirror layout area, the first current mirror layout area, the third current mirror layout area, and the fourth current mirror layout area are respectively disposed on the side of the first switch layout area, the second switch layout area, the third switch layout area, and the fourth switch layout area away from the bias circuit layout area; The selection control circuit layout area is located on the side of the third switch layout area away from the second switch layout area.

8. A layout structure according to claim 7, characterized in that, The first switch layout area and the third switch layout area are symmetrical about the center of the bias circuit layout area; The second switch layout area and the fourth switch layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the fourth current mirror layout area are symmetrical about the center of the bias circuit layout area; The second current mirror layout area and the third current mirror layout area are symmetrical about the center of the bias circuit layout area; The first current mirror layout area and the third current mirror layout area are arranged in parallel; The second current mirror layout area and the fourth current mirror layout area are arranged in parallel; The first switch layout area and the fourth switch layout area are arranged in parallel. The second switch layout area and the third switch layout area are arranged in parallel.

9. A layout structure according to claim 7, characterized in that, Based on the SOI process, a buried oxide layer is introduced into the active layer and substrate of the MOS transistor in the charge pump circuit.

10. A layout structure according to claim 7, characterized in that, The MOS transistors in the SOI-based cross-interconnect radiation-resistant charge pump circuit all use H-type gate devices.

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