Switching converter and control circuit and control method thereof

Abstract

A switching converter, its control circuit and control method are disclosed. The switching converter includes a power switch and converts an input voltage to an output voltage. The control circuit includes an input voltage detection circuit which generates a first voltage signal representing the input voltage and low-pass filters the input voltage to generate a second voltage signal; a compensation current generation circuit which generates a compensation current signal based on the first voltage signal and the second voltage signal; and a comparison circuit which generates an off control signal based on the compensation current signal, a current sample signal representing a current flowing through the power switch and a reference signal to control the off of the power switch. The switching converter can significantly reduce the overshoot or undershoot of the output voltage when the input voltage changes.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuits, and more particularly to switching converters and their control circuits and control methods. Background Technology

[0002] In recent years, many electronic devices have used OLEDs (Organic Light-Emitting Diodes). OLED drivers (such as switching power supplies) generate an output voltage based on the input voltage to drive the panel. When an electronic device is plugged into / unplugged from its adapter, the input voltage changes rapidly. To avoid panel flicker, the output voltage should remain stable when the input voltage changes abruptly. Therefore, we need to provide a switching power supply that has a good transient response to sudden changes in input voltage and can maintain a stable output voltage when the input voltage changes. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a switching converter and its control circuit and control method, which have good transient response performance when the input voltage changes.

[0004] According to an embodiment of the present invention, a control circuit for a switching converter is disclosed, wherein the switching converter includes a power switch and converts an input voltage into an output voltage. The control circuit includes: an input voltage detection circuit that generates a first voltage signal representing the input voltage and performs low-pass filtering on the input voltage to generate a second voltage signal; a compensation current generation circuit that generates a compensation current signal based on the first voltage signal and the second voltage signal; and a comparison circuit that generates a turn-off control signal based on the compensation current signal, a current sampling signal representing the current flowing through the power switch, and a reference signal to control the turn-off of the power switch.

[0005] According to another embodiment of the present invention, a switching converter is disclosed, comprising: a switching circuit including a power switch, wherein the input voltage is converted into an output voltage by turning the power switch on and off; and a control circuit as described above.

[0006] According to another embodiment of the present invention, a control method for a switching converter is disclosed, the switching converter including a power switch and converting an input voltage into an output voltage. The control method includes: monitoring the input voltage; generating a compensation current signal that varies with the input voltage; generating a peak voltage signal based on the compensation current signal and a current sampling signal representing the current flowing through the power switch; generating a reference signal based on an output voltage feedback signal representing the output voltage and an output voltage reference signal; and comparing the peak voltage signal and the reference signal to generate a turn-off control signal to control the turn-off of the power switch.

[0007] According to an embodiment of the present invention, when the input voltage changes, a compensation current that varies with the input voltage is generated, thereby rapidly changing the inductor current. The switching converter can quickly respond to changes in the input voltage, reducing overshoot or undershoot of the output voltage and maintaining the stability of the output voltage. Attached Figure Description

[0008] To better understand the present invention, it will be described in detail with reference to the following drawings:

[0009] Figure 1 A circuit block diagram of a switching converter 100 according to an embodiment of the present invention is shown;

[0010] Figure 2 The diagram shows the operating waveforms of a switching converter 100 according to an embodiment of the present invention.

[0011] Figures 3(a) and 3(b) show the simulation waveforms of a conventional switching converter and a switching converter 100 according to an embodiment of the present invention, respectively.

[0012] Figure 4 A circuit block diagram of a switching converter 100A according to another embodiment of the present invention is shown;

[0013] Figure 5 A circuit block diagram of a switching converter 100B according to another embodiment of the present invention is shown;

[0014] Figure 6 A circuit schematic diagram of a control circuit 11C for a switching converter 100 according to an embodiment of the present invention is shown;

[0015] Figure 7 A circuit schematic diagram of a control circuit 11D for a switching converter 100 according to another embodiment of the present invention is shown;

[0016] Figure 8 A flowchart of a control method 800 for a switching converter according to an embodiment of the present invention is shown. Detailed Implementation

[0017] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0018] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the illustrations provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0019] Throughout the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply an order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in that order or logical order, unless specifically specified in the language of the claims. These processing steps may be interchanged in any order without departing from the scope of the invention, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0020] Figure 1 A circuit block diagram of a switching converter 100 according to an embodiment of the present invention is shown. Figure 1As shown, the switching converter 100 includes a switching circuit 10 and a control circuit 11. The switching circuit 10 adopts a boost converter topology and includes an inductor L, a power switch HS, a power switch LS, and an output capacitor Co. The current flowing through the inductor L is IL. The switching circuit 10 converts the input voltage Vin to the output voltage Vout to power a load (not shown) by turning the power switches HS and LS on and off. Those skilled in the art will understand that the switching circuit 10 can be configured as any suitable DC / DC or AC / DC converter topology, such as synchronous or asynchronous buck, boost, buck-boost, forward, or flyback converters. The power switches HS and LS of the switching circuit 10 can be any controllable semiconductor device, such as a BJT, JFET, MOSFET, or IGBT. In other embodiments, the power switch HS can be replaced by a diode.

[0021] Control circuit 11 includes input voltage detection circuit 111, compensation current generation circuit 112, comparison circuit 113, and logic circuit 114. Control circuit 11 generates a switch control signal CTRL to control power switch LS. Those skilled in the art will understand that power switch HS can be controlled by the inverted signal of switch control signal CTRL; for simplicity, Figure 1 Not shown in the image.

[0022] The input voltage detection circuit 111 is coupled to the input voltage Vin and generates one or more signals indicating the input voltage Vin. In one embodiment, the one or more signals may indicate the direction (e.g., increasing or decreasing) and amount of change in the input voltage Vin.

[0023] exist Figure 1 In the illustrated embodiment, the input voltage detection circuit 111 generates a first voltage signal Vfst representing the input voltage Vin, and performs a low-pass filter on the input voltage Vin to generate a second voltage signal Vslw. The first voltage signal Vfst and the second voltage signal Vslw together indicate the change in the input voltage Vin.

[0024] The compensation current generating circuit 112 is coupled to the input voltage detection circuit 111 and generates a compensation current signal Icomp that varies with the input voltage Vin. In one embodiment, when the input voltage Vin increases, the compensation current signal Icomp increases; when the input voltage Vin decreases, the compensation current signal Icomp decreases.

[0025] exist Figure 1In the illustrated embodiment, the compensation current generating circuit 112 receives a first voltage signal Vfst, a second voltage signal Vslw, and a load current signal Id indicating the load, and generates a compensation current signal Icomp based on the first voltage signal Vfst, the second voltage signal Vslw, and the load current signal Id. In one embodiment, the compensation current signal Icomp is related to the difference between the first voltage signal Vfst and the second voltage signal Vslw. The compensation current signal Icomp increases as the difference between the first voltage signal Vfst and the second voltage signal Vslw increases, and decreases as the difference between the first voltage signal Vfst and the second voltage signal Vslw decreases. In one embodiment, the maximum change in the compensation current signal Icomp is related to the load current signal Id. In a further embodiment, the maximum change in the compensation current signal Icomp is proportional to the load current signal Id. Those skilled in the art will understand that the load current signal Id can be generated by detecting the inductor current IL, or by detecting the signal at the output of the switching circuit 10.

[0026] Comparator circuit 113 generates a turn-off control signal Coff based on a compensation current signal Icomp, a current sampling signal Isen representing the current flowing through power switch LS, and a reference signal REF to control the turn-off of power switch LS. In one embodiment, the turn-off control signal Coff is active (e.g., high level) when the superimposed signal of current sampling signal Isen and compensation current signal Icomp reaches the reference signal REF, or when the superimposed and scaled signal of current sampling signal Isen and compensation current signal Icomp reaches the reference signal REF, and power switch LS is turned off. In one embodiment, the reference signal REF is related to the output signal of switching converter 100 (e.g., output voltage Vout). In other embodiments, to prevent subharmonic oscillations, comparator circuit 113 further generates the turn-off control signal Coff based on a ramp current signal.

[0027] exist Figure 1 In the illustrated embodiment, the control circuit 11 further includes a current sampling circuit 115 coupled to the power switch LS for generating a current sampling signal Isen. The current sampling circuit 115 can be a resistor sampling circuit, a transformer sampling circuit, a current amplifier sampling circuit, etc. In one embodiment, when the power switch LS is turned on and the power switch HS is turned off, the inductor current IL increases, and the current flowing through the power switch LS is equal to the inductor current IL. The current sampling signal Isen represents the current during the period when the inductor current IL increases.

[0028] Logic circuit 114 generates a switch control signal CTRL based on clock signal CLK and turn-off control signal Coff to control power switch LS. In one embodiment, power switch LS is turned on when clock signal CLK arrives.

[0029] Figure 2 A waveform diagram of the operation of a switching converter 100 according to an embodiment of the present invention is shown. Figure 2 As shown, when the clock signal CLK arrives, the switch control signal CTRL changes from low to high, the power switch LS is turned on, the inductor current IL gradually increases, and the current sampling signal Isen also gradually increases. When the sum of the current sampling signal Isen and the compensation current signal Icomp increases to the reference signal REF, the switch control signal CTRL changes from high to low, the power switch LS is turned off, and the inductor current IL gradually decreases.

[0030] Before time t1, the input voltage Vin remains stable, the compensation current signal Icomp remains at the steady-state value Icomp1, the average inductor current AIL remains unchanged, and the output voltage Vout remains stable.

[0031] During the time interval t1 to t2, as the input voltage Vin increases, the difference between the first voltage signal Vfst and the second voltage signal Vslw increases, and the compensation current signal Icomp also increases accordingly, causing the average inductor current AIL to decrease rapidly. This prevents excessive energy from being stored in the inductor L, resulting in virtually no or very little additional energy being transferred to the output voltage Vout, and thus the output voltage Vout does not exhibit significant overshoot.

[0032] At time t2, the input voltage Vin stops increasing, and the compensation current signal Icomp increases to its maximum value Icomp2. At this time, the change in input voltage Vin reaches its maximum, and the change in compensation current signal Icomp also reaches its maximum value ΔIcompm1. Where ΔIcompm1 = Icomp2 - Icomp1. In one embodiment, the maximum change in compensation current signal Icomp ΔIcompm1 is proportional to the load current signal Id.

[0033] During the time period t2 to t3, the input voltage Vin remains stable, the difference between the first voltage signal Vfst and the second voltage signal Vslw decreases, the compensation current signal Icomp gradually decreases from its maximum value Icomp2 until it recovers to the steady-state value Icomp1, and the average inductor current AIL gradually decreases. The gradual decrease of the compensation current signal Icomp allows the control loop of the switching converter 100 sufficient time to adjust, the average inductor current AIL does not change abruptly, and the switching converter 100 can smoothly transition to the next steady state (e.g., during the time period t3 to t4).

[0034] During the time period t3 to t4, the switching converter 100 operates in steady state. The difference between the first voltage signal Vfst and the second voltage signal Vslw is zero. The compensation current signal Icomp remains at the steady-state value Icomp1, the average inductor current AIL also remains unchanged, and the output voltage Vout remains stable.

[0035] During the time interval t4 to t5, the input voltage Vin decreases, the difference between the first voltage signal Vfst and the second voltage signal Vslw decreases, and the compensation current signal Icomp also decreases accordingly, causing the average inductor current AIL to increase rapidly. This allows sufficient energy to be quickly stored in the inductor L and transferred to the output voltage Vout, thus preventing a significant undershoot in the output voltage Vout.

[0036] At time t5, the input voltage Vin no longer decreases, and the compensation current signal Icomp decreases to its minimum value Icomp3. At this time, the change in input voltage Vin reaches its maximum, and the change in compensation current signal Icomp also reaches its maximum value ΔIcompm2. Where ΔIcompm2 = Icomp1 - Icomp3. In one embodiment, the maximum change in compensation current signal Icomp ΔIcompm2 is proportional to the load current signal Id. In another embodiment, during the time period t1 to t6, the load current signal Id remains constant, and the change in input voltage Vin during the time period t1 to t2 is the same as its change during the time period t4 to t5. Therefore, the maximum change in compensation current signal Icomp during the time period t1 to t2 ΔIcompm1 is also the same as its maximum change during the time period t4 to t5 ΔIcompm2.

[0037] During the time interval t5 to t6, the difference between the first voltage signal Vfst and the second voltage signal Vslw increases, and the compensation current signal Icomp gradually increases from its minimum value Icomp3 until it recovers to the steady-state value Icomp1. The average inductor current AIL continues to increase. The gradual increase of the compensation current signal Icomp allows the control loop of the switching converter 100 sufficient time to adjust, preventing abrupt changes in the average inductor current AIL. The switching converter 100 can then smoothly transition to the next steady state (e.g., after time t6).

[0038] After time t6, the switching converter 100 operates in steady state. The difference between the first voltage signal Vfst and the second voltage signal Vslw is zero. The compensation current signal Icomp no longer changes and remains at the steady-state value Icomp1. The average inductor current AIL remains unchanged, and the output voltage Vout remains stable.

[0039] Those skilled in the art will understand that the above embodiments are merely illustrative and not intended to limit the invention. Other circuits capable of achieving the same or similar functions also satisfy the spirit and scope of the invention, as long as the variable compensation current signal Icomp can rapidly decrease the average inductor current AIL through the control loop when the input voltage Vin suddenly increases, and rapidly increase the average inductor current AIL through the control loop when the input voltage Vin suddenly decreases, thereby maintaining the stability of the output voltage Vout. For example, in one embodiment, the compensation current signal Icomp decreases as the input voltage Vin increases and increases as the input voltage Vin decreases. In this case, the compensation current signal Icomp is not superimposed on the current sampling signal Isen, but on the reference signal REF. When the current sampling signal Isen increases to the superposition signal of the reference signal REF and the compensation current signal Icomp, the power switch LS is turned off.

[0040] Figures 3(a) and 3(b) show the simulation waveforms of a conventional switching converter and a switching converter 100 according to an embodiment of the present invention, respectively.

[0041] As shown in Figures 3(a) and 3(b), compared to existing switching converters, when the input voltage Vin changes abruptly, the inductor current IL of the switching converter 100 can change more quickly to adapt to the change in input voltage Vin, and the overshoot and undershoot of the output voltage Vout are significantly reduced.

[0042] According to an embodiment of the present invention, when the input voltage Vin increases, the average inductor current AIL can decrease rapidly, and when the input voltage Vin decreases, the average inductor current AIL can increase rapidly. The energy stored in the inductor L can change rapidly with the change of the input voltage Vin, and there will be no excessive or insufficient energy transferred to the output voltage Vout. This significantly improves the overshoot or undershoot of the output voltage Vout, so that the output voltage Vout can remain as stable as possible when the input voltage Vin changes.

[0043] Figure 4 A circuit block diagram of a switching converter 100A according to another embodiment of the present invention is shown. The switching converter 100A employs a buck converter topology and includes a power switch HS, a power switch LS, an inductor L, and an output capacitor Co, whose connections are as follows: Figure 4 As shown. Control circuit 11A generates a switch control signal CTRL to control power switch HS. Power switch LS can be controlled by the inverted signal of switch control signal CTRL. For simplicity, Figure 4 Not shown in the image.

[0044] exist Figure 4In the illustrated embodiment, the control circuit 11A is integrated with the power switches HS and LS in the same integrated circuit IC1. Integrated circuit IC1 has multiple pins, including an input pin IN coupled to the input voltage Vin, a switch pin SW coupled to the common connection point of the power switches HS and LS, and an output pin OUT coupled to the output voltage Vout.

[0045] The control circuit 11A includes an input voltage detection circuit 111, a compensation current generation circuit 112, a comparison circuit 113, a logic circuit 114, a current sampling circuit 115, a load current detection circuit 116, an output feedback circuit 117, and an error amplifier circuit 118.

[0046] The input voltage detection circuit 111 is coupled to the input pin IN to receive the input voltage Vin and generates a first voltage signal Vfst and a second voltage signal Vslw based on the input voltage Vin.

[0047] The load current detection circuit 116 is coupled to the switch pin SW and generates a load current signal Id that indicates the load.

[0048] The compensation current generating circuit 112 is coupled to the input voltage detection circuit 111 and the load current detection circuit 116, and generates the compensation current signal Icomp based on the first voltage signal Vfst, the second voltage signal Vslw and the load current signal Id.

[0049] The current sampling circuit 115 is coupled to the switch pin SW and generates a current sampling signal Isen representing the current flowing through the power switch HS. In one embodiment, when the power switch HS is turned on and the power switch LS is turned off, the inductor current IL increases, and the current flowing through the power switch HS is equal to the inductor current IL. The current sampling signal Isen represents the current during the period when the inductor current IL increases.

[0050] The output feedback circuit 117 is coupled to the output pin OUT to receive the output voltage Vout and generate an output voltage feedback signal Vfb representing the output voltage Vout.

[0051] Error amplifier circuit 118 is coupled to output feedback circuit 117 to receive output voltage feedback signal Vfb, and generates reference signal REF based on output voltage feedback signal Vfb and an output voltage reference signal Vref.

[0052] The comparator circuit 113 generates a turn-off control signal Coff based on the compensation current signal Icomp, the current sampling signal Isen, and the reference signal REF to control the turn-off of the power switch HS.

[0053] Logic circuit 114 generates a switch control signal CTRL based on clock signal CLK and turn-off control signal Coff to control power switch HS.

[0054] Working principle of control circuit 11A Figure 1 The control circuit 11 shown is similar and will not be described again here.

[0055] Figure 5 A circuit block diagram of a switching converter 100B according to another embodiment of the present invention is shown. The switching converter 100B employs a buck-boost converter topology and includes an input capacitor Cin, a power switch S1, an inductor L, a power switch S2, and an output capacitor Co, whose connections are as follows: Figure 5 As shown.

[0056] exist Figure 5 In the illustrated embodiment, the control circuit 11B has multiple pins, including an input pin IN coupled to the input voltage Vin, a drive pin GATE1 providing a switch control signal CTRL to the power switch S1, a switch pin SW coupled to the common connection point of power switches S1 and S2, and an output pin OUT coupled to the output voltage Vout. The control circuit 11B generates the switch control signal CTRL to control the power switch S1. The power switch S2 can be controlled by the inverted signal of the switch control signal CTRL. For simplicity, Figure 5 Not shown in the image.

[0057] The working principle of control circuit 11B and Figure 1 The control circuit 11 shown and Figure 4 The control circuit 11A shown is similar and will not be described in detail here.

[0058] Figure 6 A circuit schematic diagram of a control circuit 11C for a switching converter 100 according to an embodiment of the present invention is shown. The control circuit 11C includes an input pin IN, an output pin OUT, an input voltage detection circuit 111C, a compensation current generation circuit 112C, a comparator circuit 113C, a logic circuit 114C, an output feedback circuit 117C, an error amplifier circuit 118C, and a current-to-voltage conversion circuit 119C.

[0059] The input voltage detection circuit 111C is coupled to the input pin IN to receive the input voltage Vin and generate a first voltage signal Vfst and a second voltage signal Vslw. Figure 6In the illustrated embodiment, the input voltage detection circuit 111C includes a voltage divider circuit 1111 and a low-pass filter 1112. The voltage divider circuit 1111 includes resistors R1 and R2, which divide the input voltage Vin to generate a first voltage signal Vfst. The low-pass filter 1112 includes resistor R3 and capacitor C1, which filters the input voltage Vin or its divided voltage to generate a second voltage signal Vslw. In other embodiments, the input voltage detection circuit 111C may also include an active filter composed of an operational amplifier, resistors, and capacitors, which filters the input voltage Vin or its divided voltage to generate the second voltage signal Vslw.

[0060] The compensation current generating circuit 112C receives a first voltage signal Vfst and a second voltage signal Vslw. When the first voltage signal Vfst is less than the second voltage signal Vslw, it provides a first current signal i1; when the first voltage signal Vfst is greater than the second voltage signal Vslw, it provides a second current signal i2. The compensation current generating circuit 112C generates a compensation current signal Icomp based on the first current signal i1 and the second current signal i2. In one embodiment, the first current signal i1 has a first direction, and the second current signal i2 has a second direction, the first direction being opposite to the second direction.

[0061] exist Figure 6 In the embodiment shown, the compensation current generating circuit 112C includes a first transconductance amplifier A1, a second transconductance amplifier A2, diodes d1 and d2, current sources IS0 to IS2, and a first current mirror CM1.

[0062] The first transconductance amplifier A1 has a first input terminal, a second input terminal, a bias terminal, and an output terminal. The first input terminal receives a first voltage signal Vfst, the second input terminal receives a second voltage signal Vslw, and the bias terminal is coupled to a current source IS1. In one embodiment, the current source IS1 provides a fixed current. In another embodiment, the current source IS1 is a controlled current source, and the current it provides is related to the load current signal Id.

[0063] The second transconductance amplifier A2 has a first input terminal, a second input terminal, a bias terminal, and an output terminal. The first input terminal receives a first voltage signal Vfst, the second input terminal receives a second voltage signal Vslw, and the bias terminal is coupled to a current source IS2. In one embodiment, the current source IS2 provides a fixed current. In another embodiment, the current source IS2 is a controlled current source, and the current it provides is related to the load current signal Id.

[0064] The output terminals of the first transconductance amplifier A1 and the second transconductance amplifier A2 are coupled together to provide current ivar. When the first voltage signal Vfst is less than the second voltage signal Vslw, current ivar flows from the first transconductance amplifier A1 to node 21; when the first voltage signal Vfst is greater than the second voltage signal Vslw, current ivar flows from node 21 into the second transconductance amplifier A2. When the switching converter 100 is in steady state, the first voltage signal Vfst is equal to the second voltage signal Vslw, and current ivar is zero (or essentially zero). Those skilled in the art will understand that... Figure 6 In the illustrated embodiment, diodes d1 and d2 are used to help understand the directions of the first current signal i1 flowing through the first transconductance amplifier A1 and the second current signal i2 flowing through the second transconductance amplifier A2. In practical applications, diodes d1 and d2 can be omitted.

[0065] A current source IS0 is coupled between node 21 and reference ground. A first current mirror CM1 has a power supply terminal, a first terminal, and a second terminal, wherein the power supply terminal is coupled to the supply voltage Vcc, and the first terminal is coupled to node 21. The first current mirror CM1 provides a compensation current signal Icomp at its second terminal based on the current ivar and the current provided by the current source IS0.

[0066] The current-to-voltage conversion circuit 119C generates a peak voltage signal Vipk at node 22 based on the compensation current signal Icomp, the current sampling signal Isen, and the ramp current signal Islp. Figure 6 In the illustrated embodiment, the current-to-voltage conversion circuit 119C includes a resistor Rb. In another embodiment, the current-to-voltage conversion circuit 119C includes a transimpedance amplifier.

[0067] The output feedback circuit 117C is coupled to the output pin OUT to receive the output voltage Vout and generate an output voltage feedback signal Vfb representing the output voltage Vout. Figure 6 In the illustrated embodiment, the output feedback circuit 117C includes resistors Ro1 and Ro2.

[0068] The error amplifier circuit 118C has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives an output voltage feedback signal Vfb, and the second input terminal receives an output voltage reference signal Vref. Based on the difference between the output voltage reference signal Vref and the output voltage feedback signal Vfb, the error amplifier circuit 118C generates a reference signal REF at the output terminal. In one embodiment, the error amplifier circuit 118C includes an error amplifier EA.

[0069] Comparator circuit 113C has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a peak voltage signal Vipk, and the second input terminal receives a reference signal REF. Comparator circuit 113C compares the peak voltage signal Vipk and the reference signal REF to generate a turn-off control signal Coff. In one embodiment, comparator circuit 113C includes a comparator CMP.

[0070] Logic circuit 114C includes an RS flip-flop FF1. The RS flip-flop FF1 has a set terminal S, a reset terminal R, and an output terminal Q. The set terminal S receives the clock signal CLK, the reset terminal R receives the shutdown control signal Coff, and the output terminal Q provides the switch control signal CTRL.

[0071] Figure 7 A circuit schematic diagram of a control circuit 11D for a switching converter 100 according to another embodiment of the present invention is shown. Figure 6 Unlike the control circuit 11C shown, the control circuit 11D also includes an output compensation circuit 120. For example... Figure 7 As shown, the output compensation circuit 120 generates an output compensation current signal Iop based on the output voltage reference signal Vref and the output voltage feedback signal Vfb. The output compensation current signal Iop, the compensation current signal Icomp, the current sampling signal Isen, and the ramp current signal Islp flow through the resistor Rb, generating a peak voltage signal Vipk at node 22.

[0072] In one embodiment, when the output voltage Vout is less than the expected value (i.e., the output voltage feedback signal Vfb is less than the output voltage reference signal Vref), the output compensation current signal Iop flows from node 22 into the output compensation circuit 120, the peak voltage signal Vipk decreases, and the duty cycle of the switch control signal CTRL increases, causing the output voltage Vout to quickly recover to the expected value. When the output voltage Vout is greater than the expected value (i.e., the output voltage feedback signal Vfb is greater than the output voltage reference signal Vref), the output compensation current signal Iop flows from the output compensation circuit 120 to node 22, the peak voltage signal Vipk increases, and the duty cycle of the switch control signal CTRL decreases, causing the output voltage Vout to quickly recover to the expected value.

[0073] exist Figure 7 In the embodiment shown, the output compensation circuit 120 includes a third transconductance amplifier A3, a fourth transconductance amplifier A4, a second current mirror CM2, a third current mirror CM3, and a fourth current mirror CM4.

[0074] The third transconductance amplifier A3 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the output voltage feedback signal Vfb, and the second input terminal receives the output voltage reference signal Vref. When the output voltage feedback signal Vfb is greater than the output voltage reference signal Vref, the third transconductance amplifier A3 provides a third current i3 at the output terminal.

[0075] The fourth transconductance amplifier A4 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the output voltage reference signal Vref, and the second input terminal receives the output voltage feedback signal Vfb. When the output voltage reference signal Vref is greater than the output voltage feedback signal Vfb, the fourth transconductance amplifier A4 provides a fourth current i4 at the output terminal.

[0076] The second current mirror CM2 has a first terminal, a second terminal, and a ground terminal, wherein the first terminal is coupled to the output terminal of the third transconductance amplifier A3, and the ground terminal is coupled to the reference ground.

[0077] The third current mirror CM3 has a first terminal, a second terminal, and a ground terminal, wherein the first terminal is coupled to the output terminal of the fourth transconductance amplifier A4, and the ground terminal is coupled to the reference ground.

[0078] The fourth current mirror CM4 has a first terminal, a second terminal, and a power supply terminal. The first terminal is coupled to the second terminal of the second current mirror CM2, the second terminal is coupled to the second terminal of the third current mirror CM3, and the power supply terminal is coupled to the supply voltage Vcc. The second terminals of the third current mirror CM3 and the fourth current mirror CM4 are coupled together to provide the output compensation current signal Iop.

[0079] according to Figure 7 In the embodiment shown, when the output voltage Vout deviates from the expected value, the output compensation circuit 120 generates a variable output compensation current signal Iop to change the peak voltage signal Vipk, thereby changing the duty cycle of the switch control signal CTRL, so that the output voltage Vout can quickly recover to the expected value.

[0080] Those skilled in the art will understand that the above embodiments are merely illustrative and not intended to limit the invention. Other circuits capable of achieving the same or similar functions also satisfy the spirit and scope of protection of the invention. For example, the compensation current generating circuit 112 can be implemented using two transconductance amplifiers (a third transconductance amplifier A3 and a fourth transconductance amplifier A4) and multiple current mirrors (a first current mirror CM1 to a fourth current mirror CM4) similar to the output compensation circuit 120.

[0081] Figure 8A flowchart of a control method 800 for a switching converter according to an embodiment of the present invention is shown. The switching converter has a power switch and converts an input voltage into an output voltage based on the on and off states of the power switch. The control method 800 includes steps S101 to S105.

[0082] In step S101, the input voltage is monitored.

[0083] In step S102, a compensation current signal that varies with the input voltage is generated.

[0084] In step S103, a peak voltage signal is generated based on the compensation current signal and the current sampling signal representing the current flowing through the power switch.

[0085] In step S104, a reference signal is generated based on the output voltage reference signal and the output voltage feedback signal representing the output voltage.

[0086] In step S105, the peak voltage signal and the reference signal are compared to generate a shutdown control signal to control the power switch to turn off.

[0087] In one embodiment, step S102 includes: generating a first voltage signal representing an input voltage, performing low-pass filtering on the input voltage to generate a second voltage signal, and generating a compensation current signal based on the first voltage signal and the second voltage signal.

[0088] In a further embodiment, step S102 further includes: providing a first current signal when the first voltage signal is less than the second voltage signal; providing a second current signal when the first voltage signal is greater than the second voltage signal; and generating a compensation current signal based on the first current signal and the second current signal.

[0089] In one embodiment, the compensation current signal increases when the input voltage increases and decreases when the input voltage decreases.

[0090] Note that in the flowchart described above, the functions marked in the boxes can also be arranged differently. Figure 8 The sequence shown occurs. For example, two consecutively represented boxes can actually be executed in essentially parallel order, and they can sometimes be executed in reverse order, depending on the specific function involved.

[0091] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A control circuit for a switching converter, wherein the switching converter includes a power switch and converts an input voltage into an output voltage, the control circuit comprising: The input voltage detection circuit generates a first voltage signal representing the input voltage and performs low-pass filtering on the input voltage to generate a second voltage signal. The compensation current generating circuit generates a compensation current signal based on a first voltage signal and a second voltage signal. as well as The comparator circuit generates a turn-off control signal based on a compensation current signal, a current sampling signal representing the current flowing through the power switch, and a reference signal to control the turn-off of the power switch.

2. The control circuit as described in claim 1, wherein: When the input voltage increases, the compensation current signal increases; and When the input voltage decreases, the compensation current signal decreases.

3. The control circuit as described in claim 2, wherein: When the input voltage stops changing and remains stable, the compensation current signal gradually recovers to its steady-state value.

4. The control circuit as described in claim 1, wherein the input voltage detection circuit comprises: A voltage divider circuit divides the input voltage to generate a first voltage signal; as well as A low-pass filter filters the input voltage to generate a second voltage signal.

5. The control circuit as claimed in claim 1, wherein when the first voltage signal is less than the second voltage signal, the compensation current generating circuit provides a first current signal, and when the first voltage signal is greater than the second voltage signal, the compensation current generating circuit provides a second current signal, and the compensation current generating circuit generates a compensation current signal based on the first current signal and the second current signal.

6. The control circuit as described in claim 5, wherein the compensation current generating circuit comprises: A first transconductance amplifier has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a first voltage signal and the second input terminal receives a second voltage signal. The second transconductance amplifier has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a first voltage signal, the second input terminal receives a second voltage signal, and the output terminal is coupled to the output terminal of the first transconductance amplifier. as well as The current mirror has a first end and a second end, wherein the first end is coupled to a common connection point of the output of the first transconductance amplifier and the output of the second transconductance amplifier, and the second end provides a compensation current signal.

7. The control circuit as described in claim 1, wherein: The compensation current generating circuit also receives a load current signal indicating the load and generates a compensation current signal based on the first voltage signal, the second voltage signal, and the load current signal.

8. The control circuit of claim 7, wherein the compensation current generating circuit comprises: A first transconductance amplifier has a first input terminal, a second input terminal, a bias terminal, and an output terminal, wherein the first input terminal receives a first voltage signal, the second input terminal receives a second voltage signal, and the bias terminal is coupled to a first current source controlled by a load current signal. The second transconductance amplifier has a first input terminal, a second input terminal, a bias terminal and an output terminal, wherein the first input terminal receives a first voltage signal, the second input terminal receives a second voltage signal, the bias terminal is coupled to a second current source controlled by a load current signal, and the output terminal is coupled together with the output terminal of the first transconductance amplifier. as well as The current mirror has a first end and a second end, wherein the first end is coupled to a common connection point of the output of the first transconductance amplifier and the output of the second transconductance amplifier, and the second end provides a compensation current signal.

9. The control circuit as described in claim 1, further comprising: The output feedback circuit generates an output voltage feedback signal that represents the output voltage. An error amplifier circuit generates the reference signal based on an output voltage feedback signal and an output voltage reference signal; as well as The current-to-voltage conversion circuit converts the superimposed signal of the current sampling signal, the compensated current signal, and the ramp current signal into a peak voltage signal; whereby... The comparator circuit compares the peak voltage signal with a reference signal to generate the shutdown control signal.

10. The control circuit as described in claim 9, further comprising: The output compensation circuit generates an output compensation current signal based on the output voltage feedback signal and the output voltage reference signal. in The current-to-voltage conversion circuit converts the superimposed signal of the output compensation current signal, the current sampling signal, the compensation current signal, and the ramp current signal into a peak voltage signal.

11. A switching converter, comprising: Switching circuits, including power switches, convert input voltage into output voltage by turning the power switches on and off; as well as The control circuit as described in any one of claims 1 to 10.

12. The switching converter of claim 11, wherein the switching circuit includes a buck converter, a boost converter, or a buck-boost converter.

13. A control method for a switching converter, the switching converter including a power switch and converting an input voltage into an output voltage, the control method comprising: Monitor input voltage; It generates a compensation current signal that varies with the input voltage; The peak voltage signal is generated based on the compensation current signal and the current sampling signal representing the current flowing through the power switch; A reference signal is generated based on an output voltage feedback signal representing the output voltage and an output voltage reference signal. as well as The peak voltage signal is compared with a reference signal to generate a shutdown control signal to control the power switch to turn off.

14. The control method as described in claim 13, wherein: When the input voltage increases, the compensation current signal increases; and When the input voltage decreases, the compensation current signal decreases.

15. The control method as described in claim 13, further comprising: Generate a first voltage signal representing the input voltage; as well as The input voltage is low-pass filtered to generate a second voltage signal; in The compensation current signal is generated based on the first voltage signal and the second voltage signal.

16. The control method of claim 15, further comprising: When the first voltage signal is less than the second voltage signal, a first current signal is provided; When the first voltage signal is greater than the second voltage signal, a second current signal is provided; as well as A compensation current signal is generated based on the first current signal and the second current signal.

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