Method of forming a semiconductor structure

Abstract

A method of forming a semiconductor structure includes the following steps. A plurality of bit line structures are formed in a substrate, wherein each bit line structure includes a bit line and a cap layer formed on the bit line and protruding above a top surface of the substrate. First spacers are formed on opposite sidewalls of each bit line structure. A second spacer layer is formed on the opposite sidewalls of each bit line structure covering the first spacers and a top surface of the cap layer. Third spacers are formed on the opposite sidewalls of each bit line structure on the top surface of the substrate covering the second spacer layer. A conductive landing layer is formed on the top surface of the substrate covering the plurality of bit line structures, the third spacers, the second spacer layer, and the first spacers. The conductive landing layer is patterned to form a plurality of conductive landing structures.

Description

Technical Field

[0001] This invention relates to a method for forming a semiconductor structure, and more particularly to a method for forming a memory structure. Background Technology

[0002] Dynamic random access memory (DRAM) is composed of a large number of memory cells, each of which includes a capacitor and a transistor (ITIC). The word line is connected to the gate of the transistor; the bit line is connected to the source of the transistor; and the capacitor is connected to the drain of the transistor. With the trend of miniaturization of electronic devices and the continuous improvement of performance requirements, how to enable electronic devices to include more components, or to make each component have a smaller area, is a goal that those skilled in the art are eager to pursue. Summary of the Invention

[0003] The present invention provides a method for forming a semiconductor structure, wherein a third gap wall covering a second gap wall layer is formed on the opposite side walls of each line structure on the top surface of the substrate, so that the subsequent patterning process for forming multiple conductive pad structures has good process window.

[0004] The present invention provides a method for forming a semiconductor structure, comprising: forming a plurality of bit line structures in a substrate, wherein each bit line structure includes a bit line and a capping layer formed on the bit line and protruding above the top surface of the substrate; forming a first gap wall on opposite side walls of each bit line structure; forming a second gap wall layer covering the first gap wall and the top surface of the capping layer on opposite side walls of each bit line structure; forming a third gap wall covering the second gap wall layer on opposite side walls of each bit line structure on the top surface of the substrate; forming a conductive pad layer covering the plurality of bit line structures, the third gap wall, the second gap wall layer and the first gap wall on the top surface of the substrate; and patterning the conductive pad layer to form a plurality of conductive pad structures.

[0005] The first spacer wall includes a first material layer and a second material layer formed on the first material layer. The materials of the first material layer and the second spacer wall layer are different from the materials of the second material layer and the third spacer wall. The materials of the first material layer and the second spacer wall layer include nitrides, and the materials of the second material layer and the third spacer wall include oxides.

[0006] In the step of patterning the conductive pad layer, a portion of the first gap wall, a portion of the second gap wall layer, and a portion of the third gap wall located on one of the opposite side walls of each line structure are also removed, forming a first gap wall structure on one of the opposite side walls of each line structure and a second gap wall structure on the other of the opposite side walls of each line structure.

[0007] The top surface of the first spacer wall structure is lower than the top surface of the second spacer wall structure.

[0008] In the step of patterning the conductive pad layer, a portion of each top cover layer is also removed, such that the top cover layer is formed to include a first portion and a second portion. The first portion has a top surface at the same level as the top surface of the first spacer wall structure. The second portion has a top surface at a lower level than the top surface of the second spacer wall structure.

[0009] The method of forming a semiconductor structure further includes forming an insulating pattern in an opening that separates multiple conductive pad structures, wherein the insulating pattern is in contact with a first spacer wall structure.

[0010] The method of forming a semiconductor structure further includes removing a portion of the second material layer and the third spacer wall in the first spacer wall structure exposed by the opening to form a recess before forming an insulating pattern.

[0011] In the step of forming the insulating pattern, the insulating pattern is formed above the depression but does not fill the depression, so that an air gap is formed in the depression.

[0012] The conductive pad structure includes an upper portion and a lower portion. The upper portion has a top surface at the same level as the top surface of the insulating pattern. The lower portion has a top surface at a lower level than the top surface of the first gap wall structure.

[0013] In methods for forming semiconductor structures, forming third gap walls covering the second gap wall layer on opposite sidewalls of each line structure on the top surface of the substrate provides good process margin for subsequent patterning processes that form multiple conductive pad structures. For example, the third gap wall can improve the tolerance of the patterning process in terms of overlay shift, ensuring that the portion of the conductive pad layer to be removed does not remain due to overlay shift, thus avoiding defects such as short circuits. Attached Figure Description

[0014] Figures 1A to 1E This is a cross-sectional schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0017] First, refer to Figure 1A Multiple bitline structures 110 are formed in the substrate 100. Figure 1A The cross-sectional view shown can be a cross-sectional view taken by a line that spans the active region and bit line but does not intersect with the word line, such that... Figure 1A The bit line structure 110 shown on the conductive contact 112 is on two adjacent pattern layers 103. Each bit line structure 110 may include a barrier pattern 114, bit lines 116 formed on the barrier pattern 114, and a top cover layer 118 formed on the bit lines 116 and protruding above the top surface of the substrate 100.

[0018] Substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. Substrate 100 may also include isolation structures formed in the semiconductor substrate or SOI substrate to define active regions, source / drain electrodes formed in the semiconductor substrate or SOI substrate, or word lines, dielectric layers, wiring layers, and other components formed on or therein in the semiconductor substrate or SOI substrate.

[0019] Pattern layer 103 may include suitable materials such as polysilicon. Conductive contacts 112 may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The barrier pattern 114 may include, but is not limited to, titanium nitride (TiN). Bit lines 116 may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The capping layer 118 may include nitrides such as silicon nitride.

[0020] First spacer walls 120 are formed on opposite sidewalls of each line structure 110. Each first spacer wall 120 includes a first material layer 122 and a second material layer 124 formed on the first material layer 122. The first material layer 122 may include, for example, silicon nitride (SiN). x Nitrides such as silicon dioxide (SiO2) may be present. The second material layer 124 may include silicon dioxide (SiO2) and other nitrides.x Oxides such as )

[0021] A second spacer layer 126 is formed on the opposite sidewalls of the bit line structure 110, covering the top surface of the first spacer wall 120 and the top cover layer 118. The second spacer layer 126 may include a nitride such as silicon nitride. The second spacer layer 126 covering the top surface of the top cover layer 118 helps to maintain the top profile of the bit line structure 110 in a rectangular shape, thus avoiding a tapered top profile of the bit line structure 110 that would cause problems in subsequent patterned conductive pad layers (such as...). Figure 1B In the process of the conductive pad layer (shown as including barrier layer 140 and conductive layer 150), the portion of the conductive pad layer that is to be removed remains due to insufficient tolerance for overlap offset, causing defects such as short circuits.

[0022] A third spacer 130 covering the second spacer layer 126 is formed on the opposite sidewalls of the bit line structure 110 on the top surface of the substrate 100. The third spacer 130 may include an oxide such as silicon oxide. The third spacer 130 may be formed, for example, after the storage node contact is formed. The third spacer 130 may be formed by the following steps. First, after the storage node contact is formed, a spacer material layer (not shown) covering the second spacer layer 126 is formed on the top surface of the substrate 100 by a process such as atomic layer deposition (ALD). Next, a portion of the spacer material layer on the top surface of the substrate 100 and the portion above the top surface of the bit line structure 110 is removed by a process such as etch back to form the third spacer 130 covering the portion of the second spacer layer 126 on the opposite sidewalls of the bit line structure 110.

[0023] The materials of the first material layer 122 and the second spacer layer 126 are different from the materials of the second material layer 124 and the third spacer layer 130. The materials of the first material layer 122 and the second spacer layer 126 include nitrides (such as silicon nitrides such as SiN or SiCN), and the materials of the second material layer 124 and the third spacer layer 130 include oxides (such as silicon oxides such as SiOx or SiCOx).

[0024] Please refer to Figure 1BA conductive pad layer is formed on the top surface of the substrate 100, covering a plurality of bit line structures 110, a third spacer 130, a second spacer layer 126, and a first spacer 120. The conductive pad layer includes a barrier layer 140 and a conductive layer 150 formed on the barrier layer 140. The barrier layer 140 includes, but is not limited to, titanium nitride (TiN). The conductive layer 150 includes a conductive material such as a metal or metal alloy. The metal and metal alloy are, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0025] Reference Figure 1C The conductive pad layer is patterned to form multiple conductive pad structures, each of which includes a barrier pattern 142 and a conductive pattern 152 formed on the barrier pattern 142. When the semiconductor structure is applied to a dynamic random access memory, the conductive pad structure can serve as a landing pad for connection to a storage node (e.g., a capacitor). In the patterning process described above, the third spacer wall 130 can improve the tolerance of the patterning process in terms of overlap offset, so that the portion of the conductive pad layer (including the conductive pad layer containing the barrier layer 140 and the conductive layer 150) that is expected to be removed will not remain due to overlap offset, thus avoiding short circuit problems caused by the residual barrier layer 140 (e.g., short circuit problems between the landing pad and the storage node contact). In other words, forming a third spacer wall 130 covering the second spacer wall layer 126 on the opposite sidewalls of the bit line structure 110 on the top surface of the substrate 100 allows the subsequent patterning process for forming multiple conductive pad structures to have good process margin.

[0026] like Figure 1C As shown, in the step of patterning the conductive pad layer, a portion of the first gap wall 120, a portion of the second gap wall layer 126, and a portion of the third gap wall 130 located on one of the opposite side walls of each bit line structure 110 are also removed to form a first gap wall structure SP1 on one of the opposite side walls of each bit line structure 110a and a second gap wall structure SP2 on the other of the opposite side walls of each bit line structure 110a. The first gap wall structure SP1 may include a first gap wall 120a, a second gap wall 126a, and a third gap wall 132a. The first gap wall 120a includes a first material layer 122a and a second material layer 124a. The second gap wall structure SP2 may include a first gap wall 120b, a second gap wall 126b, and a third gap wall 132b. The top surface of the first gap wall structure SP1 is lower than the top surface of the second gap wall structure SP2.

[0027] like Figure 1CAs shown, in the step of patterning the conductive pad layer, a portion of each top cover layer 118 is also removed, so that the top cover layer 118a is formed to include a first portion and a second portion, wherein the first portion has a top surface at the same level as the top surface of the first spacer wall structure SP1, and the second portion has a top surface at a lower level than the top surface of the second spacer wall structure SP2.

[0028] Please refer to Figure 1C and Figure 1D A portion of the second material layer 124a and the third spacer wall 132a in the first spacer wall structure SP1 exposed by the opening 152o, separating multiple conductive pad structures, is removed to form recesses 124ar and 132ar. A portion of the second material layer 124a and the third spacer wall 132a in the first spacer wall structure SP1 exposed by the opening 152o is then removed using diluted hydrofluoric acid to form recesses 124ar and 132ar.

[0029] Reference Figure 1D and Figure 1E An insulating pattern 160 is formed in the opening 152o that separates the multiple conductive pad structures, wherein the insulating pattern 160 is in contact with the first spacer wall structure SP1. Figure 1E As shown, the insulating pattern 160 can fill recesses 124ar and 132ar. (As...) Figure 2 As shown, in the step of forming the insulating pattern 160, the insulating pattern 160 is formed above the recesses 124ar and 132ar but does not completely fill the recesses 124ar and 132ar, so that the air gap AG is formed in the recesses 124ar and 132ar. This will help improve the stability of the semiconductor structure.

[0030] Each conductive pad structure (e.g., a conductive pad structure including conductive pattern 152 on barrier pattern 142) includes an upper portion and a lower portion, wherein the upper portion has a top surface at the same level as the top surface of insulating pattern 160, and the lower portion has a top surface at the same level as the top surface of first gap wall structure SP1.

[0031] In summary, in the above-described method for forming a semiconductor device, by additionally forming a third gap wall covering the second gap wall layer on the opposite sidewalls of each line structure on the top surface of the substrate, the subsequent patterning process for forming multiple conductive pad structures has good process margin. For example, the third gap wall can improve the tolerance of the above-described patterning process in terms of overlap offset, so that the portion of the conductive pad layer that is to be removed will not remain due to overlap offset, thus avoiding defects such as short circuits.

[0032] The foregoing embodiments have provided a detailed description of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A plurality of bit line structures are formed in a substrate, wherein each bit line structure includes a bit line and a capping layer formed on the bit line and protruding above the top surface of the substrate; A first gap wall is formed on the opposite side walls of each of the bit line structures; A second gap wall layer is formed on the opposite side walls of each of the bit line structures, covering the top surface of the first gap wall and the top cover layer; A third gap wall covering the second gap wall layer is formed on the opposite side walls of each of the bit line structures on the top surface of the substrate; A conductive pad layer covering the plurality of bit line structures, the third gap wall, the second gap wall layer and the first gap wall is formed on the top surface of the substrate; as well as The conductive pad layer is patterned to form multiple conductive pad structures.

2. The method of claim 1, wherein each of the first gap walls comprises a first material layer and a second material layer formed on the first material layer.

3. The method according to claim 2, wherein the materials of the first material layer and the second spacer wall layer are different from the materials of the second material layer and the third spacer wall.

4. The method of claim 3, wherein the materials of the first material layer and the second spacer wall layer comprise nitrides, and the materials of the second material layer and the third spacer wall comprise oxides.

5. The method of claim 4, wherein in the step of patterning the conductive pad layer, a portion of the first gap wall, a portion of the second gap wall layer, and a portion of the third gap wall located on one of the opposite side walls of each bit line structure are also removed to form a first gap wall structure on one of the opposite side walls of each bit line structure and a second gap wall structure on the other of the opposite side walls of each bit line structure.

6. The method according to claim 5, wherein the top surface of the first gap wall structure is lower than the top surface of the second gap wall structure.

7. The method of claim 6, wherein in the step of patterning the conductive pad layer, a portion of each of the top cover layers is also removed, such that the top cover layer is formed to include: The first part has a top surface that is at the same level as the top surface of the first spacer wall structure; as well as The second part has a top surface located at a lower level from the top surface of the second gap wall structure.

8. The method according to claim 6, further comprising: An insulating pattern is formed in the opening that separates the plurality of conductive pad structures, wherein the insulating pattern is in contact with the first gap wall structure.

9. The method according to claim 8, further comprising: Before forming the insulating pattern, a portion of the second material layer and the third spacer wall in the first spacer wall structure exposed by the opening is removed to form a recess.

10. The method of claim 9, wherein in the step of forming the insulating pattern, the insulating pattern is formed above the recess but does not fill the recess, such that an air gap is formed in the recess.

11. The method of claim 8, wherein each of the conductive pad structures comprises: The upper portion has a top surface at the same level as the top surface of the insulating pattern; as well as The lower portion has a top surface that is at the same level as the top surface of the first gap wall structure.

Images