Semiconductor memory device

Abstract

A semiconductor memory device includes a first wire, a first bit line spaced apart from the first wire in a first direction, a second bit line spaced apart from the first wire in the first direction, a first word line disposed between the first wire and each of the first bit line and the second bit line, a first channel pattern including a horizontal portion disposed between the first word line and the first wire and a first vertical portion, the horizontal portion of the first channel pattern connected to the first wire, and the first vertical portion of the first channel pattern connected to the first bit line, and a second channel pattern disposed between the first channel pattern and the first word line and connected to the second bit line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0011298, filed on January 24, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more specifically, to a semiconductor memory device including a vertical channel transistor (VCT) and a method of manufacturing the semiconductor memory device. Background Technology

[0004] To meet consumer demand for low-cost, high-performance devices, there is a desire to increase the integration density of semiconductor memory devices. For semiconductor memory devices, integration density is a key factor determining product cost, making higher integration densities particularly desirable.

[0005] For two-dimensional (2D) or planar semiconductor memory devices, integration density is determined by the area occupied by a single memory cell, which is significantly affected by the level of fine patterning technology. However, achieving finer patterning in 2D semiconductor memory devices requires extremely expensive equipment. As a result, while integration density has improved, it remains limited. Therefore, semiconductor memory devices employing vertical channel transistors (VCTs) have been proposed, where the channel extends vertically relative to the upper surface of the substrate. Summary of the Invention

[0006] One object of this disclosure is to provide a semiconductor memory device with improved integration density and electrical characteristics.

[0007] Another object of this disclosure is to provide a method for manufacturing a semiconductor memory device having provided integration density and electrical characteristics.

[0008] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not expressly stated will be clearly understood by those skilled in the art based on the following description.

[0009] According to one aspect of this disclosure, a semiconductor memory device includes: a first conductor on a substrate; a first bit line spaced apart from the first conductor in a first direction and extending in a second direction; a second bit line spaced apart from the first conductor in the first direction, extending in the second direction, and spaced apart from the first bit line in a third direction; a first word line disposed between the first conductor and each of the first bit line and the second bit line, and extending in a third direction; a first channel pattern including a horizontal portion extending in the second direction and disposed between the first word line and the first conductor, and a first vertical portion extending in the first direction, wherein the horizontal portion of the first channel pattern is connected to the first conductor, and wherein the first vertical portion of the first channel pattern is connected to the first bit line; and a second channel pattern disposed between the first channel pattern and the first word line and connected to the second bit line.

[0010] According to one aspect of this disclosure, a semiconductor memory device includes: a conductor on a substrate; a first bit line spaced apart from the conductor in a first direction and extending in a second direction; a second bit line spaced apart from the conductor in the first direction, extending in the second direction, and spaced apart from the first bit line in a third direction; a first word line disposed between the conductor and each of the first and second bit lines, and extending in a third direction; a first channel pattern disposed between the first word line and the conductor, and connected to the first bit line and the conductor; and a second channel pattern disposed between the first channel pattern and the first word line, and connected to the second bit line. The first word line includes a first sidewall and a second sidewall opposite to each other in the second direction. The second channel pattern includes a first vertical portion extending along the first sidewall of the first word line, a second vertical portion extending along the second sidewall of the first word line, and a horizontal portion including a first end connected to the first vertical portion and a second end connected to the second vertical portion.

[0011] According to one aspect of this disclosure, a semiconductor memory device includes: a wire disposed on a substrate and extending in a first direction; a first bit line spaced apart from the wire in a second direction and extending in the first direction; a second bit line spaced apart from the wire in the second direction, extending in the first direction, and spaced apart from the first bit line in a third direction; a first channel pattern including a horizontal portion extending in the first direction, a first vertical portion extending in the second direction, and a second vertical portion extending in the second direction, wherein the first vertical portion and the second vertical portion of the first channel pattern are respectively directly connected to opposite ends of the horizontal portion of the first channel pattern, wherein the horizontal portion of the first channel pattern is connected to the wire, and wherein the first vertical portion and the second vertical portion of the first channel pattern are connected to the first bit line; a first word line disposed between the first vertical portion and the second vertical portion of the first channel pattern; a second word line disposed between the first word line and the second vertical portion of the first channel pattern; and a second channel pattern disposed between the first channel pattern and each of the first word line and the second word line, and connected to the second bit line.

[0012] According to one aspect of this disclosure, a method of manufacturing a semiconductor memory device is provided, comprising: forming a wire; forming a first molding pattern on the wire, the first molding pattern including a first channel trench extending in a first direction; forming a pre-lower channel pattern extending along the sidewalls and bottom surface of the first channel trench and extending in the first direction; forming a channel cutting pattern within the first molding pattern to separate the pre-lower channel pattern, thereby forming a second molding pattern defining a second channel trench, wherein the lower channel pattern separated by the channel cutting pattern is formed within the second channel trench; forming a first pre-upper channel pattern on the lower channel pattern, wherein the first pre-upper channel pattern is formed along the sidewalls and bottom surface of the second channel trench; removing a portion of the second molding pattern and a portion of the first pre-upper channel pattern to form a word line trench extending in the first direction, wherein the second pre-upper channel pattern is formed during the formation of the word line trench; forming a first channel trench extending in the first direction within the word line trench. The system comprises: a first character line molding spacer and a second character line molding spacer, wherein the first character line molding spacer and the second character line molding spacer are spaced apart in a second direction perpendicular to the first direction; a character line isolation pattern extending in the first direction is formed between the first character line molding spacer and the second character line molding spacer; the first character line molding spacer and the second character line molding spacer are removed to form a first character line groove and a second character line groove; a first character line and a second character line are formed inside the first character line groove and the second character line groove; a portion of the character line isolation pattern is removed to form a channel hole between the first character line and the second character line, wherein the channel hole exposes a portion of a second pre-upper channel pattern; a third pre-upper channel pattern is formed inside the channel hole and in contact with the second pre-upper channel pattern to form an upper channel pattern on a lower channel pattern; and a first character line connected to the lower channel pattern and a second character line connected to the upper channel pattern are formed on the lower channel pattern and the upper channel pattern.

[0013] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become apparent from the following description. Attached Figure Description

[0014] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0015] Figure 1 These are circuit diagrams of semiconductor memory devices according to some embodiments.

[0016] Figure 2 and Figure 3 This is a layout diagram of a semiconductor memory device according to some embodiments.

[0017] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 They are along Figure 3 The cross-sectional view of lines AA, BB, CC, DD and EE.

[0018] Figure 9 yes Figure 4 A magnified cross-sectional view of part P in the diagram.

[0019] Figure 10 It shows Figure 2 and Figure 3 The diagram shows the planar shape of the upper connecting channel pattern.

[0020] Figure 11 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0021] Figure 12 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0022] Figure 13 and Figure 14 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0023] Figure 15 and Figure 16 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0024] Figure 17 and Figure 18 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0025] Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0026] Figure 24 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0027] Figure 25 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0028] Figure 26 , Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 , Figure 35 , Figure 36 , Figure 37 , Figure 38 , Figure 39 , Figure 40 , Figure 41 , Figure 42 , Figure 43 , Figure 44 , Figure 45 , Figure 46 , Figure 47 , Figure 48 , Figure 49 , Figure 50 , Figure 51 , Figure 52 and Figure 53 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0029] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0030] Figure 1 These are circuit diagrams of semiconductor memory devices according to some embodiments.

[0031] refer to Figure 1 The memory cell MC may include a write transistor WTR and a read transistor RTR connected to the write transistor WTR. Although not shown, a semiconductor memory device according to some embodiments may include a plurality of memory cells MC arranged in a two-dimensional (2D) or three-dimensional (3D) manner.

[0032] The write transistor WTR may include a word line WL connected to the gate terminal of the write transistor WTR and a write bit line WBL connected to the source terminal of the write transistor WTR. The read transistor RTR may include a word line WL connected to the gate terminal of the read transistor RTR and a read bit line RBL connected to the drain terminal of the read transistor RTR. The word line WL may be connected to the gate terminals of both the read transistor RTR and the write transistor WTR. The word line WL may be shared by both the write transistor WTR and the read transistor RTR. The source terminal of the read transistor RTR may be connected to ground, but is not limited thereto. Conversely, as shown, the read transistor RTR may include a read word line connected to the source terminal of the read transistor RTR.

[0033] The drain terminal of the write transistor WTR can be connected to the gate terminal of the read transistor RTR. The drain terminal of the write transistor WTR can be referred to as the storage node gate SN_G. For example, the storage node gate SN_G can be used as the gate of the read transistor RTR during a read operation. The storage node gate SN_G can be used to store charge.

[0034] In one example, programming the memory cell MC can be performed as follows: A voltage is applied to the word line WL and the write bit line WBL, turning on the write transistor WTR. As the write transistor WTR is turned on, an electrical signal (or charge) can be transferred (or charged) to the memory node gate SN_G. Therefore, the electrical signal from the write bit line WBL can be stored in the memory node gate SN_G, causing a change in the threshold voltage of the read transistor RTR.

[0035] When a voltage is applied to the word line WL, this voltage can be applied to the gate terminal of the read transistor RTR. During the programming operation of the memory cell MC, it is necessary to prevent electrical signals from moving into the channel region of the read transistor RTR. During the programming operation of the memory cell MC, a ground voltage can be applied to the read bit line RBL connected to the drain terminal of the read transistor RTR to prevent a potential difference from forming between the drain and source terminals of the read transistor RTR.

[0036] In one example, a read operation of the memory cell MC can be performed as follows: The write transistor WTR can be turned off, and a voltage can be applied to the read bit line RBL. By the current flowing through the read transistor RTR, the electrical signal stored in the gate SN_G of the memory node can be read through the read bit line RBL.

[0037] Semiconductor memory devices that include a memory cell MC can also be referred to as dual-transistor zero-capacitor (2T-OC) memory devices. According to some embodiments, semiconductor memory devices may not include a separate capacitor for storing charge.

[0038] Therefore, since the area required to form capacitors can be reduced, semiconductor memory devices according to some embodiments can achieve high integration and reduce manufacturing costs. Furthermore, by omitting the formation of capacitors, memory cell arrays comprising multiple memory cells MC can be stacked vertically. This enables semiconductor memory devices according to some embodiments to achieve high integration.

[0039] Furthermore, since the write transistor WTR and the read transistor RTR share a single word line WL, the number of wires formed in the memory cell MC can be reduced. As a result, the area required to form the memory cell array can be reduced. Therefore, a high degree of integration of the semiconductor memory device according to some embodiments can be achieved.

[0040] According to some embodiments, a semiconductor memory device including a 2T-0C memory device may include a vertical channel transistor (VCT). VCT may refer to the direction in which the channel of the transistor is perpendicular to the upper surface of the substrate 100. Figure 4 The structure extending from the third direction (DR3, i.e., the vertical direction) in the middle.

[0041] Figure 2 and Figure 3 This is a layout diagram of a semiconductor memory device according to some embodiments. Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 They are along Figure 3 The cross-sectional view of lines AA, BB, CC, DD and EE. Figure 9 yes Figure 4 A magnified cross-sectional view of part P in the diagram. Figure 10 It shows Figure 2 and Figure 3 The diagram shows the planar shape of the upper connecting channel pattern.

[0042] Specifically, Figure 2 The structure of a semiconductor memory device, excluding the first bit line 130 and the second bit line 140, is shown according to some embodiments. Figure 3 The structure of a semiconductor memory device, excluding wire 110, is shown according to some embodiments.

[0043] refer to Figures 1 to 10 According to some embodiments, a semiconductor memory device may include a wire 110, a lower connecting channel pattern CHB (i.e., a first channel pattern), an upper connecting channel pattern CHU (i.e., a second channel pattern), a first word line 120, a second word line 125, a first bit line 130, and a second bit line 140.

[0044] In one example, substrate 100 may be a silicon substrate, or may include other materials (e.g., silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide). In another example, substrate 100 may include a ceramic substrate, a quartz substrate, or a glass substrate. In yet another example, substrate 100 may include a flexible plastic material (e.g., polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), and polyester).

[0045] The lower insulating film 105 may be disposed on the substrate 100. The lower insulating film 105 may include an insulating material. Conversely, the lower insulating film 105 may not be disposed on the substrate 100. For example, the lower insulating film 105 may be omitted.

[0046] The wire 110 can be disposed on the substrate 100. The wire 110 can be disposed on the lower insulating film 105.

[0047] The conductors 110 may each extend in a first direction DR1 (i.e., a first horizontal direction). The conductors 110 may be adjacent to each other in a second direction DR2 (i.e., a second horizontal direction).

[0048] The conductor 110 may each include a first surface and a second surface opposite to each other on a third-direction DR3. The second surface of the conductor 110 may face the substrate 100 (i.e., may be adjacent to the substrate 100).

[0049] Here, the first direction DR1 and the second direction DR2 can be perpendicular to the third direction DR3. The first direction DR1 can intersect with the second direction DR2. For example, the third direction DR3 can be the thickness direction of the substrate 100. The first direction DR1 and the second direction DR2 can be parallel to the upper surface of the substrate 100.

[0050] In one example, wire 110 can be connected to ground voltage. Wire 110 can also be connected to the source terminal of the read transistor RTR.

[0051] In a semiconductor memory device according to some embodiments, the conductor 110 may include a first conductor 110_1 and a second conductor 110_2. The first conductor 110_1 and the second conductor 110_2 may each extend in a first direction DR1. The first conductor 110_1 and the second conductor 110_2 may be spaced apart in a second direction DR2. By connecting adjacent lower interconnect channel patterns CHB on the second direction DR2 to different conductors 110, the sensing margin of the memory cell array can be improved.

[0052] like Figure 7As shown, the width of the conductor 110 in the second direction DR2 increases from the substrate 100 toward the horizontal portion CHB_H of the downward connecting channel pattern CHB in the third direction DR3, but is not limited thereto.

[0053] The wire 110 may include a conductive material. The wire 110 may include at least one of, for example, a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal. The wire 110 is shown as a monolayer film, but is not limited thereto.

[0054] In semiconductor memory devices according to some embodiments, the 2D material may be a metallic material and / or a semiconductor material. The 2D material may include 2D allotropes or 2D compounds. For example, the 2D material may include graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), tungsten disulfide (WS2), copper disulfide (CuS2), copper diselenide (CuSe2), or combinations thereof, but is not limited thereto. These 2D materials are listed by way of example only, and the 2D materials that may be included in semiconductor memory devices according to some embodiments are not limited thereto.

[0055] A molded insulating pattern 160 may be disposed on the conductor 110. The molded insulating pattern 160 may be disposed on a first surface of the conductor 110. Conversely, an etch stop film may be disposed between the molded insulating pattern 160 and the conductor 110.

[0056] The molded insulating pattern 160 may include an insulating material. The molded insulating pattern 160 is shown as a single-layer film, but is not limited thereto. If an etch stop film is disposed between the molded insulating pattern 160 and the conductor 110, the etch stop film may include an insulating material. The etch stop film may include a material having etch selectivity relative to the molded insulating pattern 160.

[0057] The molded insulating pattern 160 may include a first surface and a second surface opposite to each other on a third-direction DR3. The second surface of the molded insulating pattern 160 may face the conductor 110 (i.e., may be adjacent to the conductor 110). For example, the first surface of the molded insulating pattern 160 may be the upper surface of the molded insulating pattern 160. The second surface of the molded insulating pattern 160 may be the bottom surface of the molded insulating pattern 160.

[0058] The molded insulating pattern 160 may include a plurality of word line grooves (WLTs). Each word line groove (WLT) may extend radially or longitudinally in the second direction DR2. Adjacent word line grooves (WLTs) may be spaced apart in the first direction DR1.

[0059] The word line trench (WLT) may intersect with the conductor 110. In a semiconductor memory device according to some embodiments, the word line trench (WLT) may expose multiple conductors 110. For example, the word line trench (WLT) may expose a first conductor 110_1 and a second conductor 110_2.

[0060] The bottom surface of the word line trench WLT may be defined by the conductor 110, the lower insulating film 105, and the molded insulating pattern 160. The sidewalls of each word line trench WLT may be defined by the molded insulating pattern 160.

[0061] Each word line groove (WLT) may include a first portion (WLT_1) and a second portion (WLT_2). Within each word line groove (WLT), the first portion (WLT_1) and the second portion (WLT_2) may be alternately defined along a second direction (DR2). For example, a lower connecting channel pattern (CHB) and an upper connecting channel pattern (CHU) (described later) may be provided in the first portion (WLT_1) of the word line groove (WLT). The lower connecting channel pattern (CHB) and the upper connecting channel pattern (CHU) may not be provided in the second portion (WLT_2) of the word line groove (WLT).

[0062] The width W11 of the first portion WLT_1 of the word line groove WLT in the first direction DR1 may be different from the width W12 of the second portion WLT_2 of the word line groove WLT in the first direction DR1. For example, the width W11 of the first portion WLT_1 of the word line groove WLT may be greater than the width W12 of the second portion WLT_2 of the word line groove WLT.

[0063] The height of the bottom surface of the first portion WLT_1 of the word line trench WLT, relative to the upper surface of the substrate 100, can be less than the height of the bottom surface of the second portion WLT_2 of the word line trench WLT. For example, the height of the bottom surface of the first portion WLT_1, relative to the upper surface of the substrate 100, can be lower than the height of the bottom surface of the second portion WLT_2.

[0064] A lower connection channel pattern CHB may be disposed on the conductor 110. For example, the lower connection channel pattern CHB may be disposed on a first surface of the conductor 110. The lower connection channel pattern CHB may be connected to the conductor 110. For example, the lower connection channel pattern CHB may be electrically connected to the conductor 110. In an embodiment, the lower connection channel pattern CHB may contact the conductor 110. As used herein, the term “contact” or “in contact with” refers to a direct connection (i.e., physical contact) unless the context otherwise indicates.

[0065] In a semiconductor memory device according to some embodiments, a plurality of lower interconnect channel patterns CHB spaced apart from each other on a first direction DR1 can be connected to a single conductor 110 extending longitudinally on the first direction DR1.

[0066] The lower connecting channel pattern CHB can be disposed within the word line groove WLT extending along the second direction DR2. Multiple lower connecting channel patterns CHB can be disposed within a single word line groove WLT, spaced apart along the second direction DR2. For example, the lower connecting channel patterns CHB can be arranged two-dimensionally along the intersecting first direction DR1 and second direction DR2.

[0067] The lower connection channel pattern CHB may include a first lower connection channel pattern CHB1 and a second lower connection channel pattern CHB2 spaced apart in the second direction DR2. For example, the first lower connection channel pattern CHB1 may be connected to the first conductor 110_1, but may not be connected to the second conductor 110_2. The second lower connection channel pattern CHB2 may be connected to the second conductor 110_2, but may not be connected to the first conductor 110_1. For example, the first lower connection channel pattern CHB1 may contact the first conductor 110_1, but not the second conductor 110_2. The second lower connection channel pattern CHB2 may contact the second conductor 110_2, but not the first conductor 110_1.

[0068] The lower connection channel pattern CHB can extend along the sidewalls and bottom surface of the word line trench WLT. For example, the lower connection channel pattern CHB can contact the molded insulating pattern 160. In a semiconductor memory device according to some embodiments, the lower connection channel pattern CHB can have a substantially "U" shape in a cross-section taken along the first direction DR1.

[0069] The lower connecting channel pattern CHB can each include a horizontal portion CHB_H and multiple vertical portions CHB_V. The multiple vertical portions CHB_V can include a first vertical portion CHB_V1 and a second vertical portion CHB_V2 spaced apart on the first direction DR1.

[0070] The horizontal portion CHB_H of the lower connecting channel pattern CHB can extend along the bottom surface of the letter line groove WLT. Figure 4 , Figure 5 and Figure 9 In the middle, the horizontal portion CHB_H of the lower connecting channel pattern CHB can extend in the first direction DR1. The horizontal portion CHB_H of the lower connecting channel pattern CHB can be connected to the conductor 110. For example, the horizontal portion CHB_H can contact the conductor 110.

[0071] The first vertical portion CHB_V1 and the second vertical portion CHB_V2 can be disposed on the sidewall of the corresponding word line groove WLT. The first vertical portion CHB_V1 and the second vertical portion CHB_V2 can extend along the sidewall of the corresponding word line groove WLT.

[0072] The first vertical portion CHB_V1 and the second vertical portion CHB_V2 can each protrude from the horizontal portion CHB_H of the corresponding lower connecting channel pattern CHB on the third direction DR3. The first vertical portion CHB_V1 and the second vertical portion CHB_V2 can each extend on the third direction DR3. The first vertical portion CHB_V1 and the second vertical portion CHB_V2 can each be directly connected to the horizontal portion CHB_H of the corresponding lower connecting channel pattern CHB.

[0073] For example, the vertical portion CHB_V of the lower connecting channel pattern CHB can each include an extension portion CHB_VP1 extending in the third direction DR3 and an extended portion CHB_VP2 extending in the first direction DR1. The extended portion CHB_VP2 can be located at the upper end of its corresponding vertical portion CHB_V. The extension portion CHB_VP1 can be located between the extended portion CHB_VP2 and the corresponding horizontal portion CHB_H of the lower connecting channel pattern CHB. The width of the extended portion CHB_VP2 of the vertical portion CHB_V of the lower connecting channel pattern CHB in the first direction DR1 can be greater than the width of the extension portion CHB_VP1 of the vertical portion CHB_V of the lower connecting channel pattern CHB in the first direction DR1. For example, in a cross-sectional view, the vertical portion CHB_V of the lower connecting channel pattern CHB can have an "L" shape when viewed from the cross-sectional perspective.

[0074] Conversely, the vertical portion CHB_V of the lower connecting channel pattern CHB may not include the extended portion CHB_VP2.

[0075] The lower connecting channel pattern CHB can each be used as a read transistor for two adjacent memory cells MC. Figure 1 The middle part is the channel region of the read transistor RTR. For example, the first vertical portion CHB_V1 of the lower connected channel pattern CHB can be used as the channel region of the read transistor RTR of the first memory cell MC, and can also be used as the channel region of the read transistor RTR of the second memory cell adjacent to the first memory cell MC. For example, in the first portion WLT_1 of the word line trench WLT, each of the two adjacent memory cells corresponds to Figure 1 The memory cell MC. In each of two adjacent memory cells, a single word line is formed to drive... Figure 1 The memory cell MC has a write transistor WTR and a read transistor RTR, and two adjacent memory cells share a write bit line WBL corresponding to the first bit line 130.

[0076] The upper connecting channel pattern CHU can be set on the lower connecting channel pattern CHB. The upper connecting channel pattern CHU can be set within the space defined by the lower connecting channel pattern CHB. The upper connecting channel pattern CHU can be spaced apart from the lower connecting channel pattern CHB on the third direction DR3. The upper connecting channel pattern CHU can overlap with the lower connecting channel pattern CHB on the third direction DR3.

[0077] The lower connecting channel pattern CHB can be positioned on the third-direction DR3 between the first word line 120 and the conductor 110, and between the second word line 125 and the conductor 110. The lower connecting channel pattern CHB can also be positioned on the third-direction DR3 between the upper connecting channel pattern CHU and the conductor 110. The horizontal portion CHB_H of the lower connecting channel pattern CHB can also be positioned on the third-direction DR3 between the upper connecting channel pattern CHU and the conductor 110.

[0078] The upper connecting channel pattern CHU can be set on the third-party DR3 between the lower connecting channel pattern CHB and the first letter line 120, and between the lower connecting channel pattern CHB and the second letter line 125.

[0079] The upper connecting channel pattern CHU may each include a horizontal portion CHU_H and a plurality of vertical portions CHU_V. In a semiconductor memory device according to some embodiments, the plurality of vertical portions CHU_V may include a first vertical portion CHU_V1, a second vertical portion CHU_V2, and a third vertical portion CHU_V3 spaced apart in a first direction DR1.

[0080] The horizontal portion CHU_H of the upper connecting channel pattern CHU can extend along the horizontal portion CHB_H of the lower connecting channel pattern CHB. Figure 4 , Figure 5 and Figure 9 In the middle, the horizontal portion of the upper connecting channel pattern CHU, CHU_H, can extend in the first direction DR1.

[0081] The first vertical portion CHU_V1, the second vertical portion CHU_V2, and the third vertical portion CHU_V3 can each protrude from the horizontal portion CHU_H of the corresponding upper connecting channel pattern CHU on the third-direction DR3. The first vertical portion CHU_V1, the second vertical portion CHU_V2, and the third vertical portion CHU_V3 can each extend on the third-direction DR3. The first vertical portion CHU_V1 and the second vertical portion CHU_V2 can each be directly connected to the horizontal portion CHU_H of the corresponding upper connecting channel pattern CHU. The third vertical portion CHU_V3 can contact the horizontal portion CHU_H of the corresponding upper connecting channel pattern CHU.

[0082] The first vertical portion CHU_V1 of the upper connecting channel pattern CHU can extend along the first vertical portion CHB_V1 of the lower connecting channel pattern CHB. In other words, the first vertical portion CHB_V1 of the lower connecting channel pattern CHB can extend along the first vertical portion CHU_V1 of the upper connecting channel pattern CHU.

[0083] The second vertical portion CHU_V2 of the upper connecting channel pattern CHU can extend along the second vertical portion CHB_V2 of the lower connecting channel pattern CHB. The third vertical portion CHU_V3 of the upper connecting channel pattern CHU can be disposed between the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. The third vertical portion CHU_V3 of the upper connecting channel pattern CHU can be spaced apart from the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU in the first direction DR1.

[0084] exist Figure 10 In the diagram, the width W21 of the second vertical portion CHU_V2 of the upper connecting channel pattern CHU in the second direction DR2 is shown to be greater than the width W23 of the third vertical portion CHU_V3 of the upper connecting channel pattern CHU in the second direction DR2, but is not limited thereto. Additionally, the width W22 of the second vertical portion CHU_V2 of the upper connecting channel pattern CHU in the first direction DR1 is shown to be greater than the width W24 of the third vertical portion CHU_V3 of the upper connecting channel pattern CHU in the first direction DR1, but is not limited thereto.

[0085] The upper connection channel pattern CHU can each be used as the channel region of the write transistor WTR of the two memory cells MC. The third vertical portion CHU_V3 of the upper connection channel pattern CHU and the horizontal portion CHU_H of the upper connection channel pattern CHU located below the first word line 120 can be used as the channel region of the write transistor WTR of the first memory cell, and the third vertical portion CHU_V3 of the upper connection channel pattern CHU and the horizontal portion CHU_H of the upper connection channel pattern CHU located below the second word line 125 can be used as the channel region of the write transistor WTR of the second memory cell adjacent to the first memory cell.

[0086] The first vertical portion CHU_V1 of the upper connection channel pattern CHU can be the drain terminal of the write transistor WTR of the first memory cell. The first vertical portion CHU_V1 of the upper connection channel pattern CHU can also be used as the gate of the read transistor RTR of the first memory cell. The second vertical portion CHU_V2 of the upper connection channel pattern CHU can be the drain terminal of the write transistor WTR of the second memory cell. For example, the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connection channel pattern CHU can correspond to... Figure 1 The gate SN_G of the storage node.

[0087] The lower connecting channel pattern CHB and the upper connecting channel pattern CHU may include one or a combination of silicon, germanium, silicon-germanium, III-V compound semiconductors, oxide semiconductor materials, 2D materials.

[0088] The silicon, germanium, or silicon-germanium that may be included in the lower connecting channel pattern CHB and / or the upper connecting channel pattern CHU may be polycrystalline or monocrystalline.

[0089] III-V compound semiconductors may include, for example, binary, ternary, or quaternary compounds formed by combining at least one group III element (e.g., aluminum (Al), gallium (Ga), and indium (In)) with a group V element (e.g., phosphorus (P), arsenic (As), and antimony (Sb)).

[0090] Oxide semiconductor materials can include, for example, metal oxides. In one example, the oxide semiconductor material can be an amorphous metal oxide. In another example, the oxide semiconductor material can be a polycrystalline metal oxide film. In yet another example, the oxide semiconductor material can be a combination of amorphous metal oxides and polycrystalline metal oxides. In yet another example, the oxide semiconductor material can be a c-axis oriented crystalline (CAAC) metal oxide.

[0091] Oxide semiconductor materials may include, for example, one of the following: indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide. In-Nd-Zn based oxides, In-Sm-Zn based oxides, In-Eu-Zn based oxides, In-Gd-Zn based oxides, In-Tb-Zn based oxides, In-Dy-Zn based oxides, In-Ho-Zn based oxides, In-Er-Zn based oxides, In-Tm-Zn based oxides, In-Yb-Zn based oxides, In-Lu-Zn ​​based oxides, In-Sn-Ga-Zn based oxides, In-Hf-Ga-Zn based oxides, In-Al-Ga-Zn based oxides, In-Sn-Al-Zn based oxides, In-Sn-Hf-Zn based oxides, and In-Hf-Al-Zn based oxides, but not limited to these.

[0092] In-Ga-Zn based oxides refer to oxides containing In, Ga, and Zn as the main components in any ratio of In, Ga, and Zn. For example, oxide semiconductor materials can include indium gallium zinc oxide (IGZO, In x Ga y Zn z IGZO with an In:Ga:Zn ratio of 1:1:1 (In:Ga:Zn=1:1:1) can be an In-Ga-Zn based oxide. Ga-rich IGZO with a higher Ga ratio and a lower In ratio compared to IGZO (In:Ga:Zn=1:1:1) can also be an In-Ga-Zn based oxide. Similarly, In-rich IGZO with a higher In ratio and a lower Ga ratio compared to IGZO (In:Ga:Zn=1:1:1) can also be an In-Ga-Zn based oxide.

[0093] The above description of oxide semiconductor materials uses IGZO as an example, but is not limited to this. It should be noted that the above description applies to oxide semiconductor materials including metal oxides having three or more components. Additionally, when the oxide semiconductor material includes In-Ga-Zn based oxides, it may also include one or more doped metal elements in addition to In, Ga, and Zn.

[0094] In one example, the materials of the lower connection channel pattern CHB and the upper connection channel pattern CHU can be the same. In another example, the lower connection channel pattern CHB and the upper connection channel pattern CHU can include different materials. Depending on whether the performance or reliability of the read transistor RTR and / or write transistor WTR is to be enhanced, various combinations of materials included in the lower connection channel pattern CHB and / or the upper connection channel pattern CHU can be used.

[0095] The first letter line 120 and the second letter line 125 can be disposed on the upper connecting channel pattern CHU. The first letter line 120 and the second letter line 125 can be disposed within the letter line groove WLT.

[0096] The first character line 120 and the second character line 125 may each extend longitudinally in the second direction DR2. The first character line 120 may be spaced apart from the second character line 125 in the first direction DR1.

[0097] The first letter line 120 and the second letter line 125 can be positioned on the horizontal portion CHB_H of the lower connecting channel pattern CHB. The first letter line 120 and the second letter line 125 can be positioned between the first vertical portion CHB_V1 and the second vertical portion CHB_V2 of the lower connecting channel pattern CHB.

[0098] The first character line 120 and the second character line 125 can be positioned on the horizontal portion CHU_H of the upper connecting channel pattern CHU. The first character line 120 can be positioned between the first vertical portion CHU_V1 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU. The second character line 125 can be positioned between the second vertical portion CHU_V2 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU.

[0099] The third vertical portion CHU_V3 of the upper connecting channel pattern CHU can be positioned between the first character line 120 and the second character line 125. The first vertical portion CHU_V1 of the upper connecting channel pattern CHU can be positioned between the first character line 120 and the first vertical portion CHB_V1 of the lower connecting channel pattern CHB. The second vertical portion CHU_V2 of the upper connecting channel pattern CHU can be positioned between the second character line 125 and the second vertical portion CHB_V2 of the lower connecting channel pattern CHB. The horizontal portion CHU_H of the upper connecting channel pattern CHU can be positioned between the first character line 120 and the horizontal portion CHB_H of the lower connecting channel pattern CHB, and between the second character line 125 and the horizontal portion CHB_H of the lower connecting channel pattern CHB.

[0100] The first character line 120 may each include a first sidewall 120_SW1 and a second sidewall 120_SW2 that are opposite to each other in the first direction DR1. The second character line 125 may each include a first sidewall 125_SW1 and a second sidewall 125_SW2 that are opposite to each other in the first direction DR1. The second sidewall 120_SW2 of the first character line 120 may face the second sidewall 125_SW2 of the second character line 125. For example, the second sidewall 120_SW2 of the first character line 120 may be adjacent to the second sidewall 125_SW2 of the second character line 125.

[0101] The first vertical portion CHU_V1 of the upper connecting channel pattern CHU can extend along the first sidewall 120_SW1 of the first character line 120 on the third-direction DR3. The second vertical portion CHU_V2 of the upper connecting channel pattern CHU can extend along the first sidewall 125_SW1 of the second character line 125 on the third-direction DR3. The third vertical portion CHU_V3 of the upper connecting channel pattern CHU can extend along the second sidewall 120_SW2 of the first character line 120 and the second sidewall 125_SW2 of the second character line 125 on the third-direction DR3. The third vertical portion CHU_V3 of the upper connecting channel pattern CHU can be located between the second sidewall 120_SW2 of the first character line 120 and the second sidewall 125_SW2 of the second character line 125.

[0102] The first character line 120 and the second character line 125 can correspond to Figure 1 The word line WL connects to the gate terminals of both the write transistor WTR and the read transistor RTR. For example, in Figure 9 The image shows two memory cells in the same word line trench (e.g., the first part of the word line trench WLT, WLT_1). Figure 9 Each storage unit corresponds to Figure 1 The memory cell MC. The word lines of the write transistor WTR and read transistor RTR are merged into one of the first word line 120 of the first memory cell and the second word line 125 of the second memory cell. The first word line 120 can operate as the word line of the write transistor WTR and read transistor RTR of the first memory cell. The second word line 125 can operate as the word line of the write transistor WTR and read transistor RTR of the second memory cell. The first bit line 130 connected to the upper connection channel pattern CHU can be used as the write bit line WBL and can be shared by the two memory cells. The second bit line 140 connected to the first vertical portion CHB_V1 of the lower connection channel pattern CHB can be used as the read bit line RBL of the first memory cell, and the second bit line 140 connected to the second vertical portion CHB_V2 of the lower connection channel pattern CHB can be used as the read bit line RBL of the second memory cell. In order to improve the margin of read operation, such as Figure 17As shown, the second bit line 140 can be separated into a first sub-bit line 140_1 and a second sub-bit line 140_2, which are respectively connected to the first vertical portion CHB_V1 of the lower connecting channel pattern CHB and the second vertical portion CHB_V2 of the lower connecting channel pattern CHB.

[0103] The first word line 120 and the second word line 125 may each comprise a conductive material (e.g., at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal). The first word line 120 and the second word line 125 are shown as monolayer films, but are not limited thereto.

[0104] The character line capping pattern 128 can be disposed on the first character line 120 and the second character line 125. The character line capping pattern 128 can be disposed between the first vertical portion CHU_V1 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU, and between the second vertical portion CHU_V2 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU. The character line capping pattern 128 may include insulating material.

[0105] like Figure 6 As shown, the word line isolation pattern 129 can be disposed between the first word line 120 and the second word line 125. The word line isolation pattern 129 can also be disposed on the molded insulating pattern 160. Figure 7 As shown, the word line isolation pattern 129 can be disposed between the third vertical portions CHU_V3 of adjacent upper connecting channel patterns CHU in the second direction DR2. The word line isolation pattern 129 may include insulating material.

[0106] The first gate insulating pattern GOX1 may be disposed between the lower connecting channel pattern CHB and the upper connecting channel pattern CHU. The first gate insulating pattern GOX1 may extend along the space between the lower connecting channel pattern CHB and the upper connecting channel pattern CHU. The first gate insulating pattern GOX1 is shown extending along the upper surface of the molded insulating pattern 160, but is not limited thereto.

[0107] The second gate insulating pattern GOX2 can be disposed between the upper connecting channel pattern CHU and the first word line 120, and between the upper connecting channel pattern CHU and the second word line 125. The second gate insulating pattern GOX2 can extend along the space between the upper connecting channel pattern CHU and the first word line 120. The second gate insulating pattern GOX2 can also extend along the space between the upper connecting channel pattern CHU and the second word line 125. The second gate insulating pattern GOX2 is shown to also extend along the space between the word line capping pattern 128 and the vertical portion CHU_V of the upper connecting channel pattern CHU, but is not limited thereto.

[0108] The first gate insulating pattern GOX1 and the second gate insulating pattern GOX2 may each comprise silicon oxide, silicon oxynitride, a high-k dielectric material with a dielectric constant greater than that of silicon oxide, or a combination thereof. The high-k dielectric material may comprise a metal oxide or a metal oxynitride. For example, the high-k dielectric material may comprise at least one of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0109] The upper insulating film 170 can be disposed on the lower connecting channel pattern CHB and the upper connecting channel pattern CHU. The upper insulating film 170 can be disposed on the upper surface of the molded insulating pattern 160. The upper insulating film 170 may include insulating material.

[0110] The first line 130 and the second line 140 can each be spaced apart from the conductor 110 on a third-direction DR3. The first line 130 and the second line 140 can be disposed on the lower connecting channel pattern CHB and the upper connecting channel pattern CHU. The first line 130 and the second line 140 can be disposed on the first word line 120 and the second word line 125. The first word line 120 and the second word line 125 can be disposed between the first line 130 and the conductor 110, and between the second line 140 and the conductor 110.

[0111] The first bit line 130 and the second bit line 140 may each extend in a first direction DR1. The first bit line 130 may be spaced apart from the second bit line 140 in a second direction DR2. In a semiconductor memory device according to some embodiments, a single first bit line 130 and a single second bit line 140 may be disposed on a lower interconnect channel pattern CHB arranged in the first direction DR1.

[0112] The first line 130 can be connected to the upper connecting channel pattern CHU. For example, the first line 130 can be connected to the third vertical portion CHU_V3 of the upper connecting channel pattern CHU.

[0113] The second bit line 140 can be connected to the lower interconnect channel pattern CHB. For example, the second bit line 140 can be connected to the first vertical portion CHB_V1 and the second vertical portion CHB_V2 of the lower interconnect channel pattern CHB. By connecting each second bit line 140 to the first vertical portion CHB_V1 and the second vertical portion CHB_V2 of the lower interconnect channel pattern CHB, the area of ​​the memory cell array can be reduced, and the manufacturing process can be simplified.

[0114] The first line 130 and the second line 140 may each include an extension extending in the first direction DR1 and a protrusion extending toward the lower connecting channel pattern CHB or the upper connecting channel pattern CHU. The protrusion of the first line 130 may connect to the upper connecting channel pattern CHU. The protrusion of the second line 140 may connect to the lower connecting channel pattern CHB. Conversely, the first line 130 and the second line 140 may not include the protrusion.

[0115] The first line 130 can correspond to Figure 1 The write bit line WBL is the write bit line of the write transistor WTR. The second bit line 140 can correspond to... Figure 1 The read bit line RBL of the read transistor RTR. For example, each first bit line in the first bit line 130 can correspond to Figure 1 The write bit line WBL of the memory cell MC in the middle, and each second bit line in the second bit line 140 can correspond to Figure 1 The read bit line RBL of the memory cell MC in the memory.

[0116] The first bit line 130 and the second bit line 140 may each comprise a conductive material (e.g., at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal). The first bit line 130 and the second bit line 140 are shown as monolayer films, but are not limited thereto.

[0117] Figure 11 This is a diagram illustrating a semiconductor memory device according to some embodiments. Figure 12 This is a diagram illustrating a semiconductor memory device according to some embodiments. Figure 13 and Figure 14 This is a diagram illustrating a semiconductor memory device according to some embodiments. Figure 15 and Figure 16 This is a diagram illustrating a semiconductor memory device according to some embodiments. Figure 17 and Figure 18 This is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience, the following description focuses on... Figures 1 to 10 Differences in the implementation examples.

[0118] refer to Figure 11 According to some embodiments, the semiconductor memory device may also include an insertion channel metal pattern 151.

[0119] The inserted channel metal pattern 151 can be positioned between the first letter line 120 and the first vertical portion CHB_V1 of the lower connecting channel pattern CHB, and between the second letter line 125 and the second vertical portion CHB_V2 of the lower connecting channel pattern CHB.

[0120] For example, the inserted channel metal pattern 151 can be positioned between the first vertical portion CHB_V1 of the lower connecting channel pattern CHB and the first vertical portion CHU_V1 of the upper connecting channel pattern CHU, and between the second vertical portion CHB_V2 of the lower connecting channel pattern CHB and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. The inserted channel metal pattern 151 may not be positioned between the first letter line 120 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU, nor between the second letter line 125 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU.

[0121] The inserted channel metal pattern 151 may extend along the first vertical portion CHU_V1 of the upper connecting channel pattern CHU on the third-party DR3. The inserted channel metal pattern 151 may extend along the second vertical portion CHU_V2 of the upper connecting channel pattern CHU on the third-party DR3. For example, the inserted channel metal pattern 151 may contact the upper connecting channel pattern CHU.

[0122] The insertion channel metal pattern 151 may include a conductive material (e.g., a metal).

[0123] Since the insertion channel metal pattern 151 is formed along the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU, a Schottky barrier can be formed between the insertion channel metal pattern 151 and the first vertical portion CHU_V1 of the upper connecting channel pattern CHU, and between the insertion channel metal pattern 151 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. Therefore, during programming operations, the charge stored in the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU can be retained for a longer period. Thus, the performance and reliability of the semiconductor memory device according to some embodiments can be enhanced.

[0124] refer to Figure 12 According to some embodiments, the semiconductor memory device may also include an inserted ferroelectric material pattern 153.

[0125] The ferroelectric material pattern 153 can be set between the first letter line 120 and the first vertical portion CHB_V1 of the lower connecting channel pattern CHB, and between the second letter line 125 and the second vertical portion CHB_V2 of the lower connecting channel pattern CHB.

[0126] For example, the inserted ferroelectric material pattern 153 can be positioned between the first vertical portion CHB_V1 of the lower connecting channel pattern CHB and the first vertical portion CHU_V1 of the upper connecting channel pattern CHU, and between the second vertical portion CHB_V2 of the lower connecting channel pattern CHB and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. The inserted ferroelectric material pattern 153 may not be positioned between the first letter line 120 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU, nor between the second letter line 125 and the third vertical portion CHU_V3 of the upper connecting channel pattern CHU.

[0127] The inserted ferroelectric material pattern 153 can extend along the first vertical portion CHU_V1 of the upper connecting channel pattern CHU on the third-party DR3. The inserted ferroelectric material pattern 153 can also extend along the second vertical portion CHU_V2 of the upper connecting channel pattern CHU on the third-party DR3. For example, the inserted ferroelectric material pattern 153 can be in contact with the upper connecting channel pattern CHU.

[0128] The inserted ferroelectric material pattern 153 may include ferroelectric materials.

[0129] The inserted ferroelectric material pattern 153 may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O). However, these ferroelectric materials are merely examples and do not limit the scope of this disclosure.

[0130] The inserted ferroelectric material pattern 153 may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopants included in the inserted ferroelectric material pattern 153 may vary depending on the ferroelectric material used in the inserted ferroelectric material pattern 153.

[0131] If the inserted ferroelectric material pattern 153 includes hafnium oxide, the dopant included in the inserted ferroelectric material pattern 153 may include at least one of Gd, Si, Zr, Al and Y.

[0132] If Al is used as a dopant, the inserted ferroelectric material pattern 153 may include 3 to 8 atomic percentages (at%) of Al. Here, the dopant percentage may be based on the sum of Hf and Al. If Si is used as a dopant, the inserted ferroelectric material pattern 153 may include 2 to 10 at% of Si. If Y is used as a dopant, the inserted ferroelectric material pattern 153 may include 2 to 10 at% of Y. If Gd is used as a dopant, the inserted ferroelectric material pattern 153 may include 1 to 7 at% of Gd. If Zr is used as a dopant, the inserted ferroelectric material pattern 153 may include 50 to 80 at% of Zr.

[0133] The inserted ferroelectric material pattern 153 can have a thickness sufficient to exhibit ferroelectric properties. The thickness of the inserted ferroelectric material pattern 153 can be, for example, from 0.5 to 10 nm, but is not limited thereto. Since the critical thickness for exhibiting ferroelectric properties varies depending on the ferroelectric material, the thickness of the inserted ferroelectric material pattern 153 can also vary depending on the ferroelectric material used.

[0134] In one example, the inserted ferroelectric material pattern 153 may each comprise a single ferroelectric material layer. In another example, the inserted ferroelectric material pattern 153 may each comprise multiple ferroelectric material layers spaced apart from each other. For example, the inserted ferroelectric material pattern 153 may have a stacked structure in which multiple ferroelectric material layers and at least one dielectric material layer are stacked alternately.

[0135] Since the ferroelectric material pattern 153 is formed along the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU, a Schottky barrier can be formed between the ferroelectric material pattern 153 and the first vertical portion CHU_V1 of the upper connecting channel pattern CHU, and between the ferroelectric material pattern 153 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. Therefore, the performance and reliability of the semiconductor memory device according to some embodiments can be enhanced.

[0136] refer to Figure 13 and Figure 14 According to some embodiments, the semiconductor memory device may further include a conductive pattern 155 for a connecting channel disposed between the first word line 120 and the second word line 125.

[0137] The conductive pattern 155 of the connecting channel can be disposed between the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU. The conductive pattern 155 of the connecting channel can be spaced apart from the first vertical portion CHU_V1 and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU in the first direction DR1. The first character line 120 can be disposed between the conductive pattern 155 of the connecting channel and the first vertical portion CHU_V1 of the upper connecting channel pattern CHU. The second character line 125 can be disposed between the conductive pattern 155 of the connecting channel and the second vertical portion CHU_V2 of the upper connecting channel pattern CHU.

[0138] The connecting channel conductive pattern 155 can protrude from the horizontal portion CHU_H of the upper connecting channel pattern CHU on the third direction DR3. The connecting channel conductive pattern 155 can be connected to the horizontal portion CHU_H of the upper connecting channel pattern CHU. For example, the connecting channel conductive pattern 155 can contact the horizontal portion CHU_H of the upper connecting channel pattern CHU.

[0139] The first line 130 can be connected to the connecting channel conductive pattern 155. The connecting channel conductive pattern 155 can be electrically connected to the upper connecting channel pattern CHU.

[0140] The upper connecting channel pattern CHU may not include the third vertical part ( Figure 9 (CHU_V3 in the text). The conductive pattern 155 of the connecting channel can be formed at the position of the third vertical portion CHU_V3.

[0141] In embodiments, the material of the connecting channel conductive pattern 155 may differ from the material of the upper connecting channel pattern CHU. For example, the connecting channel conductive pattern 155 may include a conductive material (e.g., at least one selected from doped semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, conductive metal oxides, and metals). In one example, the connecting channel conductive pattern 155 may include a metal.

[0142] refer to Figure 15 and Figure 16 According to some embodiments, a semiconductor memory device may include a conductive plate 115.

[0143] The conductive plate 115 can be disposed on the lower insulating film 105. The conductive plate 115 can replace the wire 110 and be disposed on the substrate 100.

[0144] Conductive plate 115 can be connected to ground voltage. Conductive plate 115 can be connected to the read transistor ( Figure 1 The source extremum of "RTR" in the text.

[0145] Adjacent lower connection channel patterns CHB on the second direction DR2 can be connected to the conductive plate 115. For example, a first lower connection channel pattern CHB1 and a second lower connection channel pattern CHB2 spaced apart from each other on the second direction DR2 can be connected to the conductive plate 115. This is achieved by providing a storage cell ( Figure 1 The conductive plate 115 is formed in the memory cell array of “MC” in the text, which can simplify the manufacturing process.

[0146] refer to Figure 17 and Figure 18 In a semiconductor memory device according to some embodiments, a single first bit line 130 and multiple second bit lines 140 may be disposed on a lower connection channel pattern CHB and extend in a first direction DR1.

[0147] Multiple second bit lines 140 may include a first sub-bit line 140_1 and a second sub-bit line 140_2. The first sub-bit line 140_1 and the second sub-bit line 140_2 may each extend in a first direction DR1.

[0148] The first sub-line 140_1 can be spaced apart from the second sub-line 140_2 on the second direction DR2. The first sub-line 130 can be set between the first sub-line 140_1 and the second sub-line 140_2.

[0149] The first sub-line 140_1 can be connected to the first vertical portion of the lower connecting channel pattern CHB. Figure 9 "CHB_V1" in the diagram, but it is not necessary to connect it to the second vertical portion of the lower connecting channel pattern CHB. Figure 9 (CHB_V2 in the text). The second sub-line 140_2 can be connected to the second vertical portion CHB_V2 of the lower connecting channel pattern CHB, but it can be left unconnected to the first vertical portion CHB_V1 of the lower connecting channel pattern CHB.

[0150] By using the read transistors of adjacent memory cells ( Figure 1 Connecting the drain terminal of the “RTR” in the memory cell array to different second bit lines 140 can improve the sensing margin of the memory cell array.

[0151] Figures 19 to 23 This is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience, the following description focuses on the references. Figures 1 to 10 Differences in the described embodiments.

[0152] For reference only. Figure 19 and Figure 20 This is a layout diagram of a semiconductor memory device according to some embodiments. Figure 21 and Figure 22 They are respectively along Figure 20The cross-sectional view taken from lines AA and BB. Figure 23 yes Figure 21 A magnified cross-sectional view of part P in the diagram.

[0153] refer to Figures 19 to 23 According to some embodiments, a semiconductor memory device may include a wire 110, a first lower channel pattern CH11, a second lower channel pattern CH12, a first upper channel pattern CH21, a second upper channel pattern CH22, a first word line 120, a second word line 125, a first bit line 130, and a second bit line 140.

[0154] The first lower channel pattern CH11 and the second lower channel pattern CH12 can be set on the conductor 110. The first lower channel pattern CH11 and the second lower channel pattern CH12 can be connected to the corresponding conductor 110.

[0155] The first lower channel pattern CH11 can be arranged on the second direction DR2. The second lower channel pattern CH12 can be arranged on the second direction DR2. The first lower channel pattern CH11 and the second lower channel pattern CH12 can be arranged alternately on the first direction DR1.

[0156] In a semiconductor memory device according to some embodiments, the first lower channel pattern CH11 and the second lower channel pattern CH12 may each have an "L" shape in a cross-sectional view taken along the first direction DR1.

[0157] The first lower channel pattern CH11 may each include a horizontal portion CH11_H and a vertical portion CH11_V. The vertical portion CH11_V of the first lower channel pattern CH11 may protrude from the horizontal portion CH11_H of the first lower channel pattern CH11 in a third direction DR3. The vertical portion CH11_V of the first lower channel pattern CH11 may be directly connected to the horizontal portion CH11_H of the first lower channel pattern CH11.

[0158] The second lower channel pattern CH12 may each include a horizontal portion CH12_H and a vertical portion CH12_V. The vertical portion CH12_V of the second lower channel pattern CH12 may protrude from the horizontal portion CH12_H of the second lower channel pattern CH12 in a third direction DR3. The vertical portion CH12_V of the second lower channel pattern CH12 may be directly connected to the horizontal portion CH12_H of the second lower channel pattern CH12.

[0159] The horizontal portion CH11_H of the first lower channel pattern CH11 and the horizontal portion CH12_H of the second lower channel pattern CH12 can be connected to the wire 110. The first lower channel pattern CH11 and the second lower channel pattern CH12 can be used as storage cells. Figure 1The read transistor of "MC" in the text ( Figure 1 The "RTR" channel area in the text.

[0160] The lower connecting channel pattern can be used ( Figure 4 The “CHB” in the diagram is divided into the first lower channel pattern CH11 and the second lower channel pattern CH12.

[0161] The first upper channel pattern CH21 can be set on the first lower channel pattern CH11. The first upper channel pattern CH21 can overlap with the first lower channel pattern CH11 on the third direction DR3.

[0162] The second upper channel pattern CH22 can be set on the second lower channel pattern CH12. The second upper channel pattern CH22 can overlap with the second lower channel pattern CH12 on the third direction DR3.

[0163] In a semiconductor memory device according to some embodiments, the first upper channel pattern CH21 and the second upper channel pattern CH22 may each have a "U" shape in a cross-sectional view taken along the first direction DR1.

[0164] The first upper channel pattern CH21 may include a horizontal portion CH21_H and multiple vertical portions CH21_V. The multiple vertical portions CH21_V may include a first vertical portion CH21_V1 and a second vertical portion CH21_V2. The first vertical portion CH21_V1 and the second vertical portion CH21_V2 may protrude from the corresponding horizontal portion CH21_H of the first upper channel pattern CH21 on a third-direction DR3. The first vertical portion CH21_V1 and the second vertical portion CH21_V2 may be directly connected to the corresponding horizontal portion CH21_H of the first upper channel pattern CH21.

[0165] The second upper channel pattern CH22 may each include a horizontal portion CH22_H and multiple vertical portions CH22_V. The multiple vertical portions CH22_V may include a first vertical portion CH22_V1 and a second vertical portion CH22_V2. The first vertical portion CH22_V1 and the second vertical portion CH22_V2 may protrude from the corresponding horizontal portion CH22_H of the second upper channel pattern CH22 onto the third direction DR3. The first vertical portion CH22_V1 and the second vertical portion CH22_V2 may be directly connected to the corresponding horizontal portion CH22_H of the second upper channel pattern CH22.

[0166] The first character line 120 can be positioned between the first vertical portion CH21_V1 and the second vertical portion CH21_V2 of the first upper channel pattern CH21. The second character line 125 can be positioned between the first vertical portion CH22_V1 and the second vertical portion CH22_V2 of the second upper channel pattern CH22.

[0167] The first upper channel pattern CH21 and the second upper channel pattern CH22 can be used as storage units. Figure 1 The write transistor of "MC" in the text ( Figure 1 The channel region of the "WTR" in the first upper channel pattern CH21. For example, the horizontal portion CH21_H and the second vertical portion CH21_V2 of the first upper channel pattern CH21 can be used as the channel region for writing the transistor WTR. Additionally, the horizontal portion CH22_H and the second vertical portion CH22_V2 of the second upper channel pattern CH22 can be used as the channel region for writing the transistor WTR. The first vertical portion CH21_V1 of the first upper channel pattern CH21 and the first vertical portion CH22_V1 of the second upper channel pattern CH22 can be the drain terminal of the transistor WTR. For example, the first vertical portion CH21_V1 of the first upper channel pattern CH21 and the first vertical portion CH22_V1 of the second upper channel pattern CH22 can correspond to... Figure 1 The gate SN_G of the storage node.

[0168] The upper connecting channel pattern can be ( Figure 4 The “CHU” in the diagram is divided into the first upper channel pattern CH21 and the second upper channel pattern CH22.

[0169] The first lower channel pattern CH11 and the second lower channel pattern CH12 may include one or a combination of silicon, germanium, silicon-germanium, III-V compound semiconductors, oxide semiconductor materials, and 2D materials. The first upper channel pattern CH21 and the second upper channel pattern CH22 may include one or a combination of silicon, germanium, silicon-germanium, III-V compound semiconductors, oxide semiconductor materials, and 2D materials.

[0170] By separating the first lower channel pattern CH11 and the second lower channel pattern CH12 from each other, interference between adjacent memory cells MC can be reduced. Therefore, the performance and reliability of semiconductor memory devices according to some embodiments can be enhanced.

[0171] The channel isolation insulation pattern 157 can be disposed between the first lower channel pattern CH11 and the second lower channel pattern CH12, and between the first upper channel pattern CH21 and the second upper channel pattern CH22. The channel isolation insulation pattern 157 can be disposed between the first letter line 120 and the second letter line 125. The channel isolation insulation pattern 157 may include insulating material.

[0172] The first gate insulating pattern GOX1 can be disposed between the first lower channel pattern CH11 and the first upper channel pattern CH21, and between the second lower channel pattern CH12 and the second upper channel pattern CH22. The second gate insulating pattern GOX2 can be disposed between the first upper channel pattern CH21 and the first word line 120, and between the second upper channel pattern CH22 and the second word line 125.

[0173] The first line 130 can be connected to the first upper channel pattern CH21 and the second upper channel pattern CH22. For example, the first line 130 can be connected to the second vertical portion CH21_V2 of the first upper channel pattern CH21 and the second vertical portion CH22_V2 of the second upper channel pattern CH22.

[0174] The protrusions of each first line 130, which connect to the second vertical portion CH21_V2 of the first upper channel pattern CH21 and the second vertical portion CH22_V2 of the second upper channel pattern CH22, are shown as separate, but are not limited thereto. Alternatively, the protrusions of each first line 130 may connect to both the second vertical portion CH21_V2 of the first upper channel pattern CH21 and the second vertical portion CH22_V2 of the second upper channel pattern CH22.

[0175] The second bit line 140 can be connected to the first lower channel pattern CH11 and the second lower channel pattern CH12. For example, the second bit line 140 can be connected to the vertical portion CH11_V of the first lower channel pattern CH11 and the vertical portion CH12_V of the second lower channel pattern CH12.

[0176] Figure 24 This is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience, the following description focuses on the references. Figures 1 to 10 Differences in the described embodiments.

[0177] refer to Figure 24 According to some embodiments, the semiconductor memory device may also include a peripheral gate structure PG.

[0178] The peripheral gate structure PG can be disposed on the substrate 100. The peripheral gate structure PG can be included in a sensing transistor, a transmission transistor, or a driving transistor. According to some embodiments, the types of transistors disposed in the cell array region and the peripheral circuit region can vary depending on the design layout of the semiconductor memory device.

[0179] The peripheral gate structure PG may include a peripheral gate insulating film 215, a lower peripheral conductive pattern 223, and an upper peripheral conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film with a dielectric constant greater than that of silicon oxide, or a combination thereof. The high-k insulating film may include, for example, at least one of a metal oxide, a metal oxynitride, a metal oxide, or a metal oxynitride, but is not limited thereto.

[0180] The lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may each include a conductive material. For example, the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal. The peripheral gate structure PG is shown as including multiple conductive patterns, but is not limited thereto.

[0181] The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 can be disposed on the substrate 100. The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 can each include insulating material.

[0182] The first peripheral wiring 241a and the peripheral contact plug 241b may be disposed within the first lower peripheral insulating film 227 and the second lower peripheral insulating film 228. The first peripheral wiring 241a and the peripheral contact plug 241b are shown as separate layers, but are not limited thereto. The boundary between the first peripheral wiring 241a and the peripheral contact plug 241b may be indistinguishable. The first peripheral wiring 241a and the peripheral contact plug 241b may each comprise a conductive material.

[0183] The first upper peripheral insulating film 261 and the second upper peripheral insulating film 262 can be disposed on the first peripheral wiring 241a and the peripheral contact plug 241b. The first upper peripheral insulating film 261 and the second upper peripheral insulating film 262 can each include insulating material.

[0184] The second peripheral wiring 243 and the peripheral via plug 242 can be disposed on the first peripheral wiring 241a. The peripheral via plug 242 can be disposed within the first upper peripheral insulating film 261. The second peripheral wiring 243 can be disposed within the second upper peripheral insulating film 262.

[0185] The second peripheral wiring 243 and the peripheral via plug 242 can be connected to the first peripheral wiring 241a. The peripheral via plug 242 can connect the first peripheral wiring 241a to the second peripheral wiring 243. The second peripheral wiring 243 and the peripheral via plug 242 may each include a conductive material. The second peripheral wiring 243 and the peripheral via plug 242 are shown as separate layers, but are not limited thereto. The boundary between the second peripheral wiring 243 and the peripheral via plug 242 may be indistinguishable.

[0186] Conductor 110, lower connecting channel pattern CHB, upper connecting channel pattern CHU, first letter line 120, second letter line 125, first position line 130, and second position line ( Figure 5 The “140” in the figure can be set on the peripheral gate structure PG.

[0187] The unit connection plug 244 can be disposed within the third upper peripheral insulating film 263. The unit connection plug 244 can be connected to the second peripheral wiring 243. The unit connection plug 244 includes a conductive material. The third upper peripheral insulating film 263 includes an insulating material.

[0188] The wire 110 can be disposed on the unit connection plug 244. The wire 110 can be connected to the unit connection plug 244. Although not shown, the first bit line 130, the second bit line 140, the first word line 120, and the second word line 125 can be connected to the second peripheral wiring 243.

[0189] Figure 25 This is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience, the following description focuses on the references. Figure 24 Differences in the described embodiments.

[0190] refer to Figure 25 According to some embodiments, the semiconductor memory device may also include a first bonding pad BP1 and a second bonding pad BP2.

[0191] The first bonding pad BP1 and the first pad plug 281 can be disposed on the second peripheral wiring 243. The first bonding pad BP1 and the first pad plug 281 can be disposed within the third upper peripheral insulating film 263.

[0192] The first pad plug 281 can be disposed between the first bonding pad BP1 and the second peripheral wiring 243. The first pad plug 281 can connect the first bonding pad BP1 to the second peripheral wiring 243.

[0193] The second bonding pad BP2 and the second pad plug 282 can be disposed on the first bonding pad BP1. The second bonding pad BP2 and the second pad plug 282 can be disposed within the fourth upper peripheral insulating film 264.

[0194] The second bonding pad BP2 can be connected to the first bonding pad BP1. For example, the second bonding pad BP2 can contact the first bonding pad BP1. Since the second bonding pad BP2 is electrically connected to the first bonding pad BP1, the second bonding pad BP2 can be connected to the first peripheral wiring 241a and the second peripheral wiring 243.

[0195] The conductor 110 can be disposed on the second bonding pad BP2. The second pad plug 282 can be disposed between the conductor 110 and the second bonding pad BP2. The second pad plug 282 can connect the conductor 110 to the second bonding pad BP2.

[0196] Since the second bonding pad BP2 is connected to the first bonding pad BP1, the first peripheral wiring 241a and the second peripheral wiring 243 can be connected to the conductor 110. Although not shown, the first bit line 130 and the second bit line ( Figure 5 The “140” in the first word line 120 and the second word line 125 can be connected to the second bonding pad BP2.

[0197] The first pad plug 281 and the second pad plug 282 may each comprise a conductive material containing metal. The first bonding pad BP1 and the second bonding pad BP2 may each comprise a conductive material containing metal. The first bonding pad BP1 and the second bonding pad BP2 are shown as a single-layer film, but are not limited thereto.

[0198] The fourth upper peripheral insulating film 264 may include an insulating material. The boundary between the third upper peripheral insulating film 263 and the fourth upper peripheral insulating film 264 is shown as distinguishable, but is not limited thereto. If the third upper peripheral insulating film 263 and the fourth upper peripheral insulating film 264 comprise the same material, their boundary may be indistinguishable and may be distinguishable based on the boundary between the first bonding pad BP1 and the second bonding pad BP2.

[0199] Although not shown, a bonding insulating film may be provided between the third upper peripheral insulating film 263 and the fourth upper peripheral insulating film 264. For example, the bonding insulating film may include SiCN, but is not limited thereto.

[0200] Figures 26 to 53 A method for manufacturing a semiconductor memory device according to some embodiments is shown.

[0201] refer to Figure 26 and Figure 27 A wire 110 can be formed on the substrate 100.

[0202] Each of the conductors 110 can extend in the first direction DR1.

[0203] In one example, a lower insulating film 105 may be formed on a substrate 100. Wire trenches may be formed within the lower insulating film 105. Subsequently, wires 110 filling the wire trenches may be formed within the lower insulating film 105.

[0204] In another example, a portion of a lower insulating film 105 may be formed on the substrate 100. A lower conductive film may be formed on this portion of the lower insulating film 105. Subsequently, a subtractive etching process may be performed to pattern the lower conductive film. As a result, conductive lines 110 may be formed on the substrate 100. Subsequently, the remaining portion of the exposed conductive lines 110 of the lower insulating film 105 may be formed on the conductive lines 110.

[0205] Subsequently, a first pre-molded pattern 161 can be formed on the lower insulating film 105 and the conductor 110. The first pre-molded pattern 161 may include a plurality of first channel trenches CH_T1. Each of the first channel trenches CH_T1 may extend in a second direction DR2. The first channel trenches CH_T1 may intersect with the conductor 110.

[0206] refer to Figure 28 and Figure 29 A pre-groove pattern CHB_P can be formed on the lower insulating film 105 and the conductor 110.

[0207] The pre-groove pattern CHB_P can be formed along the sidewall and bottom surface of the first groove CH_T1. The pre-groove pattern CHB_P can extend in the second direction DR2.

[0208] Specifically, a pre-groove film can be formed along the sidewalls and bottom surface of the first groove CH_T1. The pre-groove film can be formed along the upper surface of the first pre-molded pattern 161. Then, a pre-groove pattern CHB_P extending in the second direction DR2 can be formed by patterning the pre-groove film. The pre-groove pattern CHB_P can be formed by removing a portion of the pre-groove film formed on the upper surface of the first pre-molded pattern 161. Then, an additional first pre-molded pattern 161 can be formed in the space where a portion of the pre-groove film has been removed, such that the uppermost surface of the pre-groove pattern CHB_P is coplanar with the upper surface of the first pre-molded pattern 161.

[0209] refer to Figure 30 Impurity blocking spacers 50 can be formed on the pre-groove pattern CHB_P.

[0210] The impurity blocking spacer 50 can be formed along the sidewall of the first channel groove CH_T1. The impurity blocking spacer 50 can extend in the second direction DR2.

[0211] Subsequently, impurities can be implanted into the exposed pre-lower channel pattern CHB_P using impurity doping process 55. For example, impurities can be implanted into the horizontal portion CHB_H of the lower connection channel pattern CHB and the extension portion CHB_VP2 of the vertical portion CHB_V of the lower connection channel pattern CHB. The impurities introduced by impurity doping process 55 can be p-type or n-type. The type of implanted impurity can vary depending on the semiconductor material included in the pre-lower channel pattern CHB_P.

[0212] Based on the semiconductor material included in the pre-lower channel pattern CHB_P, the impurity doping process 55 for implanting impurities into the lower channel pattern CHB_P can be omitted.

[0213] refer to Figures 28 to 33 After the impurity doping process 55, the impurity blocking spacer 50 can be removed.

[0214] Subsequently, the lower connection channel pattern CHB can be formed by patterning the pre-lower channel pattern CHB_P. Specifically, a first sacrificial material pattern can be formed within the first channel trench CH_T1. Channel isolation trenches can be formed to cut through each pre-lower channel pattern CHB_P, thereby dividing it into a plurality of lower connection channel patterns CHB aligned in the second direction DR2. The channel isolation trenches can be formed within the first pre-molded pattern 161 and the first sacrificial material pattern. The channel isolation trenches can extend in the first direction DR1. After forming the lower connection channel pattern CHB, a channel cutting pattern 162 filling the channel isolation trench can be formed. A channel cutting pattern 162 separating the pre-lower channel patterns CHB_P can be formed. Thus, a second pre-molded pattern (161 and 162), including the first pre-molded pattern 161 and the channel cutting pattern 162, can be formed on the conductor 110 and the lower insulating film 105.

[0215] Subsequently, the second channel groove CH_T2 can be formed by removing the first sacrificial material pattern. The second channel groove CH_T2 can be defined by the first pre-molded pattern 161 and the channel cutting pattern 162. For example, the second channel groove CH_T2 can be defined by the second pre-molded patterns (161 and 162). The lower connecting channel pattern CHB can be formed within the second channel groove CH_T2.

[0216] refer to Figures 34 to 37 The first gate insulating pattern GOX1 can be formed on the lower connecting channel pattern CHB.

[0217] The first gate insulating pattern GOX1 can be formed along the sidewalls and bottom surface of the second channel trench CH_T2. The first gate insulating pattern GOX1 can also be formed along the upper surface of the second pre-molded patterns (161 and 162).

[0218] Subsequently, a first pre-top panel pattern CHU_P1 can be formed on the first gate insulating pattern GOX1. The first pre-top panel pattern CHU_P1 can be formed within the second channel trench CH_T2. The first pre-top panel pattern CHU_P1 can be formed along the sidewalls and bottom surface of the second channel trench CH_T2.

[0219] The first pre-top panel pattern CHU_P1 may have, for example, an open box shape, but is not limited to this.

[0220] Conversely, the insertion channel metal pattern can be formed prior to the formation of the first pre-top panel pattern CHU_P1. Figure 11 "151" in the text or insert a pattern of ferroelectric material ( Figure 12 (153 in the text).

[0221] refer to Figures 34 to 40 The word line groove WLT can be formed by partially removing the second pre-molded pattern (161 and 162) and the first pre-top panel pattern CHU_P1.

[0222] The word line groove WLT can extend in the second direction DR2. A molded insulating pattern 160 including the word line groove WLT can be formed. During the formation of the word line groove WLT, a second pre-top panel pattern CHU_P2 can be formed.

[0223] Specifically, a second sacrificial material pattern can be formed within the second channel groove CH_T2. Then, word line grooves WLT can be formed within the second sacrificial material pattern, the second pre-molded patterns (161 and 162), and the first pre-top panel pattern CHU_P1. Afterwards, the second sacrificial material pattern can be removed.

[0224] refer to Figure 41 A first character line molding spacer 60 and a second character line molding spacer 65 can be formed within the character line groove WLT.

[0225] The first character line molding spacer 60 and the second character line molding spacer 65 can be formed on the second pre-top panel pattern CHU_P2. The first character line molding spacer 60 and the second character line molding spacer 65 can each extend in the second direction DR2. Within the character line groove WLT, the first character line molding spacer 60 and the second character line molding spacer 65 can be spaced apart in the first direction DR1.

[0226] refer to Figure 42 and Figure 43 A letter line separation pattern 129 can be formed between the first letter line molding spacer 60 and the second letter line molding spacer 65.

[0227] The letter line isolation pattern 129 can be formed within the letter line groove WLT. The letter line isolation pattern 129 can extend in the second direction DR2.

[0228] refer to Figures 42 to 45 After removing the first molding spacer 60 and the second molding spacer 65, the first molding spacer groove 60_T and the second molding spacer groove 65_T can be formed.

[0229] The first molded spacer groove 60_T and the second molded spacer groove 65_T can expose the second pre-top panel pattern CHU_P2. The first molded spacer groove 60_T and the second molded spacer groove 65_T can be provided on both sides of the letter line isolation pattern 129. The first molded spacer groove 60_T and the second molded spacer groove 65_T can each extend in the second direction DR2.

[0230] refer to Figures 44 to 47 A second gate insulating pattern GOX2 can be formed on the second pre-upper panel pattern CHU_P2.

[0231] The second gate insulating pattern GOX2 can be formed along the sidewalls and bottom surface of the first molded spacer trench 60_T and the sidewalls and bottom surface of the second molded spacer trench 65_T.

[0232] Subsequently, a first word line 120 and a second word line 125 can be formed on the second gate insulating pattern GOX2. The first word line 120 can be formed within the first molded spacer trench 60_T. The first word line 120 can fill a portion of the first molded spacer trench 60_T. The second word line 125 can be formed within the second molded spacer trench 65_T. The second word line 125 can fill a portion of the second molded spacer trench 65_T.

[0233] A letter capping pattern 128 can be formed on the first letter 120 and the second letter 125. The letter capping pattern 128 can fill the remaining portion of the first molded spacer groove 60_T and the remaining portion of the second molded spacer groove 65_T.

[0234] like Figures 46 to 50 As shown, an upper channel hole CHU_CT can be formed between the first word line 120 and the second word line 125 by removing a portion of the word line isolation pattern 129.

[0235] The upper channel hole CHU_CT can expose a portion of the second pre-upper panel pattern CHU_P2.

[0236] like Figures 48 to 53 As shown, a third pre-upper channel pattern can be formed to fill the upper channel hole CHU_CT.

[0237] The third pre-groove pattern can contact the second pre-groove panel pattern CHU_P2. The third pre-groove pattern can correspond to Figure 9 The third vertical portion of the upper connecting channel pattern CHU is CHU_V3. Therefore, the upper connecting channel pattern CHU can be formed on the lower connecting channel pattern CHB.

[0238] Conversely, a conductive pattern connecting the channel can be formed within the upper channel hole CHU_CT. Figure 13 (155 in the text). In this case, the second pre-upper panel pattern CHU_P2 can correspond to the upper connecting channel pattern CHU.

[0239] Afterwards, refer to Figures 4 to 8 The first line 130 and the second line 140 can be formed on the upper connecting channel pattern CHU and the lower connecting channel pattern CHB.

[0240] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments of this disclosure are for general and descriptive purposes only and are not intended to be limiting.

Claims

1. A semiconductor memory device, comprising: The first conductive line is on the substrate; The first line is spaced apart from the first conductor in a first direction and extends in a second direction intersecting the first direction; The second bit line is spaced apart from the first wire in the first direction, extends in the second direction, and is spaced apart from the first bit line in a third direction where it intersects the first direction and the second direction; The first word line is disposed between the first conductor and each of the first bit line and the second bit line, and extends upward from the third. The first channel pattern includes: The horizontal portion extends in the second direction and is positioned between the first letter and the first conductor. The first vertical portion extends in the first direction. Wherein, the horizontal portion of the first channel pattern is connected to the first conductor, and Wherein, the first vertical portion of the first channel pattern is connected to the first bit line; and The second channel pattern is disposed between the first channel pattern and the first character line, and is connected to the second character line.

2. The semiconductor memory device according to claim 1, in, The second channel pattern includes: The first vertical portion is disposed between the first vertical portion of the first groove pattern and the first letter line; and The horizontal portion is positioned between the horizontal portion of the first groove pattern and the first letter line, and The first vertical portion of the second channel pattern is directly connected to the horizontal portion of the second channel pattern.

3. The semiconductor memory device according to claim 2, in, The second channel pattern further includes a second vertical portion, which is spaced apart from the first vertical portion of the second channel pattern in the second direction. Wherein, the first character line is disposed between the first vertical portion of the second groove pattern and the second vertical portion of the second groove pattern, and The second bit line is connected to the second vertical portion of the second channel pattern.

4. The semiconductor memory device according to claim 2, further comprising: The connecting channel conductive pattern is spaced apart from the first vertical portion of the second channel pattern in the second direction and extends along the sidewall of the first letter line. The first character line is positioned between the first vertical portion of the second channel pattern and the conductive pattern of the connecting channel. The conductive pattern of the connecting channel includes the lower end of the horizontal portion connected to the second channel pattern and the upper end connected to the second bit line. The first vertical portion of the second channel pattern, the first vertical portion of the first channel pattern, the first bit line, the connecting channel conductive pattern, the first bit line connected to the first vertical portion of the first channel pattern, and the second bit line connected to the connecting channel conductive pattern constitute the first memory cell.

5. The semiconductor memory device according to claim 1, further comprising: The second letter line extends upward from the third party and is spaced apart from the first letter line in the second direction. The first channel pattern further includes: The second vertical portion is spaced apart from the first vertical portion of the first channel pattern in the second direction and is directly connected to the horizontal portion of the first channel pattern. The first character line and the second character line are disposed between the first vertical portion of the first channel pattern and the second vertical portion of the first channel pattern.

6. The semiconductor memory device according to claim 5, in, The second channel pattern includes: The first vertical portion is disposed between the first vertical portion of the first groove pattern and the first letter line; The second vertical portion is disposed between the second vertical portion of the first groove pattern and the second letter line; and In the horizontal portion, the first vertical portion of the second channel pattern is connected to the second vertical portion of the second channel pattern.

7. The semiconductor memory device according to claim 6, in, The second channel pattern further includes a third vertical portion that extends in the first direction and is positioned between the first letter line and the second letter line. The third vertical portion of the second channel pattern includes a lower end connected to the horizontal portion of the second channel pattern and an upper end connected to the second bit line. The second vertical portion of the second channel pattern, the second vertical portion of the first channel pattern, the second bit line, the third vertical portion of the second channel pattern, the first bit line connected to the second vertical portion of the first channel pattern, and the second bit line connected to the third vertical portion of the second channel pattern constitute the second memory cell.

8. The semiconductor memory device according to claim 5, in, The second vertical portion of the first channel pattern is connected to the first bit line.

9. The semiconductor memory device according to claim 5, further comprising: The third line is spaced apart from the first conductor in the first direction and extends in the second direction. The second bit line is disposed between the first bit line and the third bit line, and The third bit line is connected to the second vertical portion of the first channel pattern.

10. The semiconductor memory device according to claim 1, further comprising: An insert channel metal pattern is positioned between the first vertical portion of the first channel pattern and the first letter line, and contacts the second channel pattern.

11. The semiconductor memory device according to claim 1, further comprising: A ferroelectric material pattern is inserted, positioned between the first vertical portion of the first channel pattern and the first letter line, and in contact with the second channel pattern.

12. The semiconductor memory device according to claim 1, further comprising: The second conductor is spaced apart from the first conductor in the third direction and extends in the second direction; as well as The third channel pattern, spaced apart from the first channel pattern in the third direction, is connected to the second conductor. The first conductor extends in the second direction. Wherein, the first channel pattern is not directly connected to the second conductor, and The third channel pattern is not directly connected to the first conductor.

13. The semiconductor memory device according to claim 1, further comprising: The third channel pattern is spaced apart from the first channel pattern in the third direction and is connected to the first conductor.

14. A semiconductor memory device, comprising: The wire is on the substrate; The first line is spaced apart from the conductor in the first direction and extends in a second direction intersecting the first direction; The second bit line is spaced apart from the conductor in the first direction, extends in the second direction, and is spaced apart from the first bit line in a third direction where it intersects the first direction and the second direction; A first word line is disposed between the conductor and each of the first bit line and the second bit line, and extends upward from the third. A first channel pattern is disposed between the first character line and the conductor, and is connected to the first bit line and the conductor; as well as The second channel pattern is disposed between the first channel pattern and the first character line, and is connected to the second character line. The first character line includes a first sidewall and a second sidewall that are opposite to each other in the second direction, and The second channel pattern includes: The first vertical portion extends along the first sidewall of the first character line. The second vertical portion extends along the second sidewall of the first character line, and In the horizontal portion, the first vertical portion of the second channel pattern is connected to the second vertical portion of the second channel pattern.

15. The semiconductor memory device of claim 14, further comprising: The second letter line extends upward from the third party and is spaced apart from the first letter line in the second direction. The second character line includes a first sidewall and a second sidewall that are opposite to each other in the second direction. The second sidewall of the second character line is adjacent to the second sidewall of the first character line. The second channel pattern further includes: The third vertical portion is spaced apart from the second vertical portion of the second channel pattern in the second direction and is connected to the horizontal portion of the second channel pattern. Wherein, the second vertical portion of the second channel pattern is disposed between the second sidewall of the first character line and the second sidewall of the second character line, and The third vertical portion of the second groove pattern extends along the first sidewall of the second letter line.

16. The semiconductor memory device according to claim 14, in, The first channel pattern also includes: The horizontal portion extends in the second direction between the second channel pattern and the conductor; and The first vertical portion extends along the first vertical portion of the second groove pattern in the first direction. Wherein, the horizontal portion of the first channel pattern is connected to the conductor, and The first vertical portion of the first channel pattern is connected to the first bit line.

17. The semiconductor memory device according to claim 16, in, The first channel pattern also includes: The second vertical portion is spaced apart from the first vertical portion of the first channel pattern in the second direction and is directly connected to the horizontal portion of the first channel pattern. The first character line is positioned between the first vertical portion of the first groove pattern and the second vertical portion of the first groove pattern.

18. A semiconductor memory device, comprising: A wire is disposed on a substrate and extends in a first direction; The first line is spaced apart from the conductor in a second direction intersecting the first direction, and extends in the first direction; The second bit line is spaced apart from the conductor in the second direction, extends in the first direction, and is spaced apart from the first bit line in a third direction where it intersects the first direction and the second direction; The first channel pattern includes: The horizontal portion extends in the first direction. The first vertical portion extends in the second direction, and The second vertical portion extends in the second direction. Wherein, the first vertical portion and the second vertical portion of the first channel pattern are respectively directly connected to the opposite ends of the horizontal portion of the first channel pattern. Wherein, the horizontal portion of the first channel pattern is connected to the conductor, and Wherein, the first vertical portion of the first channel pattern and the second vertical portion of the first channel pattern are connected to the first bit line; The first character line is disposed between the first vertical portion of the first groove pattern and the second vertical portion of the first groove pattern; The second letter line is disposed between the first letter line and the second vertical portion of the first groove pattern; and A second channel pattern is disposed between the first channel pattern and each of the first and second character lines, and is connected to the second character line.

19. The semiconductor memory device according to claim 18, in, The second channel pattern includes: The first vertical portion is disposed between the first vertical portion of the first groove pattern and the first letter line; The second vertical portion is disposed between the second vertical portion of the first groove pattern and the second letter line; The third vertical section is positioned between the first character line and the second character line; and The horizontal portion is disposed between the horizontal portion of the first channel pattern and each of the first letter line and the second letter line.

20. The semiconductor memory device of claim 18, further comprising: A conductive pattern for connecting channels is positioned between the first character line and the second character line. The material of the conductive pattern in the connecting channel is different from the material of the second channel pattern. The second channel pattern includes: The first vertical portion is disposed between the first vertical portion of the first groove pattern and the first letter line; The second vertical portion is disposed between the second vertical portion of the first groove pattern and the second letter line; and The horizontal portion includes the opposite ends of the first vertical portion of the second channel pattern and the second vertical portion of the second channel pattern, respectively connected to the second vertical portion of the second channel pattern. The conductive pattern of the connecting channel is connected to the horizontal portion of the second channel pattern.

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