Semiconductor structure comprising a double-sided high-density substrate and method of manufacturing thereof

Abstract

A semiconductor structure includes a substrate including a core layer, a core via through the core layer, a first redistribution line structure disposed on one side of the core layer, and a second redistribution line structure disposed on an opposite side of the core layer and electrically coupled to the first redistribution line structure through the core via. The first redistribution line structure includes an outermost dielectric layer, an outermost conductive pattern disposed in and on the outermost dielectric layer and electrically coupled to the core via, an inner dielectric layer disposed between the outermost dielectric layer and the core layer. An outermost surface of the outermost dielectric layer includes a portion that is rougher than a surface of the inner dielectric layer facing the outermost dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure comprising a double-sided high-density substrate and a method for manufacturing the same. Background Technology

[0002] High-density substrates are required for high-performance computing applications. However, traditional double-sided substrates are limited by double-sided processes and related equipment, making it difficult to achieve fine circuitry. Current equipment can only fabricate redistributed circuit layers with fine circuitry on one side, not on both sides. Therefore, there is a need for double-sided high-density substrates for high-performance computing devices. Summary of the Invention

[0003] This invention provides a semiconductor structure with double-sided high-density substrates and a method for manufacturing the same, wherein the semiconductor structure and method have better reliability and yield.

[0004] A semiconductor structure includes: a substrate including a core layer, a core via penetrating the core layer, a first redistributed circuit structure disposed on one side of the core layer, and a second redistributed circuit structure disposed on the opposite side of the core layer and electrically coupled to the first redistributed circuit structure through the core via. The first redistributed circuit structure includes an outermost dielectric layer, an outermost conductive pattern disposed in and on the outermost dielectric layer and electrically coupled to the core via, and an inner dielectric layer disposed between the outermost dielectric layer and the core layer. The outermost surface of the outermost dielectric layer includes a portion that is rougher than the surface of the inner dielectric layer facing the outermost dielectric layer.

[0005] A method of manufacturing a semiconductor structure includes: forming a core via in a core layer, wherein the core layer includes a first side and a second side opposite to the first side, and the core via extends between the first side and the second side; forming a first redistributed circuit structure on the first side of the core layer; bonding a temporary protective structure to the first redistributed circuit structure, wherein the temporary protective structure includes a temporary carrier and a temporary adhesive layer bonding the temporary carrier to the outermost surface of the first redistributed circuit structure, and the surface flatness of the surface of the temporary adhesive layer bonded to the temporary carrier is better than the surface flatness of the outermost surface of the first redistributed circuit structure; forming a second redistributed circuit structure on the second side of the core layer using the temporary protective structure as a support; and peeling the temporary protective structure from the first redistributed circuit structure.

[0006] Based on the above, using temporary protective structures during substrate formation can help compensate for warpage of semi-finished products (such as the first redistributed circuit structure and the core layer) and reduce the surface non-planarity of the semi-finished products. In this way, the overall flatness of the substrate can be improved, while also improving the reliability and yield of the semiconductor structure.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] The drawings are provided to further illustrate the invention and are incorporated in and constitute a part of this specification. The drawings depict exemplary embodiments of the invention and are used in conjunction with the text to explain the principles of the invention.

[0009] Figures 1 to 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor structure with a double-sided high-density substrate, according to some embodiments.

[0010] Figure 12 This is a schematic cross-sectional view of a double-sided high-density substrate according to some embodiments.

[0011] Figure 13 This is a schematic cross-sectional view of a double-sided high-density substrate according to some embodiments.

[0012] Figure 14 This is a schematic cross-sectional view illustrating a semiconductor structure with a double-sided high-density substrate according to some embodiments.

[0013] Figure 15 This is a schematic cross-sectional view of a double-sided high-density substrate according to some embodiments.

[0014] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor structure with a double-sided high-density substrate according to some embodiments. Detailed Implementation

[0015] The exemplary embodiments of the present invention are described in full below with reference to the accompanying drawings. However, the present invention may be implemented in different ways and should not be construed as limited to the embodiments described herein. In the drawings, for clarity, the sizes and thicknesses of various regions, portions, and layers may not be drawn to scale. For ease of understanding, the same components are described using the same reference numerals in the following description.

[0016] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be implemented in various different forms and is not limited to the embodiments described herein. For clarity, the thickness, size, and dimensions of each layer or region in the drawings are enlarged. The same reference numerals are used in the drawings and description to denote the same or similar components, and therefore will not be repeated below. Directional terms used herein (e.g., up, down, right, left, front, back, top, and bottom) refer only to the orientation of the figure itself and do not indicate absolute orientation.

[0017] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, layers, and / or portions are not limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0018] Figures 1 to 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor structure with a double-sided and high-density substrate, according to some embodiments. Reference Figure 1 A core layer 101 is provided with a plurality of core vias 103. For example, the core layer 101 includes a first side 101a and a second side 101b opposite to the first side 101a, and each core via 103 extends between the first side 101a and the second side 101b. In some embodiments, the core layer 101 is made of one or more inorganic materials (e.g., glass, ceramic, combinations thereof), one or more thermally stable materials, and / or the like. In embodiments where the core layer 101 is made of glass, the core vias 103 are referred to as through glass vias (TGV). Each core via 103 may include one or more conductive materials, such as copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, etc. For example, the spacing SP1 between two adjacent core vias 103 is on the order of several micrometers to facilitate high-density layout.

[0019] refer to Figure 2 and Figure 1A first conductive pad 111 is formed on a first side 101a of the core layer 101 and connected to the core via 103. Each first conductive pad 111 may include one or more conductive materials, such as copper, gold, nickel, aluminum, platinum, tin, combinations thereof, alloys thereof, etc. In some embodiments, the first conductive pads 111 and the core via 103 are configured in a one-to-one manner. However, the configuration of the first conductive pads 111 and the core via 103 may differ from that shown. For example, the spacing SP2 between two adjacent first conductive pads 111 is smaller than the spacing SP1 (marked in...). Figure 1 (In some embodiments, the spacing SP2 is on the order of several micrometers to facilitate high-density layout).

[0020] refer to Figure 3 , Figure 4 and Figure 2 A first dielectric material layer 112' is formed on a first side 101a of the core layer 101 and allows the first conductive pads 111 to be embedded therein. For example, the first dielectric material layer 112' is made of one or more organic polymers, one or more photosensitive materials, or any suitable dielectric material that can be used to form fine circuits / lines. In some embodiments, the first dielectric material layer 112' is made of photosensitive polyimide. Next, multiple portions of the first dielectric material layer 112' are removed by, for example, photolithography and etching or any suitable patterning process to form a first dielectric layer 112 having multiple openings 112P. For example, at least a portion of the first conductive pads 111 is exposed by the openings 112P for further electrical connection. In some embodiments, a portion of each first conductive pad 111 is exposed by one of the openings 112P. However, the openings 112P and the respective first conductive pads 111 may have different configurations than those shown.

[0021] refer to Figure 5 and Figure 4A first conductive pattern 113 is formed in and on a first dielectric layer 112. The first conductive pattern 113 may include one or more conductive materials that are the same as or similar to the material of the first conductive pad 111. For example, the first conductive pattern 113 includes a plurality of via portions 113V formed in openings 112P in the first dielectric layer 112 to make physical and electrical contact with corresponding first conductive pads 111. Each via portion 113V may taper in a direction from a first side 101a toward a second side 101b. The first conductive pattern 113 may also include a plurality of pad portions 113P connected to the via portions 113V and covering the first dielectric layer 112. The first conductive pattern 113 may also include a plurality of line portions (not shown) connected to the pad portions 113P and extending horizontally on the first dielectric layer 112. After the first conductive pattern 113 is formed, a second dielectric layer 114 including a plurality of openings 114P may be formed on the first dielectric layer 112 to cover the first conductive pattern 113. For example, at least a portion of the first conductive pattern 113 is exposed by an opening 114P in the second dielectric layer 114. The material of the second dielectric layer 114 may be the same as (or similar to) the material of the underlying first dielectric layer 112. Alternatively, the materials of the first and second dielectric layers may be different.

[0022] Continue to refer to Figure 5 A second conductive pattern 115 may be formed on the second dielectric layer 114 and fill the openings 114P of the second dielectric layer 114 to make physical and electrical contact with the first conductive pattern 113. The material and formation of the second conductive pattern 115 may be similar to those of the first conductive pattern 113. Next, a third dielectric layer 116 having a plurality of openings 116P may be formed on the second dielectric layer 114 to cover the second conductive pattern 115. The material and formation of the third dielectric layer 116 may be similar to those of the first dielectric layer 112. In some embodiments, a third conductive pattern 117 may be formed on the third dielectric layer 116 and fill the openings 116P of the third dielectric layer 116 to make physical and electrical contact with the second conductive pattern 115, and then an outermost dielectric layer 118 having a plurality of openings 118P may be formed on the third dielectric layer 116 to cover the third conductive pattern 117. The formation process and materials of the third conductive pattern 117 and the outermost dielectric layer 118 can be similar to those of the first conductive pattern 113 and the first dielectric layer 112, respectively.

[0023] Still referencing Figure 5The outermost conductive pattern 119 may be formed on the outermost dielectric layer 118 and fill the openings 118P of the outermost dielectric layer 118 to make physical and electrical contact with the third conductive pattern 117. In some embodiments, a surface finishing process is performed on the pad portions 119P of the outermost conductive pattern 119. For example, a surface finishing layer 1191 is conformally deposited on the outer surface (e.g., including a top surface and sidewalls connected to the corresponding top surface) of each pad portion 119P of the outermost conductive pattern 119. The surface finishing layer 1191 may include one or more conductive materials, such as copper, nickel, gold, etc. Alternatively, the surface finishing process may be skipped and the surface finishing layer 1191 may be omitted. The combination of dielectric layers (e.g., 112, 114, 116, and 118), conductive patterns (e.g., 113, 115, 117, and 119), and the first conductive pad 111 may be collectively referred to as the first redistribution circuit structure 110. It should be understood that the configuration of the first redistribution circuit structure 110 shown herein is for illustrative purposes only. The number of dielectric layers and the number of conductive patterns can be selected according to product and circuit requirements, and the present invention does not impose any limitations on this.

[0024] refer to Figure 6 and Figure 5 A temporary protective structure 50 is provided and bonded to the first redistributed wiring structure 110. In some embodiments, the temporary protective structure 50 includes a temporary carrier 51 provided with a temporary adhesive layer 52. For example, the temporary carrier 51 is adhered to the outermost dielectric layer 118 and the outermost conductive pattern 119 via the temporary adhesive layer 52. The pad portions 119P of the outermost conductive pattern 119 may be embedded in the temporary adhesive layer 52. The temporary adhesive layer 52 may include any suitable one or more materials that can be removed by applying external energy (e.g., ultraviolet light, visible light, heat, etc.) to the temporary adhesive layer 52. In a subsequent de-bonding process, the temporary carrier 51 can be peeled off from the first redistributed wiring structure 110 by removing the temporary adhesive layer 52.

[0025] In some embodiments where the temporary adhesive layer 52 is sufficiently thick, the pad portion 119P of the outermost conductive pattern 119 (or the surface treatment layer 1191 covering the pad portion 119P, if present) is separated from the temporary carrier 51 by the temporary adhesive layer 52. Figure 6As shown in the enlarged view, the pad portion 119P of the outermost conductive pattern 119 protrudes from the outermost surface 118t of the outermost dielectric layer 118. The outermost surface 118t of the outermost dielectric layer 118 and the outermost surface 119Pt of the pad portion 119P (or the outermost surface 1191t of the surface treatment layer 1191, if any) can be collectively referred to as the outermost surface 110t of the first redistributed wiring structure 110, and the outermost surface 110t is uneven. The temporary adhesive layer 52 can completely cover the unevenness of the outermost surface 110t of the first redistributed wiring structure 110. For example, as shown in the enlarged view, the top surface 52t of the temporary adhesive layer 52 connected to the temporary carrier 51 is higher than the outermost surface 119Pt of the pad portion 119P (or the outermost surface 1191t of the surface treatment layer 1191, if any). The top surface 52t of the temporary adhesive layer 52 may be flatter than the outermost surface 110t of the first re-laid circuit structure 110.

[0026] Continue to refer to Figure 6 The temporary carrier plate 51 of the temporary protective structure 50 may be provided in sheet, film, or similar form. In some embodiments where the temporary carrier plate 51 is a temporary sheet, the temporary carrier plate 51, provided with a temporary adhesive layer 52, can absorb surface non-planarity of the first re-laid circuit structure 110, wherein the surface non-planarity (or uneven surface) of the first re-laid circuit structure 110 is caused by the contour (or morphology) of the pad portion 119P and the outermost dielectric layer 118. In embodiments where the temporary carrier plate 51 is provided in sheet form, the temporary carrier plate 51 is made of one or more inorganic materials (e.g., glass, metal, ceramic, combinations thereof). In some embodiments where the temporary carrier plate 51 is a temporary sheet, the temporary carrier plate 51 resists process chemicals of subsequently performed processes (e.g., forming a second re-laid circuit structure). The Young's modulus of the temporary carrier 51, provided in sheet form, can be higher than that of any of the dielectric layers (e.g., 112, 114, 116, and 118) of the first re-laid circuit structure 110. The coefficient of thermal expansion (CTE) of the temporary carrier 51, provided in sheet form, can be greater than that of the core layer 101 (e.g., made of glass). Because the temporary carrier 51 has a higher CTE, warping of the first re-laid circuit structure 110 formed on the first side 101a of the core layer 101 can be compensated. By selecting a suitable CTE for the temporary carrier 51, the warped structure of the first re-laid circuit structure 110 and the core layer 101 can be flattened, and overall structural warping can be reduced.

[0027] Still referencing Figure 6In some embodiments where the temporary carrier 51 is a temporary film, the temporary carrier 51 may have high chemical resistance, ensuring that process chemicals from subsequent processes (e.g., forming a second re-laid circuit structure) do not affect the temporary protective structure 50. In embodiments where the temporary carrier 51 is a temporary film, the temporary adhesive layer 52 of the temporary protective structure 50 may absorb surface non-planarity of the first re-laid circuit structure 110 caused by the contours of the pad portion 119P and the outermost dielectric layer 118. Regardless of the type of temporary carrier 51 (e.g., sheet, film, or similar), the temporary protective structure 50 can serve as a warp control structure. By bonding the temporary protective structure 50 to the first re-laid circuit structure 110, the overall planarity (e.g., flatness) of the structure can be controlled and / or improved.

[0028] refer to Figure 7 and Figure 6 Flipable Figure 6 The structure shown is followed by subsequent processing on the second side 101b of the core layer 101. For example, a CTE mismatch between the core layer 101 and the first redistribution circuit structure 110 may cause warping. As previously described, the temporary protection structure 50 can serve as a warping control structure, and by selecting a suitable CTE for the temporary carrier 51 of the temporary protection structure 50, the warped structure of the core layer 101 and the first redistribution circuit structure 110 can be flattened, and the overall warping of the structure can be reduced. In some embodiments, the structure of the core layer 101 and the first redistribution circuit structure 110 has a concave warping (the cross-section of the warped portion is smiling), as shown by arrow A1. In the case of concave warping, the central portion of the structure is lower than the peripheral portion of the structure relative to the temporary protection structure 50. The material of the temporary carrier 51 can be selected to have a CTE lower than that of the dielectric layer of the first redistribution circuit structure 110. For example, the temporary protection structure 50 may have a convex warping (the cross-section of the warped portion is crying), as shown by arrow A2. By joining a temporary protective structure 50 with convex warping to a structure with concave warping, the overall warping of the joined structure can be reduced.

[0029] refer to Figure 8 and Figure 7A second re-layout wiring structure 120 is formed on the second side 101b of the core layer 101 and connected to the core via 103, wherein a temporary protective structure 50 may serve as a support during the formation of the second re-layout wiring structure 120. The material and formation of the second re-layout wiring structure 120 may be similar to those of the first re-layout wiring structure 110. For example, a plurality of second conductive pads 121 are formed on the second side 101b of the core layer 101 and connected to the core via 103. In some embodiments, the second conductive pads 121 and the core via 103 are configured in a one-to-one manner. For example, the spacing between two adjacent second conductive pads 121 is smaller than the spacing SP1 of the core vias 103 (marked in...). Figure 1 (in the middle) and on the order of several micrometers to facilitate high-density layout. In some embodiments, the spacing between two adjacent second conductive pads 121 is substantially equal to the spacing SP2 of the first conductive pads 111 (marked in Figure 2 (in the middle). In an alternative embodiment, the second conductive pad 121 may have a larger line width / spacing (L / S) than the first conductive pad 111.

[0030] Next, a first dielectric layer 122 having multiple openings 122P may be formed on the second side 101b of the core layer 101 and partially cover the second conductive pads 121. For example, at least a portion of each second conductive pad 121 is exposed by the openings 122P for further electrical connection. The material of the first dielectric layer 122 may be the same as or similar to the material of the first dielectric layer 112. Then, a first conductive pattern 123 may be formed in and on the first dielectric layer 122. For example, the first conductive pattern 123 includes multiple via portions 123V formed in the openings 122P of the first dielectric layer 122 for physical and electrical contact with the corresponding second conductive pads 121. Each via portion 123V may taper in a direction from the second side 101b toward the first side 101a. That is, the taper direction of the via portion 123V is opposite to the taper direction of the via portion 113V of the first conductive pattern 113. The first conductive pattern 123 may further include a plurality of pad portions 123P connected to the via portion 123V and overlying the first dielectric layer 122. The first conductive pattern 123 may further include a plurality of line portions (not shown) connected to the pad portions 123P and extending horizontally on the first dielectric layer 122.

[0031] Continue to refer to Figure 8After the first conductive pattern 123 is formed, a second dielectric layer 124 having multiple openings 124P can be formed on the first dielectric layer 122 to cover the first conductive pattern 123. For example, a portion of the first conductive pattern 123 is exposed by the openings 124P of the second dielectric layer 124. Then, a second conductive pattern 125 can be formed on the second dielectric layer 124 and fill the openings 124P of the second dielectric layer 124 to make physical and electrical contact with the first conductive pattern 123. Next, a third dielectric layer 126 having multiple openings 126P can be formed on the second dielectric layer 124 to cover the second conductive pattern 125. Then, a third conductive pattern 127 may be formed on the third dielectric layer 126 and fill the openings 126P of the third dielectric layer 126 to make physical and electrical contact with the second conductive pattern 125. Then, an outermost dielectric layer 128 having a plurality of openings 128P is formed on the third dielectric layer 126 to cover the third conductive pattern 127. Then, an outermost conductive pattern 129 may be formed on the outermost dielectric layer 128 and fill the openings 128P of the outermost dielectric layer 128 to make physical and electrical contact with the third conductive pattern 127.

[0032] Still referencing Figure 8 Surface treatment processes are selectively applied to the pad portions 129P of the outermost conductive pattern 129 for subsequent mounting processes. For example, a surface treatment layer 1291 is conformally deposited on the outermost surface of each pad portion 129P of the outermost conductive pattern 129. The combination of dielectric layers (e.g., 122, 124, 126, and 128), conductive patterns (e.g., 123, 125, 127, and 129), and the second conductive pad 121 can be collectively referred to as the second redistribution circuit structure 120. It should be understood that the configuration of the second redistribution circuit structure 120 shown herein is for illustrative purposes only, and the number of dielectric layers and conductive patterns can be selected according to product and circuit requirements, and the present invention does not impose any limitations thereon.

[0033] refer to Figure 9 and Figure 8One or more chips 210 can be mounted on the second redistribution structure 120 via chip contacts 212. Chips 210 can perform various electrical functions required for a specific application. Chips 210 can be of the same type or can include different types of devices. For example, chip 210_1 is a three-dimensional (3D) chip comprising multiple stacked semiconductor substrates. Chip 210_2 can also be a 3D chip or a different type of chip performing a different function than chip 210_1. In some embodiments, each chip 210 includes an active side 210a facing the second redistribution structure 120, a back side 210b opposite to the active side 210a, and sidewalls 210c connected to the active side 210a and the back side 210b. Chip contacts 212 are disposed on the active side 210a and can be or may include controlled-collapse chip connection (C4) bumps, microbumps, etc.

[0034] In some embodiments, each chip contact 212 includes a pillar portion 212P connected to the active side 210a and a cap portion 212C connecting the pillar portion 212P to a corresponding pad portion 129P (or surface treatment layer 1291, if present) of the second redistribution wiring structure 120. The pillar portion 212P and the cap portion 212C may be made of different materials. For example, the pillar portion 212P may comprise copper or the like, while the cap portion 212C may comprise solder. A reflow process may be performed on the cap portion 212C to physically and electrically couple the chip contact 212 to the pad portion 129P (or surface treatment layer 1291, if present) of the second redistribution wiring structure 120. The second redistribution wiring structure 120 may have finely pitched circuitry to meet the input / output (I / O) spacing requirements of the chip 210.

[0035] refer to Figure 10 and Figure 9An insulating layer 215 may be formed on the outermost dielectric layer 128 of the second redistributed wiring structure 120 to cover the chip 210 for protection. For example, the insulating layer 215 extends along the sidewalls 210c of each chip 210 and further into the gap between the active side 210a of each chip 210 and the pad portion 129P of the second redistributed wiring structure 120 to surround each chip contact 212 and each pad portion 129P (or surface treatment layer 1291, if present). The insulating layer 215 may be or may include molding compounds, molding underfills, or the like, and may be formed by molding processes or other suitable processes. Other types of insulating materials may be used. A planarization process may be selectively performed on the insulating layer 215 until the back side 210b of one or more chips 210 is exposed. For example, the back side 210b of one or more chips 210 is substantially coplanar with the top surface 215t of the insulating layer 215. As an alternative, the formation of insulating layer 215 is omitted.

[0036] refer to Figure 11 and Figure 10 The temporary protective structure 50 can be removed to expose the pad portion 119P of the outermost conductive pattern 119 (or surface treatment layer 1191, if present) and the outermost dielectric layer 118 of the first redistributed wiring structure 110. For example, the removal process of the temporary protective structure 50 includes applying external energy (e.g., ultraviolet light, visible light, heat, etc.) to the temporary adhesive layer 52 to weaken (or decompose) the temporary adhesive layer 52, thereby reducing or eliminating its adhesion. The temporary adhesive layer 52 and the temporary carrier 51 can then be peeled or stripped from the first redistributed wiring structure 110 together. Other suitable techniques (etching or the like) can be used to separate the temporary protective structure 50 from the first redistributed wiring structure 110.

[0037] In some embodiments, after the temporary adhesive layer 52 is peeled off from the first overlay wiring structure 110, some residue 521 of the temporary adhesive layer 52 may remain in the seam M1 of the first overlay wiring structure 110, as shown in the enlarged view illustrated in dashed box A. The seam M1 may include fine spacing between adjacent pad portions 119P, such as at the interface between the outermost dielectric layer 118 and the outermost conductive pattern 119 (or surface treatment layer 1191, if any).

[0038] A cleaning process (e.g., plasma treatment or the like) is selectively performed on the outermost surface 110t of the first redistributed circuit structure 110 to remove residues 521 remaining on the outermost surface 110t of the first redistributed circuit structure 110. In some embodiments, the surface roughness of the outermost surface 118t of the outermost dielectric layer 118 is increased by the cleaning process (e.g., surface treatment). For example, the surface roughness of the outermost surface 118t of the outermost dielectric layer 118 is greater than the surface roughness of the surface 116t of the third dielectric layer 116 facing (or connected to) the outermost dielectric layer 118. As can be seen from the top view of dashed box B, the surface 116t of the third dielectric layer 116 is relatively smooth and no ripples are formed thereon. As shown in dashed box C, ripples are formed on the outermost dielectric layer 118 due to the plasma treatment, resulting in a rough surface (i.e., the outermost surface 118t), as shown in the top view. The portion of the outermost surface 118t, including the corrugations, can be considered a rough portion of the outermost dielectric layer 118. In some embodiments, after a cleaning process, some residue 521 of the temporary adhesive layer 52 may still remain on the slits M1 of the first redistributed wiring structure 110. In this case, a portion of the outermost surface 118t of the outermost dielectric layer 118 may be protected from damage by the residue 521. For example, the portion of the outermost surface 118t of the outermost dielectric layer 118 with the residue 521 is smoother than another portion of the outermost surface 118t of the outermost dielectric layer 118 where corrugations are formed.

[0039] Still referencing Figure 11 A semiconductor structure 10 is provided. For example, the semiconductor structure 10 includes a substrate 100 having a first side 100a and a second side 100b opposite to the first side 100a, one or more chips 210 disposed on and electrically connected to the second side 100b of the substrate 100, and an insulating layer 215 selectively formed on the second side 100b of the substrate 100 to cover the one or more chips 210. The substrate 100 may include a core layer 101, a core via 103 penetrating the core layer 101 to provide a vertical and electrical connection between the first side 101a and the second side 101b of the core layer 101, a first redistribution circuit structure 110 disposed on the first side 101a of the core layer 101 and electrically coupled to the core via 103, and a second redistribution circuit structure 120 disposed on the second side 101b of the core layer 101 and electrically coupled to the one or more chips 210 through the core via 103.

[0040] In some embodiments, the first redistribution circuit structure 110 and the second redistribution circuit structure 120 are arranged symmetrically with respect to the core layer 101. For example, the number of dielectric layers (e.g., 112, 114, 116, and 118) in the first redistribution circuit structure 110 is equal to the number of dielectric layers (e.g., 122, 124, 126, and 128) in the second redistribution circuit structure 120. In some embodiments, conductive pads (e.g., 111 and 121) and conductive patterns (e.g., 113, 115, 117, 119, 123, 125, 127, and 129) are arranged symmetrically on opposite sides (e.g., 101a and 101b) of the core layer 101. The core vias 103 formed in the core layer 101 can be arranged in a dense manner, allowing the circuitry formed on opposite sides (e.g., 101a and 101b) of the core layer 101 to be configured as fine-pitch redistribution layers (RDLs), thus meeting the requirements of fine-pitch chip contacts 212. Therefore, the substrate 100 of the semiconductor structure 10 can be considered a double-sided high-density substrate. This semiconductor structure 10 is suitable for any high-density application.

[0041] Figure 12 This is a schematic cross-sectional view illustrating a double-sided high-density substrate according to some embodiments. Figure 11 and Figure 12 And the same reference numerals are used in the description to refer to the same or similar components. Reference Figure 12 and Figure 11 , Figure 12 The substrate 200 shown is Figure 11 The substrate 100 is similar to that in the previous example, so details will not be repeated here. The substrate 200 includes: a core layer 101 including a first side 101a and a second side 101b opposite to the first side 101a; a core via 103 penetrating the core layer 101 to provide a vertical and electrical connection between the first side 101a and the second side 101b; a first redistributed wiring structure 110 disposed on the first side 101a of the core layer 101 and electrically coupled to the core via 103; and a second redistributed wiring structure 220 disposed on the second side 101b of the core layer 101 and electrically coupled to the first redistributed wiring structure 110 through the core via 103.

[0042] Continue to refer to Figure 12The second redistribution wiring structure 220 may include a plurality of second conductive pads 121, a first dielectric layer 222 covering the second side 101b of the core layer 101 and exposing at least a portion of each second conductive pad 121, a first conductive pattern 223 including a plurality of via portions 223V passing through the first dielectric layer 222 to land on the corresponding second conductive pads 121 and a plurality of pad portions 223P covering the first dielectric layer 222 and connected to the via portions 223V, an outermost dielectric layer 224 covering the first dielectric layer 222 and exposing at least a portion of each pad portion 223P, and an outermost conductive pattern 225 including a plurality of via portions 225V passing through the outermost dielectric layer 224 to land on the corresponding pad portions 223P and a pad portion 225P covering the outermost dielectric layer 224 and connected to the via portions 225V. In some embodiments, the surface treatment layer 2251 is conformally deposited on the outer surface of each pad portion 225P of the outermost conductive pattern 225. Alternatively, the surface treatment layer 2251 is omitted.

[0043] In some embodiments, one or more dielectric layers (e.g., 222 and 224) of the second redistributed circuit structure 220 are made of a material (e.g., ABF or similar) that is different from the material of the dielectric layers (e.g., 112, 114, 116, and 118) of the first redistributed circuit structure 110. The first redistributed circuit structure 110 and the second redistributed circuit structure 220 may be arranged asymmetrically. For example, the number of dielectric layers (e.g., 222, 224) of the second redistributed circuit structure 220 may be less than the number of dielectric layers (e.g., 112, 114, 116, 118) of the first redistributed circuit structure 110. Alternatively, the number of dielectric layers of the second redistributed circuit structure 220 may be greater than the number of dielectric layers of the first redistributed circuit structure 110. Conductive patterns (e.g., 113, 115, 117, 119, 223, and 225) may be arranged asymmetrically on opposite sides (e.g., 101a and 101b) of the core layer 101. For example, the size (e.g., thickness, width, length, etc.) of the conductive patterns (e.g., 223, 225) of the second redistributed circuit structure 220 is larger than the size of the conductive patterns (e.g., 113, 115, 117, 119) of the first redistributed circuit structure 110. In some embodiments, the linewidth / spacing of the conductive patterns (e.g., 223 and 225) of the second redistributed circuit structure 220 is larger than the linewidth / spacing of the conductive patterns (e.g., 113, 115, 117, and 119) of the first redistributed circuit structure 110. For example, the second redistributed circuit structure 220 is considered a coarse redistributed circuit structure including coarse circuitry, while the first redistributed circuit structure 110 is considered a fine redistributed circuit structure including fine circuitry. With this configuration, the substrate 200 can achieve high-density integration suitable for a variety of high-density applications.

[0044] Figure 13 This is a schematic cross-sectional view illustrating a double-sided high-density substrate according to some embodiments. Figure 5 , Figure 12 and Figure 13 And the same reference numerals are used in the description to refer to the same or similar components. (See also:) Figure 13 , Figure 5 and Figure 12 , Figure 13 The substrate 300 shown is Figure 12 Similar to substrate 200, but differing in that substrate 300 also includes a third redistributed circuit structure 220_1 disposed on the first side 101a and between the core layer 101 and the first redistributed circuit structure 110. The third redistributed circuit structure 220_1 may be similar to the second redistributed circuit structure 220. For example, the third redistributed circuit structure 220_1 is also a coarse redistributed circuit structure. In some embodiments, the circuitry in both the second redistributed circuit structure 220 and the third redistributed circuit structure 220_1 is coarser than the circuitry in the first redistributed circuit structure 110.

[0045] Continue to refer to Figure 13 The via portion 223V of the first conductive pattern 223 can land on the second conductive pad 121, and the via portion 225V of the second conductive pattern 225 can connect the pad portion 223P of the first conductive pattern 223 to the first conductive pad 111 of the first redistributed circuit structure 110. The first dielectric layer 222 of the third redistributed circuit structure 220_1 can overlap with the core layer 101, and the second dielectric layer 224 can be located between the first dielectric layer 222 and the first redistributed circuit structure 110.

[0046] Figure 14 This is a schematic cross-sectional view illustrating a semiconductor structure with a double-sided high-density substrate, according to some embodiments. Figure 13 and Figure 14 The same reference numerals are used in the description to refer to the same or similar components. Reference Figure 14 Also refer to Figure 13 and Figure 11 A semiconductor structure 20 including a substrate 300 and a chip 210 can be provided. The chip 210 is electrically coupled to a first redistributed circuit structure 110 via chip contacts 212 and can be laterally covered by an insulating layer 215. The configuration of the chip 210 can be... Figure 11 The chip 210 is similar, so details will not be repeated here.

[0047] Figure 15 This is a schematic cross-sectional view illustrating a double-sided high-density substrate according to some embodiments. Figure 11 , Figure 12 and Figure 15And the same reference numerals are used in the description to refer to the same or similar components. Reference Figure 15 , Figure 11 and Figure 13 , Figure 15 The substrate 400 shown is with Figure 13 Similar to substrate 200, except that substrate 400 also includes an additional second redistribution circuit structure 120 coupled to the second redistribution circuit structure 220. The additional second redistribution circuit structure 120 can be coupled to... Figure 11 The second overlay circuit structure 120 shown is similar. For example, the second conductive pad 121 of the additional second overlay circuit structure 120 rests on the via portion 225V of the second overlay circuit structure 220. The additional second overlay circuit structure 120 may be referred to as a fine overlay circuit structure. In some embodiments, the circuitry in the second overlay circuit structure 220 and the third overlay circuit structure 220_1 is thicker than the circuitry in the additional second overlay circuit structure 120.

[0048] Figure 16 This is a schematic cross-sectional view illustrating a semiconductor structure with a double-sided high-density substrate, according to some embodiments. Figure 15 and Figure 16 The same reference numerals are used in the description to refer to the same or similar components. Reference Figure 16 and Figure 15 A semiconductor structure 30 including a substrate 400 and a chip 210 can be provided. A first portion of the chip 210 is electrically coupled to a first redistributed circuit structure 110 and may be laterally covered by an insulating layer 215. A second portion of the chip 210 is electrically coupled to an additional second redistributed circuit structure 120 and may be laterally covered by an insulating layer 215. The configuration of the chip 210 can be... Figure 11 The chip 210 is similar, so details will not be repeated here.

[0049] Based on the above, the semiconductor structure includes a substrate comprising double-sided fine circuitry fabricated using a single-sided process. For example, after the fine circuitry is formed (or partially formed) on one side of the core layer, the structure is protected and supported by a temporary protective structure (see...). Figure 6 Then, using a temporary protective structure for support and protection, subsequent processes are performed on the other side of the core layer. Another fine circuit (or...) is formed on the other side of the core layer. Figure 12 After the rough circuit shown, the temporary protective structure is removed, thus forming the double-sided circuit substrate. Using a temporary protective structure during substrate formation helps compensate for warpage of the semi-finished product and reduces surface non-planarity (see...). Figure 6 and Figure 7 In this way, the overall flatness of the substrate can be improved, as well as the reliability and yield of the semiconductor structure.

[0050] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, including: The core layer includes a first side and a second side opposite to the first side; A core perforation, penetrating the core layer; A first redistribution circuit structure is disposed on the first side of the core layer. The first redistribution circuit structure includes an outermost dielectric layer, an outermost conductive pattern disposed in and on the outermost dielectric layer and electrically coupled to the core via, and an inner dielectric layer between the outermost dielectric layer and the core layer. The outermost surface of the outermost dielectric layer includes a portion that is rougher than the surface of the inner dielectric layer facing the outermost dielectric layer. The second re-laid circuit structure is disposed on the second side of the core layer and electrically coupled to the first re-laid circuit structure through the core perforation.

2. The semiconductor structure according to claim 1, characterized in that, The residue of the temporary adhesive layer remains on another portion of the outermost surface of the outermost dielectric layer.

3. The semiconductor structure according to claim 2, characterized in that, The residue of the temporary adhesive layer is located at the spacing of the plurality of pad portions of the outermost conductive pattern.

4. The semiconductor structure according to claim 2, characterized in that, The portion of the outermost surface of the outermost dielectric layer has a surface roughness greater than that of the other portion of the outermost surface of the outermost dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that, The first and second re-laid circuit structures are arranged symmetrically with respect to the core layer.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: A third layer of wiring structure is disposed between the first layer of wiring structure and the core layer, wherein the circuits in both the second and third layers of wiring structure are thicker than the circuits in the first layer of wiring structure.

7. The semiconductor structure according to claim 6, characterized in that, Also includes: A fourth overlay circuit structure is coupled to a second overlay circuit structure, which is located between the core layer and the fourth overlay circuit structure, wherein the circuit in the second overlay circuit structure is thicker than the circuit in the fourth overlay circuit structure.

8. The semiconductor structure according to claim 1, characterized in that, The core layer of the substrate is made of an inorganic material.

9. The semiconductor structure according to claim 1, characterized in that, The first redistribution circuit structure further includes a surface treatment layer, which conformally covers the outermost conductive pattern disposed on the outermost dielectric layer.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: The chip is disposed on the second redistributed circuit structure on the substrate and electrically coupled to the second redistributed circuit structure.

11. A method for manufacturing a semiconductor structure, characterized in that, include: A core perforation is formed in the core layer, wherein the core layer includes a second side opposite to the first side and the first side, and the core perforation extends between the first side and the second side; A first redistribution circuit structure is formed on the first side of the core layer; A temporary protective structure is attached to the first redistributed circuit structure, wherein the temporary protective structure includes a temporary carrier board and a temporary adhesive layer for attaching the temporary carrier board to the outermost surface of the first redistributed circuit structure, and the surface flatness of the temporary adhesive layer attached to the temporary carrier board is better than the surface flatness of the outermost surface of the first redistributed circuit structure. A second redistribution circuit structure is formed on the second side of the core layer using the temporary protective structure as support. as well as The temporary protective structure is stripped from the first re-laid circuit structure.

12. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, The outermost surface of the first redistributed circuit structure includes the outermost surface of the outermost conductive pattern and the outermost surface of the outermost dielectric layer.

13. The method for manufacturing the semiconductor structure according to claim 12, characterized in that, After the temporary protective structure is peeled off from the first redistribution circuit structure, the residue of the temporary adhesive layer remains on the outermost surface of the outermost dielectric layer and at the spacing of the multiple pad portions of the outermost conductive pattern.

14. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, The removal of the temporary protective structure from the first redistributed line structure includes: A cleaning process is performed on the first redistributed circuit structure, wherein after the cleaning process, the outermost surface of the first redistributed circuit structure is formed on a portion of the outermost surface of the outermost dielectric layer, and the surface roughness of the portion of the outermost surface of the outermost dielectric layer is greater than the surface roughness of the surface of the dielectric layer of the first redistributed circuit structure facing the outermost dielectric layer.

15. The method for manufacturing the semiconductor structure according to claim 14, characterized in that, After the cleaning process, the residue of the temporary adhesive layer remains on another portion of the outermost surface of the outermost dielectric layer, and the surface roughness of that portion of the outermost surface of the outermost dielectric layer is greater than the surface roughness of the other portion of the outermost surface of the outermost dielectric layer.

16. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, The thermal expansion coefficient of the temporary carrier plate is greater than that of the core layer.

17. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, The Young's modulus of the temporary carrier plate is greater than that of the dielectric material in the first redistribution circuit structure.

18. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, in: After the first re-layout circuit structure is formed, the first re-layout circuit structure and the core layer warp, and Joining the temporary protective structure to the first redistribution line structure includes using the temporary protective structure to flatten the warpage of the first redistribution line structure and the core layer.

19. The method for manufacturing the semiconductor structure according to claim 11, characterized in that, Also includes: The chip is coupled to the second redistribution circuit structure, wherein the temporary protection structure acts as a support during the coupling of the chip to the second redistribution circuit structure.

20. The method for manufacturing the semiconductor structure according to claim 19, characterized in that, Also includes: An insulating layer is formed on the second redistribution circuit structure to cover the chip, wherein the temporary protective structure serves as a support during the formation of the insulating layer.

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