Cell multi-inverter

Abstract

In a unit multiple inverter in which a plurality of units are connected in a star connection to each phase of an alternating current power grid in multiple, even when an unbalance in the alternating current voltage occurs or an unbalanced alternating current voltage is intentionally output, it is not necessary to insert a unit for the corresponding phase or to raise only the unit direct current voltage for the corresponding phase, and further, a common mode current is suppressed. A phase voltage detection signal v U , v V , v W or a voltage command value v U , v V , v W is converted into a value on a rotating coordinate synchronized with the power grid frequency and a value on a rotating coordinate rotating in the opposite direction to the power grid frequency and a direct current component is extracted. A zero phase voltage d-axis component V 1d , a zero phase voltage q-axis component V 1q , a positive phase d-axis component V 2d , and a positive phase q-axis component V 2q are operated based on the direct current components. A zero phase voltage d-axis component V 0d and a zero phase voltage q-axis component V 0q are operated. The zero phase voltage d-axis component V 0d , the zero phase voltage q-axis component V 0q are multiplied by a cosine wave, a sine wave, and are added, and are added to the voltage command value v U , v V , v W as a correction voltage command value v U ', v V ', v W '.

Description

Technical Field

[0001] This invention relates to a multi-cell inverter that uses a star connection to connect multiple cells to each phase of an AC power grid. Background Technology

[0002] As an example of a multi-level inverter, a modular multilevel cascaded converter (MMCC) for a single star bridge unit (SSBC) connected to a three-phase AC grid is known. Additionally, structures in which a power supply or DC / DC converter is separately connected to the DC side of a full-bridge unit of the MMCC-SSBC are also known.

[0003] A prime example of this structure is, for instance, the solid-state transformer (SST) shown in Patent Document 1. Figure 1 This illustrates an SST consisting of three units per phase, combining a bidirectional isolated DC / DC converter using MMCC-SSBC and dual active bridge (DAB) configurations.

[0004] It can convert high-voltage AC power into DC power using series-connected units, and then convert DC power into high-frequency AC power using a transformer for insulation and rectification, thereby converting it back into DC power. Reverse power exchange is also possible. Regarding SST, because it uses a high-frequency transformer, it can be made smaller than existing power frequency transformers.

[0005] In addition, the high-voltage multi-inverter of Patent Document 2 also meets the requirements for other applications.

[0006] When connected to an unbalanced three-phase AC grid via SST, or when an unbalanced three-phase AC voltage is intentionally output using a high-voltage multi-inverter, the phase voltage amplitude of a certain phase will increase, and the AC voltage that the unit connected to that phase should output will also increase.

[0007] To address this, the DC voltage of the unit needs to be increased, but the required withstand voltage of the components also needs to be increased, leading to increased cost and size. If high-voltage switching devices are used in the unit, it will also lead to increased losses.

[0008] In addition, depending on the device, continuous operation is sometimes required even if some units fail.

[0009] Patent document 1 discloses the main circuit structure of SST, and patent document 2 discloses the structure of high voltage multi-inverter.

[0010] Patent documents 3 and 4 disclose methods for continuous operation when a cell fails. In both documents, the faulty cell is first short-circuited. However, this alone would reduce the AC voltage amplitude output by the phase with the faulty cell. Therefore, in patent document 3, a pre-prepared spare cell is connected to the corresponding phase. In patent document 4, the DC voltage of the non-faulty cell in the corresponding phase is increased.

[0011] Patent documents 5 and 6 disclose a technique for addressing voltage imbalance in MMCC-SSBC by using a zero-phase voltage. The purpose of this technique is to balance the capacitor voltages of each cell.

[0012] Patent Document 7 describes a technique for reducing the peak value of the voltage command value by superimposing the zero-phase voltage onto the voltage command value of a single-unit 3-phase inverter that has not undergone unit multiplexing. This technique can also handle unbalanced three-phase AC voltage outputs, ensuring that the peak values ​​of the voltage command values ​​for each phase are equal. The technology in Patent Document 7 can be applied to MMCC-SSBC and high-voltage multiplexed inverters.

[0013] Existing technical documents

[0014] Patent documents

[0015] Patent Document 1: Japanese Patent Application Publication No. 10-75580

[0016] Patent Document 2: Japanese Patent Application Publication No. 11-122943

[0017] Patent Document 3: Japanese Patent Application Publication No. 2012-147613

[0018] Patent Document 4: WO2017 / 094379A1

[0019] Patent Document 5: Japanese Patent Application Publication No. 2013-5694

[0020] Patent Document 6: Japanese Patent Application Publication No. 2021-19481

[0021] Patent Document 7: Japanese Patent Application Publication No. 3-107373 Summary of the Invention

[0022] The technical problem that the invention aims to solve

[0023] However, neither Patent Documents 1 nor 2 specifically mentions methods for dealing with situations such as grid connection to an unbalanced power grid, output of unbalanced voltage, or unit failure.

[0024] Patent document 3 requires assembling the backup unit into the device, and also necessitates a switch for engaging the backup unit, thus increasing cost and size. Furthermore, not using the backup unit if no fault occurs could also lead to waste.

[0025] In Patent Document 4, in order to increase the DC voltage of other units in the corresponding phase, the unit design needs to be based on this, resulting in increased cost, size, and losses. Furthermore, neither Patent Documents 3 nor 4 describe methods for addressing voltage imbalance.

[0026] In Patent Documents 5 and 6, only capacitors are connected to the DC side of each unit, envisioning applications that do not involve active power, such as reactive power compensation devices. However, in high-voltage multi-inverter or SST systems, since there is an additional path for active power, this path can be used to perform power exchange between units and balance the capacitor voltage. Therefore, the importance of the technology in Patent Documents 5 and 6 is reduced. Furthermore, neither Patent Documents 5 nor 6 describes methods for dealing with unit failures.

[0027] In Patent Document 7, an odd-numbered harmonic of 3 is superimposed as the zero-phase voltage. However, the higher the frequency of the superimposed zero-phase voltage, the greater the common-mode current flowing through the stray capacitance of the circuit. This may cause numerous problems, such as increased component heating, reduced efficiency, malfunction of the ground fault detector, insulation breakdown of the high-frequency transformer, and electromagnetic interference to other equipment. Therefore, it is necessary to reduce the frequency of the superimposed zero-phase voltage. Furthermore, Patent Document 7 does not describe a method for dealing with unit faults.

[0028] Based on the above, in a multi-unit inverter that connects multiple units to each phase of the AC grid in a star configuration, the technical challenge is that even when an imbalance occurs in the AC voltage or an unbalanced AC voltage is intentionally output, there is no need to adjust the DC voltage of the corresponding phase connected unit or only increase the DC voltage of the corresponding phase unit, thereby suppressing the common-mode current.

[0029] Technical solutions for solving technical problems

[0030] The present invention addresses the aforementioned problems in the prior art, and one aspect of it is a unit-multiplexed inverter comprising: multiple units connected in a star configuration to each phase of an AC power grid, having a full-bridge circuit on the AC power grid side; a correction voltage command value generation unit that superimposes a zero-phase voltage with the same frequency as the fundamental frequency onto a voltage command value to generate a correction voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value. The unit-multiplexed inverter is characterized in that the correction voltage command value generation unit superimposes the zero-phase voltage with the same frequency as the fundamental frequency onto the voltage command value in a manner that reduces the amplitude difference of the correction voltage command values ​​for each phase.

[0031] Alternatively, a unit-multiplexed inverter includes: multiple units connected in a star configuration to each phase of an AC grid, having a full-bridge circuit on the AC grid side; a correction voltage command value generation unit that superimposes a zero-phase voltage with the same frequency as the fundamental frequency onto a voltage command value to generate a correction voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value. The unit-multiplexed inverter is characterized in that the correction voltage command value generation unit superimposes the zero-phase voltage with the same frequency as the fundamental frequency in a manner that minimizes the difference between the three phases between the values ​​obtained by multiplying the amplitude of the correction voltage command value for each phase by the number of units in each phase and then dividing by the number of units currently operating without faults in each phase.

[0032] Additionally, as one embodiment, the correction voltage command value generation unit comprises: a phase output unit that outputs a phase ωt synchronized with the AC voltage of the power grid; a first dq converter that converts the phase voltage detection signal or the voltage command value, or the value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of units in each phase by the number of units currently operating without faults in each phase, into a value on a rotating coordinate synchronized with the power grid frequency; a second dq converter that converts the phase voltage detection signal or the voltage command value, or the value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of units in each phase by the number of units currently operating without faults in each phase, into a value on a rotating coordinate that rotates in the opposite direction to the power grid frequency; and an arithmetic unit that, based on the first... The positive-phase d-axis component and positive-phase q-axis component obtained by extracting the DC component from the output of the dq converter, and the negative-phase d-axis component and negative-phase q-axis component obtained by extracting the DC component from the output of the second dq converter, are used to calculate the zero-phase voltage d-axis component and zero-phase voltage q-axis component that make the AC side output voltage of each unit uniform; a first multiplier multiplies the zero-phase voltage d-axis component by cosωt or sinωt; a second multiplier multiplies the zero-phase voltage q-axis component by sinωt when multiplied by cosωt by the first multiplier, and multiplies the zero-phase voltage q-axis component by cosωt when multiplied by sinωt by the first multiplier; a first adder adds the output of the first multiplier to the output of the second multiplier; and a second adder adds the output of the first adder to the voltage command value and outputs it as the corrected voltage command value.

[0033] In addition, as one aspect, the arithmetic unit is characterized by calculating the d-axis component and the q-axis component of the zero-phase voltage based on equation (3).

[0034] [Mathematical Expression 3] (3) V 0dd-axis component of zero-phase voltage V 0q q-axis component of zero-phase voltage V 1d d-axis component of positive phase voltage V 1q q-axis component of positive phase voltage V 2d d-axis component of negative phase voltage V 2q : Negative phase voltage q-axis component.

[0035] In addition, as another method, the feature is that the arithmetic unit calculates the d-axis component of the zero-phase voltage and the q-axis component of the zero-phase voltage based on equation (4).

[0036] [Mathematical Expression 4] (4) V 0d d-axis component of zero-phase voltage V 0q q-axis component of zero-phase voltage V 1d d-axis component of positive phase voltage V 1q q-axis component of positive phase voltage V 2d d-axis component of negative phase voltage V 2q : Negative phase voltage q-axis component.

[0037] In addition, as another method, the feature is that the arithmetic unit calculates the d-axis component and the q-axis component of the zero-phase voltage based on equation (5).

[0038] [Mathematical Expression 5] (5) V 0d d-axis component of zero-phase voltage V 0q q-axis component of zero-phase voltage V 2d d-axis component of negative phase voltage V 2q q-axis component of negative phase voltage V1: Positive phase component of voltage.

[0039] Furthermore, as one aspect, it is characterized in that the correction voltage command value generation unit generates the value in the negative phase d-axis component V. 2d =V 1d And the negative phase q-axis component V 2q When = 0, the d-axis component V of the zero-phase voltage is made to... 0d =-V1d / 2. The zero-phase voltage q-axis component V 0q =0, in the negative phase d-axis component V 2d =-V 1d / 2 and the negative phase q-axis component V 2q =- V 1d When / 2, the d-axis component V of the zero-phase voltage is made to 0d =V 1d / 4. The zero-phase voltage q-axis component V 0q = V 1d / 4, in the negative phase d-axis component V 2d =-V 1d / 2 and the negative phase q-axis component V 2q = V 1d When / 2, the d-axis component V of the zero-phase voltage is made to 0d =V 1d / 4. The zero-phase voltage q-axis component V 0q =- V 1d / 4.

[0040] Invention Effects

[0041] According to the present invention, in a multi-unit inverter in which multiple units are connected to each phase of an AC power grid in a star configuration, even when an AC voltage imbalance occurs or an unbalanced AC voltage is intentionally output, it is not necessary to connect the corresponding phase unit or only raise the DC voltage of the corresponding phase unit, thereby suppressing common-mode current. Attached Figure Description

[0042] Figure 1 This is a circuit diagram showing the main circuit structure of embodiments 1 to 3.

[0043] Figure 2 This is a circuit diagram showing other examples of the unit.

[0044] Figure 3 This is a block diagram showing the correction voltage command value generation unit of Embodiment 1.

[0045] Figure 4 This is a block diagram showing the correction voltage command value generation unit of Embodiment 2.

[0046] Figure 5 This diagram illustrates the operation when one unit of phase U fails.

[0047] Figure 6 This is a block diagram showing the correction voltage command value generation unit of Embodiment 3.

[0048] Figure Labels

[0049] AC: Alternating current grid; 1: PLL (Phase-Locked Loop); 2, 4, 5, 7, 8: 1st to 3rd low-pass filters; 3: 1st dq converter; 6: 2nd dq converter; 9: Arithmetic unit; 10: Oscillator; 11, 12: 1st and 2nd multipliers; 13-16: 1st and 2nd adders; 17: Coefficient arithmetic unit; 18-22: Comparators; 23-25: AND (Logical AND) elements; SW1-SW6: Switches. Detailed Implementation

[0050] The following is based on Figures 1-6 Detailed description of embodiments 1-3 of the unit multi-inverter of the present invention.

[0051] [Implementation Method 1]

[0052] First, let's take a single-unit multi-inverter as an example to illustrate... Figure 1 The main circuit structure of MMCC-SSBC is shown.

[0053] like Figure 1 As shown in (a), in phase U of the AC power grid, units cellu1, cellu2, and cellu3 are connected in series via reactor Lu. Similarly, in phase V of the AC power grid, units cellv1, cellv2, and cellv3 are connected in series via reactor Lv, and in phase W of the AC power grid, units cellw1, cellw2, and cellw3 are connected in series via reactor Lw. Here, let the phase voltage (phase voltage detection signal) of the AC power grid be v. U v V and v W .

[0054] The DC terminals of units cellu1, cellu2, cellu3, cellv1, cellv2, cellv3, cellw1, cellw2, and cellw3 are connected in parallel. The DC voltage of units cellu1~cellw3 is set to V. DC .

[0055] Figure 1(b) shows the structure of each unit. One end of switching devices S1 and S3 is connected to one AC terminal of the unit. Another end of switching devices S2 and S4 is connected to the other AC terminal of the unit. The other ends of switching devices S1 and S2 are connected to one end of the first capacitor C1. The other ends of switching devices S3 and S4 are connected to the other end of the first capacitor C1. These switching devices S1, S2, S3, and S4 form a full-bridge circuit on the AC side of the AC power grid.

[0056] Switching devices S5 and S6 are connected in series between one end and the other end of the first capacitor C1. Additionally, switching devices S7 and S8 are connected in series between one end and the other end of the first capacitor C1.

[0057] One end of reactor L1 is connected to the connection point of switching devices S5 and S6. One end of reactor L2 is connected to the connection point of switching devices S7 and S8. The primary winding of transformer Tr is connected between the other ends of reactor L1 and reactor L2.

[0058] A second capacitor C2 is connected between one DC terminal and the other DC terminal of the unit. Switching devices S9 and S11 are connected in series between one end and the other end of the second capacitor C2. In addition, switching devices S10 and S12 are connected in series between one end and the other end of the second capacitor C2.

[0059] One end of reactor L3 is connected to the connection point of switching devices S9 and S11. One end of reactor L4 is connected to the connection point of switching devices S10 and S12. The secondary winding of transformer Tr is connected between the other ends of reactor L3 and reactor L4. Furthermore, [the following can be omitted] Figure 1 (b) Reactors L1~L4.

[0060] exist Figure 1 In unit (b), the phase difference of the inverter output voltages on both sides of transformer Tr is adjusted to regulate the exchanged active power. Gating signals for switching devices S5-S12 are generated so that the phase difference of the inverter output voltages on both sides of transformer Tr reaches a desired phase difference (i.e., a desired exchanged active power). Since the gating signals for switching devices S5-S12 of the inverters on both sides of transformer Tr are not directly related to the present invention, detailed descriptions are omitted here, and conventionally known methods are used.

[0061] The gate signal "gate" of the switching devices S1 to S4 of the full-bridge circuit installed on the AC side of the AC power grid is input by the gate signal generated by Implementation Method 1 described later.

[0062] Figure 2Other examples of circuit diagrams for each unit are shown. In this example, an LLC resonant converter is used as a bidirectional isolated DC / DC converter.

[0063] like Figure 2 As shown, a third capacitor C3 is connected between the connection point of switching devices S5 and S6 and reactor L1. Additionally, a fourth capacitor C4 is connected between the connection point of switching devices S7 and S8 and reactor L2. Furthermore, a fifth capacitor C5 is connected between the connection point of switching devices S9 and S11 and reactor L3. Finally, a sixth capacitor C6 is connected between the connection point of switching devices S10 and S12 and reactor L4.

[0064] The NOT (Logical Not) circuit 26 inverts the 50% duty cycle signal. The dead-time section 27 inserts a dead time between the 50% duty cycle signal and the inverted 50% duty cycle signal, outputting it as a gate signal to the inverter switching devices S5-S12 on both sides of the transformer Tr. Other circuit structures are similar to... Figure 1 (b) is the same.

[0065] exist Figure 2 In this circuit, capacitors C3 to C6 (numbers 3 to 6) are connected in series with the transformer (high-frequency transformer) Tr. This creates resonance between the leakage inductance of the transformer Tr and the reactors L1 to L4, which are connected in series. The inverters on both sides of the transformer Tr output an AC voltage at this resonant frequency. The duty cycle of the gate signals driving the inverters on both sides of the transformer Tr is fixed at 50%. Thus, the active power corresponding to the difference in DC voltage across the transformer Tr is exchanged via the transformer Tr. Since the gate signals of the switching devices S5 to S12 of the inverters on both sides of the transformer Tr are not directly related to this invention, detailed descriptions are omitted here.

[0066] The gate signal "gate" of the switching devices S1 to S4 of the full-bridge circuit installed on the AC side of the AC power grid is input according to the gate signal generated according to Embodiment 1 described later.

[0067] Figure 3 This diagram shows a block diagram of the correction voltage command value generation unit of Embodiment 1. Embodiment 1 equalizes the voltage load of each unit in applications where it is not necessary to equalize the power load of each unit.

[0068] The phase output unit (e.g., PLL: Phase-Locked Loop) 1 detects the phase voltage signal v from the AC power grid. U v V v W The output phase ωt is synchronized with the AC voltage of the power grid.

[0069] As the phase voltage detection signal vU v V v W It can detect line-to-line voltage and convert it into phase voltage through calculation. Alternatively, it can replace the phase voltage detection signal v. U v V v W The voltage command value v, which will be discussed later, U v V v W The input is given to the phase output unit 1. Furthermore, the AC voltage from the mains grid input to the phase output unit 1 can be only one phase, which can be used as a representative.

[0070] In motor driver applications of high-voltage multi-inverters, the phase ωt can be detected from a rotary encoder or rotary transformer, or the phase ωt can be estimated by an observer. Hereinafter, phase output unit 1 refers to PLL1.

[0071] The first low-pass filter 2 detects the phase voltage signal v. U v V v W (Voltage command value v) U v V v W ) to filter out switching noise, etc.

[0072] The first dq converter 3 converts the phase voltage detection signal v that has passed through the first low-pass filter 2 according to the phase ωt. U v V v W Transformed into values ​​on a rotating coordinate system synchronized with the power grid frequency.

[0073] The second low-pass filters 4 and 5 extract only the DC component from the output of the first dq converter 3. In the output of the second low-pass filters 4 and 5, the d-axis component is the phase voltage detection signal v. U v V v W The positive phase d-axis component V 1d The q-axis component is the positive phase q-axis component V. 1q Since if PLL1 is working properly, the positive phase q-axis component V output by the second low-pass filter 5 will be... 1q The value is zero, therefore it is not used.

[0074] The second dq converter 6 converts the phase voltage detection signal v that has passed through the first low-pass filter 2 according to the phase -ωt. U v V vW Transformed into values ​​on a rotating coordinate system that rotates in the opposite direction to the grid frequency.

[0075] The third low-pass filters 7 and 8 extract only the DC component from the output of the second dq converter 6. The outputs of the third low-pass filters 7 and 8 are the phase voltage detection signals v, respectively. U v V v W negative phase d-axis component V 2d and negative phase q-axis component V 2q .

[0076] Arithmetic unit 9 calculates the positive phase d-axis component V based on the obtained... 1d q-axis component V 1q Negative d-axis component V 2d and negative phase q-axis component V 2q The zero-phase voltage d-axis component V is obtained using equation (3) described later. 0d and the q-axis component of the zero-phase voltage V 0q Alternatively, equation (4) or equation (5) can be used instead of equation (3) to determine the d-axis component V of the zero-phase voltage. 0d and the q-axis component of the zero-phase voltage V 0q When the amplitudes of the positive and negative phase components of the AC voltage are approximately equal, the arithmetic unit 9 outputs V. 0d =V 0q =0.

[0077] Oscillator 10 outputs a sine wave sinωt and a cosine wave cosωt according to the phase ωt.

[0078] The first multiplier 11 calculates the d-axis component V of the zero-phase voltage. 0d The product of the cosine wave and cosωt. The second multiplier (12) calculates the q-axis component V of the zero-phase voltage. 0q The product of sinωt and the sine wave.

[0079] The first adder 13 calculates the output V of the first multiplier 11. 0d cosωt and V output by the second multiplier 12 0q The sum of sinωt.

[0080] The second adders 14, 15, and 16 respectively process the voltage command value v U v V v W Add the V obtained by the first adder 13 0d cosωt+V 0q sinωt. Voltage command value v U vV v W Sometimes it is given a fixed sine wave, and sometimes it can be obtained through voltage or current feedback control. The outputs v of the second adder 14, 15, and 16... U '、v V '、v W 'To correct the voltage command value.'

[0081] For the correction voltage command value v U '、v V '、v W In the subsequent stage (gating signal generation unit), a gating signal (on / off command signal) is generated through carrier triangular wave comparison, etc., and input to... Figure 1 (b) Figure 2 Each unit has switching devices S1 to S4 in a full-bridge circuit installed on the AC side of the AC power grid. Furthermore, Patent Document 6 discloses the aforementioned gate signal generation method.

[0082] In this embodiment 1, in order to make the correction voltage command value v of each phase... U '、v V '、v W The amplitudes of the ' are equal (the difference becomes smaller), which affects the three-phase voltage command value v. U v V v W A zero-phase voltage with the same frequency as the fundamental frequency is superimposed. Therefore, the required zero-phase voltage is calculated. Assume the voltage command value v. U v V v W With AC phase voltage (phase voltage detection signal) v U v V v W They are approximately equal, and the AC phase voltage (phase voltage detection signal) is defined according to the following formula (1): v U v V v W .

[0083] [Mathematical Expression 1] (1) Here, V 1d V represents the positive d-axis component of the AC voltage. 2d For the negative d-axis component, V 2q This is the negative q-axis component. V 1q It is the positive phase q-axis component, but it is zero if PLL1 is working normally.

[0084] V 0d V 0q These are the zero-phase voltage d-axis and q-axis components superimposed according to Embodiment 1. Since the aim is to make the amplitudes of the defined AC voltages equal, the zero-phase voltage d-axis component V satisfying equation (2) is calculated. 0d and the q-axis component of the zero-phase voltage V 0q .

[0085] [Mathematical Expression 2] (2) Solving the equation yields equation (3).

[0086] [Mathematical Expression 3] (3) If the positive phase q-axis component V 1q If it is close to zero, then equation (3) can be approximated as equation (4).

[0087] [Mathematical Expression 4] (4) If the positive phase q-axis component V 1q If the value is zero, then equation (3) can be simplified to equation (5). In equation (5), V1 represents the positive phase component of the AC voltage.

[0088] [Mathematical Expression 5] (5) In this embodiment 1, the required zero-phase voltage d-axis component V is calculated based on equation (3). 0d and the q-axis component of the zero-phase voltage V 0q And superimposed on the voltage command value v U v V v W First, the phase voltage detection signal v of the AC circuit is detected. U v V v W Alternatively, you can directly input the voltage command value V. U v V v W The value is transformed into a rotating coordinate system synchronized with the grid frequency, and the DC component is extracted, thereby obtaining the positive phase d-axis component V. 1d and positive phase q-axis component V 1q Furthermore, by extracting the DC component from the values ​​on a rotating coordinate system that rotates in the opposite direction to the grid frequency, the negative phase d-axis component V can be obtained. 2d and negative phase q-axis component V 2q .

[0089] Then, equation (3) is used to calculate the d-axis component V of the zero-phase voltage. 0d and the q-axis component of the zero-phase voltage V 0q The zero-phase voltage to be superimposed is calculated based on the product of the cosine wave (cosωt) and the sine wave (sinωt), respectively, and then applied to the voltage command value v. U v V v W In grid-connected applications, since the positive q-axis component V is generated if the PLL is working normally... 1q Since the zero phase voltage d-axis component V can be calculated using equation (4) or equation (5), it is zero. 0d and the q-axis component of the zero-phase voltage V 0q .

[0090] There is no solution when the denominator in equations (3), (4), and (5) is zero, i.e., when the amplitudes of the positive and negative phase voltages are equal, and the voltage command value v for each phase cannot be obtained. U v V v W The amplitudes are equal. Therefore, when the amplitudes of the positive and negative phase voltages are approximately equal, the zero-phase voltage d-axis component V... 0d and the q-axis component of the zero-phase voltage V 0q Set to zero.

[0091] According to Embodiment 1, in a star-connected multi-unit inverter such as MMCC-SSBC, even when an AC voltage imbalance occurs or an intentionally unbalanced AC voltage is output, the AC output voltage of the units can be made equal. Therefore, even when the voltage amplitude of a certain phase increases, it is not necessary to connect the unit to that phase or only raise the DC voltage of the unit for that phase. Furthermore, since the superimposed zero-phase voltage is only the fundamental component, common-mode current can be suppressed.

[0092] In this embodiment 1, although it is necessary to increase or raise the DC voltage of all units in advance, compared with the prior art, the increase in DC voltage can be greatly suppressed, the increase in the withstand voltage of the units can be suppressed to a minimum, and the cost and size can be reduced.

[0093] Furthermore, since the zero-phase voltage superimposed in Embodiment 1 is obtained through feedforward, it can follow the AC voltage at high speed even when there are changes, and the device is theoretically highly stable.

[0094] [Implementation Method 2]

[0095] Figure 4 A block diagram of the correction voltage command value generation unit of Embodiment 2 is shown. Embodiment 2 differs from Embodiment 1 in the following aspects.

[0096] In coefficient multiplier 17, the phase voltage detection signal v U v V v W (or voltage command value v) U v V v W Multiply by the coefficient N / n U N / n V N / n W The numerator N of the coefficient represents the number of unit cells in each phase. Figure 1 In the example, N = 3. The denominator n of the coefficients... U n V n W This represents the number of units currently operating without faults in each phase. Then, the phase voltage detection signal v used in the first dq converter 3 and the second dq converter 6... U v V v W (or voltage command value v) U v V v W ), use the value obtained by multiplying by this coefficient.

[0097] This embodiment 2 adds the function of reducing the voltage burden on the phase with the faulty unit to embodiment 1. The required zero-phase voltage originally needed to be calculated by solving equation (6).

[0098] [Mathematical Expression 6] (6) However, equation (6) has the following problems: the number of variables increases, making it difficult to derive the solution, and the derived equation is very complex and difficult to implement into the control program.

[0099] Therefore, for the phase voltage detection signal v U v V vW Multiply by a coefficient, and amplify the AC voltage of the phase including the faulty unit according to the number of faulty units, to obtain the positive phase d-axis component V. 1d q-axis component V 1q Negative d-axis component V 2d and negative phase q-axis component V 2q Substituting into equation (3) to approximately obtain the required zero-phase voltage d-axis component V 0d and the q-axis component of the zero-phase voltage V 0q .

[0100] By using the zero-phase voltage d-axis component V 0d and the q-axis component of the zero-phase voltage V 0q Superimposed on the voltage command value v U v V v W This reduces the amplitude of the voltage command value of the phase with the faulty unit. Here, N / n are used respectively. U N / n V N / n W As an example of a coefficient.

[0101] use Figure 5 Explain the effects of this second implementation method. Figure 5 (a) assumes that the number of units in each phase is N = 3, the three-phase AC voltage is balanced, and there is no negative phase voltage (V). 2d =V 2q Phasor diagram of voltage command value when =0).

[0102] Here, we consider a failure in one unit of phase U, and n U The case where = 2. Figure 5 (b) illustrates the application of Patent Document 4 to maintain the line-to-line voltage, where the remaining two units of phase U require an AC voltage output of 1.5 times. To address this, the DC voltage of the phase U units needs to be 1.5 times the AC voltage.

[0103] Figure 5 (c) is the case where the technology of Embodiment 2 is applied. By using the zero-phase voltage d-axis component V... 0d and the q-axis component of the zero-phase voltage V 0q Superimposed on the voltage command value v U v V v W This reduces the output voltage of the U-phase unit. Although the output voltages of the V-phase and W-phase units increase, the line-to-line voltage can be maintained by doubling the AC voltage of all units, including the U-phase, by approximately 1.15 times.

[0104] That is, the correction voltage command value v for each phase. U '、v V '、v W The amplitude of the vibration is multiplied by the number of units N in each phase, and then divided by the number of units n that are currently operating without faults in each phase. U n V n W The zero-phase voltage with the same frequency as the fundamental wave is superimposed in a way that makes the difference between the three phases of the division value smaller.

[0105] Furthermore, based on Figure 4 The gating signal is generated for healthy units that have not experienced a fault. For faulty units, on the AC mains side, switching devices S1 and S3 are turned on (ON), or switching devices S2 and S4 are turned on (ON) to output zero voltage, or an external switch is used to short-circuit the faulty unit. Switching devices S5 to S12 are turned off (OFF).

[0106] According to this embodiment 2, in addition to the effects of embodiment 1, even if a portion of the units fails and a short circuit is applied, the AC output voltage of the units can be made equal. Compared to the prior art, it can continue to operate even if more units fail.

[0107] [Implementation Method 3]

[0108] Figure 6 A block diagram of the correction voltage command value generation unit of Embodiment 3 is shown. The structure before the arithmetic unit 9 is the same as in Embodiment 1 or Embodiment 2. Embodiment 3 differs from Embodiment 1 and Embodiment 2 in the following aspects.

[0109] In this embodiment 3, after determining the d-axis component V of the zero-phase voltage... 0d and the q-axis component of the zero-phase voltage V 0q In the arithmetic unit 9, equation (5) is used.

[0110] Comparator 18 determines the negative phase d-axis component V. 2d Is it equal to the positive phase d-axis component V? 1d Comparator 19 determines the negative phase d-axis component V. 2d Is it equal to -V? 1d / 2. Comparator 20 determines the negative phase q-axis component V. 2q Is it equal to 0? Comparator 21 determines the negative phase q-axis component V.2q Is it equal to - V 1d / 2. Comparator 22 determines the negative phase q-axis component V. 2q Is it equal to V 1d / 2.

[0111] Furthermore, comparator 18 can also be preset with a threshold; if the negative phase d-axis component V... 2d With the positive phase d-axis component V 1d If the difference is less than a threshold, they are considered equal. The threshold can have hysteresis characteristics. The same applies to comparators 19-22.

[0112] In the negative d-axis component V 2d equal to -V 1d / 2 and negative q-axis component V 2q equal V 1d When the value is 2, AND element 23 outputs 1; otherwise, it outputs 0. If the output of AND element 23 is 1, then switch SW1 outputs V. 1d / 4 is the d-axis component of the zero-phase voltage V 0d If the value is 0, the result of equation (5) is output. If the output of AND element 23 is 1, then switch SW2 outputs - V 1d / 4 is the q-axis component of the zero-phase voltage V 0q If the result is 0, the result of equation (5) will be output.

[0113] In the negative d-axis component V 2d equal to -V 1d / 2 and negative q-axis component V 2q equal- V 1d When the value is 2, AND element 24 outputs 1; otherwise, it outputs 0. If the output of AND element 24 is 1, then switch SW3 outputs V. 1d / 4 is the d-axis component of the zero-phase voltage V 0d If the value is 0, then the result of switch SW1 is output. If the output of AND element 24 is 1, then switch SW4 outputs... V 1d / 4 is the q-axis component of the zero-phase voltage V 0q If the value is 0, then the result of switch SW2 will be output.

[0114] In the negative d-axis component V 2d Equal to the positive phase d-axis component V 1d And the negative q-axis component V 2q When the AND element 25 outputs 0, it outputs 1; otherwise, it outputs 0. If the output of the AND element 25 is 1, then switch SW5 outputs -V.1d / 2 is the d-axis component of the zero-phase voltage V 0d If the value is 0, the result of switch SW3 is output. If the output of AND element 25 is 1, switch SW6 outputs 0 as the zero-phase voltage q-axis component V. 0q If the value is 0, the result of switch SW4 will be output.

[0115] Table 1 shows the d-axis component V of the zero-phase voltage output by the final switch SW5. 0d The zero-phase voltage q-axis component V output by switch SW6 0q .

[0116] [Table 1]

[0117] Regarding equations (3), (4), and (5) used in implementation methods 1 and 2, the denominator is zero and there is no solution when the amplitudes of the positive and negative phase voltages are equal. However, if the numerator is also zero, it is generally considered that there may be a solution. Therefore, for simplification, the condition that both the numerator and denominator in equation (5) are zero is assumed to be obtained by assuming the purpose of grid connection, and equation (7) is obtained as one of them.

[0118] [Mathematical Expression 7] (7) Substituting equation (7) into equation (1), in V 1q Under the condition that = 0, the zero-phase voltage that satisfies equation (2) is recalculated, and equation (8) is obtained.

[0119] [Mathematical Expression 8] (8) At this time, the q-axis component of the zero-phase voltage V 0q It can be any value, indicating that there are infinite solutions. Among these infinite solutions, the solution with the smallest amplitude of the zero-phase voltage is given by equation (9).

[0120] [Mathematical Expression 9] (9) In addition to equation (7), there are two other conditions for both the numerator and denominator to be zero. The combinations of conditions and solutions are shown in equations (10) and (11).

[0121] [Mathematical Expression 10] (10) [Mathematical Expression 11] (11) Examples of the conditions for equations (7), (10) and (11) are line-to-line short circuits or two-phase-to-ground faults.

[0122] In this embodiment 3, the voltage conditions of equations (7), (10), and (11) are detected, and a zero-phase voltage is superimposed to make the amplitudes of the voltage command values ​​of each phase equal. When the grid is connected, there are applications where continuous operation is required even in the event of a short circuit or ground fault as a fault ride-through (FRT) requirement, and this embodiment 3 can also address such applications.

[0123] According to this embodiment 3, even when an inter-line short circuit or a two-phase ground fault occurs in the AC power grid, the effects of embodiments 1 and 2 can still be obtained.

[0124] The above description only refers to specific examples. However, it is obvious to those skilled in the art that various modifications and variations can be made within the scope of the technical concept of the present invention, and such modifications and variations naturally fall within the scope of the claims.

Claims

1. A single-unit multi-inverter, characterized in that, It comprises: multiple units connected in a star configuration to each phase of an AC power grid, having a full-bridge circuit on the AC power grid side; a correction voltage command value generation unit that superimposes a zero-phase voltage with the same frequency as the fundamental frequency onto a voltage command value to generate a correction voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein... The correction voltage command value generation unit superimposes the zero-phase voltage, which is at the same frequency as the fundamental wave, onto the voltage command value in a manner that reduces the amplitude difference of the correction voltage command values ​​for each phase.

2. A single-unit multi-inverter, characterized in that, It comprises: multiple units connected in a star configuration to each phase of an AC power grid, having a full-bridge circuit on the AC power grid side; a correction voltage command value generation unit that superimposes a zero-phase voltage with the same frequency as the fundamental frequency onto a voltage command value to generate a correction voltage command value; and a gate signal generation unit that generates a gate signal for the full-bridge circuit based on the correction voltage command value, wherein... The correction voltage command value generation unit superimposes the zero-phase voltage, which has the same frequency as the fundamental frequency, in such a way that the difference between the values ​​obtained by multiplying the amplitude of the correction voltage command value for each phase by the number of units in each phase and then dividing by the number of units that are working without faults in each phase is reduced.

3. The unit-multiplexed inverter according to claim 1 or 2, characterized in that, The correction voltage command value generation unit includes: The phase output section outputs a phase ωt synchronized with the AC voltage of the power grid; The first dq converter transforms the phase voltage detection signal or the voltage command value, or the value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of units in each phase by the number of units that are working without fault in each phase, into a value on a rotating coordinate synchronized with the grid frequency. The second dq converter transforms the phase voltage detection signal or the voltage command value, or the value obtained by multiplying the phase voltage detection signal or the voltage command value by a coefficient obtained by dividing the number of units in each phase by the number of units that are working without fault in each phase, into a value on a rotating coordinate that is in the opposite direction to the grid frequency. The arithmetic unit calculates the zero-phase voltage d-axis component and zero-phase voltage q-axis component that make the AC side output voltage of each unit uniform, based on the positive phase d-axis component and positive phase q-axis component obtained by extracting the DC component from the output of the first dq converter, and the negative phase d-axis component and negative phase q-axis component obtained by extracting the DC component from the output of the second dq converter. The first multiplier multiplies the d-axis component of the zero-phase voltage by cosωt or sinωt; The second multiplier multiplies the zero-phase voltage q-axis component by sinωt when multiplying by cosωt using the first multiplier, and multiplies the zero-phase voltage q-axis component by cosωt when multiplying by sinωt using the first multiplier. The first adder adds the output of the first multiplier to the output of the second multiplier; as well as The second adder adds the output of the first adder to the voltage command value and outputs the corrected voltage command value.

4. The unit-multiplexed inverter according to claim 3, characterized in that, The arithmetic unit calculates the d-axis component and the q-axis component of the zero-phase voltage based on equation (3). [Mathematical Expression 3] （3） V 0d d-axis component of zero-phase voltage V 0q : q-axis component of zero-phase voltage V 1d d-axis component of positive phase voltage V 1q : q-axis component of the positive phase voltage V 2d d-axis component of negative phase voltage V 2q : Negative phase voltage q-axis component.

5. The unit-multiplexed inverter according to claim 3, characterized in that, The arithmetic unit calculates the d-axis component and the q-axis component of the zero-phase voltage based on equation (4). [Mathematical Expression 4] （4） V 0d d-axis component of zero-phase voltage V 0q : q-axis component of zero-phase voltage V 1d d-axis component of positive phase voltage V 1q : q-axis component of the positive phase voltage V 2d d-axis component of negative phase voltage V 2q : Negative phase voltage q-axis component.

6. The unit-multiplexed inverter according to claim 3, characterized in that, The arithmetic unit calculates the d-axis component and the q-axis component of the zero-phase voltage based on equation (5). [Mathematical Expression 5] （5） V 0d d-axis component of zero-phase voltage V 0q : q-axis component of zero-phase voltage V 2d d-axis component of negative phase voltage V 2q : q-axis component of negative phase voltage V1: Positive phase component of voltage.

7. The unit-multiplexed inverter according to claim 6, characterized in that, The correction voltage command value generation unit: In the negative phase d-axis component V 2d =V 1d And the negative phase q-axis component V 2q When = 0, the d-axis component V of the zero-phase voltage is made to... 0d =-V 1d / 2. The zero-phase voltage q-axis component V 0q =0, In the negative phase d-axis component V 2d =-V 1d / 2 and the negative phase q-axis component V 2q =- V 1d When / 2, the d-axis component V of the zero-phase voltage is made to 0d =V 1d / 4. The zero-phase voltage q-axis component V 0q = V 1d / 4, In the negative phase d-axis component V 2d =-V 1d / 2 and the negative phase q-axis component V 2q = V 1d When / 2, the d-axis component V of the zero-phase voltage is made to 0d =V 1d / 4. The zero-phase voltage q-axis component V 0q =- V 1d / 4.

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