Voltage-controlled magnetic anisotropy magnetic tunnel junction sub-nanosecond write true random number post-processing circuit

Abstract

This invention discloses a post-processing circuit for writing true random numbers in sub-nanosecond mode using a voltage-controlled magnetic anisotropic magnetic tunnel junction (VCMA-MTJ). The circuit includes an entropy source for a 2-transistor, 2-MTJ magnetic random access memory array, a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit, and a timing control circuit. The 2T2M array acts as the physical entropy source, outputting raw random signals through two independent VCMA-MTJ channels. The readout circuit converts the impedance differences of the VCMA-MTJs into digital signals, ensuring the independence of the two signals. The latch circuit temporarily stores the initial read signal, and the cascaded XOR circuit performs an XOR operation with the second read signal to output high-quality random numbers. The timing control circuit coordinates the orderly operation of each module through asynchronous signals REN, WEN, and EN. The word line WL is a sub-nanosecond narrow pulse signal, and WEN indicates the write timing; the two work together to achieve high-speed sub-nanosecond writing. This circuit effectively resists random number deviations caused by device non-ideals and PVT (process-voltage-temperature) fluctuations, improving circuit integration.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and particularly relates to a post-processing circuit for writing true random numbers in sub-nanoseconds using a voltage-controlled magnetic anisotropic magnetic tunnel junction. Background Technology

[0002] True random number generators are core components in embedded encryption, IoT security, and other fields. The quality, stability, and power consumption of their output random numbers directly determine the reliability of the entire security system. To meet the application requirements of high-security scenarios, academia and industry are gradually shifting towards true random number generation technologies based on novel memory devices. Magnetic tunnel junctions (MTJs), with their advantages of non-volatility, high-speed read / write, and low power consumption, have become ideal physical entropy source devices for true random number generators. Among them, the voltage-controlled magnetic anisotropic magnetic tunnel junction (VCMA-MTJ) is widely used in the design of high-performance true random number generators due to its stronger randomness in magnetic moment reversal. Currently, most mainstream true random number generators in the industry adopt the MRAM architecture of 1 transistor 1 magnetic tunnel junction (1T1M) as the physical entropy source. Although this architecture is simple in structure and has high integration, it has many limitations that are difficult to overcome in practical applications.

[0003] First, the 1T1M unit can only output one raw random signal, lacking independence. It requires multiple cycles of repeated sampling and signal superposition to accumulate sufficient independent random information, resulting in low throughput and difficulty meeting the high-speed requirements of embedded encryption and high-speed key generation scenarios. Furthermore, this architecture lacks a symmetrical readout design and a stable benchmark calibration mechanism, making it extremely sensitive to process deviations, voltage fluctuations, and temperature changes. This makes the readout signal prone to offset and distortion, increasing random number deviation and reducing its statistical characteristics and reliability. In addition, the post-processing module design accompanying the 1T1M architecture is relatively simple, often employing single XOR operations or simple latching and shaping, which cannot effectively eliminate the inherent autocorrelation and periodicity of the raw random signal, making it difficult to further improve the entropy and security of the output random numbers. In existing technologies, some solutions attempt to compensate for the above defects by optimizing device parameters and adding calibration circuits, but this often leads to increased circuit complexity and power consumption, making it impossible to achieve a balance between performance and power consumption. Therefore, in view of the inherent limitations of the 1T1M architecture, there is an urgent need for an optimized post-processing circuit design that combines a more reasonable entropy source architecture and module layout to achieve highly stable, highly reliable, and low-design-complexity random number generation. Summary of the Invention

[0004] The purpose of this invention is to provide a post-processing circuit for a high-speed sub-nanosecond write true random number generator based on a voltage-controlled magnetic anisotropic magnetic tunnel junction, so as to solve the problem of random number quality degradation caused by process deviations and environmental sensitivity in traditional solutions, thereby achieving highly stable and reliable random number generation.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] A voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond post-processing circuit for writing true random numbers, the post-processing circuit including a 2-transistor 2-magnetic tunnel junction (2T2M) memory cell, a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit and a timing control circuit.

[0007] The 2T2M memory cell consists of two N-type field-effect transistors (NMOS) and two independently arranged voltage-controlled magnetic anisotropic magnetic tunnel junctions (VCMA-MTJs). The two VCMA-MTJs are two independent physical entropy sources, each composed of a fixed layer, a free layer, and a tunnel layer made of magnetic media. The fixed layer is relatively thick, and its magnetic moment direction remains fixed, serving as a stable reference. The free layer is relatively thin, and when there is no voltage, the magnetic moment will stabilize in a state parallel to the fixed layer (P) or antiparallel to the fixed layer (AP) under the influence of vertical anisotropy. When a voltage is applied, the vertical anisotropy effect weakens, the magnetic moment undergoes helical precession and random flipping, and stabilizes in a new resistive state after the voltage is removed. The auxiliary random disturbance effect of thermal noise makes the flipping direction and flipping timing of the free layer magnetic moment unpredictable and unreproducible, constituting a natural physical entropy source.

[0008] The gates of the two NMOS memory access transistors are connected to the word line (WL), the sources are grounded, and the drains are connected to one end of the corresponding VCMA-MTJ. The other end of the VCMA-MTJ is connected to the bit line (BL). The memory cell access operation is controlled by the bit line BL, the source line SL, the word line control signal WL, the read enable signal REN, the write enable signal WEN, and the timing trigger signal EN. The synchronous switching of the memory access transistors is controlled by WL and REN. The source line and the source of the memory access transistors share the same ground to ensure that there is no crosstalk in the signal transmission.

[0009] The post-processing circuit includes a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit, and a timing control circuit. When the storage unit is working, the two VCMA-MTJs independently flip their free-layer random magnetic moments, each outputting a raw random signal. These two signals are then processed collaboratively by the post-processing module to output a random number. When the free-layer magnetic moment of the VCMA-MTJ is parallel to its fixed layer, the magnetic reluctance is low (R). P When the magnetic moment of the free layer is antiparallel to that of its fixed layer, the magnetic reluctance is high, R. AP The two impedance states correspond to the high and low levels of the original random signal, respectively.

[0010] The dual-channel single-ended readout circuit consists of two completely symmetrical voltage divider readout units used to synchronously extract and convert two raw random signals. Each channel contains one PMOS transistor, one NMOS transistor, and a reference resistor R. REFThe two units share identical circuit topology, device parameters, and routing, which mitigates signal drift caused by process variations. This circuit employs a lightweight transistor-level design, with the PMOS transistor's gate sharing a common bias voltage, its source connected to VDD, and its drain connected to both the NMOS transistor's drain and the reference resistor R. REF One end is connected, the source of the NMOS transistor is grounded, and the reference resistor R REF The other end is connected to the corresponding output terminal of the VCMA-MTJ, and the VCMA-MTJ is connected to the reference resistor R. REF A voltage divider circuit is formed by connecting the circuits in series. The enable terminals of both single-ended readout circuits are connected to the read enable signal (REN). The signal input terminals of the two circuits are respectively connected to the two VCMA-MTJ output terminals of the 2T2M memory cell. The impedance difference of the VCMA-MTJ is first converted into the voltage difference between the voltage divider nodes L0 and L1, and then directly converted into a stable high and low level digital signal T by an inverter. 1a T 1b The final output is to the gated D latch circuit, which has low design complexity.

[0011] The latch circuit is a gate-level D latch composed of four two-input NAND gates, including eight PMOS transistors (P0, P1, P2, P3, P4, P5, P6, P7) and eight NMOS transistors (N0, N1, N2, N3, N4, N5, N6, N7). The PMOS transistors are connected in parallel with their sources connected to the power supply VDD, and the NMOS transistors are connected in series with their sources grounded. P0, P1, N0, and N1 form the input stage. The gates of P1 and N1 are connected to the data signal D, and the gates of P0 and N0 are connected to the timing trigger signal EN. The drains of each transistor are interconnected to form an internal O0 section. Points: P2, P3, N2, and N3 form the intermediate stage. The gates of P3 and N3 are connected to node O0, and the gates of P2 and N2 are connected to the timing trigger signal EN. The drains of each transistor are interconnected to form node O1. P4, P5, N4, and N5 form the output stage. The gates of P4 and N4 are connected to node O1, and the gates of P5 and N5 are connected to output Q. The drains of each transistor are interconnected to form node O2. P6, P7, N6, and N7 form the feedback output stage. The gates of P6 and N6 are connected to node O0, and the gates of P7 and N7 are connected to node O2. The drains of each transistor are interconnected to form the output terminal Q, i.e., T. 1a T 1b The output node Q is simultaneously fed back to the gates of P5 and N5 in the output stage, so that when EN is low, the output stage and the feedback output stage are cross-coupled through the Q node and the O2 node, forming a strong positive feedback bistable latch loop. The input of the latch circuit is connected to the output of the dual-channel single-ended read circuit, and the clock terminal is connected to the timing trigger signal (EN). When EN is high, the output follows the input signal; when EN is low, the output maintains the current level, adapting to the timing coordination requirements of the post-processing circuit.

[0012] The cascaded XOR circuit consists of three identical CMOS XOR gates and one PMOS enable control transistor. Each XOR gate comprises two PMOS transistors and two NMOS transistors, and the circuit parameters of the three CMOS XOR gates are completely identical. The PMOS enable control transistor is connected to the power supply terminals of all CMOS XOR gates to control the overall on / off state of the cascaded XOR circuit. The input terminal of the cascaded XOR circuit is connected to the output terminal of the latch circuit and the output terminal of the dual-channel single-ended readout circuit in the secondary read stage. Specifically, the first-stage XOR gate is connected to T... 1a T 1b and the signal T read twice 2a T 2b After the first-level XOR operation, intermediate signals T are output respectively. a T b The second-level XOR gate is connected to T. a T b It outputs a final 1-bit random number to introduce the independence of the dual-channel VCMA output random signal and reduce the correlation of the post-processed random sequence.

[0013] The timing control circuit generates write enable (WEN), read enable (REN), and timing trigger (EN) signals based on the external clock signal. The timing control circuit uses a combination of asynchronous timing mechanisms and combinational logic control to generate these control signals. The word line (WL) is a sub-nanosecond narrow pulse signal. When WEN is high, WL synchronously outputs a narrow pulse, which quickly turns on the NMOS memory access transistor, allowing the write voltage to be precisely applied to the VCMA-MTJ and driving the free layer magnetic moment to precess and flip rapidly. This shortens the write cycle and avoids device magnetic losses caused by prolonged transistor operation. WEN, REN, and EN work together to achieve a dual-read cycle operating mode. The signal generation process is based on the fixed action logic of the dual-read cycle operating mode and maintains a coordinated reference relationship with the external CLK clock signal. This coordinates the orderly operation of each module according to the dual-read cycle, precisely controlling the start-up, operation, and shutdown of each module, and avoiding functional conflicts caused by overlapping module actions.

[0014] The timing control circuit is configured to execute a dual-read cycle operating mode according to the following timing steps: Random write phase (SW1 phase): WEN is set high to provide a write signal; a sub-nanosecond narrow pulse WL is synchronously set high to enable the memory access transistor; the write voltage is applied to VCMA-MTJ and excites the magnetic moment to complete the sub-nanosecond random flip-flop; First read phase (RD1 phase): REN is set high, and the dual-channel single-ended read circuit outputs T1a and T1b; LAT phase (signal tracking phase): EN is set high, and the gated D latch circuit tracks T1a and T1b. 1a T 1b Signal; During the secondary readout stage (RD2 stage), REN remains high, and the dual-channel single-ended readout circuit outputs T. 2a T2b Signal; XOR post-processing stage (PP stage), cascaded XOR circuit for T a T b The signal is processed and a final random number is output. There is no overlap of actions throughout the cycle, and the modules are connected in an orderly manner.

[0015] Furthermore, the dual-read cycle operating mode is the core operating mode of the circuit, divided into two independent stages with no overlap: the read latch stage and the post-processing stage. These stages are coordinated and controlled by the WEN, REN, and EN signals output by the timing control circuit. Specifically, the write enable signal WEN is precisely coordinated with the sub-nanosecond narrow pulse word line WL timing to complete the write operation control of the 2T2M memory cell, isolated from the read operation timing. Throughout the entire cycle, the two NMOS memory access transistors of the 2T2M memory cell remain on, ensuring the continuous and stable acquisition of the two VCMA-MTJ signals.

[0016] During the read latching phase, the timing control circuit first sets the write enable signal WEN high, entering the SW1 phase. A sub-nanosecond narrow pulse WL synchronously activates the memory access transistor, applying a write voltage to the VCMA-MTJ and exciting the free-layer magnetic moment to achieve sub-nanosecond spiral precession and flipping, superimposed with thermal noise disturbance. After the SW1 phase ends, WEN is reset to low to avoid read / write conflicts. Then, the read enable signal REN is set high, entering the RD1 phase. The dual-channel single-ended read circuit synchronously reads the two VCMA-MTJ signals of the 2T2M memory cell, outputting T... 1a T 1b The data is then transmitted to the input of the latch circuit; when EN is set high, the LAT stage begins, and the latch tracks T in real time. 1a T 1b Signal level changes to ensure synchronization with the input; when T 1a T 1b After the signal stabilizes, the timing control circuit sets EN to low level, the latch circuit enters latching state, stops tracking the input signal, and keeps the current output level unchanged. At the same time, REN remains high level to provide a stable input signal for the post-processing stage, and the LAT stage ends.

[0017] During the post-processing stage, the timing control circuit keeps the read enable signal REN high and EN low, and the latch remains in the latched state, maintaining the current output T. 1a T 1bThe level remains unchanged; then, in the SW2 stage, the timing control circuit sets the write enable signal WEN high to provide a second write signal. A sub-nanosecond narrow pulse WL synchronously turns on the memory access transistor, and REN is set low, driving the free-layer magnetic moment to complete a sub-nanosecond double random flip. After the SW2 stage ends, WEN is reset to low, and then the RD2 stage begins, keeping REN high. The dual-channel single-ended readout circuit synchronously reads the two VCMA-MTJ signals, generating a T signal with independent randomness compared to the first read signal. 2a T 2b And input to the cascaded XOR circuit; the two XOR gates in the first stage respectively input to T 1a With T 2a T 1b With T 2b Performing an XOR logic operation reduces the periodicity and autocorrelation of a single random signal, outputting two decorrelation intermediate signals T. a T b The second-level XOR gate for T a T b A second XOR logic operation is performed, combining the independence of the two random signals to achieve random fusion of the two signals, further increasing the entropy value of the output signal, and finally outputting a 1-bit random number that conforms to the random statistical characteristics; after the operation is completed, the timing control circuit resets the REN signal to a low level, the circuit returns to the initial state, and waits for the next dual-read cycle to start.

[0018] When REN is high, the dual-channel single-ended readout circuit starts voltage divider reading; when REN is low, the circuit is turned off and enters standby mode to avoid unnecessary power consumption when there is no operation.

[0019] The write enable signal WEN and the read enable signal REN are isolated in timing, and the write operation and the read operation are performed in a time-sharing manner.

[0020] Furthermore, the independent layout design of the 2T2M memory cell and the symmetrical structure of the dual-channel single-ended readout circuit jointly enhance the circuit's anti-interference capability and signal consistency. In the 2T2M memory cell, one NMOS memory access transistor and one VCMA-MTJ are connected in series to form an independent random signal source. The gates of the NMOS memory access transistors of the two signal sources are connected to the word line control signal, and their drains are electrically connected to one end of the corresponding VCMA-MTJ. The sources of both are grounded. The bit line BL is connected to the other end of the two VCMA-MTJs, and the source line SL is grounded with the source of the memory access transistor. The two VCMA-MTJs adopt a physically isolated independent layout with no magnetic coupling path, ensuring the independence of the two random signals from the source and avoiding signal interference between entropy sources. The symmetrical structure of the dual-channel single-ended readout circuit can reduce the signal offset caused by process deviations, ensuring consistent extraction accuracy of the two signals and providing a balanced signal foundation for subsequent XOR operations. At the same time, the write operation controlled by the write enable signal WEN can stabilize the resistive state of the VCMA-MTJ and prevent write interference from affecting the quality of the original random signal.

[0021] The post-processing circuit for a high-speed sub-nanosecond write true random number generator based on a voltage-controlled magnetic anisotropic magnetic tunnel junction, as described in this invention, has the following advantages:

[0022] (1) The post-processing circuit of the high-speed sub-nanosecond write true random number generator based on the voltage-controlled magnetic anisotropic magnetic tunnel junction studied in this invention has the advantages of high throughput and high randomness. Traditional schemes mostly adopt a 1T1M architecture, which can only output one original random signal. It requires multiple cycles of repeated sampling to accumulate enough independent random information, resulting in low throughput. However, this invention uses two independently arranged VCMA-MTJs to form two independent entropy sources, which can output two independent original signals simultaneously without multiple cycles of sampling, greatly improving throughput. At the same time, the two VCMA-MTJs are physically isolated and have no magnetic coupling, ensuring signal independence and providing a high-quality foundation for post-processing.

[0023] (2) The post-processing circuit of the high-speed sub-nanosecond write true random number generator based on the voltage-controlled magnetic anisotropic magnetic tunnel junction studied in this invention has the advantage of high-speed sub-nanosecond write. By setting the write enable signal WEN high to provide the write signal and the word line WL synchronously outputting a sub-nanosecond narrow pulse to enable the memory access transistor, the sub-nanosecond fast flipping and writing of the VCMA-MTJ magnetic moment is realized, which greatly shortens the write stage time of the dual read cycle and significantly improves the overall working efficiency of the dual read cycle. At the same time, the sub-nanosecond narrow pulse design of WL can effectively reduce the magnetic loss of VCMA-MTJ, improve the working life of the device and the long-term reliability of the circuit.

[0024] (3) The post-processing circuit of the high-speed sub-nanosecond write true random number generator based on the voltage-controlled magnetic anisotropic magnetic tunnel junction studied in this invention has the advantages of high random number quality and low overall design complexity. Traditional XOR modules have poor decorrelation, and timing control is prone to module conflicts and high power consumption. However, the cascaded XOR circuit in this invention reduces signal correlation through two-stage operation and improves random number quality. Attached Figure Description

[0025] Figure 1 This is a structural diagram of the VCMA-MTJ device of the present invention;

[0026] Figure 2 This is a schematic diagram of the randomness mechanism of VCMA-MTJ in this invention;

[0027] Figure 3 This is an overall framework diagram of the invention;

[0028] Figure 4 This is a schematic diagram of the reading circuit and post-processing circuit structure of the present invention;

[0029] Figure 5 This is a timing waveform diagram of the dual-read cycle operation of the present invention;

[0030] Figure 6 is a scatter plot showing the independence of the VCMA-MTJ flipping probability of the present invention;

[0031] Figure 7 shows the histogram of random number statistics before and after post-processing in this invention;

[0032] Figure 8 is a schematic diagram of the autocorrelation of random numbers before and after post-processing in this invention;

[0033] Figure 9 is a theoretical analysis diagram of the post-processing deviation tolerance of the present invention;

[0034] Figure 10 is a heatmap of the four-state distribution of the post-processing output of the present invention. Detailed Implementation

[0035] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides a post-processing circuit for a high-speed sub-nanosecond write true random number generator based on a voltage-controlled magnetic anisotropic magnetic tunnel junction.

[0036] As the core physical entropy source of a true random number generator, the VCMA-MTJ has the following device structure: Figure 1 As shown, it employs a perpendicular magnetic anisotropy structure, consisting of a three-layer core structure made of magnetic media: a fixed layer, a free layer, and a tunnel layer. The fixed layer is relatively thick, and its magnetic moment direction remains constant, serving as a stable reference. The free layer is thinner and is the core for achieving random characteristics. The tunnel layer's thickness is rationally designed, isolating the fixed layer from the free layer and ensuring the independence of the magnetic moment. The randomness mechanism is as follows: Figure 2As shown, when no voltage is applied, the free layer magnetic moment, under the influence of vertical anisotropy, will deviate towards one of the polar directions, either the P-state parallel to the fixed layer or the AP-state antiparallel to the fixed layer. The VCMA-MTJ, relying on the working principle of voltage-driven regulation of magnetic anisotropy, does not require charge transfer and inherently possesses the physical characteristic of rapid magnetic moment reversal, providing the core device foundation for sub-nanosecond writing in this invention. When WEN is set high to provide the write signal, the sub-nanosecond narrow pulse WL synchronously turns on the memory access transistor, and the write voltage is rapidly applied to the VCMA-MTJ. The vertical anisotropy effect is attenuated, and the magnetic moment will achieve rapid sub-nanosecond helical precession and reversal. The superimposed random disturbances of thermal noise and magnetic coupling make the reversal direction and timing of the free layer magnetic moment unpredictable and unreproducible, which is also its core advantage as a physical entropy source.

[0037] In practical construction of post-processing circuits for high-speed sub-nanosecond write true random number generators based on VCMA-MTJ, traditional solutions often employ a 1T1M memory cell architecture. While this architecture leverages the random characteristics of VCMA-MTJ to generate the original signal, it can only provide a single-channel original random signal. The post-processing process requires numerous periodic samplings to accumulate a sufficiently independent random signal, thus significantly reducing random number throughput. Furthermore, the periodicity and autocorrelation of the single-channel signal are difficult to eliminate effectively, and its associated readout and latching modules are susceptible to PVT fluctuations. The integration optimization space is limited, making it difficult to adapt to the high-throughput, low-power, and high-security requirements of embedded applications. Addressing the core bottlenecks of the aforementioned 1T1M architecture, this invention proposes a 2T2M VCMA-MRAM array design, trading area for speed, while introducing device independence to improve post-processing quality, focusing on the fabrication of the 2T2M array and post-processing circuit.

[0038] The post-processing circuit based on a voltage-controlled magnetic anisotropic magnetic tunnel junction (VMT) described in this invention includes an entropy source for a magnetic random access memory (MRAM) array with two transistors and two magnetic tunnel junctions (2T2M), a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit, and a timing control circuit. The modules are interconnected via leads to ensure the stability of their coordinated operation. The overall framework is as follows: Figure 3 As shown, the specific structure of each module is integrated into Figure 4 The reading circuit and post-processing circuit structure shown are as follows.

[0039] The core of this invention is the 2T2M MRAM array entropy source. Its memory cell structure consists of two N-type field-effect transistors as memory access transistors, connected in series with two independently arranged VCMA-MTJs to form two independent random signal sources. The circuit topology and device parameters of the two signal sources are completely identical. Compared to the 1T1M architecture, the 2T2M architecture achieves a dual improvement in throughput and post-processing quality at the cost of approximately doubling the memory cell area. Simultaneously, the independence of the two signals effectively improves post-processing quality. Subsequent operations on the two independent signals using a cascaded XOR circuit reduce the correlation of the post-processed random sequence, improving the entropy and statistical characteristics of the output random numbers. The access operation of the memory cell is controlled by the bit line BL, the source line SL, the sub-nanosecond narrow pulse word line WL, the read enable signal REN, the write enable signal WEN, and the timing trigger signal EN. When WEN is set high, a write signal is given. WL synchronously outputs a narrow pulse to turn on the memory access transistor. The sources of the memory access transistors are all grounded, and the drains are electrically connected to one end of the corresponding VCMA-MTJ. The other end of the VCMA-MTJ is connected to the bit line BL. The source line and the source of the memory access transistor share a common ground to ensure that there is no crosstalk in the signal transmission.

[0040] The dual-channel single-ended readout circuit employs a two-channel fully symmetrical voltage divider readout design. Its core function is to synchronously extract and convert the raw random signals from the two VCMA-MTJ channels of the 2T2M memory cell. Leveraging the consistency in topology, parameters, and routing between the two channels, it effectively mitigates signal offset caused by process variations. Furthermore, the overall design is lightweight and low-complexity. Figure 4 The circuit structure shown corresponds to this. This circuit is controlled by the read enable signal REN, and its input is precisely connected to two VCMA-MTJ channels. Its core function is to convert the impedance difference of the VCMA-MTJ channels into a voltage difference, which is then converted by an inverter into a stable voltage difference. 1a T 1b The digital signal is eventually output synchronously to the gated D latch circuit, providing a stable signal foundation for subsequent latching and post-processing.

[0041] The latch circuit is a gate-level D latch composed of four two-input NAND gates, used to temporarily store and shape the T values ​​transmitted by the dual-channel single-ended readout circuit. 1a T 1b The latch's operating state is precisely controlled by the timing trigger signal EN, which precisely interfaces with the output of the readout circuit and the input of the cascaded XOR circuit to achieve reliable signal latching and stable transmission. When the timing trigger signal EN is high, the output follows the input data signal level in real time; when EN is low, a stable output is maintained through an internal feedback mechanism to ensure the stability of the latched signal and adapt to the timing coordination requirements of the post-processing circuit.

[0042] The cascaded XOR circuit consists of three identical CMOS XOR gates and one PMOS enable control transistor. The PMOS enable control transistor manages the overall circuit's on / off state, and its core function is to introduce the independence of the dual-channel VCMA output random signals, reducing the correlation of the post-processed random sequence. After latching, T... 1a T 1b Signal and T read twice 2a T 2b After the signal undergoes two-stage XOR operations, a high-quality 1-bit random number is finally output, eliminating the need for multi-cycle sampling and adapting to high-throughput requirements.

[0043] The timing control circuit employs a combination of asynchronous timing and combinational logic to generate three sets of control signals: REN, WEN, and EN. These signals coordinate with the external CLK clock signal. Its core function is to coordinate the latch circuit, cascaded XOR circuit, and dual-channel single-ended read circuit to operate in an orderly manner according to dual read cycles, avoiding overlapping and conflicting actions between modules. The dual read cycle follows the core timing logic of "write-read-latch-secondary read-XOR operation," ensuring orderly connection between modules. Simultaneously, timing isolation between WEN and REN prevents read-write interference.

[0044] Figure 6 This is a scatter plot illustrating the independence of the VCMA-MTJ flip probability in this invention, used to qualitatively characterize the correlation between the two original VCMA-MTJ signals. In this plot, the horizontal and vertical axes correspond to the flip probabilities of the two original random VCMA-MTJ signals, respectively. The scatter points exhibit a uniform but irregular distribution, without any obvious correlation texture, qualitatively indicating that the two original VCMA-MTJ signals have no obvious correlation and possess good statistical independence. This statistical independence is the core physical basis for the effective reduction of correlation by the cascaded XOR post-processing circuit of this invention. XOR operation, as a deterministic logic, cannot generate new independence, while the inherent independence of the two original VCMA-MTJ signals effectively avoids correlation propagation, providing reliable theoretical support for the post-processing effect. It also confirms the rationality and effectiveness of the independent layout design of the two VCMA-MTJ signals in the 2T2M architecture of this invention.

[0045] Figure 7 The histograms of random number statistics before and after post-processing in this invention are used to compare and characterize the differences in the statistical distribution of the two VCMA-MTJ original signals and the post-processed output signals. Due to device non-ideals, process fluctuations, and environmental disturbances, the statistical distribution of the two VCMA-MTJ original signals deviates from the ideal 50% probability, exhibiting a significant asymmetric deviation. After the two-stage cascaded XOR post-processing of this invention, the statistical distribution of the output signal significantly converges to near the ideal 50% probability. This before-and-after comparison directly verifies the ability of the post-processing circuit of this invention to correct the statistical deviation of the original signal and its effectiveness in improving the statistical uniformity of the signal.

[0046] Figure 8 This diagram illustrates the autocorrelation of random numbers before and after post-processing according to the present invention, used to compare and characterize the difference in time correlation between the original signal and the post-processed output signal. In this diagram, the horizontal axis represents the lag order (Lag), and the vertical axis represents the autocorrelation coefficient. Both original VCMA-MTJ signals exhibit significantly high autocorrelation coefficients when Lag is small, and the autocorrelation coefficient gradually decreases with increasing lag order. This phenomenon originates from the residual vibration effect after the VCMA-MTJ magnetic moment reversal, resulting in short-term time correlation in the original signal. After post-processing according to the present invention, the autocorrelation coefficients of each order of the output signal approach 0, and the average autocorrelation value decreases, demonstrating the effective suppression of signal autocorrelation by the post-processing circuit of the present invention.

[0047] Figure 9 This diagram illustrates the theoretical analysis of the post-processing deviation tolerance of this invention, used to compare and analyze the allowable range of input deviation for single-stage XOR and two-stage XOR post-processing circuits. The results show that, under the premise of a fixed 1% output error, the two-stage cascaded XOR design employed in this invention significantly improves the tolerance to deviations in the original signal compared to single-stage XOR post-processing, and can significantly enhance the circuit's robustness to process fluctuations and environmental disturbances. Figure 10 This is a heatmap showing the four-state distribution of the post-processing output of the present invention. It is used to characterize the uniformity of the distribution of the four states (00, 01, 10, 11) formed by the two adjacent bits of the post-processing output random number. It can intuitively reflect the anti-interference capability and output stability of the post-processing circuit.

[0048] To verify the effectiveness of the post-processing circuit of this invention, two sets of randomly generated random sequences of length 20,480,000 were used to simulate the original random signals output by two VCMA-MTJ devices. Comprehensive tests were conducted on the original signals and the signals after cascaded XOR post-processing according to this invention. Test data showed that VCMA1 had a mean of 0.515085 and a standard deviation of 0.007984, while VCMA2 had a mean of 0.484873 and a standard deviation of 0.007846. The difference in mean values ​​corresponds to process, voltage, and temperature fluctuations, while the difference in standard deviations corresponds to device non-ideality. Figure 7The statistical distribution deviation characteristics of the original signal are consistent, confirming the statistical defects present in the original signal. Autocorrelation tests show that the autocorrelation coefficient is high when Lag is low, and then gradually decreases as the lag order Lag increases. However, after the two-stage cascaded XOR post-processing of this invention, the statistical deviation and autocorrelation problems existing in the original signal are significantly improved. The mean of the output random numbers is 0.499963, and the standard deviation is 0.007946. The mean is close to the ideal value of 0.5, and the statistical distribution deviation is greatly suppressed, effectively offsetting the effects of process, voltage, temperature fluctuations, and device non-ideals. Furthermore, in the XOR post-processing autocorrelation test, the mean autocorrelation of the output signal is -0.000192, and the standard deviation is 0.004805. Compared to the original signal, the autocorrelation is significantly reduced, and the independence and unpredictability of the random sequence are greatly improved. The heatmap test of the four-state distribution of the post-processing output shows that the number of states (0-0, 0-1, 1-0, 1-1) formed by the two adjacent bits of the post-processing output random number are 2,558,842, 2,560,683, 2,560,684, and 2,559,792, respectively, with corresponding distribution probabilities of 24.99%, 25.01%, 25.01%, and 25.00%. The distribution is highly uniform, indicating that the anti-interference capability of the post-processing circuit of this invention is significantly improved, and it can better cope with the deviation caused by environmental disturbances and device non-idealities. The stability and reliability of the output random number meet the requirements of high-security applications.

[0049] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond post-processing circuit for writing true random numbers, characterized in that, The post-processing circuit includes a 2-transistor 2-magnetic tunnel junction (2T2M) memory cell, a dual-channel single-ended readout circuit, a latch circuit, a cascaded XOR circuit, and a timing control circuit. The 2T2M memory cell consists of two N-type field-effect transistors (NMOS) and two independently arranged voltage-controlled magnetic anisotropic magnetic tunnel junctions (VCMA-MTJs). The two VCMA-MTJs serve as two independent physical entropy sources. Each VCMA-MTJ contains a fixed layer, a free layer, and a tunnel layer. By applying a write voltage, the vertical magnetic anisotropy of the free layer is attenuated, causing its magnetic moment to undergo random spiral precession, including thermal noise perturbation, thus achieving sub-nanosecond-level random flipping. The gates of the two NMOS memory access transistors are connected to the word line (WL), the sources are both grounded, and the drains are connected to one end of the corresponding VCMA-MTJ. The other end of the VCMA-MTJ is connected to the bit line (BL). The dual-channel single-ended readout circuit has a two-channel symmetrical structure. Each channel consists of one PMOS transistor, one NMOS transistor, and a reference resistor. The reference resistor is connected in series with the corresponding VCMA-MTJ to form a voltage divider branch. The voltage divider node outputs a digital signal through an inverter. The enable terminal of the dual-channel single-ended readout circuit is connected to the read enable signal (REN). The latch circuit is a gated D latch, whose input is connected to the output of a dual-channel single-ended readout circuit, and whose clock is connected to a timing trigger signal (EN). The cascaded XOR circuit consists of three identical CMOS XOR gates and one PMOS enable control transistor. The PMOS enable control transistor is connected to the power supply terminals of all the CMOS XOR gates. The input terminal of the cascaded XOR circuit is connected to the output terminal of the latch circuit and the output terminal of the dual-channel single-ended readout circuit in the secondary readout stage. The output terminal outputs the final random number. The timing control circuit generates a write enable signal (WEN), a read enable signal (REN), and a timing trigger signal (EN) based on an external clock signal. The word line (WL) is a sub-nanosecond narrow pulse signal. When WEN is high, WL outputs a narrow pulse synchronously. WEN, REN, and EN work together to achieve a dual-read cycle working mode.

2. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, In the 2T2M storage unit, the two VCMA-MTJ channels adopt a physically isolated independent layout design with no magnetic coupling path.

3. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, The two circuit topologies and device parameters of the dual-channel single-ended readout circuit are completely identical. One end of the reference resistor of each channel is connected to the drain of the PMOS transistor and the drain of the NMOS transistor, and the other end is connected to the output terminal of the corresponding VCMA-MTJ. The VCMA-MTJ and the reference resistor are connected in series to form a voltage divider circuit. The gate of the PMOS transistor is connected to the common bias voltage, the source is connected to the power supply VDD, and the source of the NMOS transistor is grounded.

4. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond post-processing circuit for writing true random numbers according to claim 1, characterized in that, The latch circuit is a gated D latch composed of four two-input NAND gates, including eight PMOS transistors (P0, P1, P2, P3, P4, P5, P6, P7) and eight NMOS transistors (N0, N1, N2, N3, N4, N5, N6, N7). P0, P1, N0, and N1 form the input stage, with the gates of P1 and N1 connected to the data signal D, and the gates of P0 and N0 connected to the timing trigger signal EN. The drains of each transistor are interconnected to form node O0. P2, P3, N2, and N3 form the intermediate stage, with the gates of P3 and N3 connected to node O0. Point 1: P2 and N2 gates are connected to EN, and the drains of each transistor are interconnected to form node O1; P4, P5, N4, and N5 form the output stage, with P4 and N4 gates connected to node O1, P5 and N5 gates connected to output Q, and the drains of each transistor interconnected to form node O2; P6, P7, N6, and N7 form the feedback output stage, with P6 and N6 gates connected to node O0, P7 and N7 gates connected to node O2, and the drains of each transistor interconnected to form output terminal Q; When EN is high, output terminal Q follows the data signal D, and when EN is low, output terminal Q maintains the current level.

5. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, In the cascaded XOR circuit, the first-stage XOR gates perform XOR operations on the signals T1a and T1b read in the first stage and T2a and T2b read in the second stage, respectively, and output intermediate signals Ta and Tb. The second-stage XOR gates perform XOR operations on Ta and Tb, and output the final 1-bit random number. Among them, T1a, T1b, T2a, and T2b are the digital signals output by the dual-channel single-ended readout circuit in the first read stage and the second read stage, respectively.

6. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, The timing control circuit uses a combination of asynchronous timing mechanism and combinational logic control to generate WEN, REN, and EN. Narrow pulses quickly turn on the NMOS memory access transistor, so that the write voltage is applied to the VCMA-MTJ.

7. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1 or 6, characterized in that, The timing control circuit is configured to perform the following timing control steps to achieve a dual-read cycle operating mode: Random write phase (SW1): WEN is set high, WL outputs a narrow pulse, and the write voltage is applied to VCMA-MTJ to complete the first sub-nanosecond random flip; Initial read phase (RD1): WEN is reset to low level, REN is set to high, and the dual-channel single-ended read circuit outputs the first read signals T1a and T1b; Signal tracking phase (LAT): EN is set high, the latch circuit tracks the T1a and T1b signals, then EN is set low, the latch circuit holds T1a and T1b; Secondary write stage (SW2): WEN is set high again, and WL outputs a narrow pulse to complete the second sub-nanosecond random flip; Secondary read stage (RD2): WEN is reset, REN remains high, and the dual-channel single-ended read circuit outputs the second read signals T2a and T2b; Post-processing stage (PP): The cascaded XOR circuit performs operations on T1a, T2a, T1b, and T2b to output the final random number.

8. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, Throughout the entire cycle of the dual-read cycle operating mode, the two NMOS memory access transistors of the 2T2M memory cell remain on.

9. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, When the read enable signal REN is high, the dual-channel single-ended read circuit starts voltage division reading; when it is low, the dual-channel single-ended read circuit is turned off.

10. The voltage-controlled magnetic anisotropic magnetic tunnel junction subnanosecond true random number writing post-processing circuit according to claim 1, characterized in that, The write enable signal WEN and the read enable signal REN are time-isolated.

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