High-side switch output negative voltage limiting circuit and method

Abstract

The application discloses a high-side switch output negative voltage limiting circuit and method, and belongs to the technical field of electronic circuits. In order to solve the problem that the output end generates an excessively high negative voltage when a high-side switch drives an inductive load to be turned off, resulting in device breakdown, at least one Zener diode is connected in series between the gate of an NMOS power tube and the positive end of a power supply, wherein the cathode of the Zener diode is connected to the positive end of the power supply, and the anode is connected to the gate. When the gate voltage is lower than the difference between the positive end of the power supply by more than the total voltage stabilizing value of the Zener diode during turn-off, the Zener diode is reversely broken down, the gate voltage is clamped at a preset potential, the NMOS tube is turned on again, a discharge path from the source to the drain through the channel is formed, and thus the output negative voltage is limited within a safe range. The circuit is simple, low in cost, fast in response speed, high in reliability, and suitable for high-side driving of inductive loads in the fields of new energy vehicles and the like.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a high-side switch output negative voltage limiting circuit and method, which is particularly suitable for high-side power switch drive circuits with inductive loads in systems such as new energy vehicles and industrial automation. Background Technology

[0002] With the development of new energy vehicles, the number of switches required is increasing, and the requirements for intelligent control are also increasing. Traditional automotive component switches are composed of relays and relay control circuits. Traditional relays have several typical disadvantages: 1. The switching speed is relatively slow because of the mechanical parts. 2. When damaged, they need to be replaced at an auto repair shop. 3. The control circuit has high power consumption (because it needs to drive traditional electromagnets).

[0003] New energy vehicle companies, represented by Tesla, are gradually replacing relays with electronic switches to control various components. Electronic switches are divided into high-side switches and low-side switches. There is a problem with replacing relays with high-side switches: when the circuit is turned off, the current in the inductor cannot change abruptly. According to Lenz's law, the inductor will generate a reverse electromotive force in the same direction as the original current, resulting in a very low negative voltage at the top of the load. As a relay, its withstand voltage can fully accept such a high voltage difference, but as a high-side switch of an electronic device, it cannot withstand such a high withstand voltage.

[0004] This negative voltage poses a serious threat to both the high-side switch itself and the load. Excessive negative voltage may cause the source-drain or gate-source voltage of the power transistor (such as NMOS) inside the high-side switch to exceed its tolerance range, resulting in device breakdown and shortening the load life.

[0005] The current conventional solution is to connect a Zener diode in parallel between the output of the high-side switch and ground. When a negative voltage is generated during turn-off, the reverse breakdown characteristic of the Zener diode dissipates the energy to ground. Figure 1 As shown. The advantages of this scheme are its simple circuit and reliable operation; however, its disadvantages are equally obvious: it requires additional components, which increases material costs; the Zener diode introduces leakage current, and its large junction capacitance affects the system's response speed, especially in high-frequency switching applications.

[0006] Therefore, there is an urgent need for an improved technology that can effectively limit the negative voltage amplitude of the high-side switch output without significantly increasing costs or reducing system response speed. Summary of the Invention

[0007] This invention aims to provide a high-side switch output negative voltage limiting technology to solve the problem that existing high-side switches, when driving an inductive load to turn off, experience excessively high negative voltage at the output due to the back electromotive force generated by the inductive load, which may damage the high-side switch power devices and the load. Simultaneously, it overcomes the shortcomings of traditional solutions using a Zener diode connected in parallel to ground at the output, such as high component cost, large leakage current, large parasitic capacitance, and slow system response speed. To achieve the above objectives, the present invention provides a high-side switch output negative voltage limiting circuit, comprising: The NMOS power transistor has its drain directly connected to the positive terminal of the power supply, and its source as the output terminal directly connected to the first terminal of the inductive load, while the second terminal of the inductive load is grounded.

[0008] The limiting circuit consists of at least one Zener diode connected in series in the same direction. The anode of this series group is directly connected to the positive terminal of the power supply, and the cathode is directly connected to the gate of the NMOS power transistor.

[0009] When the NMOS power transistor is turned off and its gate voltage is lower than the voltage at the positive terminal of the power supply by more than the total reverse breakdown voltage of the series connection, the series connection undergoes reverse breakdown, clamping the gate voltage to a value equal to the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage. At this time, the gate-source voltage of the NMOS power transistor reaches its threshold voltage, and the NMOS power transistor is turned on again, forming a discharge path between the source and drain of the NMOS power transistor, limiting the negative voltage at the output terminal to a value greater than or equal to the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage minus the threshold voltage.

[0010] As a preferred embodiment, the limiting circuit consists of three Zener diodes connected in series, each Zener diode having a regulated voltage of 5.6V.

[0011] As a further improvement, an energy storage capacitor is connected in parallel between the positive terminal of the power supply and ground to absorb the energy fed back by the inductive load when the discharge path is turned on.

[0012] Furthermore, the present invention includes a driving circuit, the output of which is connected to the gate of the NMOS power transistor. The driving circuit provides a gate voltage higher than the positive terminal of the power supply when the NMOS power transistor is turned on, and the difference between this gate voltage and the positive terminal of the power supply is less than the total reverse breakdown voltage of the series connection, thereby keeping the limiting circuit in the off state when the NMOS power transistor is turned on. Preferably, the driving circuit is a bootstrap driving circuit or a charge pump circuit.

[0013] The limiting circuit can be integrated inside the high-side switch driver chip, which has a power supply positive terminal pin, a gate drive output pin, and a ground pin.

[0014] This invention also provides a high-side switch output negative voltage limiting method, applied in a high-side switch circuit including an NMOS power transistor, wherein the drain of the NMOS power transistor is connected to the positive terminal of the power supply, the source is connected to the first terminal of an inductive load, and the second terminal of the inductive load is grounded. The method includes the following steps: (a) At least one Zener diode is connected in series between the gate of the NMOS power transistor and the positive terminal of the power supply, wherein the anode of the series Zener diode is connected to the positive terminal of the power supply and the cathode is connected to the gate of the NMOS power transistor. (b) When the NMOS power transistor is turned off and the negative difference between its gate voltage and the positive terminal of the power supply exceeds the total reverse breakdown voltage of the series group, the Zener diode series group breaks down in reverse, clamping the gate voltage at the potential of the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage. (c) After the gate-source voltage of the NMOS power transistor reaches its threshold voltage, the NMOS power transistor is turned on again, forming a discharge current path from the source to the drain between the source and drain of the NMOS power transistor. This discharge current flows through the inductive load, the NMOS power transistor, and the positive terminal of the power supply, thereby limiting the negative voltage of the source to a value greater than or equal to the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage minus the threshold voltage.

[0015] Furthermore, the negative voltage limit at the output terminal is adjusted by selecting the number of Zener diodes and / or their voltage regulation values. An energy storage capacitor is connected in parallel between the positive terminal of the power supply and ground to absorb the energy from the discharged current feedback and prevent the voltage at the positive terminal of the power supply from rising.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Only a few small Zener diodes are connected in series between the gate of the NMOS power transistor and the positive terminal of the power supply. This eliminates the need for high-power discharge components, allowing for high integration and virtually no increase in material costs.

[0017] The limiting circuit operates in a low-current, low-capacitance gate circuit with extremely small parasitic parameters. Compared with the traditional solution of paralleling a large-size Zener diode at the output, the switching speed and drive delay of this invention are almost unaffected, making it suitable for high-frequency switching applications.

[0018] By clamping the gate, the power transistor automatically turns on when the negative voltage reaches a set value, limiting the output negative voltage to a safe range. This protects both the power transistor itself and the inductive load, preventing voltage breakdown failure.

[0019] The discharge current is fed back to the power supply terminal or energy storage capacitor through the power transistor channel, so that energy can be recovered or safely consumed. The on-state voltage of the power transistor is reduced and the heat generation is minimal.

[0020] By adjusting the number of Zener diodes or the voltage regulation value, the output negative voltage limit can be precisely set to adapt to loads and power devices with different voltage withstand requirements. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a high-side switching inductive load drive circuit that uses a Zener diode connected in parallel to ground at the output terminal in the existing technology.

[0022] Figure 2 This is a schematic diagram of the high-side switch output negative voltage limiting circuit according to an embodiment of the present invention.

[0023] In the diagram: M1 is an NMOS power transistor, D1 is a Zener diode, VCC is the power supply, OUT is the output terminal, L is the inductive load, and GND is ground. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that these specific embodiments are only for explaining the invention and are not intended to limit the scope of protection of the invention.

[0025] Example: like Figure 1 As shown, this embodiment provides a high-side switch output negative voltage limiting circuit, including: The NMOS power transistor M1 has its drain (D) electrically connected to the positive terminal VCC of the power supply, and its source (S) as the output terminal OUT electrically connected to the first terminal of the inductive load L. The second terminal of the inductive load L is grounded to GND.

[0026] The limiting circuit in this embodiment consists of three Zener diodes D1, D2, and D3 connected in series in the same direction. The voltage regulation value of each Zener diode is 5.6V (total reverse breakdown voltage V). z_total =16.8V). The cathode (usually with a horizontal line) of this series group is directly connected to the positive terminal VCC of the power supply, and the anode is directly connected to the gate G of the NMOS power transistor M1. That is: the cathode of D1 is connected to VCC, the anode of D1 is connected to the cathode of D2, the anode of D2 is connected to the cathode of D3, and the anode of D3 is connected to the gate of M1.

[0027] In this connection mode, when M1 is turned off and the gate voltage drops below VCC, the Zener diode is subjected to a reverse voltage (high for cathode VCC and low for anode gate), thus causing reverse breakdown when the voltage difference exceeds the total regulated value, thereby clamping the gate potential.

[0028] To drive the high-side NMOS power transistor M1, its gate voltage needs to be higher than its source voltage (i.e., higher than VCC). This embodiment uses a bootstrap drive circuit (a well-known technique in the art, which can be integrated into a driver chip): when M1 is off, the bootstrap capacitor (not shown in the figure) is charged to approximately VCC (12V); when M1 needs to be turned on, the drive circuit superimposes the voltage of the bootstrap capacitor onto VCC, providing a gate voltage of approximately VCC + 12V = 24V. Therefore, when M1 is turned on, the gate voltage Vg on ≈24V.

[0029] At this time, the voltage across the limiting circuit (D1~D3) is: VCC - Vg on =12V 24V= 12V. (That is, the voltage between the cathode and the anode is negative, actually forward biased, the Zener diode does not break down, and there is only a very small forward leakage current). Since the absolute value of this voltage (12V) is less than the total reverse breakdown voltage of the Zener diode series group (16.8V), the Zener diode will not enter the reverse breakdown region, the limiting circuit is in a high-impedance state, and it has no effect on the normal conduction of M1.

[0030] During the M1 turn-off period, the bootstrap capacitor is recharged from VCC through the charging diode inside the driver chip. The limiting circuit of this invention operates only briefly during the turn-off moment (microseconds) and its leakage current is extremely small (nA level), so it does not affect the normal charging of the bootstrap capacitor. Therefore, this solution is fully compatible with the bootstrap drive circuit and will not cause insufficient drive voltage when it is turned on again.

[0031] When the drive control circuit pulls the gate voltage of M1 down to 0V (shutdown command), since the current of the inductive load L cannot change abruptly, according to Lenz's law, a reverse electromotive force is generated across L, causing the output terminal OUT (source of M1) voltage to drop rapidly to a negative value. At this time, the gate voltage of M1 (initially 0V) will also change in the negative direction due to Miller capacitance coupling.

[0032] When the gate voltage Vg is lower than VCC and the difference exceeds the Zener diode's total regulated voltage (16.8V), i.e., VCC... Vg≥16.8V→Vg≤VCC 16.8V= At 4.8V, Zener diodes D1-D3 reverse-biased breakdown occurs, clamping the gate voltage to approximately [value missing]. 4.8V (ignoring Zener transistor on-resistance). Therefore, the gate voltage will not be lower than 4.8V. 4.8V.

[0033] The threshold voltage Vth of M1. When the source voltage Vs decreases, causing the gate-source voltage Vgs = Vg... When Vs≥Vth, M1 is turned on again. (Depending on Vg) min = From 4.8V, the minimum source voltage is: Vs min =Vg min Vth= 4.8V 1V= 5.8V, meaning the output negative voltage is limited to approximately 5.8V or higher.

[0034] Energy discharge path: When M1 is turned on again, the current in inductor L (flowing from ground through L to OUT) flows through the channel of M1 to the drain, and then into the VCC power supply terminal. Since a large-capacity decoupling capacitor or battery is connected in parallel to the VCC terminal in the actual system, these energy storage components can absorb the feedback energy without causing the VCC voltage to rise. The specific circuit is: Ground → Inductive load L → OUT (M1 source) → M1 channel → M1 drain → VCC node → Decoupling capacitor / battery → Ground. Therefore, the energy stored in the inductive load is safely transferred to the power supply capacitor or battery, avoiding excessive negative voltage.

[0035] Before M1 is turned on again, if the absolute value of the output negative voltage exceeds approximately 0.7V, the body diode (source to drain) of M1 will conduct in the forward direction, providing an additional initial discharge path. The conduction current of this body diode is limited by the loop impedance, and its current density is typically within a safe range. Once the M1 channel is turned on, the body diode is bypassed, and the channel bears the main discharge current. The presence of the body diode does not affect the limiting function of this invention; rather, it provides additional reliability protection.

[0036] During the off period, the duration of M1's re-conduction is extremely short. (Inductor energy storage) Most of the energy is fed back to the power supply or consumed in the load resistance and line resistance. The energy consumed by M1 itself is only the on-state voltage drop (Vsat ≈ 0.2V~0.5V) multiplied by the current and the on-time, which is a very small value.

[0037] For larger inductors or higher frequencies, similar estimations can be made to ensure that the junction temperature does not exceed the rated value. This invention is applicable to most automotive inductive loads (inductance ≤ 10mH, current ≤ 5A, frequency ≤ 2kHz). For loads exceeding this range, it is recommended to incorporate a heat dissipation design or limit the switching frequency.

[0038] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-side switch output negative voltage limiting circuit, characterized by, include: The NMOS power transistor has its drain directly connected to the positive terminal of the power supply, and its source as the output terminal directly connected to the first terminal of the inductive load, while the second terminal of the inductive load is grounded. The limiting circuit consists of at least one Zener diode connected in series in the same direction. The anode of this series group is directly connected to the positive terminal of the power supply, and the cathode is directly connected to the gate of the NMOS power transistor. Specifically, when the NMOS power transistor is turned off and its gate voltage is lower than the voltage at the positive terminal of the power supply by more than the total reverse breakdown voltage of the series group, the series group undergoes reverse breakdown, clamping the gate voltage at the potential of the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage; after the gate-source voltage of the NMOS power transistor reaches its threshold voltage, the NMOS power transistor is turned on again, forming a discharge path between the source and drain of the NMOS power transistor, limiting the negative voltage at the output terminal to a value above the value of the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage minus the threshold voltage.

2. The high-side switch output negative voltage limiting circuit of claim 1, wherein, The limiting circuit consists of three Zener diodes connected in series, each Zener diode having a regulated voltage of 5.6V.

3. The high-side switch output negative voltage limiting circuit of claim 1, wherein, An energy storage capacitor is also connected in parallel between the positive terminal of the power supply and ground to absorb the energy fed back by the inductive load when the discharge path is open.

4. The high-side switch output negative voltage limiting circuit according to claim 1, characterized in that, It also includes a driving circuit, the output of which is connected to the gate of the NMOS power transistor. The driving circuit is used to provide a gate voltage higher than the positive terminal of the power supply when the NMOS power transistor is turned on, and the difference between the gate voltage and the positive terminal of the power supply is less than the total reverse breakdown voltage of the series group, so that the limiting circuit remains in the off state when the NMOS power transistor is turned on.

5. The high-side switch output negative voltage limiting circuit according to claim 4, characterized in that, The driving circuit is a bootstrap driving circuit or a charge pump circuit.

6. The high-side switch output negative voltage limiting circuit according to claim 1, characterized in that, The limiting circuit is integrated inside the high-side switch driver chip, which has a power supply positive terminal pin, a gate drive output pin, and a ground pin.

7. A method for limiting negative voltage at the output of a high-side switch, applied in a high-side switch circuit including an NMOS power transistor, wherein the drain of the NMOS power transistor is connected to the positive terminal of a power supply, the source is connected to a first terminal of an inductive load, and the second terminal of the inductive load is grounded, characterized in that... Includes the following steps: (a) At least one Zener diode is connected in series between the gate of the NMOS power transistor and the positive terminal of the power supply, wherein the anode of the series Zener diode is connected to the positive terminal of the power supply and the cathode is connected to the gate of the NMOS power transistor. (b) When the NMOS power transistor is turned off and the negative difference between its gate voltage and the positive terminal of the power supply exceeds the total reverse breakdown voltage of the series group, the Zener diode series group breaks down in reverse, clamping the gate voltage at the potential of the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage. (c) After the gate-source voltage of the NMOS power transistor reaches its threshold voltage, the NMOS power transistor is turned on again, forming a discharge current path from the source to the drain between the source and drain of the NMOS power transistor. This discharge current flows through the inductive load, the NMOS power transistor, and the positive terminal of the power supply, thereby limiting the negative voltage of the source to a value greater than or equal to the voltage at the positive terminal of the power supply minus the total reverse breakdown voltage minus the threshold voltage.

8. The high-side switch output negative voltage limiting method according to claim 7, characterized in that, In step (a), the negative voltage limit value of the output terminal is adjusted by selecting the number of Zener diodes and / or the voltage regulation value.

9. The high-side switch output negative voltage limiting method according to claim 7, characterized in that, A storage capacitor is connected in parallel between the positive terminal of the power supply and ground to absorb the energy of the discharge current feedback in step (c) and prevent the voltage of the positive terminal of the power supply from rising.

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