Transmitter circuit for an NFC device and control method thereof, NFC device

Abstract

This application relates to the field of integrated circuit technology and discloses a transmitter circuit for an NFC device, comprising: a power transistor array configured to drive an antenna; a driving clock generation module configured to generate a clock signal driving the power transistor array; and a dead-time logic control module configured to control the driving clock generation module to insert a dead-time interval within at least one carrier cycle when switching between an unmodulated phase and a modulation phase. The dead-time interval is positioned within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated and modulation phases. Furthermore, within the dead-time interval, the dead-time logic control module controls the power transistor array to be completely turned off. The transmitter circuit of this application can avoid hysteresis effects during the cancellation of the antenna field envelope waveform, enabling a smooth transition of the antenna field envelope during modulation switching. This application also discloses a control method based on the transmitter circuit and an NFC device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, such as to a transmitter circuit for an NFC device and its control method, and an NFC device. Background Technology

[0002] When an NFC device operates as a PCD (Card Distributor), it involves establishing a transmission field and an antenna impedance matching network. In actual transmission, differences in transmission power, variations in the card distributor's internal resistance, and differences in the matching degree of the antenna matching network can all lead to overshoot or undershoot in the antenna field envelope during data transmission. According to relevant protocols such as EMV (Electronic Device Management System), strict constraints are placed on the fall time and undershoot depth of the antenna envelope from the unmodulated to the modulated phase, as well as the rise time and overshoot height from the modulated to the unmodulated phase. When the antenna field envelope waveform does not conform to these constraints, it can affect product specifications and compatibility, or even directly lead to communication failure.

[0003] In related technologies, a common suppression method is to perform envelope detection on the antenna field envelope, compare the real-time detected field envelope amplitude with the reference transmit field envelope amplitude during the unmodulated period, and feed the comparison result back to the power transistor control terminal. During the modulation stage, this feedback adjustment process is activated: when the antenna envelope overshoots, the overshoot is suppressed through negative feedback adjustment; when the antenna envelope undershoots, the transmit capability is enhanced through negative feedback adjustment to compensate for the undershoot.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: Because the negative feedback loop itself has an inherent delay, the adjustment action cannot be precisely synchronized with the occurrence of overshoot or undershoot. This results in a hysteresis effect during the cancellation of the antenna field envelope waveform, thus affecting the adjustment effect.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a transmitter circuit and control method for an NFC device, as well as an NFC device, to avoid hysteresis effects that occur during the cancellation of the antenna field envelope waveform, so that the antenna field envelope can smoothly transition during modulation switching.

[0008] In some embodiments, the transmitter circuit for an NFC device includes: a power transistor array configured to drive an antenna; a drive clock generation module electrically connected to the power transistor array and configured to generate a clock signal driving the power transistor array; and a dead-time logic control module electrically connected to the drive clock generation module and configured to control the drive clock generation module to insert a dead-time interval within at least one carrier cycle when switching between an unmodulated phase and a modulated phase; wherein the dead-time interval is positioned within the carrier cycle to avoid the dead-time interval being located at the direct switching boundary between the unmodulated phase and the modulated phase, and within the dead-time interval, the dead-time logic control module controls the power transistor array to be completely turned off, so that the antenna connection of the transmitter circuit is in a high-impedance state.

[0009] Optionally, the transmitter circuit for the NFC device further includes: a clamping circuit, the output of which is electrically connected to the antenna connection; and a dead-zone logic control module configured to enable the clamping circuit within the dead-zone interval to clamp the potential of the antenna connection to a preset intermediate potential.

[0010] Optionally, the clamping circuit includes a linear regulator and a first high-voltage switch. The output terminal of the linear regulator is electrically connected to the antenna connection terminal through the first high-voltage switch. The dead-time logic control module is configured to control the first high-voltage switch to conduct within the dead-time interval, clamping the antenna connection terminal to the output voltage of the linear regulator.

[0011] Optionally, the first high-voltage switch includes a first branch switch and a second branch switch, the first branch switch being connected in series between the first connection terminal of the antenna connection terminal and the output terminal of the linear regulator, and the second branch switch being connected in series between the second connection terminal of the antenna connection terminal and the output terminal of the linear regulator; the clamping circuit further includes a second high-voltage switch, the second high-voltage switch being connected in series between the first connection terminal and the second connection terminal of the antenna connection terminal.

[0012] Optionally, the transmitter circuit for the NFC device further includes: a level conversion circuit configured to convert a low-voltage control signal output by the dead-zone logic control module into a high-voltage control signal to drive a first high-voltage switch; wherein the voltage value of the high-voltage control signal is greater than the sum of the power supply voltage of the power transistor array and the threshold voltage of the first high-voltage switch.

[0013] Optionally, the level conversion circuit includes: a cross-coupled first PMOS transistor and a second PMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor being connected to a high-voltage power supply terminal, the drain of the first PMOS transistor being electrically connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor being electrically connected to the gate of the first PMOS transistor; a first pump capacitor, the first plate of the first pump capacitor being electrically connected to the drain of the first PMOS transistor, and the second plate of the first pump capacitor being electrically connected to a first input node; a second pump capacitor, the first plate of the second pump capacitor being electrically connected to the drain of the second PMOS transistor, and the second plate of the second pump capacitor being electrically connected to a second input node; and an initial state enable control terminal, configured to precharge the first pump capacitor and the second pump capacitor to an initial state when the level conversion circuit is not enabled.

[0014] Optionally, the power transistor array includes multiple groups of NMOS power transistors, each group of NMOS power transistors including multiple parallel power transistor units with different weights; the transmitter circuit also includes: a first register group for configuring the pull-down strength of the NMOS power transistors in the unmodulated state; a second register group for configuring the pull-down strength of the NMOS power transistors in the non-dead zone in the modulated state; and a third register group for configuring the pull-down strength of the NMOS power transistors in the dead zone; the dead zone logic control module is configured to select the first register group, the second register group, or the third register group according to the current operating state to control the number of NMOS power transistors turned on.

[0015] Optionally, the driving clock generation module includes: a duty cycle configuration unit configured to configure the driving clock duty cycles for the unmodulated stage and the modulation stage respectively; and a synchronization unit electrically connected to the duty cycle configuration unit configured to synchronize the switching edge of the duty cycle configuration unit with the modulation data so that the switching of the duty cycle is strictly aligned with the switching of the modulation state.

[0016] In some embodiments, the control method based on the transmitter circuit includes: when switching between the unmodulated phase and the modulation phase, inserting a dead zone interval within at least one carrier cycle; wherein the dead zone interval is set at a position within the carrier cycle to avoid the dead zone interval being located at the direct switching boundary between the unmodulated phase and the modulation phase, and within the dead zone interval, the dead zone logic control module controls the power transistor array to be completely turned off so that the antenna connection terminal of the transmitter circuit is in a high-impedance state.

[0017] In some embodiments, the NFC device includes: an NFC device body; and a transmitter circuit for an NFC device as described above, mounted on the NFC device body.

[0018] The transmitter circuit and control method for NFC devices, as well as the NFC devices provided in this disclosure, can achieve the following technical effects: In this disclosed technical solution, when switching between the unmodulated and modulated stages, the control drive clock generation module inserts a dead zone interval within at least one carrier cycle. The dead zone interval is positioned within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated and modulated stages. Furthermore, within the dead zone interval, the dead zone logic control module completely shuts down the power transistor array, placing the antenna connection of the transmitter circuit in a high-impedance state. Thus, at the same moment the modulation switching occurs, the drive timing is pre-intervened—the energy mutation path is blocked in advance through the dead zone interval, and the antenna connection enters a high-impedance state, avoiding the generation of overshoot or undershoot phenomena rather than post-event compensation. Simultaneously, since there is no need to wait for envelope detection and feedback loop response, active control synchronized with the switching moment is achieved, completely eliminating the cancellation hysteresis effect caused by the inherent delay of the feedback loop. This allows for a smooth transition of the antenna field envelope from the unmodulated stage to the modulated stage or in the reverse direction.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the structure of a transmitter circuit for an NFC device provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another transmitter circuit for an NFC device provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another transmitter circuit for an NFC device provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another transmitter circuit for an NFC device provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the arrangement of a power transistor array provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the state of a power transistor array provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the state of another power transistor array provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of an NMOS power transistor configuration selection provided in an embodiment of this disclosure; Figure 9This is a schematic diagram of an NMOS power transistor selection control circuit provided in an embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of an NMOS power transistor selection control circuit provided in an embodiment of this disclosure; Figure 11 This is a schematic diagram of a PMOS power transistor selection control circuit provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of a PMOS power transistor selection control circuit provided in an embodiment of this disclosure; Figure 13 This is a schematic diagram of an NMOS power transistor driving circuit provided in an embodiment of this disclosure; Figure 14 This is a schematic diagram of a driving clock generation circuit provided in an embodiment of this disclosure; Figure 15 This is a schematic diagram of a level conversion circuit provided in an embodiment of this disclosure; Figure 16 This is a schematic diagram of the structure of a linear regulator provided in an embodiment of this disclosure; Figure 17 This is a schematic diagram of the driving clock waveform from the unmodulated stage to the modulation stage provided in an embodiment of this disclosure; Figure 18 This is a waveform diagram of a dead-zone generation logic in the modulation stage provided in an embodiment of this disclosure; Figure 19 This is a schematic diagram of the timing logic for generating a fixed level by clamping TX from the unmodulated stage to the modulation stage, provided in an embodiment of this disclosure. Figure 20 This is a schematic diagram of the timing logic for generating a fixed level by clamping TX from the modulation stage to the unmodulated stage, provided in an embodiment of this disclosure. Figure 21 This is a timing diagram of a modulation stage dead zone state TX1 / TX2 being clamped to a fixed potential, provided in an embodiment of this disclosure; Figure 22 This is a schematic diagram of the antenna field envelope before and after optimization, provided in an embodiment of this disclosure; Figure 23 This is a flowchart illustrating a control method based on a transmitter circuit provided in an embodiment of this disclosure; Figure 24 This is a schematic diagram of the structure of a control device based on a transmitter circuit provided in an embodiment of this disclosure; Figure 25 This is a schematic diagram of the structure of an NFC device provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more. In embodiments of this disclosure, the character " / " indicates that the preceding and following objects are in an "OR" relationship. For example, A / B means: A or B. The term "and / or" describes an association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B. The term "correspondence" can refer to an association or binding relationship; A corresponding to B means that there is an association or binding relationship between A and B.

[0024] NFC devices, as card-to-device communication devices, follow the 14443 protocol and primarily transmit two data types: TYPE A and TYPE B. For TYPE A, the ideal transmission field's antenna envelope has two states: an unmodulated transmission field and a 100% modulated non-transmission field. For TYPE B, the ideal transmission field's antenna envelope has two states: an unmodulated transmission field and a field modulated with a modulation depth of 9% to 14%. When an NFC card-to-device device transmits a TYPE A waveform according to the 14443 protocol, overshoot can easily occur in the field strength envelope at the switching moments between the unmodulated and 100% modulated non-transmission fields, and at the switching moments from 100% modulated non-transmission back to the unmodulated transmission field. When an NFC card reader transmits a TYPE B waveform according to the 14443 protocol, an undershoot envelope is easily formed on the field strength envelope when transmitting a large field strength without modulation to transmitting a smaller field with a modulation depth of 9% to 14%; and an overshoot envelope is easily formed on the field strength envelope when transmitting a smaller field with a modulation depth of 9% to 14% to transmitting a larger field strength without modulation.

[0025] The technical solution disclosed herein intervenes in the driving timing at the same time as modulation switching occurs—by blocking the energy mutation path in advance through the dead zone interval and putting the antenna connection end into a high impedance state, thereby avoiding the hysteresis effect that occurs during the cancellation of the antenna field envelope waveform and enabling the antenna field envelope to transition smoothly during modulation switching.

[0026] See Figure 4 As shown, the transmitter circuit provided in this embodiment adopts a multi-stage power supply architecture to meet the voltage requirements of different functional modules. The external power supply VBAT serves as the overall input power supply, connected to a boost converter (DCDC), a transmitter linear regulator (PA_LDO), a digital power supply linear regulator (DIG_LDO), and a high-voltage linear regulator (HV_LDO). The boost converter (DCDC) boosts VBAT to the high-voltage control power supply VDDH, providing drive voltage for subsequent level conversion circuits and high-voltage switching transistors. The transmitter linear regulator (PA_LDO) outputs a power transistor power supply VDDPA to drive the power transistor array for antenna operation. The digital power supply linear regulator (DIG_LDO) outputs a digital control power supply VDDC to power the low-voltage logic module (LOGIC) and registers, among other digital circuits. The high-voltage linear regulator (HV_LDO) outputs a configurable clamping voltage VC to clamp the antenna connection to an intermediate potential during the dead-time phase.

[0027] At the functional module level, the transmitter circuit mainly includes a low-voltage logic module (LOGIC), a P-power transistor data register (Prigster), an N-power transistor data register (Nrigster), a level shifter / level conversion circuit (LevelShift), a high-voltage driver (HV_Driver), and a power transistor array (Power MOS). Among them, the low-voltage logic module (LOGIC) serves as the control core, receiving modulation data and clock signals, generating dead-time logic control signals, and outputting them to the P-power transistor data register, the N-power transistor data register, and the level shifter, respectively. The P-power transistor data register and the N-power transistor data register output corresponding power transistor configuration data according to the current operating state (unmodulated, modulated without dead time, dead time), which, after being driven by the high-voltage driver (HV_Driver), controls the conduction and cutoff of the PMOS and NMOS transistors in the power transistor array (Power MOS).

[0028] To achieve antenna clamping during dead-time conditions, the transmitter circuit further integrates a boost converter (DCDC), a high-voltage linear regulator (HV_LDO), NMOS switches for the TX1 and TX2 branches, and a dead-time logic control module (LOGIC). Within the dead-time range, the LOGIC outputs a low-voltage control signal to a level converter. The level converter, using the high-voltage power supply VDDH provided by the boost converter, converts the low-voltage signal into a high-voltage control signal LOGIC_CTRL_H. This high-voltage control signal simultaneously activates the NMOS switches for both the TX1 and TX2 branches, transmitting the configurable clamping voltage VC output from the HV_LDO to the first connection terminal (TX1) and the second connection terminal (TX2) of the antenna connection. This actively clamps the antenna potential to an intermediate potential during the high-impedance dead-time period, preventing voltage jumps introduced by the floating state.

[0029] Through the coordinated operation of the aforementioned power supply architecture and functional modules, the transmitter circuit can achieve a smooth transition of the antenna field envelope by using a combination of dead-zone insertion, power transistor shutdown, and antenna clamping mechanisms when switching between unmodulated and modulated states, effectively suppressing overshoot and undershoot phenomena.

[0030] Combination Figure 1 As shown, this embodiment of the present disclosure provides a transmitter circuit 100 for an NFC device, including: a power transistor array 110 configured to drive an antenna 101; a driving clock generation module 120 electrically connected to the power transistor array 110 and configured to generate a clock signal driving the power transistor array 110; and a dead-time logic control module 130 electrically connected to the driving clock generation module 120 and configured to control the driving clock generation module 120 to insert a dead-time interval within at least one carrier cycle when switching between an unmodulated phase and a modulated phase. The dead-time interval is positioned within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated phase and the modulated phase. Furthermore, within the dead-time interval, the dead-time logic control module 130 controls the power transistor array 110 to be completely turned off, so that the antenna 101 connection terminal of the transmitter circuit 100 is in a high-impedance state.

[0031] Optionally, the transmitter power transistor array 110 includes a first power transistor array 110 for driving the first connection terminal (TX1) of the antenna 101 and a second power transistor array 110 for driving the second connection terminal (TX2) of the antenna 101. Both the first power transistor array 110 and / or the second power transistor array 110 include multiple sets of PMOS power transistors (as upper transistors) and multiple sets of NMOS power transistors (as lower transistors). Each set of power transistors is composed of multiple power transistor units connected in parallel to achieve fine-tuning of the driving intensity.

[0032] In some possible implementations, the power transistors in the power transistor array 110 are designed hierarchically according to weights. The first power transistor array 110 and / or the second power transistor array 110 include power transistors with a weight of 1 and power transistors with a weight less than 1 (e.g., weights of 1 / 2, 1 / 4, 1 / 8, etc.). The power transistors with a weight of 1 are used to adjust the transmit energy over a wide range, while the power transistors with a weight less than 1 are used for fine-tuning the transmit energy. By configuring the number of power transistors with different weights, the equivalent on-resistance can be continuously adjusted, thereby precisely controlling the drive current and pull-down strength at the antenna 101.

[0033] In practical applications, the transmitter power transistor array 110 adopts a differential symmetrical structure to drive the antenna 101 connection terminals TX1 and TX2 respectively. For example... Figure 5 As shown, the TX1 side power transistor array 110 includes 18 PMOS transistors (P1-P18) and 18 NMOS transistors (N1-N18), and the TX2 side power transistor array 110 includes 18 PMOS transistors (P19-P36) and 18 NMOS transistors (N19-N36).

[0034] The power transistor units in each power transistor array 110 are designed hierarchically according to weights. Specifically, taking the TX1 side as an example: P1, P2, and P3 are PMOS transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, used for fine-tuning; P4-P18 are PMOS transistors with a weight of 1, used for coarse-tuning over a wide range; N1, N2, and N3 are NMOS transistors with weights of 1 / 8, 1 / 4, and 1 / 2 respectively, used for fine-tuning; N4-N18 are NMOS transistors with a weight of 1, used for coarse-tuning over a wide range. The power transistor array 110 on the TX2 side adopts the same weight distribution structure (P19-P21 and N19-N21 are fine-tuning transistors, and P22-P36 and N22-N36 are coarse-tuning transistors).

[0035] During transmitter operation, each 16 carrier cycles constitute a configuration cycle. By selectively activating power transistors with different weight combinations, the equivalent on-resistance can be flexibly adjusted to achieve a wide range of adjustments and fine-tuning of the transmitted energy, thereby adaptively canceling overshoot or undershoot based on the degree of overshoot or undershoot on the antenna's 101 field envelope.

[0036] The aforementioned power transistor array 110 structure achieves multi-level adjustment capability of transmit energy from macroscopic to microscopic by classifying the power transistor units according to weights (weight 1 is used for coarse adjustment, and weights 1 / 2, 1 / 4, and 1 / 8 are used for fine adjustment). Combined with the dynamic configuration mechanism every 16 carrier cycles, it can adjust the drive strength and pull-down impedance in real time according to the actual overshoot or undershoot of the antenna 101 field envelope. This provides a precise execution basis for dead-zone insertion and clamping mechanisms at the hardware level, ensuring that the antenna 101 field envelope can achieve a smooth transition during modulation switching, effectively meeting the stringent requirements of EMV and other protocols for envelope waveform quality.

[0037] Optionally, switching between the unmodulated phase and the modulation phase includes: switching from the unmodulated phase to the modulation phase, and switching from the modulation phase to the unmodulated phase.

[0038] Combination Figure 17 As shown, the drive clock duty cycle is 50% during the unmodulated phase; during the modulation phase, the drive clock duty cycle is greater than or less than 50%. At the moment of switching, due to the abrupt change in drive state, undershoot (from unmodulated to modulated) or overshoot (from modulated to unmodulated) phenomena in the antenna's 101-field envelope are easily generated. Therefore, this application has specifically designed the drive clock at the switching moment and the power transistor configuration in the dead-time state.

[0039] The drive clock generation module 120 is configured to generate clock signals for driving the power transistor array 110. Taking two consecutive 13.56MHz carrier cycles as an example, the drive clock signals CLK_TX1 and CLK_TX2 are used to drive the TX1 and TX2 power transistor arrays 110, respectively, and their phases are opposite during the transmission phase. One clock cycle in the unmodulated phase is defined as phase A, with a duty cycle of 50%, and the drive clocks for TX1 and TX2 are out of phase. Within one clock cycle in the modulated phase, it is divided into three phases: phase B, which is continuous with phase A and maintains the same clock phase; phase C, where the drive clocks for TX1 and TX2 are both set to high level, i.e., the dead zone; and phase D, where the drive clock phase is opposite to that of phase A. The above four phases A, B, C, and D constitute a complete timing waveform that transitions continuously from phase A to phase B, through the dead zone phase C, and then into the inverted phase D. Among them, phases A and B are continuous, phase C is the dead zone, and phase D is the inverted transmission.

[0040] Combination Figure 6 As shown, Figure 17 The power transistor states corresponding to each driving clock stage are as follows: Stage A driving clock corresponding to... Figure 6 (B) and Figure 6 (A) combination state; B stage driving clock corresponding Figure 6 (B) State; C stage (dead zone) driving clock corresponding Figure 6(C) State (N-channel transistor is on and pulled down) or Figure 7 State (P-stage and N-stage transistors are both off); D-stage drive clock corresponding to Figure 6 (A) State. Among them, Figure 6 (C) The state is defined as the dead zone state in the modulation stage, and its proportion in one carrier cycle is positively correlated with the modulation depth.

[0041] In some possible implementations, the N-power transistor is in a pull-down state during the dead time. The larger the dead time ratio, the more the transmit energy is suppressed and the deeper the modulation depth.

[0042] Figure 6 In (C), the TX power transistor is in the state where all the P power transistors of TX1 and TX2 are off, and the N power transistors of TX1 and TX2 are in the state of being pulled down. This state is defined as the dead zone state in the modulation stage. The larger the proportion of the dead zone state in a 13.56MHz cycle, the more the transmitted energy is suppressed, the smaller the amplitude of the field envelope, and the deeper the modulation depth.

[0043] In some possible implementations, the N power transistor is configured to be fully off during the dead time state, so that both the PMOS and NMOS are in a high-impedance state.

[0044] Combination Figure 7 As shown, Figure 6 (C) The pull-down state of the N power transistor in the dead time state is changed to the off state. That is, in the dead time state, both the P power transistor and the N power transistor are turned off, and the entire TX1 and TX2 power transistors are in a high impedance state.

[0045] During the dead zone (C phase), the drive states of the power transistor array 110 are as follows: PMOS power transistors (i.e., P power transistors) are forcibly turned off by the drive clock (P_CLK=0, P_CTRL is pulled to VDDPA); NMOS power transistors (i.e., N power transistors) are jointly controlled by the drive clock and register configuration.

[0046] In transmitter circuit 100, the PMOS and NMOS power transistors on the TX1 and TX2 sides are controlled by independent register bits. The bit width of the register corresponds to the number of power transistor cells in each group of power transistors. The correspondence between the register bit width and the number of power transistor cells in the PMOS power transistors is as follows:

[0047] Where W is the bit width of the register and N is the number of power transistor units in each group of power transistors.

[0048] For example: Figure 5The power transistor array 110 shown requires a 19-bit register to control the on / off state of each PMOS power transistor and each NMOS power transistor.

[0049] Optionally, the power transistor array 110 includes multiple groups of NMOS power transistors, each group of NMOS power transistors including multiple parallel power transistor units with different weights; the transmitter circuit 100 further includes: a first register group for configuring the pull-down strength of the NMOS power transistors in the unmodulated state; a second register group for configuring the pull-down strength of the NMOS power transistors in the non-dead zone in the modulated state; and a third register group for configuring the pull-down strength of the NMOS power transistors in the dead zone; the dead zone logic control module 130 is configured to select the first register group, the second register group, or the third register group according to the current operating state to control the number of NMOS power transistors turned on.

[0050] For NMOS power transistors, such as Figure 8 As shown, three sets of registers are configured to correspond to different working states: the first register group (DN_1) is used in the unmodulated stage and is configured with a larger pull-down strength; the second register group (DN_2) is used in the non-dead zone of the modulation stage and is configured with a smaller pull-down strength; the third register group (DN_3) is used in the dead zone and can be configured to all 0s to achieve full NMOS shutdown.

[0051] NMOS power transistor state control circuit, such as Figure 9 As shown, it uses two-stage multiplexers (MUX1, MUX2, specifically implemented as follows) Figure 10 (As shown) This implements the selection of configuration values ​​for the three sets of registers. The configuration of the NMOS power transistor is determined by the modulation data TXD and the logic control signal LOGIC_CTRL. The specific selection logic is as follows: When TXD = 1, the transmitter is in the unmodulated stage. The S terminal of MUX2 selects the A path and enables the first register group DN_1<18:0>. This register group configures the pull-down strength of the NMOS power transistor in the unmodulated state (usually configured to a large value). When TXD = 0, the transmitter is in the modulation phase, and the S terminal of MUX2 selects the B path. At this time, the selection of MUX1 is further controlled by the LOGIC_CTRL signal: if LOGIC_CTRL = 0, it indicates that it is in the non-dead zone of the modulation phase, the A path of MUX1 is selected, and the second register group DN_2<18:0> is output. This register group configures the pull-down strength of the NMOS power transistor in the non-dead zone state of modulation (usually configured to a small value); if LOGIC_CTRL = 1, it indicates that it is in the dead zone of the modulation phase, the B path of MUX1 is selected, and the third register group DN_3<18:0> is output. This register group configures the conduction state of the NMOS power transistor in the dead zone state (usually configured to all 0s to achieve complete turn-off of the NMOS transistor).

[0052] Through the above two-stage selection mechanism, the NMOS power transistor can be independently configured in three operating states: unmodulated, modulated non-dead zone, and dead zone, to achieve fine segmented control of the pull-down strength.

[0053] PMOS power transistor state control circuit, such as Figure 11 As shown. Unlike NMOS, PMOS power transistors only require two registers (DP_1<18:0>, DP_2<18:0>), which are directly selected by the modulation data TXD, without the need for staged configuration. Specifically: when TXD = 1 (unmodulated stage), the first register group DP_1<18:0> is selected; when TXD = 0 (modulated stage), the second register group DP_2<18:0> is selected. The PMOS power transistor's turn-off is not directly achieved by register configuration, but is controlled by the drive clock. During the dead time interval (LOGIC_CTRL = 1), the drive clock P_CLK is set to 0, and after... Figure 12 After the NAND gate driver circuit shown, P_CTRL is forced to the power supply level VDDPA, turning off the PMOS power transistor and making it unaffected by the DP register configuration.

[0054] Within the dead zone (LOGIC_CTRL = 1), to achieve complete shutdown of the power transistor array 110, the following cooperative control is employed: For NMOS power transistors, by configuring the third register group DN_3<18:0> to all 0s, Figure 13 In the NOR gate driver circuit shown, the N_CTRL output is 0, thus turning off the NMOS power transistor. For the PMOS power transistor, it is forcibly turned off by the driving clock (P_CLK = 0), pulling P_CTRL to VDDPA, thereby turning off the PMOS power transistor. Through the above mechanism, both the PMOS and NMOS power transistors are turned off within the dead time interval, keeping the antenna 101 connection terminal in a high-impedance state, providing the necessary conditions for the operation of the subsequent clamping circuit 140.

[0055] like Figure 12 As shown, the PMOS power transistor drive circuit consists of NAND gates P1, P2, N1, and N2, where P_CLK is the input clock signal and DP is the PMOS power transistor strobe signal. During the dead time interval (LOGIC_CTRL=1), the drive clock P_CLK is set to 0. At this time, regardless of the value of DP, the NAND gate output P_CTRL is forcibly pulled to the power supply level VDDPA, turning off the PMOS power transistor. Therefore, the turn-off of the PMOS power transistor is entirely controlled by the drive clock and is not affected by the register configuration DP.

[0056] like Figure 13 As shown, the NMOS power transistor driver circuit consists of a NOR gate structure composed of P3, P4, N3, and N4, where N_CLK is the input clock signal and DN is the NMOS power transistor strobe signal. During the dead time interval (LOGIC_CTRL=1), the driver clock N_CLK is set to 0. At this time, the state of the NOR gate output N_CTRL is determined by DN. To achieve complete turn-off of the NMOS power transistor during the dead time, the third register group DN_3<18:0> is configured to all 0s, making the N_CTRL output 0, thereby turning off the NMOS power transistor.

[0057] Through the above mechanism, within the dead zone (LOGIC_CTRL=1): the PMOS power transistors are forcibly turned off by the driving clock (P_CLK=0); the NMOS power transistors are turned off by configuring all zeros in the register (DN_3=all zeros). The two work together to completely turn off the power transistor array 110, putting the antenna 101 connection terminal in a high-impedance state, providing the necessary operating conditions for the subsequent clamping circuit 140.

[0058] The timing of the dead-time logic control module 130 is as follows: Figure 18As shown. This module generates the control selection signal LOGIC_CTRL during modulation by combining the modulation data control signal (TXD) with the TX1 and TX2 drive clock control signals through combinational logic design. The NMOS power transistor's register configuration selection is jointly controlled by TXD and LOGIC_CTRL. The specific selection logic is as follows: When TXD = 1, the transmitter is in the unmodulated stage, and the first register configuration value (N-transistor register configuration value 1) is selected. This value is usually configured with a large pull-down strength to maintain a stable unmodulated transmission field. When TXD = 0, the transmitter is in the modulation stage. At this time, the selection is further based on LOGIC_CTRL: If LOGIC_CTRL = 0, it indicates that it is in the non-dead zone of the modulation stage, and the second register configuration value (N-transistor register configuration value 2) is selected. This value is usually configured with a small pull-down strength to achieve the required modulation depth. If LOGIC_CTRL = 1, it indicates that it is in the dead zone of the modulation stage, and the third register configuration value (N-transistor register configuration value 3) is selected. This value can be flexibly configured. In the preferred implementation, it is configured as all 0s to completely turn off the NMOS power transistor. Through the above two-level selection mechanism, the dead-time logic control module 130 realizes independent configuration of the NMOS power transistor in three working states: unmodulated stage, modulation non-dead-time stage, and modulation dead-time stage, providing the transmitter with flexible energy adjustment and envelope shaping capabilities.

[0059] Optionally, the drive clock generation module 120 includes: a duty cycle configuration unit configured to configure the drive clock duty cycle for the unmodulated stage and the modulated stage respectively; and a synchronization unit electrically connected to the duty cycle configuration unit and configured to synchronize the switching edge of the duty cycle configuration unit with the modulation data so that the switching of the duty cycle is strictly aligned with the switching of the modulation state.

[0060] In some possible implementations, the duty cycle configuration unit employs a multi-stage delay chain structure, adjusting the duty cycle by controlling the delay between the rising and falling edges of the clock signal. For example... Figure 14 As shown, taking the two branches CLK_TX1 and CLK_TX2 as examples, each branch is configured with a 3-bit control register to select different delay link lengths. The 3-bit register can be configured with 8 different delay values, corresponding to 8 different clock duty cycles. In the unmodulated stage, the 3-bit register is configured to a certain value, making the driving clock duty cycle 50%; in the modulation stage, the 3-bit register is configured to another value, making the driving clock duty cycle greater than or less than 50%, to achieve the required modulation depth.

[0061] In some possible implementations, the synchronization unit employs a two-stage synchronization mechanism, including a first-stage synchronization and a second-stage synchronization. The first-stage synchronization synchronizes the modulated data TXD with the first-stage digital clock, generating a synchronized TXD signal. The second-stage synchronization re-synchronizes the previously synchronized TXD with the transmit clock (13.56MHz carrier clock), ensuring that the switching edge of the 3-bit register is strictly aligned with the transition edge of the TXD. This two-stage synchronization ensures that the switching timing of the duty cycle configuration unit precisely matches the switching timing of the modulation state, eliminating clock glitches and phase jitter introduced by asynchronous switching.

[0062] For example, assuming the unmodulated phase drive clock duty cycle is 50% (3-bit register configured as "000") and the modulation phase drive clock duty cycle is 30% (3-bit register configured as "011"), when the TXD signal transitions from high (unmodulated) to low (modulated), the synchronization unit synchronizes this transition edge with the transmit clock at two levels, generating a register switching enable signal. This enable signal is triggered on the rising edge of the transmit clock, switching the 3-bit register from "000" to "011". Because the switching edge is strictly aligned with the TXD transition edge and occurs at a stable clock edge, the drive clock waveform produces no glitches before and after the switch, resulting in a smooth duty cycle transition and avoiding antenna 101-field envelope disturbances caused by sudden clock changes.

[0063] The driving clock generation module 120 of this embodiment employs a multi-level delay chain structure for its duty cycle configuration unit, enabling flexible configuration of different duty cycles for the unmodulated and modulated stages to meet the protocol's requirements for modulation depth. The synchronization unit, through a two-level synchronization mechanism, strictly aligns the switching edge configured in the register with the modulation data transition edge, completely eliminating clock glitches and phase jitter caused by asynchronous duty cycle switching and modulation state switching. Through the collaborative work of the duty cycle configuration unit and the synchronization unit, the driving clock generation module 120 achieves precise synchronous switching of the driving clock duty cycle and modulation state, avoiding timing disturbances at the switching moment from the clock source. This provides a clean and stable clock foundation for subsequent dead-time insertion, power transistor shutdown, and antenna 101 clamping mechanisms, ensuring a smooth transition of the antenna 101 field envelope during modulation switching and effectively suppressing overshoot and undershoot phenomena.

[0064] Using the transmitter circuit 100 provided in this embodiment, when switching between the unmodulated stage and the modulation stage, the control drive clock generation module 120 inserts a dead zone interval within at least one carrier cycle. The dead zone interval is positioned within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated stage and the modulation stage. Furthermore, within the dead zone interval, the dead zone logic control module 130 completely shuts down the power transistor array 110, causing the antenna 101 connection of the transmitter circuit 100 to be in a high-impedance state. Thus, at the same moment the modulation switching occurs, the drive timing is pre-intervened—the energy mutation path is blocked in advance through the dead zone interval, and the antenna 101 connection enters a high-impedance state, avoiding the generation of overshoot or undershoot phenomena instead of post-event compensation. Simultaneously, since there is no need to wait for envelope detection and feedback loop response, active control synchronized with the switching moment is achieved, completely eliminating the cancellation hysteresis effect caused by the inherent delay of the feedback loop, thereby enabling a smooth transition of the antenna 101 field envelope from the unmodulated stage to the modulation stage or in the reverse direction.

[0065] In some embodiments, combined with Figure 2 As shown, the transmitter circuit 100 for the NFC device further includes: a clamping circuit 140, the output of which is electrically connected to the antenna 101 connection terminal; and a dead-zone logic control module 130 configured to enable the clamping circuit 140 within the dead-zone interval to clamp the potential of the antenna 101 connection terminal to a preset intermediate potential.

[0066] Optionally, the clamping circuit 140 includes a linear regulator and a first high-voltage switch. The output terminal of the linear regulator is electrically connected to the connection terminal of the antenna 101 through the first high-voltage switch. The dead-time logic control module 130 is configured to control the first high-voltage switch to conduct within the dead-time interval, clamping the connection terminal of the antenna 101 to the output voltage of the linear regulator.

[0067] Optionally, the first high-voltage switch includes a first branch switch and a second branch switch. The first branch switch is connected in series between the first connection terminal of the antenna 101 connection terminal and the output terminal of the linear regulator, and the second branch switch is connected in series between the second connection terminal of the antenna 101 connection terminal and the output terminal of the linear regulator. The clamping circuit 140 also includes a second high-voltage switch, which is connected in series between the first connection terminal and the second connection terminal of the antenna 101 connection terminal.

[0068] Combination Figure 3As shown, within the dead time interval, the PMOS power transistor is forcibly turned off by the driving clock, and the NMOS power transistor is completely turned off by configuring the third register group DN_3<18:0> to all zeros. At this time, the transmitter antenna 101 connection terminals (TX1, TX2) are in a high-impedance state. In this state, the clamping circuit 140 is enabled, clamping the antenna 101 connection terminals to the output terminal of the linear regulator through the high-voltage NMOS switch.

[0069] The clamping circuit 140 specifically includes: a linear regulator (HV_LDO), a first branch high-voltage NMOS switch, a second branch high-voltage NMOS switch, and a second high-voltage NMOS switch. The output of the linear regulator is electrically connected to the first connection terminal (TX1) of the antenna 101 connection terminal via the first branch high-voltage NMOS switch, and electrically connected to the second connection terminal (TX2) of the antenna 101 connection terminal via the second branch high-voltage NMOS switch. The second high-voltage NMOS switch is connected in series between TX1 and TX2, and is used to short-circuit the differential antenna 101 terminal during clamping to further stabilize the common-mode potential.

[0070] Combination Figure 19 , Figure 20 As shown, the dead-zone logic control module 130 outputs a low-voltage control signal within the dead-zone interval. This signal is then converted by the level conversion circuit 150 (e.g., Figure 15 The signal (shown) is converted into a high-voltage control signal LOGIC_CTRL_H. The level conversion circuit 150 adopts a pump capacitor assisted structure, and its power supply voltage VDDH is provided by a boost converter (DCDC) to ensure that the voltage value of the high-voltage control signal is greater than the sum of the power supply voltage VDDPA of the power transistor array 110 and the threshold voltage of the high-voltage NMOS switch, thereby ensuring that the high-voltage NMOS switch can be fully turned on during the dead time.

[0071] When LOGIC_CTRL_H is high, the first branch high-voltage NMOS switch and the second branch high-voltage NMOS switch are turned on simultaneously, transmitting the output voltage of the linear regulator to TX1 and TX2 respectively; at the same time, the second high-voltage NMOS switch is turned on, shorting TX1 and TX2, so that the potential at the differential antenna 101 terminal tends to be consistent.

[0072] like Figure 16 As shown, the linear regulator employs a two-stage amplifier structure, including a first-stage amplifier, a second-stage amplifier, a reference voltage generation circuit, and a feedback network. The first-stage amplifier consists of P2, P3, N3, N4, N5, N6, and N7, forming a differential input stage. P2 and P3 form a differential pair, N3 and N4 form an active load, and N5, N6, and N7 form a tail current source. The second-stage amplifier consists of P4, R4, and R5, forming a common-source amplifier structure. P4 acts as the amplifying transistor, R4 is its load resistor, and R4 and R5 form a feedback voltage divider network.

[0073] The negative input of the first-stage amplifier is electrically connected to the reference voltage VREF, and the positive input is electrically connected to the feedback voltage VFB, amplifying the difference between the reference voltage and the feedback voltage. The second-stage amplifier further amplifies the error signal output from the first-stage amplifier, generating the output voltage VOUT. The reference voltage VREF is generated by a zero-temperature coefficient current source. The zero-temperature coefficient current is mirrored by a current mirror formed by P5, P6, P7, and P8, and then flows through resistor R3, generating a reference voltage VREF with zero temperature coefficient across R3. The output voltage VOUT is divided by resistors R4 and R5 to generate the feedback voltage VFB, which is fed back to the positive input of the first-stage amplifier, forming a closed-loop negative feedback control.

[0074] During the dead zone of the modulation phase, the linear regulator is enabled. Its operating principle is as follows: The first-stage amplifier amplifies the difference between the reference voltage VREF and the feedback voltage VFB. The second-stage amplifier further amplifies this difference to output VOUT. The output voltage VOUT is divided by resistors R4 and R5 to form VFB, which is fed back to the first-stage amplifier. When VOUT rises, VFB rises accordingly, causing VOUT to fall through the negative feedback loop; when VOUT falls, VFB falls, causing VOUT to rise through the negative feedback loop. Through this closed-loop negative feedback mechanism, the output voltage VOUT is stabilized at the set value. The set value of the output voltage VOUT is determined by the ratio of the reference voltage VREF to the voltage divider resistors R4 and R5, satisfying: VOUT = VREF × (1 + R4 / R5). Since VREF has a zero temperature coefficient and R4 and R5 use the same type of resistor, the output voltage VOUT has good temperature stability.

[0075] During the dead time interval, the output of the linear regulator is electrically connected to the antenna 101 terminals TX1 and TX2 via a high-voltage NMOS switch, clamping TX1 and TX2 to a stable output voltage VOUT. The clamping waveforms of TX1 and TX2 during the dead time are as follows: Figure 21 As shown, the potential at the antenna 101 terminal is stabilized at a preset intermediate potential, providing a definite starting condition for the power transistor to resume driving after the dead zone ends.

[0076] The output DC value of the linear regulator can be configured independently, such as... Figure 16 As shown, different clamping voltages can be set by adjusting the ratio of voltage divider resistors R4 and R5. In the default implementation, the clamping voltage is set to half of the power supply voltage VDDPA of the power transistor array 110 (i.e., VDDPA / 2). This intermediate potential can minimize the voltage change amplitude at the antenna 101 before and after the dead zone, achieving a smooth transition of the envelope waveform.

[0077] Through the above mechanism, within the dead zone, the power transistor array 110 is completely turned off, causing the antenna 101 terminal to be in a high-impedance state. The clamping circuit 140 actively fixes the antenna 101 terminal to the intermediate potential. The two work together to achieve dual control of "energy cut-off" and "state fixation", providing a definite starting condition for the power transistor to resume driving after the dead zone ends.

[0078] The clamping circuit 140 actively clamps the antenna 101 connection to a configurable intermediate potential during the high-impedance dead zone, completely eliminating the floating potential problem at the antenna 101 terminal caused by the power transistor being fully off, and avoiding additional voltage jumps introduced by the uncertainty of the initial potential after the dead zone ends. Specifically, the first branch switch and the second branch switch are symmetrically set to achieve balanced clamping of the differential antenna 101 terminal; the introduction of the second high-voltage switch further stabilizes the differential common-mode potential and enhances the reliability of the clamping. The configurable characteristic of the linear regulator output voltage allows the clamping potential to be flexibly adjusted according to the load characteristics of the antenna 101 and the modulation depth requirements. When the default setting is VDDPA / 2, the voltage change amplitude before and after the dead zone can be minimized to achieve a smooth transition of the antenna 101 field envelope from "energy output" to "potential fixation" and then to "energy recovery". This clamping mechanism works in conjunction with the power transistor being fully off to fundamentally suppress overshoot and undershoot phenomena at the moment of modulation switching.

[0079] In some embodiments, combined with Figure 2 As shown, the transmitter circuit 100 for the NFC device further includes a level conversion circuit 150 configured to convert the low-voltage control signal output by the dead-zone logic control module 130 into a high-voltage control signal to drive the first high-voltage switch; wherein the voltage value of the high-voltage control signal is greater than the sum of the power supply voltage of the power transistor array 110 and the threshold voltage of the first high-voltage switch.

[0080] Optionally, the level conversion circuit 150 includes: a cross-coupled first PMOS transistor and a second PMOS transistor, the source of the first PMOS transistor and the source of the second PMOS transistor being connected to a high-voltage power supply terminal, the drain of the first PMOS transistor being electrically connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor being electrically connected to the gate of the first PMOS transistor; a first pump capacitor, the first plate of the first pump capacitor being electrically connected to the drain of the first PMOS transistor, and the second plate of the first pump capacitor being electrically connected to a first input node; a second pump capacitor, the first plate of the second pump capacitor being electrically connected to the drain of the second PMOS transistor, and the second plate of the second pump capacitor being electrically connected to a second input node; and an initial state enable control terminal, configured to precharge the first pump capacitor and the second pump capacitor to an initial state when the level conversion circuit 150 is not enabled.

[0081] To ensure reliable conduction of the high-voltage NMOS switch within the dead zone, the low-voltage control signal LOGIC_CTRL (VHV domain) output by the dead-zone logic control module 130 needs to be converted into a high-voltage control signal LOGIC_CTRL_H (VDDH domain). Since the source of the high-voltage NMOS switch is connected to the antenna 101 terminal (potential up to VDDPA), its gate drive voltage must be at least greater than the sum of VDDPA and the NMOS threshold voltage VTH to ensure full conduction of the switch. Therefore, the level conversion circuit 150 employs a pump capacitor-assisted switching structure, utilizing the high-voltage power supply VDDH (VDDH > VDDPA + VTH) provided by the boost converter to achieve level conversion from the low-voltage signal to the high-voltage domain.

[0082] Combination Figure 15 As shown, the first PMOS transistor P1 and the second PMOS transistor P2 form a cross-coupled structure. The sources of P1 and P2 are connected to the high-voltage power supply terminal VDDH. The drain of P1 is electrically connected to the gate of P2, and the drain of P2 is electrically connected to the gate of P1. This cross-coupled PMOS transistor pair structure is used to form positive feedback and accelerate level switching. The positive plate of the first pump capacitor C0 is electrically connected to the drain of P2, and the negative plate is electrically connected to the first input node A. The positive plate of the second pump capacitor C1 is electrically connected to the drain of P3, and the negative plate is electrically connected to the second input node B. C0 and C1 are used to assist in raising the node potential during signal switching, thereby achieving voltage boosting. The second stage of the level conversion circuit 150 consists of an inverter forming a level shaping circuit. The gate of the P5 transistor of the inverter is connected to the upper plate of C1, and the drain is connected to the output terminal LOGIC_CTRL_H. The gate of the N1 transistor of the inverter is connected to node B, and the drain is connected to the output terminal LOGIC_CTRL_H. This stage is used to shape the waveform of the converted signal and provide a stable high voltage output. The initial state enable control terminal EN is used to precharge the pump capacitor to its initial state when the level conversion circuit 150 is not enabled, preventing erroneous level flipping during power-on or non-operating states. Specifically: when EN=0 (disabled), the upper plate of C0 is clamped to a high level in the VDDH domain through the switch P1, and the lower plate is clamped to a high level in the VHV domain through the NAND gate NAND1; the upper plate of C1 is clamped to a high level in the VDDH domain through the switch P4, and the lower plate is clamped to a high level in the VHV domain through the NAND gate NAND2; at the same time, the gate of the second-stage N1 transistor is clamped to a high level in the VHV domain, and the output terminal LOGIC_CTRL_H is fixed at a low level; when EN=1 (enabled), the initial state is released, and the level conversion circuit 150 enters the normal operating state.

[0083] Continue to combine Figure 15As shown, the operation of the level shifting circuit 150 is as follows: When the input signal LOGIC_CTRL is low in the VHV domain, point A is low and point B is high. At this time, the cross-coupled PMOS transistors and the pump capacitor work together to make the output terminal LOGIC_CTRL_H low in the VDDH domain. When the input signal LOGIC_CTRL is high in the VHV domain, point A is high and point B is low. The pump capacitors C0 and C1 assist in raising the node potential through the charge pump effect. The cross-coupled PMOS transistors form positive feedback, causing the output terminal LOGIC_CTRL_H to quickly flip to the high level of the VDDH domain. After EN is enabled, the circuit can correctly respond to changes in the input signal and output a high-voltage control signal that is in phase with the input logic.

[0084] Through the above mechanism, the level conversion circuit 150 reliably converts the LOGIC_CTRL signal in the low voltage domain (VHV) into the LOGIC_CTRL_H signal in the high voltage domain (VDDH), and the output high voltage level VDDH satisfies the condition VDDH>VDDPA + VTH, ensuring that the high voltage NMOS switch can be fully turned on.

[0085] The level shifting circuit 150 achieves reliable level shifting from the low-voltage domain (VHV) to the high-voltage domain (VDDH) through a cross-coupled PMOS transistor pair and a pump capacitor-assisted switching structure. The output high-voltage control signal LOGIC_CTRL_H has a voltage value greater than the sum of the power supply voltage VDDPA of the power transistor array 110 and the threshold voltage of the high-voltage NMOS switch, ensuring full conduction of the high-voltage NMOS switch during the dead time period. This allows the output voltage of the linear regulator to be fully transmitted to the antenna 101 connection terminal. Simultaneously, the circuit introduces an initial-state enable control terminal EN, which pre-charges the pump capacitor to its initial state when disabled, effectively preventing false level switching due to floating during power-on or non-operating states, thus improving the system's power-on safety and operational robustness. This level shifting circuit 150 has a simple structure, rapid response, and can withstand high voltage without the use of thick gate oxide devices, reducing chip manufacturing costs and providing a crucial guarantee for reliable antenna 101 clamping during the dead time period.

[0086] In this embodiment, the power transistor array 110 is composed of a PMOS power transistor array (upper transistor) and an NMOS power transistor array (lower transistor), which are electrically connected to the first connection terminal (TX1) and the second connection terminal (TX2) of the antenna connection terminal, respectively. The power transistor array (P1-P18, N1-N18) on the TX1 side is connected to the TX1 terminal, and the power transistor array (P19-P36, N19-N36) on the TX2 side is connected to the TX2 terminal, forming a full-bridge or half-bridge driving structure to jointly drive the antenna 101. The output terminal of the driving clock generation module 120 is electrically connected to the driving input terminal of the power transistor array 110. Specifically, it is connected to the TX1 side power transistor driving circuit (…) via the CLK_TX1 signal line. Figure 12 , Figure 13 The dead-time logic control module 130 is electrically connected to the power transistor drive circuit on the TX2 side via the CLK_TX2 signal line to provide the drive clock signal. The input terminals of the dead-time logic control module 130 are electrically connected to the modulation data signal line (TXD) and the clock output terminal of the drive clock generation module 120, respectively, to obtain the modulation state and clock state; the output terminal is electrically connected to the control input terminal of the drive clock generation module 130, and simultaneously outputs a low-voltage control signal LOGIC_CTRL to the level conversion circuit 150. The input terminal of the level conversion circuit 150 is electrically connected to the output terminal of the dead-time logic control module 130, receiving the low-voltage control signal LOGIC_CTRL (VHV domain); the output terminal is electrically connected to the gate of the high-voltage NMOS switch in the clamping circuit 140, outputting a high-voltage control signal LOGIC_CTRL_H (VDDH domain); and the power supply terminal is electrically connected to the output terminal of the boost converter (DCDC), receiving the high-voltage power supply VDDH. The clamping circuit 140 consists of a linear regulator (HV_LDO) and a high-voltage NMOS switch. The output of the linear regulator is electrically connected to TX1 through the first branch high-voltage NMOS switch and to TX2 through the second branch high-voltage NMOS switch. The second high-voltage NMOS switch is connected in series between TX1 and TX2. The gate of each high-voltage NMOS switch is electrically connected to the output of the level conversion circuit 150 to receive the high-voltage control signal LOGIC_CTRL_H. The antenna connection terminal of the antenna 101 is electrically connected to the output of the power transistor array 110 and is also electrically connected to the clamping circuit 140 through a high-voltage NMOS switch.

[0087] The transmitter circuit provided in this disclosure achieves a smooth transition of the antenna field envelope during modulation switching through the coordinated action of multiple mechanisms, including dead-zone position optimization, complete power transistor array shutdown, active antenna clamping, and synchronous switching of drive clock duty cycle. Figure 22As shown, the antenna field envelope waveform (A) before optimization exhibits significant undershoot when switching from the unmodulated stage to the modulation stage, and significant overshoot when switching from the modulation stage to the unmodulated stage. However, after adopting the transmitter circuit provided in this embodiment, the undershoot and overshoot phenomena in the optimized antenna field envelope waveform (B) are effectively suppressed, and the envelope waveform is smooth and the transition is clean. It can be seen that this embodiment fundamentally solves the adjustment lag problem caused by the feedback loop delay, transforming the traditional passive response control of "detect first and then cancel" into an active preventive control of "synchronization with switching", completely eliminating the overshoot and undershoot of the antenna field envelope during modulation switching. This enables the transmitter to meet the stringent requirements of international protocols such as EMV for the rise time, fall time, and overshoot and undershoot depth of the envelope waveform, significantly improving the communication reliability and protocol compatibility of NFC devices.

[0088] In some embodiments, the control method based on the transmitter circuit includes: when switching between the unmodulated phase and the modulation phase, inserting a dead zone interval within at least one carrier cycle; wherein the dead zone interval is set at a position within the carrier cycle to avoid the dead zone interval being located at the direct switching boundary between the unmodulated phase and the modulation phase, and within the dead zone interval, the dead zone logic control module controls the power transistor array to be completely turned off so that the antenna connection terminal of the transmitter circuit is in a high-impedance state.

[0089] Optionally, switching between the unmodulated phase and the modulation phase includes switching from the unmodulated phase to the modulation phase, and switching from the modulation phase to the unmodulated phase. In the case of switching from the unmodulated phase to the modulation phase, a dead-time interval is inserted within at least one carrier cycle, including: generating four consecutive clock drive phases, wherein the first phase drives the power transistors while maintaining the clock phase of the unmodulated phase; the second phase drives the power transistors while maintaining a clock phase continuous with the first phase; the third phase is a dead-time interval in which the power transistor array is completely turned off; and the fourth phase drives the power transistors with a clock phase opposite to that of the unmodulated phase.

[0090] Optionally, controlling the power transistor array to be completely turned off includes: converting the low-voltage control signal output by the dead-time logic control module into a high-voltage control signal; wherein the voltage value of the high-voltage control signal is greater than the sum of the power supply voltage of the power transistor array and the threshold voltage of the first high-voltage switch; and using the high-voltage control signal to drive the first high-voltage switch to establish a clamping path within the dead-time interval.

[0091] In some possible implementations, controlling the power transistor array to be completely turned off also includes: selecting a first register group, a second register group, or a third register group according to the current operating state to control the number of NMOS power transistors turned on; wherein, during the dead time interval, the third register group is selected and configured to all 0s to completely turn off the NMOS power transistors.

[0092] Optionally, the control method based on the transmitter circuit further includes: enabling the clamping circuit within the dead zone to clamp the potential of the antenna connection terminal to a preset intermediate potential.

[0093] In some possible implementations, clamping the potential at the antenna connection terminal to a preset intermediate potential includes: controlling the first high-voltage switch to turn on, so that the output voltage of the linear regulator is transmitted to the antenna connection terminal.

[0094] In some possible implementations, controlling the first high-voltage switch to turn on includes: controlling the first branch switch to turn on, transmitting the output voltage of the linear regulator to the first connection terminal of the antenna connection terminal; and controlling the second branch switch to turn on, transmitting the output voltage of the linear regulator to the second connection terminal of the antenna connection terminal.

[0095] In some possible implementations, clamping the potential of the antenna connection terminal to a preset intermediate potential also includes: controlling the second high-voltage switch to turn on, short-circuiting the first connection terminal and the second connection terminal.

[0096] Optionally, the control method based on the transmitter circuit further includes: configuring the drive clock duty cycle for the unmodulated stage and the modulated stage respectively; synchronizing the switching edge of the drive clock duty cycle with the modulated data so that the switching of the duty cycle is strictly aligned with the switching of the modulation state.

[0097] In some embodiments, combined with Figure 23 As shown, a control method based on a transmitter circuit is provided, including the following steps: S2301 configures the duty cycle of the drive clock for the unmodulated stage and the modulation stage respectively, and synchronizes the switching edge of the drive clock duty cycle with the modulation data so that the switching of the duty cycle is strictly aligned with the switching of the modulation state.

[0098] S2302, when switching between the unmodulated phase and the modulated phase, insert a dead zone interval within at least one carrier cycle.

[0099] S2303 enables the clamping circuit within the dead zone to clamp the potential at the antenna connection terminal to a preset intermediate potential.

[0100] The control method based on the transmitter circuit provided in this disclosure eliminates clock glitches caused by the asynchrony between duty cycle switching and modulation state switching by strictly synchronizing the switching edge of the driving clock duty cycle with the modulation data, fundamentally avoiding timing disturbances at the moment of switching. Based on this, a position-optimized dead-time interval is actively inserted at the modulation switching moment, constructing a buffer transition band of "phase continuity—energy cutoff—phase recovery" in timing. During the dead time, a clamping circuit fixes the antenna terminal potential to an intermediate potential, ensuring that the antenna terminal has a definite initial state at the end of the dead time. This achieves a fundamental shift from hysteresis feedback regulation of "detection before cancellation" to active preventative control of "synchronization with switching," completely eliminating the regulation hysteresis effect caused by the inherent delay of the feedback loop. This ensures a smooth transition of the antenna field envelope during modulation switching, effectively meeting the stringent requirements of protocols such as EMV for envelope rise time, fall time, and overshoot / undershoot depth.

[0101] Combination Figure 24 As shown, this embodiment of the disclosure provides a control device 240 based on a transmitter circuit, including a processor 2400 and a memory 2401, and may also include a communication interface 2402 and a bus 2403. The processor 2400, communication interface 2402, and memory 2401 can communicate with each other via the bus 2403. The communication interface 2402 can be used for information transmission. The processor 2400 can call logical instructions in the memory 2401 to execute the control method based on the transmitter circuit described in the above embodiment.

[0102] Furthermore, the logic instructions in the aforementioned memory 2401 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0103] The memory 2401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 2400 executes functional applications and data processing by running the program instructions / modules stored in the memory 2401, that is, it implements the control method based on the transmitter circuit in the above method embodiments.

[0104] The memory 2401 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 2401 may include high-speed random access memory and may also include non-volatile memory.

[0105] Processor 2400 is a circuit with signal processing capabilities. In one implementation, processor 2400 can be a circuit with instruction read and execute capabilities, such as a central processing unit (CPU), microprocessor, graphics processing unit (GPU) (which can be understood as a type of microprocessor), or digital signal processor (DSP). In another implementation, processor 2400 can achieve certain functions through the logical relationships of hardware circuits. These logical relationships of hardware circuits are fixed or reconfigurable. For example, processor 2400 can be a hardware circuit implemented as an ASIC or a programmable logic device (PLD), such as an FPGA. In reconfigurable hardware circuits, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the processor loading instructions to achieve the functions of some or all of the above modules. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as a neural network processing unit (NPU), tensor processing unit (TPU), or deep learning processing unit (DPU). The processor 2400 is used to execute related programs to implement the functions required by the units in the transmitter circuit-based control device of the present application embodiments, or to execute the transmitter circuit-based control method of the present application method embodiments.

[0106] As can be seen, each module in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor types.

[0107] Furthermore, the modules in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these modules are integrated together as a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or for implementing the functions of the modules of the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0108] In some embodiments, combined with Figure 25 As shown, the NFC device 250 includes: an NFC device body 2500; and a transmitter circuit 100 for an NFC device as described above, which is mounted on the NFC device body 2500.

[0109] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the aforementioned control method based on transmitter circuitry.

[0110] This disclosure provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer, cause the computer to perform the aforementioned control method based on the transmitter circuit.

[0111] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0112] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0113] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. The scope of the embodiments of this disclosure includes the entire scope of the claims and all available equivalents of the claims. While the terms “first,” “second,” etc., may be used in this application to describe elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be called a second element without changing the meaning of the description, and similarly, a second element may be called a first element, provided that all occurrences of “first element” are consistently renamed and all occurrences of “second element” are consistently renamed. First and second elements are both elements, but may not be the same element. Moreover, the terminology used in this application is only for describing embodiments and is not intended to limit the claims. As used in the description of the embodiments and claims, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. Similarly, the term “and / or” as used herein means including one or more of the associated listed any and all possible combinations. Additionally, when used herein, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase “comprising an…” does not exclude the presence of additional identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0114] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0115] The methods and products disclosed in the embodiments herein (including but not limited to devices and equipment) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A transmitter circuit for an NFC device, characterized by include: A power transistor array is configured to drive the antenna; The drive clock generation module is electrically connected to the power transistor array and is configured to generate a clock signal to drive the power transistor array. The dead-time logic control module, which is electrically connected to the drive clock generation module, is configured to control the drive clock generation module to insert a dead-time interval within at least one carrier cycle when switching between the unmodulated phase and the modulated phase. The dead zone is set within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated and modulated phases. Within the dead zone, the dead zone logic control module completely shuts down the power transistor array to keep the antenna connection of the transmitter circuit in a high-impedance state.

2. The transmitter circuit of claim 1, wherein, Also includes: The clamping circuit's output terminal is electrically connected to the antenna connection terminal. The dead-zone logic control module is configured to enable the clamping circuit within the dead-zone interval, clamping the potential of the antenna connection terminal to a preset intermediate potential.

3. The transmitter circuit according to claim 2, characterized in that, The clamping circuit includes a linear regulator and a first high-voltage switch. The output terminal of the linear regulator is electrically connected to the antenna connection terminal through the first high-voltage switch. The dead-zone logic control module is configured to control the first high-voltage switch to turn on within the dead-zone interval, clamping the antenna connection terminal to the output voltage of the linear regulator.

4. The transmitter circuit according to claim 3, characterized in that, The first high-voltage switch includes a first branch switch and a second branch switch. The first branch switch is connected in series between the first connection terminal of the antenna connection terminal and the output terminal of the linear regulator, and the second branch switch is connected in series between the second connection terminal of the antenna connection terminal and the output terminal of the linear regulator. The clamping circuit also includes a second high-voltage switch, which is connected in series between the first and second connection terminals of the antenna connection.

5. The transmitter circuit of claim 3, wherein, Also includes: The level conversion circuit is configured to convert the low-voltage control signal output by the dead-time logic control module into a high-voltage control signal to drive the first high-voltage switch; The voltage value of the high-voltage control signal is greater than the sum of the power supply voltage of the power transistor array and the threshold voltage of the first high-voltage switch.

6. The transmitter circuit of claim 5, wherein, The level conversion circuit includes: A first PMOS transistor and a second PMOS transistor are cross-coupled. The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the high-voltage power supply terminal. The drain of the first PMOS transistor is electrically connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is electrically connected to the gate of the first PMOS transistor. The first pump capacitor has its first plate electrically connected to the drain of the first PMOS transistor, and its second plate electrically connected to the first input node. The second pump capacitor has its first plate electrically connected to the drain of the second PMOS transistor and its second plate electrically connected to the second input node. The initial state enable control terminal is configured to precharge the first pump capacitor and the second pump capacitor to the initial state when the level conversion circuit is not enabled.

7. The transmitter circuit according to any one of claims 1 to 6, characterized in that, The power transistor array includes multiple groups of NMOS power transistors, and each group of NMOS power transistors includes multiple parallel power transistor units with different weights; The transmitter circuit also includes: The first register group is used to configure the pull-down strength of the NMOS power transistor in the unmodulated state; The second register group is used to configure the pull-down strength of the NMOS power transistor in the non-dead zone during modulation. The third register group is used to configure the pull-down strength of the NMOS power transistor within the dead zone. The dead-time logic control module is configured to select the first register group, the second register group, or the third register group according to the current operating state to control the number of NMOS power transistors that are turned on.

8. The transmitter circuit according to any one of claims 1 to 6, characterized in that The drive clock generation module includes: The duty cycle configuration unit is configured to configure the drive clock duty cycle for the unmodulated phase and the modulated phase, respectively. The synchronization unit, electrically connected to the duty cycle configuration unit, is configured to synchronize the switching edge of the duty cycle configuration unit with the modulation data so that the switching of the duty cycle is strictly aligned with the switching of the modulation state.

9. A control method based on the transmitter circuit according to any one of claims 1 to 8, characterized in that, include: When switching between the unmodulated phase and the modulated phase, a dead zone interval is inserted within at least one carrier cycle; The dead zone is set within the carrier cycle to avoid it being located at the direct switching boundary between the unmodulated and modulated phases. Within the dead zone, the dead zone logic control module completely shuts down the power transistor array to keep the antenna connection of the transmitter circuit in a high-impedance state.

10. An NFC device, characterized in that, include: NFC device body; The transmitter circuit for an NFC device as described in any one of claims 1 to 8 is installed on the main body of the NFC device.

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