A communication method and a communication device

Abstract

The embodiment of the present application provides a communication method and a communication device, the method comprises the following steps: a first communication device acquires a first bit sequence and a second bit sequence, the length of the first bit sequence and the length of the second bit sequence are both a first length; then the first bit sequence and the second bit sequence are subjected to XOR processing to obtain a third bit sequence; then a fourth bit sequence is determined based on a first cyclic shift length, the second bit sequence and the third bit sequence, the fourth bit sequence comprises the second bit sequence and the third bit sequence, and the first cyclic shift length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence; the first communication device outputs an encoded sequence to a second communication device, and the encoded sequence comprises the fourth bit sequence. The method can improve the error correction performance of channel coding with lower complexity, so that the decoding performance can be improved.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a communication method and a communication device. Background Technology

[0002] Channel coding, as a fundamental wireless access technology, employs various methods, such as polar codes and low-density parity-check (LDPC) codes. Polar codes, selected as the control channel coding scheme in the 5th generation (5G) standard, are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, offering advantages such as good decoding performance and low complexity. LDPC codes, selected as the data channel coding scheme in the 5G standard, are linear block codes with a sparse parity-check matrix. They not only possess good performance approaching the Shannon limit but also exhibit low decoding complexity and flexible structure.

[0003] To improve the error correction performance of channels, some channel coding schemes propose the use of interleaving. Interleaving methods include row-column interleaving in Starlight communication, triangular interleaving in New Radio (NR), and interleaving in hierarchical polar codes, among others. However, current interleaving methods are highly complex to implement, leading to a series of problems such as high resource consumption and long processing times.

[0004] Designing a low-complexity interleaving method to improve the error correction performance of channel coding is one of the problems that needs to be solved. Summary of the Invention

[0005] This application provides a communication method and a communication device that can improve the error correction performance of channel coding with a low-complexity interleaving method.

[0006] In a first aspect, embodiments of this application provide a communication method, the method comprising: a first communication device acquiring a first bit sequence and a second bit sequence, wherein the length of the first bit sequence and the length of the second bit sequence are both a first length; performing an XOR operation on the first bit sequence and the second bit sequence to obtain a third bit sequence; determining a fourth bit sequence based on a first cyclic displacement length, the second bit sequence, and the third bit sequence, wherein the fourth bit sequence includes the second bit sequence and the third bit sequence, and the first cyclic displacement length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence; and the first communication device outputting an encoded sequence to a second communication device, wherein the encoded sequence includes the fourth bit sequence.

[0007] The first communication device and the second communication device mentioned above are different communication devices. The first communication device (or the second communication device) may be a communication device (such as a network device or a terminal device), or a component in the communication device (such as a processor, a chip, or a chip system), or a logic module or software that can realize all or part of the functions of the communication device.

[0008] For example, the first communication device is a network device, and the second communication device is a terminal device. Alternatively, the first communication device is a terminal device, and the second communication device is a network device. Alternatively, the first communication device is a terminal device, and the second communication device is another terminal device. Alternatively, the first communication device is a network device, and the second communication device is another network device.

[0009] In the above method, the first communication device performs an XOR operation (i.e., an encoding process) on the first and second bit sequences to obtain the third bit sequence. Then, based on the first cyclic shift length, the second bit sequence, and the third bit sequence, it performs a cyclic shift operation to determine the fourth bit sequence. The fourth bit sequence includes the second and third bit sequences. The first cyclic shift length is used to determine the position information of the second and / or third bit sequences within the fourth bit sequence. The first communication device outputs the encoded sequence, which includes the fourth bit sequence, to the second communication device. In this method, the encoding end / transmitter performs cyclic shift operations on the bit sequences during the encoding process to achieve interleaving, which improves the error correction performance of the channel coding, thereby improving the decoding performance of the decoding end / receiving end. Furthermore, the processing complexity is relatively low.

[0010] In one possible implementation, the first communication device acquires a first bit sequence by: acquiring a first sub-bit sequence and a second sub-bit sequence, both having a length of a second length, which is less than a first length; performing an XOR operation on the first and second sub-bit sequences to obtain a third sub-bit sequence; and then determining the first bit sequence based on a second cyclic shift length, the second sub-bit sequence, and the third sub-bit sequence, wherein the first bit sequence includes the second and third sub-bit sequences, and the second cyclic shift length is used to determine the position information of the second and / or third sub-bit sequences within the first bit sequence. Through this implementation, the first communication device can obtain the first bit sequence by performing XOR and cyclic shift operations based on a smaller-length sub-bit sequence.

[0011] In one possible implementation, the second loop displacement length is the same as the first loop displacement length. Since the loop displacement processing at each level can be regarded as a processing step in the encoding process, this implementation allows the same loop displacement length to be used in the loop displacement processing at different levels. This not only reduces the complexity of the encoding process but also reduces the complexity of the decoding process.

[0012] In one possible implementation, the first and second sub-bit sequences do not include shortened or punctured bits. This implementation avoids the cyclic shifting of shortened or punctured bits during rate matching, thus facilitating subsequent rate matching.

[0013] In one possible implementation, the first communication device determines a fourth bit sequence based on a first cyclic displacement length, a second bit sequence, and a third bit sequence, including: performing cyclic displacement processing on the second bit sequence and the third bit sequence respectively based on the first cyclic displacement length to obtain the fourth bit sequence. This implementation can effectively complete the cyclic displacement of each bit sequence.

[0014] In another possible implementation, the first communication device determines the fourth bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence. This includes: during the XOR operation of the first and second bit sequences, performing a cyclic shift operation on the second sub-bit sequence based on the first cyclic shift length to obtain the fourth bit sequence. This implementation allows the cyclic shift operation to be performed synchronously during the XOR operation, thereby reducing the latency of the encoding process (which includes both XOR and cyclic shift operations).

[0015] In one possible implementation, the first and second bit sequences do not include shortened or punctured bits. This implementation ensures that shortened or punctured bits are not involved in the cyclic shifting process during rate matching, thus facilitating subsequent rate matching.

[0016] Secondly, embodiments of this application provide a communication method, the method comprising: a second communication device obtaining a sequence to be decoded, the sequence to be decoded including a fourth bit sequence, the fourth bit sequence being determined based on a first cyclic shift length, a second bit sequence, and a third bit sequence, the first cyclic shift length being used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence, the fourth bit sequence including the second bit sequence and the third bit sequence, the third bit sequence being obtained by XORing the first bit sequence and the second bit sequence, the lengths of the first bit sequence and the second bit sequence being both a first length; the second communication device obtaining a de-cyclic shifted second bit sequence and / or a de-cyclic shifted third bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence; and the second communication device performing a de-XORing process on the de-cyclic shifted third bit sequence to obtain a first bit sequence.

[0017] The first communication device and the second communication device mentioned above are different communication devices. The first communication device (or the second communication device) may be a communication device (such as a network device or a terminal device), or a component in the communication device (such as a processor, a chip, or a chip system), or a logic module or software that can realize all or part of the functions of the communication device.

[0018] For example, the first communication device is a network device, and the second communication device is a terminal device. Alternatively, the first communication device is a terminal device, and the second communication device is a network device. Alternatively, the first communication device is a terminal device, and the second communication device is another terminal device. Alternatively, the first communication device is a network device, and the second communication device is another network device.

[0019] In the above method, the second communication device obtains the sequence to be decoded, which includes a fourth bit sequence. This fourth bit sequence is determined by the first communication device based on a first cyclic shift length, a second bit sequence, and a third bit sequence. The fourth bit sequence includes both the second and third bit sequences, and the third bit sequence is obtained by the first communication device after XORing the first and second bit sequences. Thus, the second communication device obtains the de-cyclic-shifted second bit sequence and / or the de-cyclic-shifted third bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence. Then, it performs a de-XOR operation on the de-cyclic-shifted third bit sequence to obtain the first bit sequence. Therefore, in this method, the encoding end / transmitter performs cyclic shifting on the bit sequence during the encoding process to achieve interleaving, which improves the error correction performance of the channel coding, thereby improving the decoding performance of the decoding end / receiving end. Furthermore, the processing complexity is relatively low.

[0020] In one possible implementation, the second communication device obtains the second bit sequence and / or the third bit sequence after de-cyclic displacement based on the first cyclic displacement length, the second bit sequence, and the third bit sequence, including: the second communication device performs de-cyclic displacement processing on the second bit sequence and the third bit sequence in the fourth bit sequence based on the first cyclic displacement length to obtain the second bit sequence and the third bit sequence after de-cyclic displacement.

[0021] In another possible implementation, the second communication device obtains the second bit sequence after de-cyclic displacement and / or the third bit sequence after de-cyclic displacement based on the first cyclic displacement length, the second bit sequence, and the third bit sequence, including: in the de-XOR processing based on the third bit sequence after de-cyclic displacement, the second communication device performs de-cyclic displacement processing on the second bit sequence based on the first cyclic displacement length to obtain the second bit sequence after de-cyclic displacement processing.

[0022] In one possible implementation, the first bit sequence is determined based on a second cyclic shift length, a second sub-bit sequence, and a third sub-bit sequence. The second cyclic shift length is used to determine the position information of the second sub-bit sequence and / or the third sub-bit sequence within the first bit sequence. The first bit sequence includes the second and third sub-bit sequences. The third sub-bit sequence is obtained by XORing the first and second sub-bit sequences. The lengths of both the first and second sub-bit sequences are second lengths, and the second length is less than the first length. The method further includes: a second communication device obtaining a de-cyclic-shifted second sub-bit sequence and / or a de-cyclic-shifted third sub-bit sequence based on the second cyclic shift length, the second sub-bit sequence, and the third sub-bit sequence; and then performing a de-XOR operation on the de-cyclic-shifted third sub-bit sequence to obtain the first sub-bit sequence. Optionally, this implementation can be performed after the second communication device obtains the first bit sequence.

[0023] In one possible implementation, the length of the second cyclic displacement is the same as the length of the first cyclic displacement. This implementation can also reduce the complexity of the second communication device (i.e., the receiving end) in processing the cyclic displacement.

[0024] In one possible implementation, the first and second sub-bit sequences do not include shortened or punctured bits. This implementation facilitates rate matching at both the transmitting and receiving ends.

[0025] In one possible implementation, the first and second bit sequences do not include shortened or punctured bits. This implementation facilitates rate matching at both the transmitting and receiving ends.

[0026] Thirdly, embodiments of this application also provide a communication device that can be used to perform the method of the first aspect.

[0027] In one possible implementation, the communication device may include modules or units corresponding to the methods / operations / steps / actions described in the first aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software. In another possible implementation, the communication device may include a processing unit (also called a processing module) and a communication unit (also called a communication module). The communication unit may be used to perform receiving and / or sending functions, and the processing unit may be used to perform the methods described in the first aspect or any of the possible implementations of the first aspect.

[0028] Fourthly, embodiments of this application also provide a communication device that can be used to perform the method of the second aspect.

[0029] In one possible implementation, the communication device may include modules or units corresponding to the methods / operations / steps / actions described in the second aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software. In another possible implementation, the communication device may include a processing unit (also called a processing module) and a communication unit (also called a communication module). The communication unit may be used to perform receiving and / or sending functions, and the processing unit may be used to perform the methods described in the second aspect or any of the possible implementations of the second aspect.

[0030] Fifthly, embodiments of this application provide a communication device including a processor; the processor is configured to, through logic circuits and / or by executing a computer program, cause the communication device to perform the method provided by the first aspect or any possible implementation thereof, or to perform the method provided by the second aspect or any possible implementation thereof.

[0031] In one possible design, the communication device may further include an input / output interface and / or a memory, the memory for storing the computer program and the input / output interface for inputting and / or outputting information.

[0032] Alternatively, the processor and the memory can be integrated together, or the processor and the memory can be set separately.

[0033] In one possible design, the communication device described in the fifth aspect can be a chip.

[0034] Sixthly, embodiments of this application provide a communication system, which includes a first communication device and a second communication device. The first communication device is used to implement the method provided in the first aspect or any possible implementation thereof, and the second communication device is used to implement the method provided in the second aspect or any possible implementation thereof.

[0035] In a seventh aspect, embodiments of this application provide a computer storage medium storing a software program that, when read and executed by one or more processors, can implement the method provided by the first aspect or any of the possible implementations described above, or implement the method provided by the second aspect or any of the possible implementations described above.

[0036] Eighthly, embodiments of this application provide a computer program product containing instructions that, when run on a computer, cause the method provided by the first aspect or any of its possible implementations to be executed, or cause the method provided by the second aspect or any of its possible implementations to be executed.

[0037] Ninthly, embodiments of this application provide a chip system including a processor for supporting a first communication device in implementing the functions involved in the first aspect; or for supporting a second communication device in implementing the functions involved in the second aspect.

[0038] In one possible design, the chip system further includes a memory for storing necessary program instructions and data to be executed by the loading device. The chip system can be composed of chips or may include chips and other discrete components.

[0039] It should be noted that the technical effects that can be achieved by any of the third to ninth aspects or any of the third to ninth aspects can be referred to the description of the technical effects that can be achieved by any of the first and second aspects or any of the first and second aspects; they will not be repeated here. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the embodiments of this application;

[0041] Figure 2 A schematic diagram illustrating a processing flow between the information source and the information sink;

[0042] Figure 3A This is a schematic diagram of an 8×8 polarization transformation matrix;

[0043] Figure 3B This is a schematic diagram of the SC decoding calculation process;

[0044] Figure 3C This is a schematic diagram of the decoding path in the SCL decoding method;

[0045] Figure 4 This is a schematic diagram of interlacing in a polar layer;

[0046] Figure 5 A flowchart illustrating a communication method provided in an embodiment of this application;

[0047] Figure 6 A flowchart illustrating one embodiment of this application;

[0048] Figure 7 A schematic diagram of an encoding process provided for an embodiment of this application;

[0049] Figure 8 A flowchart illustrating another embodiment provided in this application;

[0050] Figure 9 A schematic diagram illustrating another encoding process provided for an embodiment of this application;

[0051] Figure 10 A flowchart illustrating yet another embodiment of this application;

[0052] Figure 11A A schematic diagram of a frozen bit that does not participate in the cyclic shift process provided in this application;

[0053] Figure 11B A schematic diagram of another type of frozen bit that does not participate in the cyclic shift process provided in this application;

[0054] Figure 12 A schematic diagram of a communication device provided in an embodiment of this application;

[0055] Figure 13 A schematic diagram of another communication device provided in the embodiments of this application;

[0056] Figure 14 This is a schematic diagram of a chip device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. This application will focus on various aspects, embodiments, or features of a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these solutions may also be used.

[0058] In the embodiments of this application, the terms "exemplary," "for example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0059] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, Wireless Fidelity (Wi-Fi), Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Worldwide Interoperability for Microwave Access (WiMAX) communication systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0060] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1 The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0061] (1) Network equipment

[0062] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0063] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0064] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) layers of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) and media access control (MAC) layers of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RA equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0065] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0066] (2) Terminal equipment

[0067] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be, for example, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, smart glasses, etc.), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), satellite terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability user equipment (REDCAP UE), wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, robotic arms, workshop equipment, wireless terminals in autonomous driving, wireless terminals in smart healthcare, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (such as smart robots, hot air balloons, drones, airplanes), etc. The terminal can also be a vehicle device, such as a complete vehicle device, an in-vehicle module, an in-vehicle chip, an on-board unit (OBU), or a telematics box (T-BOX). In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing the functions, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0068] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0069] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0070] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0071] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0072] The system architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0073] The relevant technologies and terms involved in the embodiments of this application will be explained below. Unless otherwise specified, these explanations are for the purpose of supporting the meaning of the relevant technologies and terms and making the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0074] I. Channel coding and channel decoding:

[0075] Figure 2 This is a schematic diagram illustrating a processing flow between the information source and the information sink. For example... Figure 2 As shown, at the transmitting end, the source first performs source coding to obtain the bit sequence to be encoded (i.e., the information bit sequence). Then, channel coding is performed on the bit sequence to obtain the encoded bit sequence. Next, rate matching is performed on the encoded bit sequence, followed by modulation mapping to obtain the modulation symbol sequence. The transmitting end then transmits the modulation symbol sequence. Correspondingly, at the receiving end, after receiving the modulation symbol sequence, demodulation mapping is performed first, followed by rate matching, then channel decoding (also known as channel decoding), and finally source decoding or source recovery to obtain the destination information.

[0076] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0077] There are various channel coding methods, such as polar codes and LDPC codes. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0078] II. Polar code encoding and polar code decoding:

[0079] Polar code encoding: Polar code encoding strategies utilize noise-free channels to transmit useful user information, while transmitting predetermined information or no information in a noisy channel. Polar codes are linear block codes, and their generator matrix is ​​G. N Its encoding process is as follows It is a binary row vector with a length of N (i.e., code length); and Defined as the Kronecker product of log₂N matrices F₂, x₁ N These are the encoded bits (also called codewords). With the generating matrix G N Multiplying them together yields the encoded bits; the process of multiplication is the encoding process.

[0080] During the encoding process of polar codes, A portion of the bits are used to carry information, called the information bit set, and the set of indices of these bits is denoted as A; the other portion of the bits are set to fixed values ​​agreed upon in advance by the receiver and the transmitter, called the fixed bit set or frozen bit set, and the set of its bit indices is the complement of A, A' ... c These freeze bits are typically set to 0, but they can be set arbitrarily as long as the receiver and sender agree in advance.

[0081] The encoding process of polar codes also includes the construction process. The construction process refers to obtaining a Polar code based on a given code length N and information bit length K. The construction process of a polar code can also be viewed as the selection process of set A, or the process used to determine the information bits and frozen bits. Generally, the reliability of each sub-channel is sorted, and the bit indices of the K channels with the highest reliability are used as elements of set A, while the bit indices corresponding to the remaining NK channels are used as elements of set A. c The elements. Or, in other words, bits with higher reliability are set as information bits (data), and bits with lower reliability are set as frozen bits.

[0082] Currently, in NR, the frozen bits and information bits of the polar code are determined based on the reliability sequence corresponding to the mother code length. This reliability sequence can be calculated offline to reduce encoding complexity. The mother code length is a power of 2, and it represents the length of the bit sequence after polar code encoding; the mother code length can also be called the encoding length. Taking a mother code length of 8 as an example, assuming the reliability sequence is [0 1 2 4 3 5 6 7], the reliability of the bits from highest to lowest is: the bit corresponding to bit number 7, the bit corresponding to bit number 6, ..., the bit corresponding to bit number 1, and the bit corresponding to bit number 0. Here, a bit can be understood as a sub-channel of bits. The bit number can be understood as an index or identifier of the bit. For example, when constructing a polar code with a master code length of 8 and an information length of 4, the bits corresponding to bit number 7, bit number 6, bit number 5, and bit number 3 are selected from the end to the beginning as information bits, while the bits corresponding to bit number 4, bit number 2, bit number 1, and bit number 0 are selected as frozen bits.

[0083] Figure 3AAn 8×8 polarization transformation matrix is ​​shown, where the left side can be understood as the encoding side, with bits on the left denoted by u, and the right side can be understood as the encoding side (or codeword side), with bits on the right denoted by x. The process from left to right represents the encoding of the bit sequence at the transmitting end. The information bits to be encoded are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1). After the polarization transformation matrix, the encoded bits are represented by the sequence x(0, ​​1, 0, 1, 0, 1, 0, 1). Mapping x to modulation symbols allows transmission through channel W. Bits corresponding to high channel reliability are used to map information bits, while bits corresponding to low channel reliability are used to map frozen bits. For example... Figure 3A As shown, {u0, u1, u2, u4} are frozen bits, i.e., the positions of the frozen bits, and {u3, u5, u6, u7} are information bits, i.e., the positions of the information bits. In this embodiment, the information bits are also called information bits. The frozen bits are also called frozen positions.

[0084] See Figure 3A In the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0085] Polar code decoding: There are various methods for decoding polar codes, such as successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0086] The SC decoding method involves calculating the LLR of each decoded bit based on the log likelihood ratio (LLR) sequence corresponding to the bit sequence to be decoded, and then making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is always set to 0 regardless of the LLR value. Figure 3B This is a schematic diagram of the SC decoding calculation process, taking 4 decoding bits as an example. Figure 3B There are a total of 8 computation nodes, including 4 F nodes and 4 G nodes. The F nodes correspond to F operations and the G nodes to G operations, respectively. An F node operation requires two LLR inputs to its right, and a G node operation requires two LLR inputs to its right as well as the output of the previous level as input. The output can only be calculated after all inputs have been computed. According to these computation rules... Figure 3B Starting from the right, the decoded bits are calculated sequentially as ①→②→③→④, and the decoding is now complete.

[0087] The SCL decoding method refers to using the LLR sequence corresponding to the bit sequence to be decoded, and saving the decoding results corresponding to 0 and 1 as two branch decoding paths (referred to as path splitting) when decoding each information bit. Figure 3C This is a schematic diagram of the decoding path in the SCL decoding method, as shown below. Figure 3C As shown, each level represents one decoded bit. If the decoding result is 0, the path is developed along the left subtree; if the decoding result is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (generally L = 2, 4, 8, 16, or 32), the L paths with the best path metric (PM) value are selected, saved, and the path development continues to decode subsequent bits. The PM value is used to judge the quality of the path, and the PM value is calculated using LLR. For each level of decoded bits, the PM values ​​of the L paths are sorted in ascending order, and the correct path is selected by filtering out the PM values. This process is repeated until the last bit is decoded.

[0088] III. Modulation and Demodulation:

[0089] See Figure 2 As shown, the transmitting end can also map the encoded bit sequence to multiple modulation symbols, and then transmit multiple modulation symbols; correspondingly, the receiving end can receive multiple modulation symbols and then demodulate them to obtain the sequence of symbols to be decoded.

[0090] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain the modulation symbols. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0091] Higher-order modulation refers to mapping multiple bits to the same modulation symbol, thereby further improving spectral efficiency. Common higher-order modulation schemes include 16QAM, 64QAM, and 256QAM. In the mapping process, 16QAM maps 4 bits to the same modulation symbol, 64QAM maps 6 bits to the same modulation symbol, and 256QAM maps 8 bits to the same modulation symbol. Since the real and imaginary parts are independent, the real and imaginary parts of 256QAM each correspond to a 16ASK modulation, meaning 4 bits are mapped to the same 16ASK modulation symbol.

[0092] In bit-interleaved coded modulation (BICM) schemes, the basic construction method for coding is based on an additive white Gaussian noise (AWGN) channel, thus assuming that the capacity of the input sub-channels at each bit position is consistent. However, in reality, once higher-order modulation is used, or if fading channels exist in the channel, the consistency of the input sub-channel capacity at each bit cannot be guaranteed. For example, during higher-order modulation demodulation, the signal energy of multiple bits within a symbol is not the same after demodulation. This can be understood as the sub-channel capacities of multiple bits within a higher-order modulation being inconsistent. When consecutive bits of a codeword are mapped to a symbol, the demodulation result shows regular changes in the sub-channel capacity of the codeword, thus not conforming to the assumed channel environment during coding construction. This leads to a deterioration in decoding results. Similarly, fading channels also cause similar problems, resulting in significant differences in capacity between some consecutive positions of a codeword and other consecutive positions.

[0093] To address this issue, an interleaving method was developed to randomize the sub-channel gap, thus homogenizing the capacity of each sub-channel across the entire codeword. For example, the encoded sequence A = {a0, a1, a2…} and the modulated sequence B = {b0, b1, b2…} are used. Every 6 consecutive bits in sequence B are modulated into a QAM64 symbol S = {s0, s1, s2…} according to the codebook. QAM64's I / Q channels are independent; therefore, the codebook design for every 3 bits is shown in Table 1 below. For example, 3 bits of 000 correspond to the symbol 7.

[0094] Table 1

[0095]

[0096] After modulation according to the codebook, symbols are transmitted and received at the receiving end. The six bits (I / Q) of the symbol are simultaneously demodulated to obtain six LLR values ​​(parallel demodulation using correlation techniques). After deinterleaving according to the interleaving sequence, the deinterleaved LLRs are decoded to obtain the decoding result.

[0097] IV. Interleaving and deinterleaving processes:

[0098] Interleaving refers to the process of altering the information structure to mitigate sudden errors during transmission, thereby improving the reliability and stability of a communication system. Current interleaving schemes include the following:

[0099] (1) Sub-block based bit interleaved coding modulation (BICM) scheme: In Polar code encoding, the encoded bits are divided into blocks according to their mapped modulation bits. Each block is interleaved independently, and the interleaved bit sequence is used for higher-order modulation mapping. This scheme, by introducing independent interleaving within sub-blocks, can further utilize the different error protection capabilities of different bits in higher-order modulation, thereby further improving error correction performance.

[0100] (2) Row-column interleaving: In the StarSpark standard, Polar codes are used as the encoding and decoding scheme for both control and data channels. A channel bit interleaving scheme is designed for Polar codes, specifically modulo 14 row-column interleaving, where there are 14 rows and E / 14 columns, where E is the codeword transmission length and / is the division sign. For example, the input bit sequence for channel interleaving is e0, e1, e2, e3, ..., e E-1 The output bit sequence of the channel interleaving is f0, f1, f2, f3, ... f E-1 f0 is the bit output by the interleaver first. The pseudocode for this method is as follows:

[0101]

[0102]

[0103] As shown in the pseudocode above, the length E is decomposed into a rectangle with a length of E / 14 rounded up and a height of 14. Then, data is written row-wise and read column-wise. Data where the number of rows written exceeds E is skipped.

[0104] (3) Triangular interleaving: In 5G NR, Polar codes are used as the coding scheme for uplink and downlink control channels. During uplink transmission, after the Polar codes have completed coding and rate matching, channel bit interleaving is required. In the coding of the 5G uplink control channel, triangular interleaving is used for channel bit interleaving.

[0105] For example, the input sequence to be interleaved is: e0, e1, e2, ..., e E-1The output interleaved bit sequence is f0, f1, f2, ..., f E-1 f0 is the bit output by the interleaver first, and the generated pseudocode is as follows:

[0106]

[0107] In the above, E is the transmission length of the codeword, that is, the length after rate matching; T is the number of rows of triangular interleaving, which is the area of ​​the triangle.

[0108] As shown in the pseudocode above, length E is decomposed into a right-angled triangle with length T and height T, then written row by row and read column by column. Any portion of the triangle whose number of rows exceeds E is skipped.

[0109] (4) Interleaving method in layered Polar:

[0110] Current forward error correction (FEC) schemes require the following interleaving objectives:

[0111] 1. Counteracting higher-order modulation: In Polar codes, if higher-order modulation is performed without interleaving, adjacent bits will exhibit a distribution of high and low energy levels. Under modulations such as QAM16 and QAM256, this is because the subcode length of the Polar code itself is 2... n Coupling can lead to performance degradation.

[0112] 2. Perform system bit protection: For example, in NR-LDPC, after interleaving, the system bits can be mapped to the high-energy bit positions of the modulation symbols, which can improve the performance by about 0.3 to 1 dB under high-order modulation.

[0113] 3. Resisting the effects of channel fading:

[0114] Because the interleaving method in layered Polar is based on symbol energy, after the interleaving is completed in the interleaver, the anti-fading part requires an additional second layer of interleaving. For example... Figure 4 As shown, layered Polar requires two layers of interleaving. The first layer, similar to NR-LDPC interleaving, maps bits in a sub-block to different energy levels of the corresponding interleaved symbols. For example, QAM256 has four energy levels of bits, which need to be mapped to four different coded sub-blocks, thus performing a simple row-column interleaving. The second layer is to combat fading. Within each sub-block, interleaving is also required. This interleaving can use row-column interleaving in star flash, triangular interleaving in NR, or other interleaving methods to prevent bits in a symbol from prematurely coupling through codewords during decoding, thus amplifying the fading effect.

[0115] Deinterleaving can be the inverse operation or inverse process of interleaving.

[0116] V. Rate Matching:

[0117] Taking polar codes as an example, as mentioned above, the encoding length of a polar code is an integer power of 2. In practical applications, the required length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to repeatedly transmit some bits to achieve code length matching. This process is usually called rate matching.

[0118] Typically, channel codecs have a limited maximum codeword length. When the transport block (TB) size exceeds the maximum length supported by the current encoder and decoder, the TB needs to be segmented to ensure that the size of the segmented code block (CB) does not exceed the length supported by the current codec. Currently, after segmenting the code block, the length of each segment is not the length of the original code; therefore, the original code needs to be matched to a suitable CB length before transmission. Polar codes generally employ the following three methods for rate matching:

[0119] Punching: This refers to directly punching holes in certain bit positions of the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding "punched" position, the LLR of the corresponding bit is set to 0.

[0120] Shortening: By designing the polar code, certain bit positions in the encoded bit sequence are fixed values, thus eliminating the need for transmission. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0121] Repetition: When the length of the transmitted codeword is greater than the length of the encoded codeword, some or all of the codewords are retransmitted, that is, some or all of the codewords are sent more than once.

[0122] As described above, some channel coding schemes employ interleaving to improve error correction performance. Examples of interleaving methods include row-column interleaving in Starlight Communication, triangular interleaving in NR (Radio Normative Interleaving), and interleaving in hierarchical polar codes. However, current interleaving methods are complex to implement, leading to problems such as high resource consumption and long processing times. Therefore, designing a less complex interleaving method to improve the error correction performance of channel coding is one of the problems that needs to be solved.

[0123] To address the aforementioned problems, embodiments of this application propose a communication method and a communication device that can improve the error correction performance of channel coding with a lower complexity interleaving method. The communication method and communication device are based on the same inventive concept. Since the principles underlying the problems solved by the communication method and communication device are similar, their implementations can be mutually referenced, and repeated details will not be elaborated further.

[0124] The technical solution of this application is described below with reference to specific embodiments.

[0125] This application provides a communication method, which can be applied to, but is not limited to, [the following]. Figure 1 The communication system shown is described. This method can be implemented by a first communication device and a second communication device. The first communication device can act as a transmitter and / or a receiver, and the second communication device can also act as a transmitter and / or a receiver. For example, if the first communication device is the transmitter, then the second communication device is the receiver; or if the first communication device is the receiver, then the second communication device is the transmitter. The transmitter can be called the encoding end, and the receiver can be called the decoding end.

[0126] The following example uses a first communication device as the transmitting / encoding end and a second communication device as the receiving / decoding end. The first and second communication devices are different communication devices. The first (or second) communication device can be a communication device (e.g., a network device, a terminal device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system), or a logic module or software capable of implementing all or part of the functions of that communication device. For example: the first communication device is a network device, and the second communication device is a terminal device. Alternatively, the first communication device is a terminal device, and the second communication device is a network device. Alternatively, the first communication device is a terminal device, and the second communication device is another terminal device. Alternatively, the first communication device is a network device, and the second communication device is another network device.

[0127] This application does not impose specific limitations on the specific structure of the execution entities (such as the first communication device and the second communication device) or the number of each execution entity in the embodiments of this application. As long as communication can be performed according to the methods provided in the embodiments of this application by running a program that records the code of the methods provided in the embodiments of this application, the following description uses the interaction between the first communication device and the second communication device as an example. See also Figure 5 As shown, the method provided in this application embodiment includes the following steps:

[0128] S501: The first communication device acquires the first bit sequence and the second bit sequence.

[0129] Wherein, the length of the first bit sequence and the length of the second bit sequence are both the first length.

[0130] In one possible implementation, the first communication device acquires the first bit sequence by: acquiring a first sub-bit sequence and a second sub-bit sequence, wherein the lengths of the first and second sub-bit sequences are both second lengths, and the second length is less than the first length; the first communication device performs an XOR operation on the first and second sub-bit sequences to obtain a third sub-bit sequence; and then, based on a second cyclic displacement length, the second sub-bit sequence, and the third sub-bit sequence, determines the first bit sequence, wherein the first bit sequence includes the second and third sub-bit sequences, and the second cyclic displacement length is used to determine the position information of the second and / or third sub-bit sequences within the first bit sequence.

[0131] For specific examples of the first bit sequence, the second bit sequence, the first sub-bit sequence, and the second sub-bit sequence, please refer to the description in the following implementation.

[0132] In this embodiment of the application, the acquisition of the second bit sequence by the first communication device is the same as the acquisition of the first bit sequence by the first communication device. The acquisition of the second bit sequence by the first communication device can be obtained by referring to the above-described method of the first communication device acquiring the first bit sequence, which will not be described in detail here.

[0133] In one possible implementation, the first and second sub-bit sequences do not include shortened or punctured bits. This implementation not only facilitates rate matching during transmission but also further reduces the complexity of the cyclic shifting process.

[0134] S502: The first communication device performs an XOR operation on the first bit sequence and the second bit sequence to obtain the third bit sequence.

[0135] The XOR operation performed by the first communication device on the first bit sequence and the second bit sequence can be performed with reference to the XOR operation in the current encoding, and will not be described in detail here.

[0136] S503: The first communication device determines the fourth bit sequence based on the first cyclic displacement length, the second bit sequence, and the third bit sequence.

[0137] The fourth bit sequence includes the second bit sequence and the third bit sequence, and the first cyclic shift length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence.

[0138] In this application embodiment, S503 can be implemented in several possible ways, including but not limited to the following:

[0139] Implementation Method 1: The first communication device determines the fourth bit sequence based on the first cyclic displacement length, the second bit sequence, and the third bit sequence, including: performing cyclic displacement processing on the second bit sequence and the third bit sequence respectively based on the first cyclic displacement length to obtain the fourth bit sequence.

[0140] Implementation Method Two: The first communication device determines the fourth bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence. This includes: during the XOR operation of the first and second bit sequences, performing a cyclic shift operation on the second sub-bit sequence based on the first cyclic shift length to obtain the fourth bit sequence. That is, Implementation Method Two can be executed synchronously with the above-described S502.

[0141] In one possible implementation, the first and second bit sequences do not include shortened or punctured bits. This implementation not only facilitates rate matching during transmission but also further reduces the complexity of the cyclic shifting process.

[0142] In one possible implementation of S501 above, the first communication device determines the first bit sequence based on the second cyclic displacement length, the second sub-bit sequence, and the third sub-bit sequence, which can be specifically executed with reference to either implementation method one or implementation method two above.

[0143] In one possible implementation, the lengths of the first and second cyclic displacements are the same. This approach reduces the complexity of the cyclic displacement processing.

[0144] In the embodiments of this application, the first cyclic displacement length and the second cyclic displacement length may also be different. Furthermore, the first cyclic displacement length and the second cyclic displacement length may be pre-agreed upon by the two or more communicating parties, stipulated by a protocol, or sent by the sending end to the receiving end; no specific limitations are imposed on these.

[0145] In this embodiment, performing XOR processing and cyclic shifting based on a bit sequence of first length can be considered as an encoding process at one level. Performing XOR processing and cyclic shifting based on a bit sequence of second length can be considered as an encoding process at another level.

[0146] The above S502 and S503 can be considered as performing an encoding process at a single level (such as an intermediate or final level). The encoding process includes XOR processing and cyclic bit shifting. The second and third bit sequences in the fourth bit sequence can be considered as examples of the results of an encoding process. Similarly, there are other bit sequences of the first length at this level, which can be executed with reference to the first and second bit sequences in S502 and S503 above, and will not be elaborated here.

[0147] In one possible implementation, the first communication device may further perform the next XOR operation and cyclic shift operation based on the second bit sequence (or the third bit sequence) and other bit sequences of the first length. In another possible implementation, the first communication device may further perform the next level of XOR operation and cyclic shift operation based on the fourth bit sequence and other bit sequences of the same length as the fourth bit sequence, which will not be described in detail here.

[0148] S504: The first communication device outputs the encoded sequence.

[0149] Correspondingly, the second communication device obtains the sequence to be decoded.

[0150] The sequence to be decoded obtained by the second communication device corresponds to the encoded sequence output by the first communication device. For example, the sequence to be decoded is the encoded sequence. The sequence to be decoded (or the encoded sequence) includes a fourth bit sequence.

[0151] In this embodiment, the first communication device can send an encoded sequence to the second communication device via a component (e.g., a communication module, antenna, etc.) within the first communication device, and correspondingly, a component (e.g., a communication module, antenna, etc.) in the second communication device receives the encoded sequence. Alternatively, the first communication device can output the encoded sequence via its communication interface, and correspondingly, the communication interface of the second communication device obtains the encoded sequence. Or, the first communication device can output the encoded sequence via a component (e.g., a chip) corresponding to the first communication device, and correspondingly, the second communication device obtains the encoded sequence via a component (e.g., a chip) corresponding to the second communication device. Therefore, this application does not limit the specific implementation method of the first communication device transmitting the encoded sequence to the second communication device.

[0152] In one possible implementation, when the first communication device outputs the encoded sequence, it includes performing steps such as modulation mapping and rate matching. These steps can be specifically implemented with reference to current modulation mapping and rate matching methods, which will not be detailed here.

[0153] S505: The second communication device obtains the second bit sequence after de-cyclic displacement and / or the third bit sequence after de-cyclic displacement based on the first cyclic displacement length, the second bit sequence, and the third bit sequence.

[0154] In one possible implementation, when the second communication device executes S505, it performs de-cyclic shift processing on the second and third bit sequences in the fourth bit sequence based on the first cyclic shift length, to obtain the de-cyclic shifted second bit sequence and the de-cyclic shifted third bit sequence. This implementation corresponds to implementation method one in S503 above, that is, the second communication device performs the reverse process of implementation method one in S503.

[0155] In another possible implementation, when the second communication device executes S505, it includes: in the de-XOR processing based on the third bit sequence after de-circular shift, the second communication device performs de-circular shift processing on the second bit sequence based on the first circular shift length to obtain the second bit sequence after de-circular shift processing. This implementation corresponds to the second implementation in S503 above, that is, the second communication device executes the reverse process of the second implementation in S503, and this implementation can be executed synchronously with S506 below.

[0156] S506: The second communication device performs XOR processing on the third bit sequence after decyclic shifting to obtain the first bit sequence.

[0157] Through the above S505 and S506, the second communication device obtains the second bit sequence and the first bit sequence after decyclic shifting, which can be regarded as an example of a decoding result at one level.

[0158] Based on one possible implementation of S501 above, the first bit sequence is determined based on the second cyclic shift length, the second sub-bit sequence, and the third sub-bit sequence. The second cyclic shift length is used to determine the position information of the second sub-bit sequence and / or the third sub-bit sequence in the first bit sequence. The first bit sequence includes the second sub-bit sequence and the third sub-bit sequence. The third sub-bit sequence is obtained by XORing the first sub-bit sequence and the second sub-bit sequence. The lengths of both the first and second sub-bit sequences are the second length, and the second length is less than the first length. The method of this application embodiment may also include the following:

[0159] The second communication device obtains the second sub-bit sequence after de-cyclic displacement and / or the third sub-bit sequence after de-cyclic displacement based on the second cyclic displacement length, the second sub-bit sequence, and the third sub-bit sequence; it then performs a de-XOR operation on the third sub-bit sequence after de-cyclic displacement to obtain the first sub-bit sequence. Optionally, this implementation can be executed after S506.

[0160] In the above scheme, the first communication device performs an XOR operation (i.e., an encoding process) on the first and second bit sequences to obtain the third bit sequence. Then, based on the first cyclic shift length, the first bit sequence, and the third bit sequence, it performs a cyclic shift operation to determine the fourth bit sequence. The fourth bit sequence includes the second and third bit sequences. The first cyclic shift length is used to determine the position information of the second and / or third bit sequences within the fourth bit sequence. The first communication device outputs the encoded sequence, which includes the fourth bit sequence, to the second communication device. In this method, the encoding end / transmitter performs cyclic shift operations on the bit sequences during the encoding process, which achieves an interleaving effect, thereby improving the error correction performance of the channel coding and thus improving the decoding performance of the decoding end / receiving end. Furthermore, the processing complexity is relatively low.

[0161] Based on the above Figure 5 The solution shown below will be described in detail through specific implementation methods.

[0162] Implementation Method 1:

[0163] In implementation method one, based on the above... Figure 5 The first implementation of S503 in the illustrated scheme introduces the scheme of this application embodiment. See also Figure 6 As shown, the specific process of the method in Implementation Method 1 includes the following steps:

[0164] S601: The first communication device obtains the code block to be encoded.

[0165] The code block to be encoded may include multiple sub-blocks, each sub-block having a length of 2. n bit, where n is an integer greater than or equal to 0.

[0166] The "multiple sub-blocks" mentioned in the embodiments of this application can be two sub-blocks or more than two sub-blocks. This will be explained uniformly here and will not be repeated elsewhere.

[0167] S602: The first communication device performs an XOR operation on the code block to be encoded to obtain the XOR-processed code block.

[0168] The number of code blocks after XOR processing can be one or more.

[0169] S603: The first communication device performs cyclic shift processing on the code block after XOR processing to obtain the cyclically shifted code block.

[0170] The number of code blocks after cyclic shift can be one or more.

[0171] In one possible implementation, the first communication device is based on a length of 2. n After performing an XOR operation on multiple sub-blocks of a bit, a cyclic shift operation is performed.

[0172] The following is a detailed introduction to S602 and S603.

[0173] For example, the encoded code block includes multiple sub-blocks, each with a length of 32 bits. Taking four 32-bit sub-blocks as an example, such as... Figure 7 As shown, these four 32-bit sub-blocks are designated as sub-block #1, sub-block #2, sub-block #3, and sub-block #4. The following steps are performed on these four 32-bit sub-blocks:

[0174] Step 1.1: See Figure 7 As shown, copy sub-block #2, and then copy sub-block #1 (which is the one described above). Figure 5 Example of the first sub-bit sequence in the scheme shown) and sub-block #2 (i.e., the above) Figure 5 The example of the second sub-bit sequence in the scheme shown is XORed to obtain sub-block #1' (i.e., the one described above). Figure 5 (Example of the third sub-bit sequence in the scheme shown), the length of sub-block #1' is 32 bits.

[0175] Step 1.2: Based on the cyclic displacement value #1 (i.e., the above) Figure 5 (Example of the second cyclic displacement length in the scheme shown) cyclic displacement processing is performed on sub-block #2 and sub-block #1' respectively to obtain sub-block #2 and sub-block #1' after cyclic displacement.

[0176] Similarly, for sub-blocks #3 and #4, both with a length of 32 bits, perform the following steps as described in steps 1.1 and 1.2 above:

[0177] Step 2.1: Copy sub-block #4, and XOR sub-block #3 and sub-block #4 to obtain sub-block #2', which has a length of 32 bits.

[0178] Step 2.2: Based on the cyclic displacement value #1, perform cyclic displacement processing on sub-block #4 and sub-block #2' respectively to obtain sub-block #4 and sub-block #2' after cyclic displacement.

[0179] The two steps (i.e., steps 1.1 and 1.2) executed based on sub-blocks #1 and #2, each with a length of 32 bits, and the two steps (i.e., steps 2.1 and 2.2) executed based on sub-blocks #3 and #4, each with a length of 32 bits, can be executed synchronously or asynchronously, and there is no specific restriction on the order of execution.

[0180] For example, the pseudocode for cyclic displacement processing includes the following:

[0181] for(i=0; i <Z;i=i+1)

[0182] b[i] = a[mod(i+S,Z)].

[0183] Where a is the input sequence, i.e. the code block information before the cyclic shift; b is the output sequence, i.e. the code block information after the cyclic shift; Z is the length of the sequence, i.e. the length of the code block; S is the cyclic shift value, i.e. the cyclic shift length; mod represents the modulo operation.

[0184] Figure 7 The four 32-bit sub-blocks shown are examples. If there are other 32-bit sub-blocks, these sub-blocks can be XORed and then cyclically shifted, following the steps described above. These steps will not be detailed here.

[0185] The encoding process described above, which uses 32-bit sub-blocks as units (including XOR processing and cyclic shift processing), can be considered as one level of encoding process. The encoding process described below, which uses 64-bit sub-blocks as units, can be considered as another level of encoding process. The encoding processes using sub-blocks of other lengths as units are similar.

[0186] In one possible implementation, the first communication device can further determine multiple sub-blocks of 64 bits each, based on the multiple sub-blocks of 32 bits each after the aforementioned XOR and cyclic shift processing. That is, a 64-bit sub-block is obtained from every two 32-bit sub-blocks, and the next XOR and cyclic shift processing is performed based on these multiple 64-bit sub-blocks. Alternatively, the first communication device can continue to perform the next XOR and cyclic shift processing based on the multiple 32-bit sub-blocks. In the next cyclic shift processing, either cyclic shift value #1 or cyclic shift value #2 can be used.

[0187] After completion Figure 7 After XORing and cyclic shifting of the four 32-bit sub-blocks shown, these four 32-bit sub-blocks can be combined into a single 128-bit sub-block #11. Furthermore, this 128-bit sub-block #11 (i.e., the aforementioned...) Figure 5 Example of the first bit sequence in the scheme shown) and other sub-blocks of length 128 bits (such as...) Figure 7 The 128-bit sub-block #22 shown above (is the one mentioned above) Figure 5 The example of the second bit sequence in the scheme shown is XORed once to obtain a sub-block #11' of length 128 bits (i.e., the one mentioned above). Figure 5 Example of the third bit sequence in the scheme shown), after completing the XOR process, the cyclic shift value #3 (i.e., the one mentioned above) is used. Figure 5 (Example of the first cyclic displacement length in the scheme shown) Perform a cyclic displacement process on sub-blocks #11' and #22, both with a length of 128 bits.

[0188] Similarly, for Figure 7 The sub-blocks #33 and #44, both with a length of 128 bits, are XORed once to obtain sub-block #22' with a length of 128 bits. Then, the cyclic shift value #3 is used to perform a cyclic shift process on sub-blocks #22' and #44, both with a length of 128 bits.

[0189] In the embodiments of this application, such as Figure 7 The sub-blocks #22, #33, and #44, each 128 bits long, are obtained by referring to the method used to obtain sub-block #11, which is also 128 bits long. These four 128-bit sub-blocks can be interconnected by following the steps performed on the four 32-bit sub-blocks mentioned above: after one XOR operation, a cyclic shift operation is performed. Figure 7 The example uses four sub-blocks, each 128 bits long. In actual applications, there may be more or fewer sub-blocks of 128 bits long, which will not be listed or described in detail here.

[0190] In one possible implementation, if there is a need for multiple XOR operations and cyclic shift operations, the first communication device can continue to perform one or more XOR operations and cyclic shift operations based on at least two sub-blocks of 128 bits in length after performing one XOR operation and one cyclic shift operation based on multiple sub-blocks of 128 bits in length, or continue to perform one or more XOR operations and cyclic shift operations based on at least two sub-blocks of longer length, until the encoding process ends.

[0191] In one possible implementation, the cyclic displacement values ​​used for each level are all equal. For example, the cyclic displacement values ​​#1, #2, and #3 mentioned above are all equal, which can reduce the complexity of the cyclic displacement processing.

[0192] In the embodiments of this application, the cyclic displacement values ​​used for each level of cyclic displacement may be unequal or partially equal.

[0193] The encoding process can be completed through the above S602 and S603 to obtain the encoded code block, which includes the code block after XOR processing and cyclic shift processing.

[0194] S604: The first communication device outputs the encoded code block; correspondingly, the second communication device obtains the encoded code block.

[0195] The encoded code block includes code blocks after XOR processing and cyclic shift processing.

[0196] S605: The second communication device performs de-cyclic shift processing on the code block after XOR processing and cyclic shift processing to obtain the de-cyclic shifted code block.

[0197] S605 is the reverse operation of S603 performed by the second communication device.

[0198] S606: The second communication device performs XOR processing based on the code block after decyclic shifting.

[0199] S606 is the reverse operation of S602 performed by the second communication device.

[0200] In Implementation Method 1, a cyclic shift process is performed on the code block during the encoding process to achieve an interleaving effect. In high-order modulation scenarios, this can prevent multiple bits of the same symbol from being coupled during the decoding process, thereby improving decoding performance. This method does not require special interleaving operations to resist channel fading, thus effectively reducing the complexity of the encoding and decoding processes.

[0201] Implementation Method Two:

[0202] Compared to Implementation Method 1, the main difference in Implementation Method 2 is that, for the two types of sub-blocks to be encoded, such as the U code and V code in the automatic repeat request technique, cyclic shift processing can be performed simultaneously during the XOR processing. See also Figure 10 As shown, the specific process of Implementation Method Two includes the following steps:

[0203] S801: The first communication device obtains the code block to be encoded.

[0204] The code block to be encoded may include multiple sub-blocks, of which some sub-blocks are V codes and others are U codes.

[0205] S802: The first communication device performs XOR processing on the code block to be encoded and performs cyclic shift processing on the U code.

[0206] For example, when decoupling U-code and V-code, cyclic shift processing can be implemented in the following two ways:

[0207] Method 1: Perform cyclic shift processing on U code and V code respectively.

[0208] Method 2: Perform cyclic displacement processing on U code or V code.

[0209] In Method 1, when the cyclic shift values ​​used for the U code and V code are different, the cyclic shift value used in Method 2 is equal to the difference between the two cyclic shift values ​​in Method 1. The two methods are equivalent. Therefore, after or during the XOR operation of every two sub-blocks (i.e., U code and V code), it is possible to choose to perform cyclic shift operation only on one sub-block (such as U code or V code).

[0210] In the embodiments of this application, the U code can be called the initial transmission code, the V code can be called the retransmission code, or the U code and V code can have other commands, which are not limited in this application.

[0211] In S802, the example of performing cyclic shifting on the U code during XOR processing based on the code block to be encoded is used for illustration. The following is a detailed description of S802.

[0212] For example, the encoded code block includes multiple sub-blocks, which include U code and V code. Each sub-block is 32 bits long. Taking four 32-bit sub-blocks as an example, such as... Figure 9 As shown, these four 32-bit sub-blocks are represented as sub-block #1, sub-block #2, sub-block #3, and sub-block #4, respectively. Sub-block #1 and sub-block #3 are V-code, and sub-block #2 and sub-block #4 are U-code. The following steps are executed:

[0213] See Figure 9 As shown, for sub-blocks #1 and #2, both with a length of 32 bits, in the process of copying sub-block #2 and performing XOR operation on sub-blocks #1 and #2 to obtain a new sub-block, sub-block #2 is simultaneously subjected to cyclic shift operation based on cyclic shift value #1.

[0214] Similarly, for sub-blocks #3 and #4 with a length of 32 bits, the following steps are performed as described above: copying sub-block #4, performing XOR operation on sub-blocks #3 and #4 to obtain a new sub-block, and simultaneously performing cyclic shift operation on sub-block #4 based on the cyclic shift value #1.

[0215] The processes of performing XOR and cyclic shift operations on sub-blocks #1 and #2 (both 32 bits in length) and on sub-blocks #3 and #4 (both 32 bits in length) can be implemented in parallel. However, in some special cases, parallel processing may not be necessary.

[0216] Figure 9 The four 32-bit sub-blocks shown are one example. In the case of other 32-bit sub-blocks, the steps performed on the other 32-bit sub-blocks are implemented in accordance with the steps of the above sub-blocks. That is, when the first communication device performs XOR processing on two sub-blocks (such as U code and V code), it can simultaneously perform cyclic shift processing on one of the sub-blocks (such as U code), thereby reducing the time delay of XOR processing and cyclic shift processing between the two sub-blocks.

[0217] The above processing steps can be regarded as a hierarchical XOR process and cyclic shift process, that is, an XOR process and a cyclic shift process are performed on a sub-block of length 32 bits.

[0218] In one possible implementation, the first communication device may further perform the next XOR operation based on the two 32-bit sub-blocks after the aforementioned XOR and cyclic shift operations. During the XOR operation, the cyclic shift value #2 is used synchronously to perform a cyclic shift operation on one of the sub-blocks. Alternatively, the first communication device may determine at least two 64-bit sub-blocks based on the multiple 32-bit sub-blocks after the aforementioned XOR and cyclic shift operations, i.e., every two 32-bit sub-blocks result in one 64-bit sub-block; then, for these at least two 64-bit sub-blocks, the next XOR and cyclic shift operation is performed on every two 64-bit sub-blocks in the aforementioned manner. In the next cyclic shift operation, either the aforementioned cyclic shift value #1 or the cyclic shift value #2 can be used.

[0219] After completion Figure 9 After XORing and cyclic shifting the four 32-bit sub-blocks shown, these four 32-bit sub-blocks can be combined into a single 128-bit sub-block #11. This 128-bit sub-block #11 can then be combined with other 128-bit sub-blocks (such as...) Figure 9 The 128-bit sub-block #22 shown continues to be XORed, and during the XOR process, the 128-bit sub-block #22 is simultaneously cyclically shifted using the cyclic shift value #3.

[0220] Similarly, sub-blocks #33 and #44, which are 128 bits in length, can be processed in the same way as sub-blocks #11 and #22, which are 128 bits in length. During the XOR process, the cyclic shift value #3 is used synchronously to perform cyclic shift processing on sub-block #44, which is 128 bits in length.

[0221] Figure 9The 128-bit sub-blocks #11 and #33 shown can be considered as V-code. Figure 9 The 128-bit sub-blocks #22 and #44 shown can be considered as U-code.

[0222] In this second implementation method, Figure 9 The four 128-bit sub-blocks shown are one example. If there are other 128-bit sub-blocks, the XOR operation and cyclic shift operation can be performed by referring to the 128-bit sub-blocks #11 and #22, or the 128-bit sub-blocks #33 and #44. These will not be described in detail here.

[0223] In one possible implementation, if there is a need for multiple XOR operations and cyclic shift operations, the first communication device can continue to perform one or more XOR operations and cyclic shift operations based on at least two sub-blocks of 128 bits in length after performing one XOR operation and one cyclic shift operation based on multiple sub-blocks of 128 bits in length, or continue to perform one or more XOR operations and cyclic shift operations based on at least two sub-blocks of longer length, until the encoding process ends.

[0224] In one possible implementation, the cyclic displacement values ​​used for each level are all equal. For example, the cyclic displacement values ​​#1, #2, and #3 mentioned above are all equal, which can reduce the complexity of cyclic displacement processing.

[0225] In the embodiments of this application, the cyclic displacement values ​​used for each level of cyclic displacement may be unequal or partially equal.

[0226] In S802, the first communication device selects to perform cyclic shift processing only on the U code during the XOR process of V code and U code. In this application, the first communication device can also select to perform cyclic shift processing only on the V code during the XOR process of V code and U code. For details, please refer to the above implementation, which will not be described in detail here.

[0227] S803: The first communication device outputs the encoded code block; correspondingly, the second communication device obtains the encoded code block.

[0228] The encoded code block includes code blocks after XOR processing and cyclic shift processing.

[0229] S804: The second communication device performs de-cyclic shift processing on the code block after XOR processing and cyclic shift, and then performs de-XOR processing.

[0230] S804 is the reverse operation of S802 performed by the second communication device.

[0231] In the second implementation method, for each of the two sub-blocks to be encoded (such as V code and U code), while performing XOR processing, one of the sub-blocks (such as U code) can also be subjected to cyclic shift processing. This can effectively reduce the latency of the encoding process at the transmitting end, and the receiving end can also perform de-XOR processing while performing cyclic shift processing, thereby reducing the latency of the decoding process.

[0232] Implementation Method 3:

[0233] Compared to Embodiments 1 and 2, the main difference in Embodiment 3 is that, during the cyclic shift process, cyclic shift processing is not performed on certain bits or sub-blocks. These bits or sub-blocks correspond to positions that need to be shortened or punctured during rate matching. See also... Figure 10 As shown, the specific process of the method in Implementation Method 3 includes the following steps:

[0234] S1001: The first communication device obtains the code block to be encoded.

[0235] S1002: The first communication device performs XOR processing and cyclic shift processing based on the code block to be encoded.

[0236] The sub-blocks that perform cyclic shifting do not include bits that are frozen, punched, or shortened.

[0237] In S1002, it can be executed with reference to S602 and S603 in Embodiment 1 above, or with reference to S802 in Embodiment 2 above, but the main difference in S1002 is as follows:

[0238] If a punching operation is performed during rate matching, such as Figure 11A As shown, no cyclic shifting is performed on bits at punched or frozen positions in a sub-block.

[0239] If a shortening operation is performed during rate matching, such as Figure 11B As shown, no cyclic shifting is performed on bits at shortened or frozen positions in a sub-block.

[0240] S1003: The first communication device outputs the encoded code block; correspondingly, the second communication device obtains the encoded code block.

[0241] The encoded code block includes code blocks after XOR processing and cyclic shift processing.

[0242] S1004: The second communication device performs de-cyclic shift processing and de-XOR processing on the code blocks after XOR processing and cyclic shift processing.

[0243] S1004 is the reverse operation of the second communication device performing the above-mentioned S1002.

[0244] In Implementation Method 3, considering that rate matching needs to be performed during actual transmission, some bits need to be punctured or shortened. Therefore, during the encoding process, the bits or sub-blocks at the punctured or shortened positions are excluded from the cyclic shift process. This not only facilitates rate matching during transmission but also further reduces the complexity of the encoding process (including XOR processing and cyclic shift processing). Similarly, for the receiving end, it facilitates rate matching and reduces the complexity of the decoding process.

[0245] It should be understood that the above embodiments may change as the technical solutions evolve, and this application is not limited to the contents shown in the above embodiments.

[0246] It should be noted that different embodiments or some steps (e.g., any one or more steps) in different embodiments of this application can be combined with each other to form new embodiments. Furthermore, this application does not limit the inclusion of any one or more steps in different embodiments as including optional steps in a certain embodiment, mandatory steps in a certain embodiment, or both optional and mandatory steps in a certain embodiment.

[0247] It should be noted that, unless otherwise specified or there is a logical conflict, the terminology and / or descriptions between different implementation methods are consistent and can be referenced from each other.

[0248] It should be noted that the order of the steps in the embodiments of this application is determined by the logic of the scheme, and this application does not limit it.

[0249] It should be noted that the order in which different conditions are judged in the embodiments of this application is not limited by this application.

[0250] It should be noted that the terms "after" and "time" in this application do not strictly limit the specific point in time.

[0251] It should be noted that the nouns and terms used in this application are merely examples and may be other names, which are not limited in this application.

[0252] In the embodiments provided above, the methods provided by the embodiments of this application have been described from the perspective of interaction between various devices. To implement the functions of the methods provided in the embodiments or implementations of this application, the first communication device or the second communication device may include hardware structures and / or software modules, implementing the above functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is executed in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0253] The module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments or implementations of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0254] Similar to the above concept, such as Figure 12 As shown, this application embodiment also provides a communication device 1200 for implementing the functions of the first or second communication device in the above method. For example, the communication device 1200 can be a software module or a chip system. In this application embodiment, the chip system can be composed of chips or can include chips and other discrete devices. The communication device 1200 may include: a communication unit 1201 and a processing unit 1202.

[0255] In this embodiment, the communication unit 1201, also known as the transceiver unit, may include a sending unit and / or a receiving unit, respectively used to perform the sending and receiving steps of the first or second communication device in the above method embodiments. The processing unit 1202 may be used to read instructions and / or data from the storage module so that the communication device 1200 implements the aforementioned method embodiments.

[0256] Optionally, the communication device 1200 may further include a storage unit 1203, which is equivalent to a storage module and can be used to store instructions and / or data.

[0257] The following, combined with Figures 12 to 13 This application provides a detailed description of the communication device provided in its embodiments. It should be understood that the descriptions of the device embodiments correspond to the descriptions of the method embodiments; therefore, any content not described in detail can be found above. Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The method shown is used to achieve this, and for the sake of simplicity, it will not be described in detail here.

[0258] The communication unit 1201 can also be referred to as a transceiver, transceiver, or transceiver device. The processing unit can also be referred to as a processor, processing board, processing module, or processing device. Optionally, the device in the communication unit 1201 used to implement the receiving function can be considered as a receiving unit, and the device in the communication unit 1201 used to implement the transmitting function can be considered as a transmitting unit; that is, the communication unit 1201 includes both a receiving unit and a transmitting unit. The communication unit can sometimes also be referred to as a transceiver, transceiver circuit, or transceiver unit. The receiving unit can sometimes be referred to as a receiver, receiver, or receiving circuit. The transmitting unit can sometimes be referred to as a transmitter, transmitter, or transmitting circuit.

[0259] When the communication device 1200 is applied in the above embodiment Figure 5 In the process shown, the first communication device is used:

[0260] The communication unit 1201 is used to acquire a first bit sequence and a second bit sequence, wherein the length of the first bit sequence and the length of the second bit sequence are both a first length.

[0261] The processing unit 1202 is configured to perform an XOR operation on the first bit sequence and the second bit sequence to obtain a third bit sequence; the processing unit 1202 is also configured to determine a fourth bit sequence based on a first cyclic displacement length, the second bit sequence and the third bit sequence, wherein the fourth bit sequence includes the second bit sequence and the third bit sequence, and the first cyclic displacement length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence;

[0262] The communication unit 1201 is also used to output the encoded sequence, which includes the fourth bit sequence.

[0263] When the communication device 1200 is applied in the above embodiment Figure 5 In the process shown, the second communication device is used:

[0264] The communication unit 1201 is used to obtain a sequence to be decoded, the sequence to be decoded including a fourth bit sequence, the fourth bit sequence being determined based on a first cyclic shift length, a second bit sequence, and a third bit sequence, the first cyclic shift length being used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence, the fourth bit sequence including the second bit sequence and the third bit sequence, the third bit sequence being obtained by XORing the first bit sequence and the second bit sequence, the lengths of the first bit sequence and the second bit sequence being a first length;

[0265] The processing unit 1202 is used to obtain the second bit sequence after decirculation and / or the third bit sequence after decirculation based on the first cyclic displacement length, the second bit sequence and the third bit sequence;

[0266] The processing unit 1202 is further configured to perform XOR processing on the third bit sequence after the decyclic shift to obtain the first bit sequence.

[0267] The above is just an example. Processing unit 1202 and communication unit 1201 can also perform other functions. For a more detailed description, please refer to [link / reference needed]. Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The relevant descriptions in the method embodiments shown will not be repeated here.

[0268] like Figure 13 The image shown is a communication device 1300 provided in an embodiment of this application. Figure 13 The communication device shown can be Figure 12 The diagram illustrates one hardware circuit implementation of the communication device. This communication device 1300 can be applied to the flowchart shown above to perform the functions of the first or second communication device in the method embodiments described. For ease of explanation, Figure 13 Only the main components of the communication device are shown.

[0269] like Figure 13 As shown, the communication device 1300 includes a communication interface 1301 and a processor 1302. The communication interface 1301 and the processor 1302 are coupled to each other. It is understood that the communication interface 1301 can be a transceiver or an input / output interface, or an interface circuit such as a transceiver circuit. Optionally, the communication device 1300 may further include a memory 1303 for storing instructions executed by the processor 1302, or storing input data required by the processor 1302 to execute instructions, or storing data generated after the processor 1302 executes instructions.

[0270] When the communication device 1300 is used to achieve the above Figure 5 and Figure 6 , Figure 8 as well as Figure 10 In the method shown, the communication interface 1301 is used to implement the functions of the communication unit 1201, and the processor 1302 is used to implement the functions of the processing unit 1202.

[0271] This application embodiment does not limit the specific connection medium between the communication interface 1301, processor 1302, and memory 1303. This application embodiment... Figure 13The memory 1303, processor 1302, and communication interface 1301 are connected via a communication bus 1304. The communication bus 1304 is in... Figure 13 The connections between other components are shown in bold and are for illustrative purposes only, not as limiting information. The communication bus 1304 can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 13 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0272] When the aforementioned communication device is a chip. Figure 14 A simplified schematic diagram of a chip device structure is shown. The chip 1400 includes interface circuitry 1401 and one or more processors 1402. Optionally, the chip 1400 may also include a bus. Wherein:

[0273] Processor 1402 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the method for determining the service node information described above can be completed by the integrated logic circuitry in the hardware of processor 1402 or by instructions in software form. Processor 1402 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods and steps disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0274] The interface circuit 1401 can be used to send or receive data, instructions or information. The processor 1402 can use the data, instructions or other information received by the interface circuit 1401 to process the data, instructions or other information, and can send the processed information out through the interface circuit 1401.

[0275] Optionally, chip 1400 also includes memory 1403, which may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of memory 1403 may also include non-volatile random access memory (NVRAM).

[0276] Optionally, the memory stores executable software modules or data structures, and the processor can execute corresponding operations by calling the operation instructions stored in the memory (which may be stored in the operating system).

[0277] Optionally, the chip can be used in the first or second communication device involved in the embodiments of this application. Optionally, the interface circuit 1401 can be used to output the execution result of the processor 1402. For the communication methods provided by one or more embodiments of this application, please refer to the foregoing embodiments, which will not be repeated here.

[0278] It should be noted that the functions of the interface circuit 1401 and the processor 1402 can be implemented through hardware design, software design, or a combination of hardware and software; no restrictions are imposed here.

[0279] This application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by the first communication device or the second communication device in the above method embodiments.

[0280] For example, when the computer program is executed by a computer, it enables the computer to implement the method executed by the first communication device or the second communication device in the above method embodiments.

[0281] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to implement the method performed by the first communication device or the second communication device in the above method embodiments.

[0282] This application also provides a chip, including a processor, for calling computer programs or computer instructions stored in the memory, so that the processor executes the above-mentioned... Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The communication method shown is a specific implementation method.

[0283] In one possible implementation, the chip's input corresponds to the above... Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The receiving operation shown in the implementation corresponds to the output of the chip described above. Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The sending operation in the implementation shown.

[0284] Optionally, the processor is coupled to the memory via an interface.

[0285] Optionally, the chip also includes a memory that stores computer programs or computer instructions.

[0286] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more processors used to control the above. Figure 5 and Figure 6 , Figure 8 as well as Figure 10 The illustrated implementation is an integrated circuit for program execution using a communication method. The memory mentioned above can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0287] It should be noted that, for the sake of convenience and brevity, the explanations and beneficial effects of the relevant content in any of the communication devices provided above can be referred to the corresponding service node information determination method embodiments provided above, and will not be repeated here.

[0288] The module division in this embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in each embodiment of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0289] Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments of this application can be implemented in hardware, firmware, or a combination thereof. When implemented in software, the above functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a computer. For example, but not limited to, computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible to a computer. Furthermore, any connection can suitably be a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used in embodiments of this application, disks and discs include compact discs (CDs), laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while discs optically copy data using lasers. The combinations above should also be included within the scope of protection for computer-readable media.

[0290] In summary, the above descriptions are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A communication method characterized by comprising: include: Obtain a first bit sequence and a second bit sequence, wherein the length of the first bit sequence and the length of the second bit sequence are both a first length; The first bit sequence and the second bit sequence are XORed to obtain the third bit sequence; Based on the first cyclic displacement length, the second bit sequence, and the third bit sequence, a fourth bit sequence is determined, wherein the fourth bit sequence includes the second bit sequence and the third bit sequence, and the first cyclic displacement length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence; Output the encoded sequence, which includes the fourth bit sequence.

2. The method of claim 1, wherein, The process of obtaining the first bit sequence includes: Obtain a first sub-bit sequence and a second sub-bit sequence, wherein the length of the first sub-bit sequence and the length of the second sub-bit sequence are both the second length, and the second length is less than the first length; The first sub-bit sequence and the second sub-bit sequence are XORed to obtain the third sub-bit sequence; Based on the second cyclic displacement length, the second sub-bit sequence, and the third sub-bit sequence, the first bit sequence is determined, wherein the first bit sequence includes the second sub-bit sequence and the third sub-bit sequence, and the second cyclic displacement length is used to determine the position information of the second sub-bit sequence and / or the third sub-bit sequence in the first bit sequence.

3. The method of claim 2, wherein, The second cyclic displacement length is the same as the first cyclic displacement length.

4. The method of claim 2, wherein, The first sub-bit sequence and the second sub-bit sequence do not include shortened bits or punched bits.

5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the fourth bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence includes: Based on the first cyclic shift length, the second bit sequence and the third bit sequence are subjected to cyclic shift processing respectively to obtain the fourth bit sequence.

6. The method according to any one of claims 1-4, characterized in that, The step of determining the fourth bit sequence based on the first cyclic shift length, the second bit sequence, and the third bit sequence includes: During the XOR operation on the first bit sequence and the second bit sequence, the second sub-bit sequence is subjected to the cyclic shift operation based on the first cyclic shift length to obtain the fourth bit sequence.

7. The method according to any one of claims 1 to 6, characterized in that, The first bit sequence and the second bit sequence do not include shortened bits or punched bits.

8. A communication method characterized by comprising: include: A sequence to be decoded is obtained, the sequence to be decoded includes a fourth bit sequence, the fourth bit sequence is determined based on a first cyclic shift length, a second bit sequence, and a third bit sequence, the first cyclic shift length is used to determine the position information of the second bit sequence and / or the third bit sequence in the fourth bit sequence, the fourth bit sequence includes the second bit sequence and the third bit sequence, the third bit sequence is obtained by XORing the first bit sequence and the second bit sequence, and the lengths of the first bit sequence and the second bit sequence are both a first length; Based on the first cyclic displacement length, the second bit sequence, and the third bit sequence, the second bit sequence after decyclic displacement and / or the third bit sequence after decyclic displacement are obtained; The first bit sequence is obtained by performing a de-XOR operation on the third bit sequence after the decyclic shift.

9. The method of claim 8, wherein, The step of obtaining the second bit sequence and / or the third bit sequence after de-circuit shifting based on the first cyclic shift length, the second bit sequence, and the third bit sequence includes: Based on the first cyclic shift length, the second bit sequence and the third bit sequence in the fourth bit sequence are respectively subjected to decyclic shift processing to obtain the decyclic shifted second bit sequence and the decyclic shifted third bit sequence.

10. The method of claim 8, wherein, The step of obtaining the second bit sequence and / or the third bit sequence after de-circuit shifting based on the first cyclic shift length, the second bit sequence, and the third bit sequence includes: In the de-XOR processing of the third bit sequence based on the de-cyclic shift, the second bit sequence is de-cyclic shifted based on the first cyclic shift length to obtain the second bit sequence after the de-cyclic shift.

11. The method according to any one of claims 8-10, characterized in that, The first bit sequence is determined based on the second cyclic shift length, the second sub-bit sequence, and the third sub-bit sequence. The second cyclic shift length is used to determine the position information of the second sub-bit sequence and / or the third sub-bit sequence in the first bit sequence. The first bit sequence includes the second sub-bit sequence and the third sub-bit sequence. The third sub-bit sequence is obtained by XORing the first sub-bit sequence and the second sub-bit sequence. The lengths of the first sub-bit sequence and the second sub-bit sequence are both the second length, and the second length is less than the first length. The method further includes: Based on the second cyclic displacement length, the second sub-bit sequence, and the third sub-bit sequence, the second sub-bit sequence after decyclic displacement and / or the third sub-bit sequence after decyclic displacement are obtained; The first sub-bit sequence is obtained by performing a de-XOR operation on the third sub-bit sequence after the decyclic shift.

12. The method of claim 11, wherein, The second cyclic displacement length is the same as the first cyclic displacement length.

13. The method of claim 11, wherein, The first sub-bit sequence and the second sub-bit sequence do not include shortened bits or punched bits.

14. The method according to any one of claims 8-12, characterized in that, The first bit sequence and the second bit sequence do not include shortened bits or punched bits.

15. A communications device, characterized by It includes units or modules for performing the method as described in any one of claims 1-7, or units or modules for performing the method as described in any one of claims 8-14.

16. A communications device, characterized by Includes a processor configured to cause the communication device to perform the method as described in any one of claims 1-7, or the method as described in any one of claims 8-14, via logic circuitry and / or by executing a computer program.

17. The communication apparatus according to claim 16, wherein It also includes input / output interfaces and / or memory, the memory being used to store the computer program, and the input / output interfaces being used to input and / or output information.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer-readable program or instructions that, when executed on a communication device, cause the method described in any one of claims 1-7 to be performed, or the method described in any one of claims 8-14 to be performed.

19. A computer program product, characterised in that, The computer program product includes a computer program or instructions that, when run on a computer, cause the method as described in any one of claims 1-7 to be performed, or the method as described in any one of claims 8-14 to be performed.

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