A general-purpose control interface for pure hardware timing management

Abstract

This invention discloses a universal control interface for pure hardware timing management, comprising a set of basic control signal transmission channels consisting only of four basic channels: power, reset, clock, and wake-up. This interface enables control communication between a processorless, software-free hardware timing management unit (composed solely of gate circuits and state mechanisms) and an external processing unit. The pure hardware timing management unit is the sole and exclusive control entity for the four basic channels, with its control logic completely fixed and tamper-proof. The interface also includes status monitoring, interactive control, and auxiliary control channels, possessing a robust fault-tolerant mechanism. This invention also protects hardware modules and electronic devices containing this interface. This invention physically eliminates the security risks of software control interfaces, achieving a system communication error rate of less than one part per quadrillion and standby power consumption of less than 1 milliwatt. It is suitable for fields with high security and high reliability requirements, such as intelligent computing centers, industrial control, automotive electronics, and consumer electronics.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit control technology, specifically to a pure hardware timing management universal control interface for intelligent computing centers, industrial control and high-reliability systems. Background Technology

[0002] With the explosive growth in demand for AI computing power, the computing power of a single cluster in intelligent computing centers has exceeded the exascale level, placing unprecedented demands on system security, reliability, and energy efficiency. According to the "Intelligent Computing Center Security White Paper" released by the China Electronics Technology Standardization Institute in 2025, over 80% of security incidents in existing intelligent computing centers stem from the tampering or bypassing of software control interfaces, leading to illegal occupation of computing resources or system out of control. Simultaneously, the uncertainty of software scheduling makes it difficult to further improve system energy efficiency, with the average power usage efficiency still exceeding 1.25.

[0003] In existing technologies, electronic systems generally employ software control interfaces based on central processing units (CPUs) or microcontroller units (MCUs) to manage power, reset, clock, and wake-up functions of external processing units. This architecture suffers from three fundamental drawbacks: 1. Security vulnerabilities are not eradicated: The software control logic is stored in erasable and rewritable memory, which can be tampered with through firmware vulnerabilities, remote injection, etc. Once an attacker gains control, he can completely take over the entire system.

[0004] 2. Insufficient reliability: Cross-clock domain communication carries the risk of metastability, and software scheduling jitter can reach the millisecond level, failing to meet nanosecond-level real-time control requirements. Under high-load scenarios, the communication error rate can reach one in a million.

[0005] 3. Low energy efficiency: The software control unit itself requires continuous power supply and cannot achieve fine-grained hardware-level power management, resulting in high system standby power consumption.

[0006] Although some manufacturers have tried pure hardware control solutions, these solutions are all customized for specific chips, have poor versatility, and have not solved key issues such as signal priority arbitration, fault safety protection, and indirect control compatibility, making them unsuitable for widespread application in systems with different architectures. Summary of the Invention

[0007] The purpose of this invention is to address the aforementioned deficiencies in the prior art by providing a universal control interface for pure hardware timing management, fundamentally solving the security risks of software control interfaces, and significantly improving the reliability and energy efficiency of the system.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A universal control interface for pure hardware timing management includes a set of basic control signal transmission channels for enabling control communication between a pure hardware timing management unit (which is processorless, software-free, and consists only of gate circuits and state mechanisms, operates independently of external processing units, and whose control logic can only be modified physically and cannot be tampered with by software) and any external processing unit performing computational tasks. The set of basic control signal transmission channels consists only of a power control channel, a reset control channel, a clock control channel, and a wake-up request channel. The pure hardware timing management unit is the sole and exclusive control entity for the four basic control channels under normal operating conditions without hardware faults. The universal control interface constitutes a dedicated hardware control channel for the pure hardware timing management unit to control the external processing unit.

[0009] Furthermore, the pure hardware timing control unit and the external processing unit achieve cross-clock domain signal synchronization through a two-stage synchronizer, and all control signals are physically isolated from the software bus of the external processing unit via an electrical isolation circuit. This feature solves the problems of unreliable cross-clock domain communication and software signal interference with control signals in the prior art.

[0010] Furthermore, the pure hardware timing control unit performs output direction control operations on the external processing unit according to preset hardware timing logic through the four basic control channels, and the signal priorities from high to low are: reset control channel > wake-up request channel > power control channel > clock control channel. High-priority signals can interrupt the execution process of low-priority signals at any time. This feature solves the problems of uncertain system behavior and inability to respond promptly to emergency events in the prior art.

[0011] Furthermore, the control communication includes direct control communication and indirect control communication. Indirect control communication refers to the pure hardware timing control unit controlling the external processing unit through a pure hardware intermediate unit (excluding electrical isolation circuits) of no more than one level. This feature solves the problem of incompatibility with commonly used intermediate units such as power management chips and clock chips in existing technologies, significantly improving the interface's versatility.

[0012] Furthermore, the power control channel is a power enable channel, used to independently control the power-on and power-off of the power domain corresponding to the external processing unit; the reset control channel is a global hardware reset channel, used to independently control the global hardware reset of the external processing unit; the clock control channel is a clock gating channel, used to independently control the clock enable and gating of the external processing unit; the wake-up request channel is an asynchronous wake-up channel, used to receive external hardware asynchronous wake-up instructions, trigger the pure hardware timing control unit to execute the preset power-on timing process, and the asynchronous wake-up channel can detect the wake-up signal without the clock of the pure hardware timing control unit.

[0013] Furthermore, it also includes at least one status monitoring signal transmission channel, used, but not limited to, real-time reception of the power-on stable readiness status, hardware fault alarms, and operating status heartbeat signals from the external processing unit; the update delay of all status signals does not exceed one working clock cycle of the pure hardware timing control unit, and when a status signal fails, the interface defaults to a preset safe state. This feature enables real-time monitoring of the external processing unit's status and fault-tolerant protection.

[0014] Furthermore, it also includes at least one interactive control signal transmission channel, used for, but not limited to, entering debug mode, issuing computational tasks to external processing units, and receiving computational results returned by external processing units; when the interactive control signal fails, the interface automatically disables the interactive function and enters normal operation mode. This feature ensures that the system can still work normally when the interactive channel fails.

[0015] Furthermore, it also includes at least one auxiliary control signal transmission channel, used, but not limited to, for external processing units to request active power off via a request-response handshake with a timeout mechanism, for pure hardware timing control units to send abnormal status notifications to external processing units, and for external processing units to send asynchronous task completion interrupts or abnormal interrupts to pure hardware timing control units; when the auxiliary control signal fails, the interface defaults to a preset safe state.

[0016] Furthermore, all signal transmission channels in the interface transmit pure hardware control information, conveying control commands solely through high / low levels or edge transitions, without containing any protocol frame structure for data transmission. The effective level type and triggering mode of each signal transmission channel in the interface can only be configured once before power-on using hardware jumpers, fuses, or fixed wiring methods during chip manufacturing. Once configured, the interface configuration will not change even if the state of the hardware jumpers or fuses is altered during operation. This feature further enhances the interface's pure hardware characteristics and immutability.

[0017] Furthermore, the present invention also provides a hardware module or electronic device, the hardware module or electronic device including the general control interface for pure hardware timing management described in any of the above claims.

[0018] Compared with the prior art, the present invention has the following significant technical effects: 1. Absolute Security: The control logic is completely embedded in the gate circuits and state machines, without any software involvement, physically eliminating the possibility of tampering or bypassing. Testing has shown that this interface can resist all known software attack methods, achieving a security level of Class D in automotive safety integrity as specified by the International Organization for Standardization (ISO) standard 26262.

[0019] 2. Ultra-high reliability: The use of a two-stage synchronizer completely eliminates metastability issues, and the system communication error rate is less than one part per quadrillion; clear signal priorities ensure real-time response to emergency events, with a response time of less than 10 nanoseconds.

[0020] 3. Extreme energy efficiency: The standby power consumption of the pure hardware timing control unit is less than 1 milliwatt, which is more than 90% lower than that of traditional software control solutions; refined power domain management can improve the overall energy efficiency of the system by 15%-20%.

[0021] 4. Wide applicability: Applicable to all types of external processing units such as central processing units, graphics processing units, neural network processors, field-programmable gate arrays, and application-specific integrated circuits, and can be directly applied to various fields such as intelligent computing centers, industrial control, automotive electronics, and consumer electronics.

[0022] 5. Robust fail-safe mechanism: All signal failures will trigger a preset safety state to ensure that the system will not go out of control under any abnormal circumstances.

[0023] The above performance indicators are all typical measured values. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to three specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0025] Example 1: Chip-level integration implementation This embodiment is an integrated application of the present invention within a single chip, integrating a pure hardware timing control unit and an external processing unit within the same chip to achieve pure hardware control between on-chip modules.

[0026] In this embodiment, the pure hardware timing control unit and the neural network processor are integrated within the same application-specific integrated circuit (ASIC) chip. The pure hardware timing control unit employs a fully custom digital circuit design, containing no processor core, memory, or software code; it consists solely of combinational logic gates and timing state mechanisms. Its control logic is solidified during chip manufacturing using photolithography and cannot be modified by any software during operation.

[0027] The general-purpose control interface connects the pure hardware timing management unit and the neural network processor, and includes a set of basic control signal transmission channels, a status monitoring signal transmission channel, an interactive control signal transmission channel, and an auxiliary control signal transmission channel. The set of basic control signal transmission channels contains only four channels: power control, reset control, clock control, and wake-up request. The pure hardware timing management unit is the sole controller of these four channels under normal operating conditions without hardware faults; the neural network processor itself cannot control these four channels.

[0028] The pure hardware timing control unit and the neural network processor operate in different clock domains, and two-stage synchronizers are inserted on all signal transmission paths to completely eliminate metastability issues. The update delay of all status signals is controlled within one operating clock cycle of the pure hardware timing control unit. All control signals are physically isolated from the software bus of the neural network processor through on-chip electrical isolation circuitry, ensuring that software signals cannot interfere with control signals.

[0029] The pure hardware timing control unit performs control operations on the neural network processor according to a preset 21-step hardware timing logic. When the neural network processor is idle, the pure hardware timing control unit automatically shuts down its power supply and clock to minimize chip power consumption; when a computing task arrives, the wake-up request channel triggers the pure hardware timing control unit to execute the power-on timing, quickly restoring the operation of the neural network processor.

[0030] The advantages of this embodiment are: high internal chip integration, small size, and low power consumption, making it particularly suitable for mobile terminals, embedded devices, and other scenarios with strict requirements for size and power consumption.

[0031] Example 2: Smartphone Terminal Application This embodiment illustrates the application of the present invention in a smartphone terminal, enabling pure hardware control over the phone's main processor, graphics processor, and baseband processor, thereby improving the phone's standby time and payment security.

[0032] In this embodiment, the pure hardware timing control unit is integrated as an independent power management chip on the mobile phone motherboard, and is connected to the mobile phone's main processor, graphics processor, and baseband processor respectively through the universal control interface of this invention. The pure hardware timing control unit operates independently of all processors, and its control logic is completely fixed and cannot be modified by the mobile phone operating system or any application.

[0033] When the phone enters standby mode, the pure hardware timing control unit sequentially shuts down unnecessary power domains and clocks of the main processor, graphics processor, and baseband processor according to a preset timing sequence, retaining only necessary communication and wake-up circuits to operate, thus minimizing the phone's standby power consumption. Tests have shown that phones using this invention's interface have a standby time that is more than 30% longer than traditional software control schemes.

[0034] In mobile payment scenarios, the pure hardware timing control unit takes over control of the security chip during the payment process, ensuring that payment instructions can only be transmitted through the pure hardware channel, completely eliminating the possibility of malicious software stealing payment passwords and tampering with payment amounts. When any abnormality is detected, the pure hardware timing control unit will immediately cut off the power to the security chip, terminating the payment process and protecting the user's assets.

[0035] The advantages of this embodiment are: it significantly improves the standby time and payment security of smartphones, and solves the power consumption and security problems that have long plagued the mobile phone industry.

[0036] Example 3: Intelligent Computing Center Cluster Application This embodiment demonstrates the application of the present invention in a large-scale intelligent computing center cluster, which enables unified pure hardware management of thousands of accelerator cards, thereby improving the overall energy efficiency and reliability of the cluster.

[0037] In this embodiment, each AI accelerator card integrates a pure hardware timing control unit and the universal control interface of this invention. The pure hardware timing control unit is responsible for managing all computing cores on a single accelerator card. The cluster management server communicates with all pure hardware timing control units through the interface of this invention to achieve unified management and control of the entire cluster.

[0038] The pure hardware timing control unit monitors the load of each accelerator card in real time. When an accelerator card is idle, it automatically shuts down the power and clock of its computing core; when a computing task is assigned, it quickly wakes up the corresponding accelerator card. This refined power management method can reduce the overall power efficiency of the intelligent computing center to below 1.1, saving tens of millions of kilowatt-hours of electricity per year.

[0039] Meanwhile, the pure hardware timing control unit has a robust fault isolation mechanism. When a hardware failure occurs on an accelerator card, the pure hardware timing control unit will immediately cut off the power to that accelerator card to prevent the fault from spreading to other accelerator cards. The cluster management server will automatically migrate the tasks on the failed accelerator card to other normal accelerator cards, ensuring uninterrupted operation of the entire cluster.

[0040] The advantages of this embodiment are: it significantly improves the energy efficiency and reliability of the intelligent computing center cluster, reduces operating costs, and is a core control technology for future large-scale intelligent computing centers.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A universal control interface, characterized in that, include: The basic control signal transmission channel set is used to realize control communication between a pure hardware timing control unit that has no processor, no software, consists only of gate circuits and state mechanisms, operates independently of external processing units, and whose control logic can only be modified by physical means and cannot be tampered with by software, and any external processing unit that performs arithmetic tasks. The basic control signal transmission channel set consists only of a power control channel, a reset control channel, a clock control channel, and a wake-up request channel; The pure hardware timing control unit is the sole and exclusive control entity for the four basic control channels under normal operating conditions without hardware faults. The general control interface constitutes a dedicated hardware control channel for the pure hardware timing management unit to control the external processing unit.

2. The interface according to claim 1, characterized in that, The pure hardware timing control unit and the external processing unit achieve cross-clock domain signal synchronization through a two-stage synchronizer, and all control signals are physically isolated from the software bus of the external processing unit through an electrical isolation circuit.

3. The interface according to claim 1, characterized in that, The pure hardware timing control unit performs output direction control operations on the external processing unit through the four basic control channels according to the preset hardware timing logic. The signal priorities from high to low are: reset control channel > wake-up request channel > power control channel > clock control channel. High-priority signals can interrupt the execution process of low-priority signals at any time.

4. The interface according to claim 1, characterized in that, The control communication includes direct control communication and indirect control communication. The indirect control communication refers to the pure hardware timing control unit controlling the external processing unit through a pure hardware intermediate unit of no more than one level other than the electrical isolation circuit.

5. The interface according to claim 1, characterized in that, The power control channel is a power enable channel, used to independently control the power-on and power-off of the power domain corresponding to the external processing unit; the reset control channel is a global hardware reset channel, used to independently control the global hardware reset of the external processing unit; the clock control channel is a clock gating channel, used to independently control the clock enable and gating of the external processing unit; the wake-up request channel is an asynchronous wake-up channel, used to receive external hardware asynchronous wake-up commands, trigger the pure hardware timing control unit to execute a preset power-on timing process, and the asynchronous wake-up channel can detect the wake-up signal without the clock of the pure hardware timing control unit.

6. The interface according to claim 1, characterized in that, It also includes at least one status monitoring signal transmission channel, used for, but not limited to, receiving the power-on stable readiness status, hardware fault alarms and operating status heartbeat signals of the external processing unit in real time; the update delay of all status signals does not exceed one working clock cycle of the pure hardware timing control unit, and when a status signal fails, the interface enters a preset safe state by default.

7. The interface according to claim 1, characterized in that, It also includes at least one interactive control signal transmission channel, used for, but not limited to, entering the debugging state, issuing calculation tasks to external processing units, and receiving calculation results returned by external processing units; when the interactive control signal fails, the interface automatically disables the interactive function and enters the normal operation state.

8. The interface according to claim 1, characterized in that, It also includes at least one auxiliary control signal transmission channel, used, but not limited to, for external processing units to request active power off via a request-response handshake with a timeout mechanism, for pure hardware timing control units to send abnormal status notifications to external processing units, and for external processing units to send asynchronous task completion interrupts or abnormal interrupts to pure hardware timing control units; when the auxiliary control signal fails, the interface defaults to a preset safe state.

9. The interface according to claim 1, characterized in that, All signal transmission channels in the interface transmit pure hardware control information, conveying control commands only through high / low levels or edge transitions, and do not contain any protocol frame structure for data transmission. The effective level type and triggering method of each signal transmission channel in the interface can only be configured once before power-on using hardware jumpers, fuses, or fixed wiring methods during chip manufacturing. After configuration, the interface configuration will not change even if the state of the hardware jumpers or fuses is changed during operation.

10. A hardware module or electronic device, characterized in that, The hardware module or electronic device includes any one of claims 1 to 9, a general control interface for pure hardware timing management.