Semiconductor package substrates and their manufacturing methods, wiring substrates, and semiconductor packages

Abstract

A substrate for a semiconductor package has a side surface having an arithmetic mean roughness Ra of less than 450 nm. The side surface can be a polished surface. Alternatively, it can have a substrate body comprising an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer.

Description

Technical Field

[0001] This invention relates to a substrate for semiconductor packaging, a method for manufacturing the same, a wiring substrate, and a semiconductor package. Background Technology

[0002] In semiconductor packages, semiconductor chips are sometimes mounted on a wiring substrate having a core substrate formed of a substrate material and a multilayer wiring layer formed on the core substrate (e.g., Patent Document 1).

[0003] Previous technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-11156 Summary of the Invention

[0006] The technical problem to be solved by the invention

[0007] In semiconductor packages that house electronic components containing semiconductor chips mounted on a wiring board, cracks may occur on the substrate constituting the wiring board due to internal stress caused by the difference in thermal expansion coefficients accompanying thermal shock, physical impacts caused by contact with other objects, etc.

[0008] This invention relates to a substrate for semiconductor packaging that is less prone to cracking.

[0009] means for solving technical problems

[0010] The present invention includes the following.

[0011] [1] A substrate for a semiconductor package has a side surface having an arithmetic mean roughness Ra of less than 450 nm.

[0012] [2] The substrate for semiconductor packaging according to [1], wherein,

[0013] The side surface is a ground surface.

[0014] [3] The semiconductor package substrate according to [1] or [2] has an insulating substrate comprising an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer.

[0015] [4] The substrate for semiconductor packaging according to [3] further includes a protective resin portion disposed around the insulating substrate to form the side surface having an arithmetic mean roughness Ra of 450 nm or less.

[0016] [5] A substrate for a semiconductor package according to any one of [1] to [4], having a curved angle.

[0017] [6] A method for manufacturing a substrate for a semiconductor package, comprising the following steps:

[0018] Cutting substrates for multiple semiconductor packages from sheet substrate material; and

[0019] By smoothing the side surface of the substrate for the semiconductor package, the side surface is formed to have an arithmetic mean roughness Ra of less than 450 nm.

[0020] [7] A wiring substrate comprising a substrate for a semiconductor package as described in any one of [1] to [5].

[0021] [8] A semiconductor package comprising:

[0022] [7] The wiring board described above; and

[0023] Electronic components, mounted on the wiring substrate, include semiconductor chips.

[0024] Invention Effects

[0025] It can suppress the occurrence of cracks in the substrate of semiconductor packages. By suppressing the occurrence of cracks, the reliability of semiconductor packages can be improved.

[0026] In the process before semiconductor packages are mounted on electronic devices and other equipment, they may be subjected to physical impacts such as contact with other objects. For example, during the transport of substrate material, it may come into contact with manufacturing equipment and other substrate materials, and it may come into contact with the floor due to falling from a fixed position on the production line. By smoothing the sides of the substrate, it is possible to suppress the occurrence of cracks caused by these physical impacts.

[0027] Semiconductor packages may be subjected to thermal shock during processes prior to being mounted onto devices, such as heating used to cure resin layers laminated on a substrate and heating used to mount semiconductor chips. Furthermore, after the semiconductor package is mounted onto various devices, it may be heated by heat generated during device operation and by external gases. The substrate, wiring, building film, solder resist, and other resin materials constituting the semiconductor package, as well as the semiconductor chip, have different coefficients of thermal expansion. In particular, the substrate, sandwiched between wiring, resin materials, and the semiconductor chip, is prone to cracking at corners and other locations due to internal stresses from both sides. Smoothing the sides of the substrate can suppress cracking caused by thermal shock. Attached Figure Description

[0028] Figure 1 This is a plan view illustrating an example of a method for manufacturing a substrate for a semiconductor package.

[0029] Figure 2 This is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package.

[0030] Figure 3 This is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package.

[0031] Figure 4 This is a cross-sectional view showing an example of a method for manufacturing a substrate for a semiconductor package.

[0032] Figure 5 This is a plan view showing an example of a semiconductor package.

[0033] Figure 6 This is a cross-sectional view showing an example of a semiconductor package.

[0034] Figure 7 This is a plan view showing an example of a semiconductor package.

[0035] Figure 8 This is a cross-sectional view illustrating an example of a method for manufacturing substrate material.

[0036] Figure 9 This is a cross-sectional view illustrating an example of a method for manufacturing substrate material.

[0037] Figure 10 This is a cross-sectional view illustrating an example of a method for manufacturing substrate material. Detailed Implementation

[0038] This invention is not limited to the following examples. In this specification, "thickness direction" refers to the direction perpendicular to the two principal surfaces with the largest area in the sheet material.

[0039] Figure 1 , Figure 2 and Figure 3 This is a plan view or cross-sectional view schematically illustrating an example of a method for manufacturing a substrate for a semiconductor package. For example... Figure 1 As shown in the plan view, a sheet substrate material 100 is prepared for forming a substrate for a semiconductor package. The substrate material 100 may be an insulating substrate comprising an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer. The substrate material 100 may further have a metal foil disposed on one or both sides of the insulating substrate.

[0040] The width of the substrate material 100 can be 200–2650 mm. The thickness of the substrate material 100 can be 200–2000 μm.

[0041] Multiple semiconductor package substrates 20 are cut from a sheet-like substrate material 100. An example of a single cut semiconductor package substrate 20 is shown below. Figure 2The semiconductor package substrate 20 has a first surface S1, which is a rectangular main surface, a second surface S2, and a side surface S3 between the first surface S1 and the second surface S2. The side surface S3 of the semiconductor package substrate 20 has a relatively high roughness due to cutting by a blade or the like. Next, as... Figure 3 As shown, side surface S3 is smoothed. The smoothed side surface S3 has an arithmetic mean roughness Ra of 450 nm or less. The semiconductor package substrate 20 with the smoothed side surface S3 is less prone to stress concentration, and therefore less prone to cracking caused by thermal shock or physical impact. From the same point of view, the arithmetic mean roughness Ra of the smoothed side surface S3 can be 420 nm or less, 400 nm or less, 380 nm or less, 360 nm or less, 340 nm or less, or 320 nm or less. The arithmetic mean roughness Ra of the smoothed side surface S3 can be 100 nm or more, 150 nm or more, 200 nm or more, or 250 nm or more. When the substrate material 100 has an insulating substrate and a metal foil, the side surface of the semiconductor package substrate including the metal foil, or the side surface of the insulating substrate without the metal foil, i.e., the semiconductor package substrate, can have an arithmetic mean roughness Ra of 450 μm or less.

[0042] The arithmetic mean roughness Ra is a value calculated according to JIS B0601. Regarding the arithmetic mean roughness Ra, it is measured in the thickness direction of the substrate 20 for semiconductor packaging using a contact profilometer, for example, under the conditions of a measuring distance of 0.5 mm, a measuring speed of 100 μm, and a measuring load of 0.2 mg.

[0043] Methods for smoothing the side surface S3 can be, for example, chemical reaction-based methods or abrasion-based methods. Chemical reaction-based methods can, for example, involve immersing the side surface S3 in a solution of a material constituting the substrate. By immersion in the solution, unevenness and microcracks in the side surface S3 are removed, thereby smoothing the side surface S3. The solution can, for example, be a cleaning solution. Abrasion methods can, for example, involve contact with abrasive paper or a metal file, laser irradiation, or ion abrasion.

[0044] The entire side surface S3 of the semiconductor package substrate 20 can be smoothed. Alternatively, only the portions of the side surface S3 with larger unevenness due to bumps, microcracks, etc., can be smoothed. For example, only the portion of the side surface S3 near the corner of the substrate can be smoothed. Typically, the side surface S3 is smoothed to give the entire side surface S3 an arithmetic mean roughness of 450 nm or less. The side surface of the substrate material 100 before the semiconductor package substrate 20 is cut can also be smoothed.

[0045] Figure 4This is a cross-sectional view showing another example of a semiconductor package substrate having smoothed side surface S3. Figure 4 The semiconductor package substrate 20 shown has an insulating substrate 10 cut from a substrate material 100 and a protective resin portion 22 disposed around the insulating substrate 10, having side surfaces S3 with an arithmetic mean roughness Ra of 450 nm or less. The insulating substrate 10 may also include an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer. Metal foil may also be disposed on one or both sides of the insulating substrate 10, with the side surface including the insulating substrate and the metal foil covered by the protective resin portion 22.

[0046] The protective resin portion 22 may also be a cured product of a thermosetting or UV-curable resin composition. The protective resin portion 22 may also contain a thermoplastic resin. The thermosetting resin may have one or more reactive functional groups at the molecular ends or in the molecular chain. Examples of reactive functional groups include epoxy, hydroxyl, carboxyl, amino, amide, isocyanate, acryloyl, methacryloyl, vinyl, and maleic anhydride groups. The thermoplastic resin may be, for example, at least one selected from acrylic resins, polyamide resins, polyimide resins, and polyurethane resins.

[0047] The protective resin portion 22 is formed, for example, by a method including the steps of: applying a thermosetting or UV-curable resin composition to the side surface of the substrate body portion 21; and curing the applied resin composition. The method of applying the resin composition to the side surface of the substrate body portion 21 may be, for example, dispensing, laminating, spraying, or impregnating with the resin composition.

[0048] Each semiconductor package substrate obtained from substrate material 100 is used to form a wiring substrate for mounting semiconductor packages. When substrate material 100 has an insulating substrate and a metal foil, for example, wiring can be formed on the insulating substrate using a construction method or the like, utilizing the metal foil of substrate material 100 or after removing the metal foil, thereby manufacturing a semiconductor package wiring substrate with fine wiring. The semiconductor package substrate can be used as a core material for forming the semiconductor package wiring substrate.

[0049] Figure 5 This is a plan view showing an example of a semiconductor package. Figure 6 yes Figure 5 VI-VI line end face diagram. Figure 5 and Figure 6The semiconductor package 50 shown includes: a wiring substrate 30; an electronic component 40 mounted on the wiring substrate 30, including a semiconductor chip; and bumps 35 disposed on the side of the wiring substrate 30 opposite to the electronic component 40. The wiring substrate 30 has a semiconductor package substrate 20 with a core material obtained from a substrate material, and a construction layer 25 containing wiring disposed on a first surface S1 side and a second surface S2 side of the semiconductor package substrate 20. In the semiconductor package substrate 20, on the first surface S1 side of the semiconductor package substrate 20, the electronic component 40 is flip-chip connected to the wiring substrate 30 via a connection terminal 41. The space between the electronic component 40 (semiconductor chip) and the wiring substrate 30 can be filled with an underfill 42.

[0050] Figure 7 This is a plan view showing another example of a semiconductor package. Figure 7 In the semiconductor package shown, the wiring substrate 30 and the semiconductor package substrate 20 forming the wiring substrate 30 have four curved corners C. The curved corners also help suppress cracking. A curved corner represents a surface shape with a radius of curvature greater than 0 mm. From the viewpoint of easily ensuring the area for forming wiring, the radius of curvature of the curved corner C can be less than or equal to the length of the short side of the first face S1 of the rectangle, or less than 1 / 4 of the length of the short side of the first face S1 of the rectangle. From the viewpoint of more effectively dispersing internal stress, the radius of curvature of the curved corner C can be greater than or equal to 1 / 10 of the length of the short side of the first face S1 of the rectangle. The short side of the first face S1 of the rectangle is two of the four straight lines surrounding the first face S1. When the four straight lines surrounding the first face S1 are equal, the length of any one of the straight lines is considered the length of the short side.

[0051] The curved corner C of the substrate 20 for semiconductor packaging can be formed, for example, by applying external force through methods such as grinding and cutting. Examples of grinding include methods that use abrasive paper or a metal file to remove the corner portion. Examples of cutting include methods that use a diamond cutter, a cut saw, a milling cutter, a laser, a shear cutter, or a dicer.

[0052] The curved corner C of the semiconductor package substrate 20 can be formed by a chemical reaction method, such as immersing the corner portion of the semiconductor package substrate 20 in a chemical solution. The chemical solution can be, for example, a cleaning solution.

[0053] Figure 8 , Figure 9 and Figure 10 It means manufacturing Figure 1 A cross-sectional view illustrating an example of a method for using substrate materials. Figures 8-10The method shown includes the following steps: preparing a plurality of prepregs 1, each prepreg comprising a sheet-like inorganic fiber substrate 11 and a thermosetting resin composition 12 impregnated in the inorganic fiber substrate 11; and forming an insulating substrate 10 by heating and pressurizing a laminate 5 comprising the plurality of prepregs 1. Figure 9 The laminate 5 shown also has two metal foils 3 arranged to hold multiple prepregs 1 stacked from both sides. Through a molding process including pressing the laminate 5 while simultaneously raising the temperature of the laminate 5, a structure is formed as shown... Figure 10 The substrate material 100 shown has an insulating substrate 10 integrally formed from two or more prepregs 1 and metal foils 3 disposed on both sides of the insulating substrate 10. An insulating resin layer may be disposed between the metal foils 3 and the laminate 5. The thermosetting resin composition 12 is cured by heating the laminate 5 to form the insulating resin layer 12A of the substrate material 100.

[0054] The inorganic fiber substrate 11 can be, for example, a woven or nonwoven fabric containing inorganic fibers. The inorganic fibers constituting the inorganic fiber substrate 11 can be glass fibers, carbon fibers, or combinations thereof. The inorganic fiber substrate 11 can be a glass cloth made of glass fibers. The proportion of glass fibers in the inorganic fibers constituting the inorganic fiber substrate can be 80–100% by mass, 90–100% by mass, 95–100% by mass, or 99–100% by mass. The glass fibers can be, for example, E-glass, S-glass, or quartz glass. The thickness of the inorganic fiber substrate 11 can be 0.01–0.20 μm.

[0055] Thermosetting resin composition 12 comprises a thermosetting resin component. Thermosetting resin composition 12 may also comprise an inorganic filler. When thermosetting resin composition 12 comprises an inorganic filler, the portion of thermosetting resin composition 12 from which the inorganic filler has been removed can be considered as the resin component.

[0056] Thermosetting resin is a component that cures upon heating, and may include, for example, a thermosetting resin and a curing accelerator. Thermosetting resin is a compound that forms a cross-linked polymer upon heating, and typically has reactive functional groups that produce a cross-linking reaction. Reactive functional groups may be, for example, epoxy, hydroxyl, carboxyl, amino, amide, isocyanate, acryloyl, methacryloyl, vinyl, maleic anhydride, or combinations thereof. Thermosetting resin may contain epoxy resins having two or more epoxy groups, acrylate compounds having two or more (meth)acryloyl groups, or combinations thereof. Based on the total mass of the components other than the inorganic filler in the thermosetting resin composition 12, the content of the thermosetting resin may, for example, be 20 to 80% by mass.

[0057] Thermosetting resins may contain thermosetting elastomers having reactive functional groups. Examples of thermosetting elastomers include styrene-based elastomers, olefin-based elastomers, polyurethane-based elastomers, polyester-based elastomers, polyamide-based elastomers, acrylic elastomers, and silicone elastomers. Based on the total mass of the components other than inorganic fillers in the thermosetting resin composition, the content of the thermosetting elastomer may be, for example, 10–70% by mass or 20–60% by mass.

[0058] Examples of curing accelerators include peroxides, imidazole compounds, organophosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. These can be used alone or in combination of two or more. In the case of epoxy resins, the curing accelerator can be, for example, an imidazole compound. Based on the total mass of the components in the thermosetting resin composition excluding inorganic fillers, the content of the curing accelerator can be, for example, 0.1–10% by mass, 0.5–5% by mass, or 0.75–3% by mass.

[0059] The thermosetting resin composition 12 may further include a thermoplastic resin as a resin component. Based on the total mass of the components other than the inorganic filler in the thermosetting resin composition 12, the content of the thermoplastic resin may be, for example, 20 to 80% by mass.

[0060] The thermoplastic resin may be, for example, at least one selected from acrylic resins, polyamide resins, polyimide resins, and polyurethane resins. The thermoplastic resin may contain siloxane groups. For example, acrylic resins, polyamide resins, polyimide resins, or polyurethane resins may contain siloxane groups. Resins containing siloxane groups may be silicone resins. Polyimide resins containing siloxane groups may, for example, be polymers generated by the reaction of siloxane diamine with tetracarboxylic dianhydride, or polymers generated by the reaction of siloxane diamine with bismaleimide.

[0061] Thermoplastic resins may have one or more reactive functional groups at the molecular ends or in the molecular chain. Examples of reactive functional groups include epoxy, hydroxyl, carboxyl, amino, amide, isocyanate, acryloyl, methacryloyl, vinyl, and maleic anhydride groups.

[0062] The proportion of the thermosetting resin component in the thermosetting resin composition 12 relative to the mass of the thermosetting resin composition 12 can be 20% or more by mass, 30% or more by mass, or 40% or more by mass, or it can be less than 100% by mass or less than 80% by mass.

[0063] Examples of inorganic fillers include alumina, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, aluminum nitride, crystalline silica, amorphous silica, boron nitride, titanium dioxide, glass, iron oxide, ceramics, and carbon.

[0064] Based on the total mass of the components in the thermosetting resin composition 12 excluding the inorganic filler, the content of the inorganic filler may be, for example, 40 to 300 by mass.

[0065] The average particle size of the inorganic filler can be less than 10 μm or less than 5 μm, or greater than 0.001 μm. The maximum particle size of the filler can be less than 30 μm or less than 20 μm, or greater than 0.001 μm. The average and maximum particle sizes of the inorganic filler can be, for example, the maximum width in a two-dimensional image of the inorganic filler observed by a scanning electron microscope (SEM) as the particle size, and can be their average and maximum values.

[0066] Thermosetting resin compositions may further include other components as needed. Examples of other components include: adhesive aids, silane coupling agents, triazole compounds, tetraazole compounds, ion scavengers, antioxidants, and organic fillers.

[0067] Based on the mass of prepreg 1, the content of thermosetting resin composition 12 in prepreg 1 can be 40 to 80% by mass.

[0068] The width of the prepreg 1 can be, for example, 200 to 1300 mm. The thickness of the prepreg 1 can be, for example, 15 to 300 μm. If the thickness of the prepreg 1 is less than 15 μm, the flatness of the substrate tends to be relatively reduced due to the unevenness originating from the inorganic fiber substrate 11. If the thickness of the prepreg 1 is large, the warping of the substrate tends to be greater.

[0069] Prepreg 1 can be obtained, for example, by a method comprising the steps of: impregnating an inorganic fiber substrate 11 with a resin varnish comprising a thermosetting resin composition 12 and a solvent; and removing the solvent from the resin varnish.

[0070] From the viewpoint of conductivity, the metal foil 3 may contain copper, gold, silver, nickel, platinum, molybdenum, ruthenium, aluminum, tungsten, iron, titanium, chromium, or an alloy containing at least one of these metallic elements. The metal foil 3 may be copper foil or aluminum foil, or only copper foil. An insulating resin layer may be provided on the surface of the prepreg side of the metal foil 3.

[0071] The heating conditions used to form the substrate material 100 may include the following steps: raising the temperature of the laminate 5 to a molding temperature at a predetermined heating rate; and maintaining the temperature of the laminate 5 at the molding temperature. The molding temperature may, for example, be 100–300°C or 150–250°C. The heating and pressurization time at the molding temperature may, for example, be 0.1–5 hours.

[0072] During the heating of the laminate 5, the laminate 5 is typically under continuous pressure. The pressure applied to the laminate 5 can be, for example, 0.2 to 10 MPa.

[0073] The apparatus for heating and pressurizing the laminate 5 can be a hot press. The hot press can be, for example, a multi-stage press, a multi-stage vacuum press, a continuous forming machine, or an autoclave forming machine. When the apparatus for heating and pressurizing the laminate 5 is a hot press, a metal plate can be placed on the surface of the metal foil 3 opposite to the prepreg 1.

[0074] The dielectric constant of the insulating resin layer 12A in the cured thermosetting resin composition can be 3.0 or less or 2.8 or less at 10 GHz. The dielectric loss tangent of the insulating resin layer 12A at 10 GHz can be 0.005 or less. The dielectric constant can be measured using a test piece with a length of 60 mm, a width of 2 mm, and a thickness of 300 μm of the cured thermosetting resin composition. The test piece can be vacuum-dried at 30 °C for 6 hours before measurement. The dielectric loss tangent can be calculated based on the resonant frequency and the unloaded Q value obtained at 10 GHz. The measuring device can be a Keysight Technologies E8364B vector network analyzer, a Kanto Electronics Application Development Co., Ltd. CP531 (10 GHz resonator), and CPMAV2 (program). The measurement temperature can be 25 °C.

[0075] The glass transition temperature of the insulating resin layer 12A, which is a cured thermosetting resin composition, can be 120°C or higher, or 140°C or higher. The glass transition temperature of the insulating resin layer 12A can be 240°C or lower, or 220°C or lower.

[0076] A wiring substrate for a semiconductor package can be obtained, for example, by a method including the steps of forming wiring on a metal foil 3 of a semiconductor package substrate 20 obtained from substrate material 100 by a subtractive method; or forming wiring by a semi-additive method after removing the metal foil 3 as needed. If necessary, through-holes penetrating the insulating substrate 10 can be formed, and conductive through-holes filling the through-holes can be formed.

[0077] Alternatively, a build-up layer can be formed on the semiconductor package substrate 20, which serves as the core material. In this case, wiring for connection to the semiconductor chip can be formed on the build-up layer. The build-up layer can be formed by methods such as subtraction, full addition, semi-additive process (SAP), modified semi-additive process (m-SAP), or trenching.

[0078] The trench method includes the following steps: forming a building layer material or photosensitive insulating material layer with a pattern including trenches on a semiconductor package substrate 20, which serves as the core material; and filling the trenches with conductive material. The conductive material formed other than the trenches is removed by methods such as CMP or flying cut.

[0079] Semiconductor packages are manufactured by mounting electronic components containing semiconductor chips at predetermined positions on a wiring substrate prepared using a semiconductor package substrate 20.

[0080] Symbol Explanation

[0081] 1-Prepreg, 5-Laminate, 10-Insulating substrate, 11-Inorganic fiber substrate, 12-Thermosetting resin composition, 20-Substrate for semiconductor package, 22-Protective resin part, 30-Wire connection substrate, 40-Electronic component (semiconductor chip), 50-Semiconductor package, C-Bent angle, S1-First side, S2-Second side, S3-Side side.

Claims

1. A substrate for a semiconductor package having a side surface having an arithmetic mean roughness Ra of less than 450 nm.

2. The substrate for a semiconductor package according to claim 1, wherein, The side surface is a ground surface.

3. The substrate for a semiconductor package according to claim 1, comprising an insulating substrate, the insulating substrate comprising an insulating resin layer and an inorganic fiber substrate disposed within the insulating resin layer.

4. The substrate for a semiconductor package according to claim 3, further comprising a protective resin portion disposed around the insulating substrate, the protective resin portion forming the side surface having an arithmetic mean roughness Ra of 450 nm or less.

5. The substrate for a semiconductor package according to claim 1, wherein it has a curved angle.

6. A method for manufacturing a substrate for a semiconductor package, comprising the following steps: Cutting substrates for multiple semiconductor packages from sheet substrate material; and By smoothing the side surface of the substrate for the semiconductor package, the side surface is formed to have an arithmetic mean roughness Ra of less than 450 nm.

7. A wiring substrate comprising the semiconductor package substrate of claim 1.

8. A semiconductor package comprising: The wiring substrate according to claim 7; and Electronic components, mounted on the wiring substrate, include semiconductor chips.

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