Vector mask processing method and apparatus, electronic device, and medium

Abstract

This application provides a vector mask processing method, apparatus, electronic device, and medium, relating to the field of vector processor technology. The method includes: configuring at least one cache register and a status flag unit for each mask processing thread; responding to a vector mask generation instruction, updating the status flag bit of a target cache register in at least one cache register based on the mask readiness time of the vector mask generation instruction, so as to cache the generated vector mask in the target cache register according to the status flag bit and the mask caching time; responding to a vector mask read instruction, determining whether the target cache register is valid based on the status flag bit, so as to read the vector mask from the target cache register at the mask caching time if the target cache register is valid. This enables read instructions to directly read the vector mask from the cache register without waiting for write instructions to complete the write-back operation of the vector mask, thereby eliminating pipeline stalls caused by write-read dependency conflicts.

Description

Technical Field

[0001] This application relates to the field of vector processor technology, and in particular to a vector mask processing method, apparatus, electronic device and medium. Background Technology

[0002] In AI processors with a Very Long Instruction Word (VLIW) architecture, vector masks serve as core control data for operations such as vector conditional execution and predicate merging. The efficiency of their generation and retrieval directly affects the processor's instruction throughput.

[0003] In related technologies, write instructions that generate vector masks typically have multi-cycle pipeline delays (such as the final result being generated only after multiple execution stages). Subsequent read instructions that rely on this vector mask need to wait for the result to be written to the Vector Accumulator (VACC) for storage after the write-back stage before they can read the vector mask from the VCC and send it to the subsequent execution unit for execution.

[0004] However, the relevant technologies have the following problems: On the one hand, there is a read-after-write (RAW) dependency conflict, that is, the read instruction must wait for the write instruction to complete the write-back operation of the vector mask before it can read, during which the pipeline is frequently interrupted, which seriously restricts the instruction throughput; on the other hand, there is a VCC read port conflict, that is, in a multi-threaded parallel scenario, multiple read instructions accessing the VCC storage block at the same time will cause a storage block conflict, and all read mask instructions must access the VCC, which further exacerbates the read port contention. Summary of the Invention

[0005] This application provides a vector mask processing method, apparatus, electronic device, and medium to at least solve the problems in the related art of frequent pipeline pauses caused by write-after-read dependency conflicts and increased memory block conflicts caused by VCC read port contention.

[0006] A first aspect of this application provides a vector masking method, comprising: configuring at least one cache register and a status flag unit for each masking thread in at least one masking processing thread, wherein the at least one cache register is used to cache vector masks at different masking caching times, and the status flag unit is used to record status flag bits of the at least one cache register; in response to a vector masking generation instruction, determining a target cache register in the at least one cache register based on the masking ready time and masking caching time of the vector masking generation instruction, and updating the status flag bits of the target cache register in the status flag unit, so as to correspond to the status flag bits and the target cache register. The generated vector mask is cached in the target cache register at the mask caching time. The update of the status flag bit and the caching of the vector mask correspond to different processing stages of the vector mask generation instruction in the pipeline. In response to the vector mask read instruction, based on the status flag bit of at least one cache register in the status flag unit, it is determined whether at least one cache register is valid. If the status flag bit indicates that the corresponding target cache register is valid, the vector mask is read from the target cache register at the mask caching time corresponding to the target cache register. The validity judgment of at least one cache register and the reading of the vector mask correspond to different processing stages of the vector mask read instruction in the pipeline.

[0007] In some embodiments, in response to a vector mask generation instruction, a target cache register in at least one cache register is determined based on the mask ready time and mask caching time of the vector mask generation instruction, and the status flag bit of the target cache register in the status flag unit is updated, so as to cache the generated vector mask to the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. Before this, the method includes: determining whether the vector mask meets the caching conditions based on the vector mask generation instruction, so as to cache the vector mask to at least one cache register if the vector mask meets the caching conditions; wherein the caching conditions include at least one of the following: the storage address of the vector mask in the vector mask generation instruction is the target address in the vector register, and the vector mask generation instruction instructs to store the entire vector mask to the target address.

[0008] In some embodiments, determining a target cache register in at least one cache register based on the mask ready time and mask caching time of the vector mask generation instruction, and updating the status flag bit of the target cache register in the status flag unit, so as to cache the generated vector mask into the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register, includes: determining a target cache register for caching the vector mask in at least one cache register according to the size relationship between the mask ready time and the mask caching time of each cache register in at least one cache register; updating the status flag bit of the target cache register from a first value to a second value in the first stage of the vector mask generation instruction; and caching the vector mask into the target cache register at the mask caching time corresponding to the target cache register in the second stage of the vector mask generation instruction, wherein the first stage and the second stage are different processing stages of the vector mask generation instruction in the pipeline.

[0009] In some embodiments, in the second stage of the vector mask generation instruction, after the vector mask is cached in the target cache register at the mask cache time corresponding to the target cache register, the method includes: in the third stage of the vector mask generation instruction, storing the vector mask in the vector register, wherein the third stage and the second stage and the first stage are different processing stages of the vector mask generation instruction in the pipeline.

[0010] In some embodiments, in response to a vector mask read instruction, determining whether at least one cache register is valid based on the status flag bit of at least one cache register in the status flag unit, and reading the vector mask from the target cache register at the mask cache time corresponding to the target cache register when the status flag bit indicates that the corresponding target cache register is valid, includes: in response to the vector mask read instruction, in the fourth stage of the vector mask read instruction, determining the status flag bit of at least one cache register based on the status flag unit; if the status flag bit of the first cache register is a second value, determining that the first cache register is valid and determining the first cache register as the target cache register, the first cache register being any one of the at least one cache registers; in the fifth stage of the vector mask read instruction, reading the vector mask from the target cache register at the mask cache time corresponding to the target cache register, the fourth stage and the fifth stage being different processing stages of the vector mask read instruction in the pipeline.

[0011] In some embodiments, after determining whether at least one cache register is valid based on the status flag bit of at least one cache register in the status flag unit, the method includes: if at least one cache register is invalid, reading a vector mask from a vector register.

[0012] In some embodiments, the method further includes: in response to a vector mask base address update instruction, updating the status flag bit to a first value if the status flag bit of at least one cache register in the status flag unit is a second value.

[0013] A second aspect of this application provides a vector masking processing apparatus, the apparatus comprising: A configuration unit is used to configure at least one cache register and a status flag unit for each mask processing thread in at least one mask processing thread. The at least one cache register is used to cache vector masks at different mask caching times, and the status flag unit is used to record the status flag bits of at least one cache register. The caching unit is used to respond to the vector mask generation instruction, determine the target cache register in at least one cache register based on the mask ready time and the mask caching time of the vector mask generation instruction, and update the status flag bit of the target cache register in the status flag unit so as to cache the generated vector mask to the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. The update of the status flag bit and the caching of the vector mask correspond to different processing stages of the vector mask generation instruction in the pipeline. The read unit is used to respond to the vector mask read instruction, determine whether at least one cache register is valid based on the status flag bit of at least one cache register in the status flag unit, and read the vector mask from the target cache register at the mask cache time corresponding to the target cache register if the status flag bit indicates that the corresponding target cache register is valid. The validity determination of at least one cache register and the reading of the vector mask correspond to different processing stages of the vector mask read instruction in the pipeline.

[0014] A third aspect of this application provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this application.

[0015] A fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this application.

[0016] In summary, according to the vector mask processing method proposed in this application, at least one cache register and a status flag unit are configured for each mask processing thread in at least one mask processing thread. The at least one cache register is used to cache vector masks at different mask caching times, and the status flag unit is used to record the status flag bits of the at least one cache register. In response to a vector mask generation instruction, based on the mask ready time and mask caching time of the vector mask generation instruction, a target cache register in the at least one cache register is determined, and the status flag bits of the target cache register in the status flag unit are updated so that the generated vector mask is cached in the target cache register according to the status flag bits and the mask caching time corresponding to the target cache register. In response to a vector mask read instruction, based on the status flag bits of the at least one cache register in the status flag unit, it is determined whether the at least one cache register is valid, and if the status flag bits indicate that the corresponding target cache register is valid, the vector mask is read from the target cache register at the mask caching time corresponding to the target cache register. This approach caches the vector mask immediately after generation in the cache register, rather than waiting for it to be written to VCC during the write-back phase. Subsequent read instructions can directly read the vector mask from the cache register without waiting for the write instruction to complete the write-back operation, thus eliminating pipeline stalls caused by write-after-read dependency conflicts. Simultaneously, by reading the vector mask from the cache register, read instructions bypass the VCC read port access, reducing memory block conflicts in multi-threaded parallel scenarios and improving the actual throughput of the parallel pipeline.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0019] Figure 1 A flowchart illustrating the first vector masking method provided in this application embodiment; Figure 2 A flowchart illustrating the second vector masking method provided in this application embodiment; Figure 3 A schematic diagram illustrating an exemplary vector mask read / write operation without a cached register, provided in an embodiment of this application; Figure 4 A schematic diagram illustrating a first exemplary vector mask read / write with a cache register provided in this application embodiment; Figure 5 A schematic diagram of a second exemplary vector mask read / write with a cache register provided in this application embodiment. Figure 6 A schematic diagram of a vector mask processing device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0021] In VLIW architecture AI processors, vector masks serve as core control data for operations such as vector conditional execution and predicate merging, and their generation and retrieval efficiency directly affects the processor's instruction throughput.

[0022] In related technologies, write instructions that generate vector masks typically have multi-cycle pipeline delays (such as the final result being generated only after multiple execution stages). Subsequent read instructions that rely on this vector mask need to wait for the result to be written to the Vector Accumulator (VACC) for storage after the write-back stage before they can read the vector mask from the VCC and send it to the subsequent execution unit for execution.

[0023] However, the related technologies have the following problems: On the one hand, there is a RAW dependency conflict, that is, read instructions that depend on vector masks must wait for the write instructions to complete the write-back operation before they can be read from the issue stage. During this period, a large number of wait cycles are inserted into the pipeline, causing frequent pipeline pauses and severely restricting the processor's instruction throughput. On the other hand, there is a VCC memory read port conflict, that is, in scenarios with multiple vector processing threads or multiple pipelines running in parallel, multiple read instructions may simultaneously access different memory banks of the VCC or even the same memory bank, resulting in bank conflicts, causing additional pipeline pauses. Moreover, all vector mask read instructions need to access the VCC, further exacerbating read port contention.

[0024] To address the aforementioned issues, this application proposes a vector mask processing method. By configuring cache registers and status flag units for each mask processing thread, write instructions pre-set the status flags in the cache registers to a valid state based on the mask readiness time. Read instructions directly read the vector mask from the cache registers when the status flags are valid, without waiting for the write instructions to complete the write-back operation, thus eliminating pipeline stalls caused by write-read dependency conflicts. Simultaneously, by reading the vector mask from the cache registers, read instructions bypass VCC memory read access, reducing access contention for VCC read ports in multi-threaded parallel scenarios, thereby lowering the probability of memory block conflicts and improving the actual throughput of the parallel pipeline. Furthermore, this application requires only a small number of cache registers and corresponding status flags for each mask processing thread, resulting in low hardware overhead, timing friendliness, and simple implementation.

[0025] The vector masking method provided in this application will be described in detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a flowchart illustrating the first vector masking method provided in an embodiment of this application. Figure 1 As shown, the vector masking processing method includes steps 101-103.

[0027] Step 101: Configure at least one cache register and status flag unit for each mask processing thread in at least one mask processing thread.

[0028] In the embodiments of this application, the mask processing thread refers to the parallel execution unit in the vector processor responsible for performing vector mask-related operations, and each thread independently processes its own data stream.

[0029] A cache register is a fast storage unit in the pipeline used to temporarily store vector masks, with read / write latency much lower than that of VCC (vector accumulator). The pipeline refers to the instruction pipeline in a vector processor used to execute vector instructions, which divides the execution process of an instruction into multiple consecutive processing stages (such as instruction issue, execution, and write-back stages). Different stages of different instructions are executed concurrently to improve instruction throughput.

[0030] During the hardware design phase, this application allocates an independent set of cache registers (taking two cache registers, VM_FF0 and VM_FF1, as an example) and corresponding status flag units for each mask processing thread. The width of each cache register is the same as the width of the vector mask. The read / write operations of cache register VM_FF0 are fixed at execution cycle EXm, and the read / write operations of cache register VM_FF1 are fixed at execution cycle EXn, where EXm and EXn correspond to the mask caching time, and EXm is earlier than EXn (i.e., EXm < EXn). The two cache registers correspond to different instruction latency types: VM_FF0 is used to cache the vector mask generated by short-latency write instructions, and VM_FF1 is used to cache the vector mask generated by long-latency write instructions. The cache registers and status flag units of each mask processing thread are independent and do not interfere with each other, thereby supporting accelerated read / write operations of vector masks in multi-threaded parallel scenarios.

[0031] The status flag unit is a single-bit recorder, a single-bit storage unit used to record the valid status of each cache register. Each cache register corresponds to a status flag bit (marking whether each cache register is valid; only when a cache register is valid can subsequent read instructions read the vector mask from that cache register). The status flag bit is set or cleared by the write control logic during the instruction issue phase and read by the read control logic during the instruction decoding phase. The update of the status flag bit does not depend on the actual writing or reading of data in the cache register, but is completed in advance by the write control logic based on the instruction issue and condition judgment. This achieves "pre-set trust," allowing read instructions to determine the data source in advance based on the status flag bit before the data is written to the cache register, without waiting for the data to be actually ready before making a judgment, thus avoiding selector delays on the critical path of the pipeline.

[0032] Understandably, cache registers do not require address decoding and have extremely low access latency (approximately one cycle); VCCs, implemented using a Static Random Access Memory (SRAM) array, are located at the back end of the memory hierarchy, and access requires address decoding, bit line charge / discharge operations, resulting in higher latency (multiple cycles). This application "migrates" the vector mask from the VCC to the cache register, enabling read instructions to retrieve data at register-level speeds, fundamentally shortening the data retrieval path.

[0033] Step 102: In response to the vector mask generation instruction, based on the mask ready time and mask caching time of the vector mask generation instruction, determine the target cache register in at least one cache register, and update the status flag bit of the target cache register in the status flag unit, so as to cache the generated vector mask into the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register.

[0034] In the embodiments of this application, the vector mask generation instruction refers to the write instruction that generates a vector mask, such as a vector comparison instruction or a vector logic operation instruction. After the instruction is executed, a complete vector mask will be generated.

[0035] The mask readiness time refers to the point in time after the vector mask generation instruction has been executed through multiple pipeline cycles and the vector mask is generated and ready to be written into VCC. The readiness time varies for different instructions.

[0036] When the vector mask generation instruction enters the issue phase (EX1) of the pipeline, the write control logic first decodes the instruction to obtain its mask ready time (EXw). Based on the relationship between EXw and the mask cache times (e.g., EXm, EXn) of each cache register, the write control logic determines which cache register (i.e., the target cache register) to store the vector mask generated by this instruction. Subsequently, during the instruction issue phase (EX1), the write control logic sets the status flag of the target cache register in the status flag unit to a valid state (e.g., updating from 0 to 1). At this time, the mask data has not yet been generated, but the valid bit has been set in advance, allowing subsequent read instructions to determine the data source in advance. After the write instruction completes its calculation during the execution phase, the generated vector mask data is written to the target cache register at the mask cache time (EXm or EXn). Simultaneously, the instruction finally writes the generated vector mask to VCC during the write-back phase to complete a persistent backup.

[0037] Step 103: In response to the vector mask read instruction, determine whether at least one cache register is valid based on the status flag bit of at least one cache register in the status flag unit, and if the status flag bit indicates that the corresponding target cache register is valid, read the vector mask from the target cache register at the mask cache time corresponding to the target cache register.

[0038] In the embodiments of this application, a vector mask reading instruction refers to a subsequent instruction that requires the use of a vector mask as control data. For example, a vector addition instruction determines which elements to perform the operation based on the mask, and a vector selection instruction selects data from two source vectors based on the mask.

[0039] When the status flag bit of the cache register is 1, the cache register is valid, indicating that the data cached in the cache register is valid and can be read.

[0040] When a vector mask read instruction enters the decoding stage of the pipeline, the read control logic reads the status flag bits of the corresponding cache registers in the status flag unit to determine whether the cache registers are valid. If the cache registers are valid, the read instruction continues normally in the pipeline, reading the vector mask data from the cache register at the corresponding cache register's mask cache time (EXm or EXn) (corresponding to the execution stage). If all cache registers are invalid, the read instruction cannot obtain data from the cache registers and falls back to the traditional path, i.e., the pipeline pauses, waiting for the vector mask generation instruction to complete the write-back operation before reading the vector mask from VCC.

[0041] In summary, according to the vector mask processing method provided in this application, at least one cache register and a status flag unit are configured for each mask processing thread in at least one mask processing thread. In response to a vector mask generation instruction, based on the mask readiness time and mask caching time of the vector mask generation instruction, a target cache register in at least one cache register is determined, and the status flag bit of the target cache register in the status flag unit is updated, so that the generated vector mask is cached in the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. In response to a vector mask read instruction, based on the status flag bit of at least one cache register in the status flag unit, it is determined whether at least one cache register is valid, and if the status flag bit indicates that the corresponding target cache register is valid, the vector mask is read from the target cache register at the mask caching time corresponding to the target cache register. This achieves that the vector mask is cached in the cache register immediately after generation, instead of waiting for the write-back stage to write to VCC before it can be read. Subsequent read instructions can directly read the vector mask from the cache register without waiting for the write instruction to complete the write-back operation, thereby eliminating pipeline stalls caused by write-after-read dependency conflicts. Meanwhile, the read instruction bypasses the VCC read port access by reading the vector mask from the cache register, reducing memory block conflicts in multi-threaded parallel scenarios and improving the actual throughput of the parallel pipeline.

[0042] Figure 2 This is a flowchart illustrating the second vector masking method provided in this application embodiment. Figure 2 based on Figure 1 The illustrated embodiment further defines steps 102 and 103. Figure 2 In the illustrated embodiment, step 102 includes steps 201, 202, 203, 204, and 205, and step 103 includes steps 206, 207, and 208. Figure 2 As shown, the method includes the following steps: Step 201: In response to the vector mask generation instruction, determine whether the vector mask meets the caching conditions based on the vector mask generation instruction.

[0043] In the embodiments of this application, the caching condition refers to the determination condition for whether the mask data of the vector mask generation instruction is allowed to be cached in the cache register. In this application, the caching condition includes two sub-conditions: first, the storage address of the vector mask in the instruction is the target address (denoted as the base address VCC0, which is the VCC address unit specified by the Vector Address Base (VAB) and used to store the physical address of the vector mask); second, the instruction indicates that the vector mask is fully stored in the target address, that is, the complete vector mask is written (the write enable signal is all 1s), rather than only updating some bits (i.e., partial writing, the write enable signal is not all 1s).

[0044] When both of the above sub-conditions are met simultaneously, the vector mask generation instruction is determined to meet the caching condition, that is, the vector mask can be cached in the cache register.

[0045] Step 202: If the vector mask satisfies the caching condition, determine the target cache register for caching the vector mask in at least one cache register according to the size relationship between the mask ready time and the mask caching time of each cache register in at least one cache register.

[0046] In the embodiments of this application, "size relationship" refers to the order on the timeline between the mask ready time (EXw) and the mask caching time of each cache register (such as EXm, EXn, where EXm < EXn). Based on this, this application divides the write instruction (i.e. the vector mask generation instruction) into short-delay instructions and long-delay instructions so that the generated vector mask can be cached in different cache registers respectively.

[0047] In one example, the write control logic compares the mask ready time EXw with the mask cache times of each cache register (such as EXm and EXn). If EXw is earlier than EXm (i.e., EXw < EXm), it indicates that the write instruction is a short-delay instruction, and the cache register corresponding to EXm (such as VM_FF0) is selected as the target cache register; if EXw is later than EXn (i.e., EXw > EXn), it indicates that the write instruction is a long-delay instruction, and the cache register corresponding to EXn (such as VM_FF1) is selected as the target cache register.

[0048] Step 203: In the first stage of the vector mask generation instruction, the status flag bit of the target cache register is updated from the first value to the second value.

[0049] In the embodiments of this application, the first stage refers to the emission stage (EX1) of the vector mask generation instruction in the pipeline. Updating the status flag bit of the target buffer register from a first value (e.g., 0) to a second value (1) indicates that the target buffer register is set to an active state.

[0050] Specifically, during the issue phase of the vector mask generation instruction (EX1), the write control logic sets the status flag of the target buffer register to 1. At this time, the vector mask generation instruction has just entered the pipeline, and the vector mask data has not yet begun to be calculated (before the execution phase), but the status flag has already been set to a valid state. This "pre-set trust" mechanism allows subsequent vector mask read instructions to see this valid flag during the decoding phase (in the same cycle as EX1 or slightly later), thus making a decision in advance to read data from the target buffer register without waiting for the data to be actually written to the buffer register before making a judgment, avoiding selector delays on the critical path of the pipeline. At the same time, this application ensures through the "pre-set trust" mechanism that the data has already been written to the target buffer register when the read instruction actually reads the vector mask.

[0051] Optionally, all updates to the status flags occur in the first phase (i.e., the issue phase EX1). The write control logic completes the setting and clearing of all status flags within the EX1 cycle. For example, when an instruction to write to the cache register is issued in EX1, the corresponding valid bit of the cache register is immediately set to 1 (even if the data has not yet been actually written to the cache register). By updating the status flags during the instruction issue phase rather than the actual data write phase, subsequent vector mask read instructions can read the valid flag during the decoding phase (in the same cycle as EX1), thereby determining the data source one or more cycles in advance and achieving zero-pause execution of read instructions.

[0052] When an instruction that meets the clear / invalidate condition is issued in EX1, the valid bits of the corresponding cache registers are immediately cleared to 0. For example, when an instruction that modifies the vector mask base address (i.e., modifies the VAB register, i.e., modifies the VCC0 address) is issued, the valid bits of all cache registers are unconditionally cleared to zero (i.e., updated from the second value to the first value). After the valid bits are cleared, the old vector mask data stored in the cache registers is not cleared, but because the status flag is invalid, subsequent read instructions will not access this cache register, thus ensuring data consistency. The data stored in the vector accumulator VCC0 is unaffected because after the base address changes, the logical address of VCC0 points to a different physical storage location, and the old data is no longer accessed by VCC0.

[0053] Step 204: In the second stage of the vector mask generation instruction, the vector mask is cached in the target cache register at the mask cache time corresponding to the target cache register.

[0054] In the embodiments of this application, the second stage refers to the execution stage of the vector mask generation instruction in the pipeline, that is, the stage when the vector mask calculation is completed. The write control logic will write the vector mask into the target cache register in this stage.

[0055] Specifically, after the vector mask generation instruction completes its calculation during the execution phase, the calculated vector mask data is written to the target cache register at the corresponding mask cache time (EXm if the target cache register is VM_FF0; EXn if the target cache register is VM_FF1). After writing, the target cache register stores valid vector mask data, and subsequent read instructions can read the vector mask data from the target cache at this mask cache time.

[0056] It should be noted that the time of reading the target cache must be strictly aligned with the time of writing to the target cache (for example, writing to VM_FF0 from EXm must be done after EXm is read, and cannot be done across cycles).

[0057] Optionally, for short-delay instructions (where the mask readiness time EXw is earlier than or equal to the mask buffer time EXm), the vector mask is written to VM_FF0 in the EXm cycle and simultaneously written to VM_FF1 in the EXn cycle via clocking, ensuring that data can be read from the buffer register regardless of whether the read instruction falls in EXm or EXn. For long-delay instructions (where EXw is later than EXn), data is written to VM_FF1 only in the EXn cycle.

[0058] Through the above mechanism, when the read instruction arrives at the target cache register at the corresponding mask cache time, the data has already been written. The read instruction can read the newly written vector mask data from the target cache register in the same cycle, realizing read-write cycle alignment and uninterrupted reading.

[0059] Step 205: In the third stage of the vector mask generation instruction, the vector mask is stored in the vector register.

[0060] In the embodiments of this application, the third stage refers to the write-back stage of the vector mask generation instruction in the pipeline. The vector register refers to VCC (vector accumulator), which is the final storage location of the vector mask (e.g., VCC0).

[0061] During the write-back phase of the vector mask generation instruction, the vector mask data is written to VCC to complete a persistent backup. This operation occurs after the data is cached to the cache register, and regardless of whether it is written to the cache register, the vector mask will eventually be written to the actual vector mask memory (i.e., the vector register), ensuring that even if the data in the cache register is overwritten by subsequent instructions, the complete mask data is still retained in VCC.

[0062] Step 206: In response to the vector mask read instruction, in the fourth stage of the vector mask read instruction, at least one status flag bit of a buffer register is determined based on the status flag unit.

[0063] In the embodiments of this application, the fourth stage refers to the decoding stage of the vector mask read instruction in the pipeline.

[0064] When a vector mask read instruction enters the decoding stage of the pipeline, the read control logic reads the status flag unit and checks the status flag bits of the corresponding mask processing thread and its respective cache registers to determine whether each cache register is valid. At this point, the read instruction only makes a decision and does not actually read the data.

[0065] Step 207: If the status flag bit of the first cache register is the second value, determine that the first cache register is valid and determine the first cache register as the target cache register.

[0066] In embodiments of this application, the second value represents a valid state (e.g., 1). The first cache register is any one of at least one cache registers.

[0067] If the status flag of a cache register (such as VM_FF0) is the second value (1), then the cache register (i.e., the target cache register) is determined to be valid, and subsequent read instructions will read the vector mask from that cache register. If the status flag of all cache registers is the first value (0), then all cache registers are invalid, and read instructions will fall back to reading from VCC.

[0068] Step 208: In the fifth stage of the vector mask read instruction, the vector mask is read from the target cache register at the mask cache time corresponding to the target cache register.

[0069] In the embodiments of this application, the fifth stage refers to the execution stage of the vector mask reading instruction in the pipeline, that is, the stage of actually reading the mask data.

[0070] Specifically, during the execution phase of the vector mask read instruction, after determining the valid target cache register in step 207, the vector mask data is read from the cache register at the corresponding mask cache time (EXm or EXn) and sent to the subsequent execution unit. At this time, the write instruction has already written the data to the cache register at the same time or earlier, and the read instruction can complete the reading in the same cycle, achieving zero pause.

[0071] If a read instruction needs to read from VCC (where all cache registers are invalid), it must wait for the write instruction to complete the write-back operation during the write-back phase and then read in the next cycle after the write-back operation, which will introduce a pipeline pause.

[0072] Optionally, to ensure the correct operation of the single-bit status flag in the aforementioned buffer register and status flag unit, the following design constraints are adopted: Constraint 1: All instructions that cache vector masks to cache registers are issued sequentially during the issue phase (EX1), so that the writing order of multiple write instructions to the same cache register is consistent with the issue order.

[0073] Constraint 2: If a single instruction packet contains two instructions that read from and write to the same cache register, the read instruction must be issued before the write instruction to avoid data uncertainty caused by read-write contention within the same cycle.

[0074] Under the two constraints mentioned above, there will be no read-after-write (RAW) hazards between instructions that require additional interval information. Therefore, a single-bit status flag is sufficient to ensure the correctness of cached data. There is no need to maintain multiple bits of status information or multiple entries of historical records for each cache register, which further reduces hardware overhead.

[0075] Furthermore, to aid in better understanding, this application provides a comparison of the effects of mechanisms with and without cached registers, such as... Figure 3 , Figure 4 and Figure 5 As shown, where, Figure 3 This application provides an exemplary schematic diagram of vector mask read / write without buffered registers, as shown in the embodiments of this application. Figure 4 This is a schematic diagram illustrating a first exemplary vector mask read / write operation with a cache register, provided in an embodiment of this application. Figure 5 This is a schematic diagram of a second exemplary vector mask read / write with a cache register provided in the embodiments of this application. In the above figure, EX2 corresponds to the moment of reading VCC0, and ID1 corresponds to the fourth stage (i.e., the decoding stage) of this application.

[0076] Reference Figure 3 Corresponding to the traditional pause scheme, write instructions (corresponding to) Figure 3 The write instruction (VA0, i.e., VCC0) in the code only produces a result after multiple cycles such as EX1, EX2, and EXw. The generated vector mask is written to VCC0 during EXw. The read instruction detects a dependency after EX1 is issued and needs to pause for EXw-2 cycles to wait for data to be written to VCC0 before it can read (the actual read time is...). Figure 3 In EX2), the production line efficiency is severely reduced.

[0077] Reference Figure 4For the scenario where EXw < EXm (short delay instruction), at time EX1, the write instruction first sets the valid bit of the buffer register VM_FF0 corresponding to EXm. After generating the vector mask, the write instruction writes the vector mask into the buffer register VM_FF0 in EXm. The read instruction detects that VM_FF0 is valid after EX1 is issued, and without any pause, the pipeline proceeds normally to EXm. In EXm, the vector mask is directly read from VM_FF0, achieving a non-pause read. At the same time, VM_FF1 is also written in the EXn cycle through time-stamping, so that data can be read from the buffer register regardless of whether the read instruction falls in EXm or EXn.

[0078] Reference Figure 5 For the scenario of EXw > EXn (long delay instruction), at EX1, the write instruction first sets the valid bit of the cache register VM_FF1 corresponding to EXn. After the write instruction generates the vector mask, it writes the vector mask into the cache register VM_FF1 at EXn. The read instruction detects that VM_FF0 is valid after EX1 is issued, so there is no need to pause. The pipeline proceeds normally to EXn, and the vector mask is read directly from VM_FF1 at EXn, achieving uninterrupted reading.

[0079] In summary, this application configures cache registers and status flag units for each mask processing thread. Write instructions enable the cache registers in advance during the issue phase, and read instructions directly read the vector mask from the cache registers based on the status flags while the cache registers are valid, without waiting for the write instructions to complete the write-back operation. For AI workloads involving frequent read / write operations of vector masks, such as sparse attention and conditional loops, this significantly reduces pipeline stalls caused by write-after-read dependency conflicts. Simultaneously, by reading the vector mask from the cache registers, read instructions bypass VCC read port access, reducing memory block conflicts in multi-threaded parallel scenarios and improving the actual throughput of the parallel pipeline. Furthermore, this application requires only a small number of cache registers and corresponding status flags for each mask processing thread, resulting in low hardware overhead and simple implementation, making it highly applicable.

[0080] To implement the above embodiments, this application also provides a vector mask processing apparatus. Figure 6 This is a schematic diagram of the structure of a vector mask processing device 300 provided in an embodiment of this application. Figure 6 As shown, the device includes: Configuration unit 310 is used to configure at least one cache register and status flag unit for each mask processing thread in at least one mask processing thread. At least one cache register is used to cache vector masks at different mask caching times, and the status flag unit is used to record the status flag bits of at least one cache register. The cache unit 320 is used to respond to the vector mask generation instruction, determine the target cache register in at least one cache register based on the mask ready time and the mask cache time of the vector mask generation instruction, and update the status flag bit of the target cache register in the status flag unit so as to cache the generated vector mask to the target cache register according to the status flag bit and the mask cache time corresponding to the target cache register. The update of the status flag bit and the caching of the vector mask correspond to different processing stages of the vector mask generation instruction in the pipeline. The read unit 330 is used to respond to the vector mask read instruction, determine whether at least one cache register is valid based on the status flag bit of at least one cache register in the status flag unit, and read the vector mask from the target cache register at the mask cache time corresponding to the target cache register if the status flag bit indicates that the corresponding target cache register is valid. The validity determination of at least one cache register and the reading of the vector mask correspond to different processing stages of the vector mask read instruction in the pipeline.

[0081] In some embodiments, the apparatus includes: a determination unit, configured to, in response to a vector mask generation instruction, determine a target cache register in at least one cache register based on a mask ready time and a mask caching time in the vector mask generation instruction, and update a status flag bit in the target cache register in a status flag unit, so as to cache the generated vector mask to the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. Prior to this, the apparatus determines whether the vector mask meets caching conditions based on the vector mask generation instruction, so as to cache the vector mask to at least one cache register if the vector mask meets the caching conditions; wherein the caching conditions include at least one of the following: the storage address of the vector mask in the vector mask generation instruction is the target address in the vector register; or the vector mask generation instruction instructs the vector mask to be fully stored in the target address.

[0082] In some embodiments, the caching unit 320 is configured to: determine a target cache register for caching a vector mask in at least one cache register based on the size relationship between the mask ready time and the mask caching time of each cache register in at least one cache register; update the status flag bit of the target cache register from a first value to a second value in the first stage of the vector mask generation instruction; and cache the vector mask into the target cache register at the mask caching time corresponding to the target cache register in the second stage of the vector mask generation instruction, wherein the first stage and the second stage are different processing stages of the vector mask generation instruction in the pipeline.

[0083] In some embodiments, the cache unit 320 is configured to: store the vector mask into a vector register in the third stage of the vector mask generation instruction, wherein the third stage and the second stage are different processing stages of the vector mask generation instruction in the pipeline compared with the first stage.

[0084] In some embodiments, the read unit 330 is configured to: respond to a vector mask read instruction, in the fourth stage of the vector mask read instruction, determine the status flag bit of at least one cache register based on the status flag unit; if the status flag bit of the first cache register is a second value, determine that the first cache register is valid and determine the first cache register as the target cache register, wherein the first cache register is any one of the at least one cache registers; in the fifth stage of the vector mask read instruction, read the vector mask from the target cache register at the mask cache time corresponding to the target cache register, wherein the fourth stage and the fifth stage are different processing stages of the vector mask read instruction in the pipeline.

[0085] In some embodiments, the read unit 330 is configured to: read a vector mask from a vector register when at least one cache register is invalid.

[0086] In some embodiments, the apparatus further includes an update unit for: updating a status flag bit to a first value when, in response to a vector mask base address update instruction, at least one status flag bit in a cache register of the status flag unit is a second value.

[0087] Since the apparatus provided in this application corresponds to the methods provided in the above-mentioned embodiments, the implementation of the methods is also applicable to the apparatus provided in this embodiment, and will not be described in detail in this embodiment.

[0088] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0089] Figure 7 This is a block diagram illustrating an electronic device 500 for implementing the above-described vector masking processing method according to an exemplary embodiment.

[0090] Reference Figure 7The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0091] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0092] Memory 404 is configured to store various types of data to support the operation of electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0093] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0094] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0095] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0096] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0097] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0098] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0099] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0100] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0101] Embodiments of this application also propose a chip including one or more interface circuits and one or more processors; the interface circuits are used to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory, and when the processor executes the computer instructions, it causes the electronic device to perform the vector masking processing method described in the above embodiments of this application.

[0102] Embodiments of this application also propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the vector masking processing method described in the above embodiments of this application.

[0103] Embodiments of this application also propose a computer program product, including a computer program that is executed by a processor using the vector masking processing method described in the above embodiments of this application.

[0104] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0106] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0107] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0108] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0109] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0110] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0111] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A vector masking processing method, characterized in that, The method includes: At least one cache register and a status flag unit are configured for each mask processing thread in at least one mask processing thread. The at least one cache register is used to cache vector masks at different mask caching times, and the status flag unit is used to record the status flag bits of the at least one cache register. In response to a vector mask generation instruction, based on the mask ready time of the vector mask generation instruction and the mask caching time, a target cache register in the at least one cache register is determined, and the status flag bit of the target cache register in the status flag unit is updated, so that the generated vector mask is cached in the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. The update of the status flag bit and the caching of the vector mask correspond to different processing stages of the vector mask generation instruction in the pipeline. In response to a vector mask read instruction, based on the status flag bits of the at least one cache register in the status flag unit, it is determined whether the at least one cache register is valid. If the status flag bits indicate that the corresponding target cache register is valid, the vector mask is read from the target cache register at the mask cache time corresponding to the target cache register. The validity determination of the at least one cache register and the reading of the vector mask correspond to different processing stages of the vector mask read instruction in the pipeline.

2. The method according to claim 1, characterized in that, In response to a vector mask generation instruction, based on the mask ready time of the vector mask generation instruction and the mask caching time, a target cache register in the at least one cache register is determined, and the status flag bit of the target cache register in the status flag unit is updated, so that the generated vector mask is cached in the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. Prior to this, the method includes: Based on the vector mask generation instruction, it is determined whether the vector mask meets the caching conditions, so that if the vector mask meets the caching conditions, the vector mask is cached in the at least one cache register; The caching conditions include at least one of the following: the storage address of the vector mask in the vector mask generation instruction is the target address in the vector register; or the vector mask generation instruction instructs the vector mask to be fully stored in the target address.

3. The method according to claim 1, characterized in that, The step of determining the target cache register in the at least one cache register based on the mask ready time of the vector mask generation instruction and the mask cache time, and updating the status flag bit of the target cache register in the status flag unit, so as to cache the generated vector mask into the target cache register according to the status flag bit and the mask cache time corresponding to the target cache register, includes: Based on the size relationship between the mask ready time and the mask caching time of each cache register in at least one cache register, determine the target cache register in the at least one cache register used to cache the vector mask; In the first stage of the vector mask generation instruction, the status flag bit of the target cache register is updated from a first value to a second value; In the second stage of the vector mask generation instruction, the vector mask is cached in the target cache register at the mask cache time corresponding to the target cache register. The first stage and the second stage are different processing stages of the vector mask generation instruction in the pipeline.

4. The method according to claim 3, characterized in that, In the second stage of the vector mask generation instruction, after caching the vector mask into the target cache register at the mask caching time corresponding to the target cache register, the method includes: In the third stage of the vector mask generation instruction, the vector mask is stored in a vector register. The third stage and the second stage are different processing stages of the vector mask generation instruction in the pipeline compared with the first stage.

5. The method according to claim 1, characterized in that, The step of responding to a vector mask read instruction, determining whether the at least one cache register is valid based on the status flag bit of the at least one cache register in the status flag unit, and reading the vector mask from the target cache register at the mask cache time corresponding to the target cache register when the status flag bit indicates that the corresponding target cache register is valid, includes: In response to a vector mask read instruction, in the fourth stage of the vector mask read instruction, the status flag bit of the at least one cache register is determined based on the status flag unit; When the status flag bit of the first cache register is the second value, the first cache register is determined to be valid, and the first cache register is determined to be the target cache register, wherein the first cache register is any one of the at least one cache registers; In the fifth stage of the vector mask read instruction, the vector mask is read from the target cache register at the mask cache time corresponding to the target cache register. The fourth stage and the fifth stage are different processing stages of the vector mask read instruction in the pipeline.

6. The method according to claim 1, characterized in that, After determining whether the at least one cache register is valid based on the status flag bit of the at least one cache register in the status flag unit, the method includes: If at least one of the buffer registers is invalid, the vector mask is read from the vector register.

7. The method according to claim 1, characterized in that, The method further includes: In response to a vector mask base address update instruction, if the status flag bit of the at least one cache register in the status flag unit is a second value, the status flag bit is updated to a first value.

8. A vector mask processing device, characterized in that, The device includes: A configuration unit is used to configure at least one cache register and a status flag unit for each mask processing thread in at least one mask processing thread. The at least one cache register is used to cache vector masks at different mask caching times, and the status flag unit is used to record the status flag bits of the at least one cache register. A caching unit is configured to respond to a vector mask generation instruction by determining a target cache register in at least one cache register based on the mask ready time of the vector mask generation instruction and the mask caching time, and updating the status flag bit of the target cache register in the status flag unit, so as to cache the generated vector mask to the target cache register according to the status flag bit and the mask caching time corresponding to the target cache register. The update of the status flag bit and the caching of the vector mask correspond to different processing stages of the vector mask generation instruction in the pipeline. The read unit is configured to respond to a vector mask read instruction by determining whether the at least one cache register is valid based on the status flag bit of the at least one cache register in the status flag unit, and if the status flag bit indicates that the corresponding target cache register is valid, read the vector mask from the target cache register at the mask cache time corresponding to the target cache register. The validity determination of the at least one cache register and the reading of the vector mask correspond to different processing stages of the vector mask read instruction in the pipeline.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

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