Chip programming whole-process quality detection and real-time feedback correction method

Abstract

The present application relates to a kind of chip programming whole process quality detection and real-time feedback correction method, wherein the method includes: obtaining the detection seat sub of adapting corresponding chip, and the adaptation identification instruction of detection platform is accepted by physical interface;Virtual working circuit is constructed, the attribute benchmark of corresponding chip under virtual circuit is obtained, and attribute determination threshold library is constructed;Through the control instruction of process detection, the program burning instruction of multiple chips is executed, and the real-time monitoring of chip burning process is carried out simultaneously;The program of chip read is compared with standard program, and the abnormal performance of chip is identified;By determining the root cause type of exception, according to the hierarchical principle of external hardware environment and internal software parameter, the correction action matching current chip and seat is generated, and the corresponding feedback correction instruction is obtained;Second correction programming is carried out to chip, and full-amount retest is carried out simultaneously, and the whole process quality determination result of multiple types of chips is obtained;Chip programming whole process quality detection and real-time feedback correction are realized.

Description

Technical Field

[0001] This invention belongs to the field of chip process testing technology, specifically relating to a method for quality inspection and real-time feedback correction of the entire chip programming process. Background Technology

[0002] Currently, chip manufacturing process testing still has the following areas that need improvement: With the rapid development of consumer electronics, industrial control, and automotive electronics, chip types and packaging forms are becoming increasingly diversified. Multi-packaged chips such as SOP, MSOP, TSSOP, SSOP, QFN, USON, WSON, TSOP, and SOT23 have become the mainstream for mass production. Chips must undergo a full range of processes including programming, functional testing, and quality assessment. Traditional testing and programming methods are gradually failing to meet production demands in terms of multi-model compatibility, automation, testing accuracy, and closed-loop calibration capabilities. Specifically, they have the following shortcomings: Different packaged chips require frequent replacement of dedicated test sockets. Matching the socket with the chip pins relies on manual or semi-automated operations, which can easily lead to problems such as uneven contact impedance, coplanarity deviation, and incorrect pin mapping. This can result in abnormal power-on, data reading failure, and unstable programming, seriously affecting the reliability of test results and process yield.

[0003] Traditional chip testing relies on discrete components such as physical resistors, capacitors, and crystal oscillators to build the working circuit. Different chips require redesigning and replacing the hardware circuit, resulting in long construction cycles, poor compatibility, and low flexibility. This makes it impossible to quickly adapt to the testing needs of multiple varieties and small batches of chips, thus limiting production efficiency.

[0004] Existing programming methods mostly use a one-way process of write-readback-verify, which lacks real-time monitoring of process parameters such as programming timing, voltage ripple, power-on response, and circuit continuity. Hidden faults such as program misalignment, bad blocks, and function silence errors cannot be detected in time during the process, which can easily lead to defective products being shipped out.

[0005] When abnormalities occur during programming or testing, it cannot automatically distinguish between chip failure, socket contact problems, virtual circuit parameter deviations, or programming command errors. Manual troubleshooting is time-consuming and inefficient. Correction actions are lagging and parameter adjustments are coarse, making it difficult to achieve accurate compensation and form a stable closed loop.

[0006] Different chip models lack standardized attribute benchmarks and judgment threshold libraries, and quality judgment relies on experience, resulting in poor consistency. At the same time, the entire process data lacks reliable evidence storage and linkage traceability mechanisms, which cannot support process optimization, yield improvement and quality traceability, and is difficult to meet the quality control requirements of industrialized mass production.

[0007] In summary, existing chip programming and testing technologies have significant shortcomings in areas such as multi-package compatibility, virtual circuit construction, real-time process monitoring, root cause localization of anomalies, real-time feedback correction, and closed-loop quality control throughout the entire process. There is an urgent need for a chip programming quality testing method that can cover the entire process, support multiple models, and provide real-time monitoring and automatic correction in order to improve the stability, accuracy, and production yield of chip programming. Summary of the Invention

[0008] To address the aforementioned problems in the existing technology, this invention provides a method for quality inspection and real-time feedback correction throughout the entire chip programming process; The objective of this invention can be achieved through the following technical solutions: S1: Obtain the test socket that is compatible with the corresponding chip, and receive the adaptation and identification instructions from the test platform through the physical interface; use virtual software to control the path status of the product under test, and at the same time simulate the attribute characteristics of the chip to build a virtual working circuit; execute the chip power-on timing control instructions, read the original program inside the chip, obtain the attribute benchmark of the corresponding chip under the virtual circuit, and build an attribute judgment threshold library. S2: Based on the attribute judgment threshold library and the control instructions of process detection, program burning instructions are executed on various chips in the virtual working circuit, and the chip burning process is monitored in real time; the read chip program is compared with the standard program using the program readback instruction to identify abnormal chip behavior; S3: Based on the abnormal behavior of the chip and the characteristics of the chip in the virtual circuit environment, cross-reference is performed to determine the type of abnormal root cause; according to the hierarchical principle of external hardware environment and internal software parameters, a correction action matching the current chip and socket is generated, and the corresponding feedback correction instruction is obtained; secondary correction programming is performed on the chip, and full functional retest is performed at the same time to obtain the full process quality judgment results of multiple types of chips.

[0009] As a preferred embodiment of the present invention, the specific process of receiving the adaptation and identification instructions from the detection platform through the physical interface includes: Based on the replaceable pin contact structure, the system calls the socket model database and chip package parameter library to automatically identify and calibrate the adapter socket, and obtain the socket pin distribution, contact impedance and coplanarity data. By using the connector adapter identification command, the device feeds back its own model, pin definition and adapter parameters to the process quality inspection platform in real time, thereby obtaining the mapping relationship of the interface pins. Impedance compensation is achieved through voltage fine-tuning to correct contact deviations, while the command transmission status of the corresponding interface is monitored to obtain the process status of the adaptation and recognition commands.

[0010] Specifically, the process of constructing the virtual working circuit includes: Extract the standard parameter range of capacitance and resistance required for chip operation, combine it with the chip's operating voltage and current requirements, obtain the configuration parameters of virtual components, generate analog signals of equivalent capacitance and equivalent resistance, and control the circuit on / off state of the product under test. Simulate the crystal oscillator's start-up waveform, frequency, and phase characteristics to construct a virtual working circuit; Send a self-test command to the virtual working circuit, obtain the on / off logic signals and crystal oscillator simulation accuracy data of the virtual working circuit, and compare the circuit parameters of the chip working scenario. Based on the comparison results, the virtual circuit was tested by fine-tuning the virtual capacitor, virtual resistor parameters and crystal oscillator simulation parameters, and the complete virtual working circuit construction process was obtained.

[0011] Specifically, the process of executing the chip power-on timing control instruction includes: Based on the virtual working circuit, the circuit voltage is adjusted to the voltage range of the preset chip structure, while the current is adjusted to the no-load working current. The voltage response signal of the chip pin is acquired in real time through a voltage monitoring mechanism, the power-on status of the chip is monitored in real time, and the power-on delay time and voltage stabilization time of the pin are recorded. Check the virtual circuit parameters and the contact status of the socket, adjust the virtual circuit voltage parameters and the socket contact position, and re-execute the power-on timing control command.

[0012] Specifically, the process of reading the original program inside the chip includes: Locate the chip placement position and check for abnormal pin contacts; According to the internal program storage address of the chip, read the program data inside the chip, and at the same time verify the read data.

[0013] Specifically, the process of constructing the attribute determination threshold library includes: By replacing the adapter and configuring the virtual working circuit, the chip power-on, program reading and function data acquisition operations are repeatedly performed to obtain multiple sets of sample data; Based on the aforementioned multiple sets of sample data, and in conjunction with the Grubbs criterion, abnormal sample data caused by defects in the sample itself, poor contact of the socket, or deviation of virtual circuit parameters are identified and eliminated. The average values ​​of the program baseline, functional baseline, and circuit response baseline are calculated, and the deviation between the sample data and the average values ​​is also calculated. The benchmark classification results of the corresponding chip types are entered into the database. At the same time, the judgment thresholds of the corresponding chip types are preset, the correspondence between chip models and standard benchmarks and judgment thresholds is constructed, and the attribute judgment threshold library is obtained.

[0014] Specifically, the process of burning programs to various chips includes: Extract the baseline programming parameters and socket adaptation parameters corresponding to the current chip type, and combine multi-channel parallel programming and dynamic parameter adjustment to obtain the adjustment range of programming parameters. The adjustment range includes the numerical range of writing timing, programming current, and programming voltage. By combining the pin definitions of the current chip with the electrical characteristics of the virtual circuit, the write timing, programming current, and programming voltage are calibrated to obtain the calibrated programming parameters. Based on the programming parameters, the programmer sends a programming start command, a writing timing control command, and a current and voltage adjustment command to the programmer, thereby activating the programmer's multi-channel parallel programming mechanism to program multiple chips. It synchronously monitors the programming progress and chip operating status, acquires the chip's voltage and current response signals, and identifies abnormal states during the programming process.

[0015] Specifically, the process of real-time monitoring of the chip programming process includes: The operating status data of the virtual circuit is obtained based on the parameters of the virtual working circuit, and the circuit voltage and current change data during the burning process are also obtained to monitor the circuit stability. The on / off logic of the virtual circuit is determined by the circuit on / off status detection command; The real-time frequency and phase data of the crystal oscillator are obtained based on the continuity test results, and then compared with the parameters of the standard crystal oscillator. Based on the comparison results, circuit problems are identified and real-time feedback is provided, and the programming parameters are adjusted synchronously.

[0016] Specifically, the process of comparing the read chip program with the standard program using the program readback instruction includes: The silent error detection identifies program deviations, omissions, misalignments, and silent error issues, while recording the location, type, and degree of deviation during the comparison process. The comparison results are combined with the chip's functional operating status, and the read chip program is compared with the standard program.

[0017] Specifically, the process for determining the type of abnormal root cause includes: Extract the characteristic parameters and occurrence sequence of abnormal defects to obtain abnormal characteristic data; Based on the aforementioned abnormal feature data, a comparison relationship of corresponding chip data features is constructed; By comparing the chip's own parameters, socket contact state, virtual circuit parameters, and programming instruction parameters, and using a chaotic particle swarm optimization algorithm, the differences between the chip's abnormal and normal characteristics are distinguished, and the root cause type is determined.

[0018] Specifically, the process of obtaining the corresponding feedback correction instruction includes: Based on the hierarchical principle of external hardware environment and internal software parameters, and combined with the current chip type and socket specifications, corresponding calibration actions are preset. The calibration actions include at least: virtual component parameter adjustment, socket contact compensation, and programming instruction optimization. Transform the correction logic into machine-recognizable control commands and add virtual circuit configuration fields, programming parameter adjustment fields, and socket adaptation fields. Based on the control instructions after adding fields, corresponding feedback correction instructions are obtained by combining the edge-side federated inference correction mechanism.

[0019] Specifically, the process for obtaining the full-process quality assessment results of multiple types of chips includes: Based on the data from secondary calibration programming and full functional retest, a multi-dimensional quality label is formed by combining chip model, socket type, virtual circuit parameters, programming parameters, and calibration records; The multi-dimensional quality labels are matched item by item with the attribute judgment threshold library to obtain a classification conclusion of chip qualification, downgraded use, or scrap. By using blockchain on-chain and TrustZone encryption, the hierarchical conclusions, the entire process instruction chain, and the retest data are reliably stored. Statistical reports are generated based on chip type, process step, and anomaly type to obtain full-process quality judgment results and process optimization suggestions for multiple types of chips.

[0020] The beneficial effects of this invention are as follows: With its replaceable socket automatic adaptation and software virtual working circuit, it can quickly adapt to various packaged chips such as SOP, TSSOP, QFN, and USON. It can simulate the working environment of resistors, capacitors, on / off circuits and crystal oscillators without the need for physical external hardware, which greatly improves the chip compatibility and debugging efficiency, and reduces hardware costs and contact failure rate.

[0021] By acquiring data throughout the entire process and building an attribute threshold library, unified quantitative detection of chip power-on, program reading, and burning processes can be achieved. Combined with real-time monitoring and silent error identification, hidden faults can be accurately captured, significantly improving programming consistency and first-time success rate.

[0022] By automatically identifying the root causes of anomalies and providing real-time feedback correction, a closed-loop control system of detection, programming, correction, and retesting is formed, replacing manual troubleshooting and achieving intelligent parameter optimization. It also supports quality grading and reliable evidence storage, effectively improving the quality control level of the entire process. Attached Figure Description

[0023] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0024] Figure 1 This is a flowchart illustrating a chip programming process quality inspection and real-time feedback correction method according to the present invention. Figure 2 This is a structural block diagram of the abnormal root cause analysis and correction feedback in this invention. Detailed Implementation

[0025] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided.

[0026] Please see Figure 1-2 A method for quality inspection and real-time feedback correction throughout the entire chip programming process, comprising: S1: Obtain the test socket that is compatible with the corresponding chip, and receive the adaptation and identification instructions from the test platform through the physical interface; use virtual software to control the path status of the product under test, and at the same time simulate the attribute characteristics of the chip to build a virtual working circuit; execute the chip power-on timing control instructions, read the original program inside the chip, obtain the attribute benchmark of the corresponding chip under the virtual circuit, and build an attribute judgment threshold library. S2: Based on the attribute judgment threshold library and the control instructions of process detection, program burning instructions are executed on various chips in the virtual working circuit, and the chip burning process is monitored in real time; the read chip program is compared with the standard program using the program readback instruction to identify abnormal chip behavior; S3: Based on the abnormal behavior of the chip and the characteristics of the chip in the virtual circuit environment, cross-reference is performed to determine the type of abnormal root cause; according to the hierarchical principle of external hardware environment and internal software parameters, a correction action matching the current chip and socket is generated, and the corresponding feedback correction instruction is obtained; secondary correction programming is performed on the chip, and full functional retest is performed at the same time to obtain the full process quality judgment results of multiple types of chips.

[0027] As a preferred embodiment of the present invention, the specific process of receiving the adaptation and identification instructions from the detection platform through the physical interface includes: Based on the replaceable pin contact structure, the system calls the socket model database and chip package parameter library to automatically identify and calibrate the adapter socket, and obtain the socket pin distribution, contact impedance and coplanarity data. By using the connector adapter identification command, the device feeds back its own model, pin definition and adapter parameters to the process quality inspection platform in real time, thereby obtaining the mapping relationship of the interface pins. Impedance compensation is achieved through voltage fine-tuning to correct contact deviations, while the command transmission status of the corresponding interface is monitored to obtain the process status of the adaptation and recognition commands.

[0028] In this embodiment, the replaceable pin contact structure adopts a modular design. The physical interface between the adapter and the testing platform uses a standardized snap-fit ​​connection, with an anti-loosening sealing structure at the snap-fit ​​connection. This significantly reduces the difficulty of adapter replacement, adapts to the rapid switching requirements of multiple chip types, and meets the scenario of alternating testing of multiple chip specifications in industrial mass production. The adapter model database and chip package parameter database are pre-loaded with parameters for various package models specified in the work instructions, covering core information such as pin count, pin spacing, package size, and pin function definitions. This comprehensively matches the testing requirements of chips with different package types, improving the automation level of the testing process. The identification module uses a combination of machine vision and resistance detection. Machine vision is responsible for identifying the adapter's external markings and pin distribution, while resistance detection is responsible for verifying the pin contact conductivity. The two work together to accurately obtain the adapter's pin distribution, contact impedance, and coplanarity data, ensuring the contact accuracy between the adapter and the chip pins. When feeding back adaptation parameters, a high-speed serial port transmission method is used, along with a data encryption protocol, to quickly generate the interface pin mapping relationship; voltage fine-tuning adopts step adjustment, and while performing impedance compensation, the command transmission status of the corresponding interface is monitored in real time. Through signal strength detection and bit error rate analysis, transmission anomalies are promptly identified and a reset mechanism is triggered to re-execute the adaptation identification process.

[0029] Specifically, the process of constructing the virtual working circuit includes: Extract the standard parameter range of capacitance and resistance required for chip operation, combine it with the chip's operating voltage and current requirements, obtain the configuration parameters of virtual components, generate analog signals of equivalent capacitance and equivalent resistance, and control the circuit on / off state of the product under test. Simulate the crystal oscillator's start-up waveform, frequency, and phase characteristics to construct a virtual working circuit; Send a self-test command to the virtual working circuit, obtain the on / off logic signals and crystal oscillator simulation accuracy data of the virtual working circuit, and compare the circuit parameters of the chip working scenario. Based on the comparison results, the virtual circuit was tested by fine-tuning the virtual capacitor, virtual resistor parameters and crystal oscillator simulation parameters, and the complete virtual working circuit construction process was obtained.

[0030] In this embodiment, the standard parameter ranges of capacitance and resistance required for chip operation are extracted according to the specifications of different packaged chips, combined with key factors such as the actual working characteristics, power consumption, and operating temperature range of the chip. Virtual component configuration parameters are automatically matched based on the chip model, quickly calling preset parameters to suit operators of different skill levels. Specifically, an FPGA+MCU dual-core heterogeneous architecture is adopted. The FPGA is responsible for high-speed parallel processing of virtual component analog signal generation, circuit logic simulation, and real-time data computation. Leveraging its hardware parallel computing advantages, it achieves high-speed generation and precise adjustment of equivalent capacitance and equivalent resistance analog signals, ensuring the real-time performance and accuracy of the analog signals. The MCU is responsible for system instruction parsing, parameter configuration, logic control, and external communication, coordinating the FPGA's computational flow and the overall working state of the virtual circuit. The two communicate and collaborate via a high-speed bus, generating highly accurate equivalent capacitance and equivalent resistance analog signals that can accurately simulate the working state and electrical characteristics of physical components. Simultaneously, digital switches control the circuit on / off of the product under test, adjusting circuit parameters in real time according to changes in the chip's working state. The crystal oscillator simulation uses a programmable module to simulate various frequencies and phases with precise phase adjustment. The constructed virtual working circuit accurately simulates the electrical characteristics of the chip's real-world operating scenario, reproducing the circuit environment, signal transmission characteristics, and interference scenarios during actual chip operation, ensuring a high degree of consistency between the virtual circuit and the chip's actual operating state. After the self-test command is sent, key information such as the on / off logic signals of the virtual circuit and the crystal oscillator simulation accuracy data are collected in real time and comprehensively compared with the circuit parameters of the chip's actual operating scenario. If the comparison deviation exceeds a reasonable range, the virtual capacitor, virtual resistor parameters, and crystal oscillator simulation parameters are automatically fine-tuned, and the virtual circuit test is repeatedly executed until the preset simulation accuracy is achieved.

[0031] Specifically, the process of executing the chip power-on timing control instruction includes: Based on the virtual working circuit, the circuit voltage is adjusted to the voltage range of the preset chip structure, while the current is adjusted to the no-load working current. The voltage response signal of the chip pin is acquired in real time through a voltage monitoring mechanism, the power-on status of the chip is monitored in real time, and the power-on delay time and voltage stabilization time of the pin are recorded. Check the virtual circuit parameters and the contact status of the socket, adjust the virtual circuit voltage parameters and the socket contact position, and re-execute the power-on timing control command.

[0032] In this embodiment, the electrical timing control is implemented using an FPGA+MCU dual-core heterogeneous architecture with a programmable timing generator. The voltage range of the preset chip structure is configured precisely and differentially based on the chip package type, electrical tolerance threshold, and static operating characteristics. Combined with the chip power consumption and no-load operating parameters, the circuit current is calibrated to the chip's standard no-load range. The voltage monitoring mechanism uses a multi-channel synchronous high-speed sampling mode to perform parallel voltage response acquisition on all chip pins, capture the transient waveform of pin power-on in real time, quantify and record the power-on delay time, voltage ramp-up rate, and voltage stabilization time of each pin, and generate a pin-level power-on timing feature map. If abnormalities such as excessive voltage fluctuation, excessively long stabilization time, or power-on / power-off are detected, the system automatically starts a virtual circuit-socket contact dual closed-loop adaptive correction: quickly fine-tuning the voltage output slope and ripple suppression parameters of the virtual working circuit, and synchronously correcting the contact pressure and alignment accuracy of the socket pins. After correction, the power-on timing control command is automatically re-triggered, forming a closed-loop control of sampling-monitoring-correction-re-execution.

[0033] Specifically, the process of reading the original program inside the chip includes: Locate the chip placement position and check for abnormal pin contacts; According to the internal program storage address of the chip, read the program data inside the chip, and at the same time verify the read data.

[0034] In this embodiment, high-definition imaging and dual-CCD binocular vision positioning technology are used. The dual-CCD vision module simultaneously acquires high-definition images of the chip and the detection socket from both left and right perspectives, obtaining two-dimensional image information of the chip outline, pin arrangement, and socket pads. It identifies chip placement deviations and pin contact states, capturing contact details between the chip and the socket. Especially for packaged chips without exposed pins, visual positioning confirms the chip-socket alignment. If problems such as poor pin contact, chip misalignment, or pin oxidation are found, the socket position correction mechanism is immediately triggered, automatically adjusting the chip placement position and cleaning the pin contact surfaces. After adjustment, the data transmission link is re-established to ensure good contact. When reading program data, it is read sequentially according to the chip's internal program storage address, following the chip storage protocol. A reliable verification method is used to verify the read data, covering data integrity and accuracy checks. If an error is found during verification, the program data at the corresponding address is immediately reread until the read data passes verification.

[0035] Specifically, the process of constructing the attribute determination threshold library includes: By replacing the adapter and configuring the virtual working circuit, the chip power-on, program reading and function data acquisition operations are repeatedly performed to obtain multiple sets of sample data; Based on the aforementioned multiple sets of sample data, and in conjunction with the Grubbs criterion, abnormal sample data caused by defects in the sample itself, poor contact of the socket, or deviation of virtual circuit parameters are identified and eliminated. The average values ​​of the program baseline, functional baseline, and circuit response baseline are calculated, and the deviation between the sample data and the average values ​​is also calculated. The benchmark classification results of the corresponding chip types are entered into the database. At the same time, the judgment thresholds of the corresponding chip types are preset, the correspondence between chip models and standard benchmarks and judgment thresholds is constructed, and the attribute judgment threshold library is obtained.

[0036] In this embodiment, both the adapter replacement and the virtual working circuit configuration adopt an automatic switching mode. Specifically, the automatic switching mode employs a collaborative control architecture of PLC + edge computing unit, combined with multi-sensor fusion feedback control technology. The specific operation process is as follows: The system obtains the model information of the chip to be tested through a chip identification module (using machine vision to identify the chip package appearance, pin distribution, and chip surface markings, combined with an image recognition algorithm, which can automatically identify new packaged chips without manual updating of the identification template). The chip model data is synchronously transmitted to the PLC controller and the edge computing unit. The edge computing unit synchronously collects the environmental parameters (temperature, humidity) of the current testing station and the historical data of previous switching operations, performing real-time analysis and optimization. The PLC controller, combined with the optimization suggestions output by the edge computing unit, calls the preset correspondence table between chip models and adapter / virtual circuit parameters, and dynamically corrects the adapter parameters through a fuzzy control algorithm to determine the required adapter model and virtual working circuit parameter configuration scheme for the current chip. The PLC controller switches to the adapter switching actuator (using a servo motor drive module, combined with a ball screw guide rail to realize the adapter switching mechanism). Compared to traditional pneumatic drives, the translation and positioning of the connector offers higher positioning accuracy and eliminates pneumatic impact, reducing connector wear. The PLC controller sends a switching command, and the connector switching actuator receives the command and uses a displacement sensor to provide real-time feedback on the connector's position. Based on this feedback, the PLC controller performs closed-loop adjustment, automatically and smoothly moving the currently compatible connector out of the testing station while simultaneously and precisely moving the matching connector to the testing station. The connector is quickly positioned and fixed using positioning pins and elastic snap-fit ​​structures, completing the automatic connector switching. During the switching process, contact impedance pre-detection is performed simultaneously to ensure the connector is installed correctly. Simultaneously, the PLC controller sends parameter configuration commands to the virtual working circuit control module. The virtual working circuit control module (based on an FPGA+MCU dual-core heterogeneous architecture) automatically calls preset virtual component parameters such as capacitors, resistors, and crystal oscillators based on the commands. It also dynamically adjusts the electrical characteristics of the virtual circuit by combining environmental adaptation parameters fed back by the edge computing unit, completing the automatic configuration of the virtual working circuit. The entire switching and configuration process forms a closed-loop control system of identification-analysis-decision-execution-feedback, adapting to the needs of industrial mass production and rapid switching between multiple chip specifications. For each chip package type, the chip power-on, program reading, and functional data acquisition operations were repeatedly performed to collect sufficient sample data. This sample data covered parameter information of the chip under different operating states and environments, ensuring that the sample data comprehensively reflected the chip's operating status and possessed good representativeness and versatility. The Grubbs criterion was used to screen the sample data, and statistical analysis methods were employed to accurately identify and eliminate abnormal sample data caused by factors such as defects in the sample itself, poor contact of the connector, deviation of virtual circuit parameters, and environmental interference.After removing outlier data, a mean calculation algorithm is used to accurately calculate the average values ​​of the program benchmark, functional benchmark, and circuit response benchmark. Simultaneously, the deviation of the remaining valid sample data from the average value is calculated, and deviation analysis ensures that the deviation is within a reasonable range, guaranteeing the stability of the benchmark data. The benchmark classification results for each packaged chip are entered into a database, and a judgment threshold for the corresponding chip type is preset. The threshold setting adopts a dynamic adjustment mechanism, which can be optimized in real time based on sample data, changes in the production environment, and updates to chip specifications during subsequent production processes, ensuring the applicability and accuracy of the thresholds. Finally, a one-to-one correspondence between chip models, standard benchmarks, and judgment thresholds is established, forming an attribute judgment threshold library.

[0037] Specifically, the process of burning programs to various chips includes: Extract the baseline programming parameters and socket adaptation parameters corresponding to the current chip type, and combine multi-channel parallel programming and dynamic parameter adjustment to obtain the adjustment range of programming parameters. The adjustment range includes the numerical range of writing timing, programming current, and programming voltage. By combining the pin definitions of the current chip with the electrical characteristics of the virtual circuit, the write timing, programming current, and programming voltage are calibrated to obtain the calibrated programming parameters. Based on the programming parameters, the programmer sends a programming start command, a writing timing control command, and a current and voltage adjustment command to the programmer, thereby activating the programmer's multi-channel parallel programming mechanism to program multiple chips. It synchronously monitors the programming progress and chip operating status, acquires the chip's voltage and current response signals, and identifies abnormal states during the programming process.

[0038] In this embodiment, the baseline programming parameters and socket adaptation parameters are automatically extracted from the attribute judgment threshold library. The system quickly matches the corresponding parameter information according to the current chip model, and combines multi-channel parallel programming and dynamic parameter adjustment mechanisms to reasonably determine the adjustment range of programming parameters. The dynamic parameter adjustment mechanism can flexibly adjust programming parameters according to factors such as the chip's real-time working status and programming progress to ensure the stability of the programming process. Different adjustment ranges are set for the programming requirements of different packaged chips, taking into account factors such as the number of pins, package structure, and storage characteristics of the chip, to ensure that the programming parameters conform to the chip characteristics and avoid programming anomalies caused by parameter uniformity. Based on the pin definitions of the current chip and the electrical characteristics of the virtual circuit, the write timing, programming current, and programming voltage are precisely calibrated. The calibration process combines the standard parameters in the chip datasheet with the simulated data of the virtual circuit. When issuing programming commands to the programmer, a synchronous triggering method is used to ensure that multi-channel programming commands are issued synchronously. The system synchronously monitors the programming progress and chip operating status. It acquires the chip's voltage and current response signals in real time through the monitoring module, and identifies abnormal states such as overcurrent, overvoltage, programming interruption, and data transmission anomalies. Once an anomaly is detected, the programming work of the corresponding channel is immediately suspended, and the anomaly information is recorded and fed back to the testing platform.

[0039] Specifically, the process of real-time monitoring of the chip programming process includes: The operating status data of the virtual circuit is obtained based on the parameters of the virtual working circuit, and the circuit voltage and current change data during the burning process are also obtained to monitor the circuit stability. The on / off logic of the virtual circuit is determined by the circuit on / off status detection command; The real-time frequency and phase data of the crystal oscillator are obtained based on the continuity test results, and then compared with the parameters of the standard crystal oscillator. Based on the comparison results, circuit problems are identified and real-time feedback is provided, and the programming parameters are adjusted synchronously.

[0040] In this embodiment, the operating status data of the virtual circuit is collected in real time. The data acquisition frequency is synchronized with the burning rhythm, comprehensively grasping key information such as the parameter values ​​of virtual capacitors and resistors, circuit on / off status, and signal transmission strength. Through real-time data analysis, it is ensured that abnormalities in the virtual circuit can be detected in a timely manner. Circuit voltage and current changes during the burning process are collected through a high-speed sampling module. This module has high sampling accuracy and response speed, accurately capturing subtle changes in voltage and current. By analyzing data fluctuations, circuit stability is monitored in real time, and a fluctuation early warning mechanism is established. If voltage or current fluctuations exceed reasonable ranges, a circuit stability warning is immediately triggered, reminding staff to handle the situation promptly. Simultaneously, emergency adjustment measures are automatically initiated, temporarily adjusting relevant parameters. Circuit on / off status detection commands are issued periodically, and the detection frequency can be flexibly adjusted according to the burning progress. This quickly determines the on / off logic of the virtual circuit, promptly detecting abnormalities such as open circuits, short circuits, and poor contacts. If such abnormalities are detected, a power-off command is immediately issued to disconnect the relevant circuits, effectively preventing damage to the programmer and chip due to circuit abnormalities, reducing equipment wear and chip scrap rate. The crystal oscillator frequency tracking command is issued based on the continuity test results. It acquires the real-time frequency and phase data of the crystal oscillator in real time and compares them precisely with the standard crystal oscillator parameters. The comparison process uses the deviation rate analysis method, which calculates the percentage difference between the real-time crystal oscillator parameters and the standard parameters. By setting a reasonable deviation rate threshold, it is determined whether the crystal oscillator parameters are within the normal range. If the deviation rate exceeds the threshold, it is immediately identified as a circuit abnormality and fed back to the detection platform in real time. At the same time, the programmed parameters and the simulated crystal oscillator parameters are adjusted synchronously until the crystal oscillator parameters are restored to the standard range.

[0041] Specifically, the process of comparing the read chip program with the standard program using the program readback instruction includes: The silent error detection identifies program deviations, omissions, misalignments, and silent error issues, while recording the location, type, and degree of deviation during the comparison process. The comparison results are combined with the chip's functional operating status, and the read chip program is compared with the standard program.

[0042] In this embodiment, silent error detection employs a combination of comparison methods, integrating byte-by-byte comparison, checksum comparison, and logical consistency comparison. This approach accurately identifies various issues such as program deviations, missing values, misalignments, and silent errors. Silent errors encompass highly concealed errors like bad blocks in chip storage, program redundancy, and data tampering. The comparison process meticulously records key information such as deviation location, type, and severity. Deviation location is accurate to the chip storage address, deviation type is clearly distinguished as missing bytes, byte errors, and logical misalignments, and deviation severity is quantitatively analyzed, generating a complete and standardized program comparison report. The report includes core information such as chip model, programming time, comparison results, anomaly details, and deviation analysis, with a standardized format and detailed content. The comparison results are combined with the chip's functional operating status to perform a secondary comparison between the read chip program and the standard program. This secondary comparison focuses on verifying the completeness of the program logic and the effectiveness of its functions, comprehensively verifying the accuracy of the program burning. If the comparison results are consistent and the chip functions normally, the program burning is deemed successful. If there are discrepancies in the comparison or the chip functions abnormally, it is determined to be a burning error, triggering the error handling process to address the burning problem promptly. For storage chips, an additional program read / write stability test is added. By repeatedly executing read / write operations, the read / write scenarios in actual chip use are simulated, and the consistency of each read / write operation is compared to ensure the stability of the chip's storage function, the reliability of data read / write, and compliance with practical application requirements.

[0043] Specifically, the process for determining the type of abnormal root cause includes: Extract the characteristic parameters and occurrence sequence of abnormal defects to obtain abnormal characteristic data; Based on the aforementioned abnormal feature data, a comparison relationship of corresponding chip data features is constructed; By comparing the chip's own parameters, socket contact state, virtual circuit parameters, and programming instruction parameters, and using a chaotic particle swarm optimization algorithm, the differences between the chip's abnormal and normal characteristics are distinguished, and the root cause type is determined.

[0044] In this embodiment, by extracting the characteristic parameters and occurrence sequence of abnormal defects in real time, the detection platform, virtual working circuit, and programmer work in real time to comprehensively and quickly collect various types of data related to the abnormality. Based on the abnormal feature data, a comparison relationship of corresponding chip data features is constructed. The abnormal feature data is correlated and compared with the normal feature data in the attribute judgment threshold library. Through feature difference analysis, logical correlation analysis, and other methods, the difference between abnormal and normal states is clearly distinguished. A comprehensive comparison is made of various related factors such as chip parameters, socket contact status, virtual circuit parameters, and programming instruction parameters. The correlation between various factors and abnormal features is checked one by one to eliminate the interference of irrelevant factors and focus on the core influencing factors. The chaotic particle swarm optimization algorithm is used for root cause analysis. This algorithm has the characteristics of fast convergence speed and high optimization accuracy. It can quickly distinguish the difference between abnormal and normal features of the chip, accurately determine the root cause type, and cover common abnormal types such as chip body failure, poor socket contact, virtual circuit parameter deviation, programming parameter error, and environmental interference.

[0045] Specifically, the process of obtaining the corresponding feedback correction instruction includes: Based on the hierarchical principle of external hardware environment and internal software parameters, and combined with the current chip type and socket specifications, corresponding calibration actions are preset. The calibration actions include at least: virtual component parameter adjustment, socket contact compensation, and programming instruction optimization. Transform the correction logic into machine-recognizable control commands and add virtual circuit configuration fields, programming parameter adjustment fields, and socket adaptation fields. Based on the control instructions after adding fields, corresponding feedback correction instructions are obtained by combining the edge-side federated inference correction mechanism.

[0046] In this embodiment, following the hierarchical principle of external hardware environment and internal software parameters, external hardware environment-related issues are corrected first, followed by internal software parameter correction, ensuring the targeted and efficient nature of the correction work. Based on the current chip type and socket specifications, corresponding correction actions are preset. In addition to core correction actions such as virtual component parameter adjustment, socket contact compensation, and programming instruction optimization, auxiliary correction actions such as crystal oscillator parameter fine-tuning, interface reset, and contact surface cleaning are added to comprehensively adapt to different types of anomaly root causes. The correction logic is converted into machine-recognizable control instructions, and various related configuration fields such as virtual circuit configuration fields, programming parameter adjustment fields, socket adaptation fields, and correction timing fields are added. The edge-side federated inference correction mechanism adopts an advanced distributed inference architecture, which can combine historical correction data, current anomaly characteristics, chip model parameters, and other multi-dimensional information to optimize control instructions. The optimization process balances correction effect and efficiency, resulting in accurate feedback correction instructions.

[0047] Specifically, the process for obtaining the full-process quality assessment results of multiple types of chips includes: Based on the data from secondary calibration programming and full functional retest, a multi-dimensional quality label is formed by combining chip model, socket type, virtual circuit parameters, programming parameters, and calibration records; The multi-dimensional quality labels are matched item by item with the attribute judgment threshold library to obtain a classification conclusion of chip qualification, downgraded use, or scrap. By using blockchain on-chain and TrustZone encryption, the hierarchical conclusions, the entire process instruction chain, and the retest data are reliably stored. Statistical reports are generated based on chip type, process step, and anomaly type to obtain full-process quality judgment results and process optimization suggestions for multiple types of chips.

[0048] In this embodiment, after the secondary calibration programming is completed, the chip undergoes a full functional retest. The retest covers all core aspects, including chip power-on, program reading, functional operation, stability testing, and anti-interference testing. The retest process is consistent with the formal testing process, comprehensively verifying the chip's working status after calibration. Retest data is collected and stored in real time using encrypted storage to ensure data traceability and tamper-proofness. Combining various information such as chip model, socket type, virtual circuit parameters, programming parameters, calibration records, and retest results, a multi-dimensional quality label is formed. The label data covers key parameters and status information of the entire chip process, accurately reflecting the quality status of the entire chip process. The multi-dimensional quality label is matched item by item with the attribute judgment threshold library. The matching process uses a precise comparison algorithm, and based on the matching results, a classification conclusion is given for the chip as qualified, downgraded for use, or scrapped. The classification standards are clear and unified. Downgraded use is for chips where some parameters exceed the threshold but do not affect the core function, achieving rational resource utilization and reducing production costs. By leveraging blockchain technology and encryption, information such as graded conclusions, the entire process instruction chain, retest data, and anomaly records are reliably stored. This stored data is tamper-proof and traceable, facilitating quality traceability and process review, and meeting industry quality control requirements. Statistical reports are generated by chip type, process stage, and anomaly type. These reports include key information such as yield statistics, anomaly root cause distribution, correction success rate, and process time. Furthermore, targeted process optimization suggestions are provided based on actual production conditions, ultimately yielding comprehensive quality assessment results and process optimization recommendations for multiple chip types.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for quality inspection and real-time feedback correction throughout the entire chip programming process, characterized in that, include: S1: Obtain the test socket that is compatible with the corresponding chip, and accept the adaptation and identification instructions from the test platform through the corresponding interface; use virtual software to control the path status of the product under test, and at the same time simulate the attribute characteristics of the chip to build a virtual working circuit; execute the timing control instructions for chip power-on, read the original program inside the chip, obtain the attribute benchmark of the corresponding chip under the virtual circuit, and build an attribute judgment threshold library. S2: Based on the attribute judgment threshold library and the control instructions of process detection, program burning instructions are executed on various chips in the virtual working circuit, and the chip burning process is monitored in real time; the read chip program is compared with the standard program using the program readback instruction to identify abnormal chip behavior; S3: Based on the abnormal behavior of the chip and the characteristics of the chip in the virtual circuit environment, cross-reference is performed to determine the type of abnormal root cause; according to the hierarchical principle of external hardware environment and internal software parameters, a correction action matching the current chip and socket is generated, and the corresponding feedback correction instruction is obtained; secondary correction programming is performed on the chip, and full functional retest is performed at the same time to obtain the full process quality judgment results of multiple types of chips.

2. The method according to claim 1, characterized in that, The specific process of receiving adaptation and identification instructions from the detection platform through the physical interface includes: Based on the replaceable pin contact structure, the system calls the socket model database and chip package parameter library to automatically identify and calibrate the adapter socket, and obtain the socket pin distribution, contact impedance and coplanarity data. By using the connector adapter identification command, the device feeds back its own model, pin definition and adapter parameters to the process quality inspection platform in real time, thereby obtaining the mapping relationship of the interface pins. Impedance compensation is achieved through voltage fine-tuning to correct contact deviations, while the command transmission status of the corresponding interface is monitored to obtain the process status of the adaptation and recognition commands.

3. The method according to claim 1, characterized in that, The specific process of constructing the virtual working circuit includes: Extract the standard parameter range of capacitance and resistance required for chip operation, combine it with the chip's operating voltage and current requirements, obtain the configuration parameters of virtual components, generate analog signals of equivalent capacitance and equivalent resistance, and control the circuit on / off state of the product under test. Simulate the crystal oscillator's start-up waveform, frequency, and phase characteristics to construct a virtual working circuit; Send a self-test command to the virtual working circuit, obtain the on / off logic signals and crystal oscillator simulation accuracy data of the virtual working circuit, and compare the circuit parameters of the chip working scenario. Based on the comparison results, the virtual circuit was tested by fine-tuning the virtual capacitor, virtual resistor parameters and crystal oscillator simulation parameters, and the complete virtual working circuit construction process was obtained.

4. The method according to claim 1, characterized in that, The specific process of executing the timing control instructions for chip power-on includes: Based on the virtual working circuit, the circuit voltage is adjusted to the voltage range of the preset chip structure, while the current is adjusted to the no-load working current. The voltage response signal of the chip pin is acquired in real time through a voltage monitoring mechanism, the power-on status of the chip is monitored in real time, and the power-on delay time and voltage stabilization time of the pin are recorded. Check the virtual circuit parameters and the contact status with the socket, adjust the voltage parameters of the virtual circuit and the contact position with the socket, and re-execute the timing control instructions for chip power-on.

5. The method according to claim 1, characterized in that, The specific process of reading the original program inside the chip includes: Locate the chip placement position and check for abnormal pin contacts; According to the internal program storage address of the chip, read the program data inside the chip, and at the same time verify the read data.

6. The method according to claim 1, characterized in that, The specific process of constructing the attribute determination threshold library includes: By replacing the adapter and configuring the virtual working circuit, the chip power-on, program reading and function data acquisition operations are repeatedly performed to obtain multiple sets of sample data; Based on the aforementioned multiple sets of sample data, and in conjunction with the Grubbs criterion, abnormal sample data caused by defects in the sample itself, poor contact of the socket, or deviation of virtual circuit parameters are identified and eliminated. The average values ​​of the program baseline, functional baseline, and circuit response baseline are calculated, and the deviation between the sample data and the average values ​​is also calculated. The benchmark classification results of the corresponding chip types are entered into the database. At the same time, the judgment thresholds of the corresponding chip types are preset, the correspondence between chip models and standard benchmarks and judgment thresholds is constructed, and the attribute judgment threshold library is obtained.

7. The method according to claim 1, characterized in that, The specific process of burning programs to various chips includes: Extract the baseline programming parameters and socket adaptation parameters corresponding to the current chip type, and combine multi-channel parallel programming and dynamic parameter adjustment to obtain the adjustment range of programming parameters. The adjustment range includes the numerical range of writing timing, programming current, and programming voltage. By combining the pin definitions of the current chip with the electrical characteristics of the virtual circuit, the write timing, programming current, and programming voltage are calibrated to obtain the calibrated programming parameters. The programmer's multi-channel parallel programming mechanism is activated to program multiple chips. It synchronously monitors the programming progress and chip operating status, acquires the chip's voltage and current response signals, and identifies abnormal states during the programming process.

8. The method according to claim 1, characterized in that, The specific process of real-time monitoring of the chip programming process includes: The operating status data of the virtual circuit is obtained based on the parameters of the virtual working circuit, and the circuit voltage and current change data during the burning process are also obtained to monitor the circuit stability. The on / off logic of the virtual circuit is determined by the circuit on / off status detection command; The real-time frequency and phase data of the crystal oscillator are obtained based on the continuity test results, and then compared with the parameters of the standard crystal oscillator. Based on the comparison results, circuit problems are identified and real-time feedback is provided, and the programming parameters are adjusted synchronously.

9. The method according to claim 1, characterized in that, The specific process of comparing the read chip program with the standard program using the program readback instruction includes: The silent error detection identifies program deviations, omissions, misalignments, and silent error issues, while recording the location, type, and degree of deviation during the comparison process. The comparison results are combined with the chip's functional operating status, and the read chip program is compared with the standard program.

10. The method according to claim 1, characterized in that, The specific process for determining the type of abnormal root cause includes: Extract the characteristic parameters and occurrence sequence of abnormal defects to obtain abnormal characteristic data; Based on the aforementioned abnormal feature data, a comparison relationship of corresponding chip data features is constructed; By comparing the chip's own parameters, socket contact state, virtual circuit parameters, and programming instruction parameters, and using a chaotic particle swarm optimization algorithm, the differences between the chip's abnormal and normal characteristics are distinguished, and the root cause type is determined.

11. The method according to claim 1, characterized in that, The specific process of obtaining the corresponding feedback correction instruction includes: Based on the hierarchical principle of external hardware environment and internal software parameters, and combined with the current chip type and socket specifications, corresponding calibration actions are preset. The calibration actions include at least: virtual component parameter adjustment, socket contact compensation, and programming instruction optimization. Transform the correction logic into machine-recognizable control commands and add virtual circuit configuration fields, programming parameter adjustment fields, and socket adaptation fields. Based on the control instructions after adding fields, corresponding feedback correction instructions are obtained by combining the edge-side federated inference correction mechanism.

12. The method according to claim 1, characterized in that, The specific process for obtaining the full-process quality assessment results of multiple types of chips includes: Based on the data from secondary calibration programming and full functional retest, a multi-dimensional quality label is formed by combining chip model, socket type, virtual circuit parameters, programming parameters, and calibration records; The multi-dimensional quality labels are matched item by item with the attribute judgment threshold library to obtain a classification conclusion of chip qualification, downgraded use, or scrap. By using blockchain on-chain and TrustZone encryption, the hierarchical conclusions, the entire process instruction chain, and the retest data are reliably stored. Statistical reports are generated based on chip type, process step, and anomaly type to obtain full-process quality judgment results and process optimization suggestions for multiple types of chips.

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