Solar cell and method of manufacturing the same, battery module, and photovoltaic system

Abstract

This invention relates to the field of solar cells, specifically disclosing a solar cell, its fabrication method, a cell module, and a photovoltaic system. The fabrication method includes: sequentially forming a first tunneling layer and a first doped layer on a silicon substrate; forming a first doped source layer on the first doped layer in a first electrode region to obtain a first intermediate; wherein the doping elements of the first doped source layer and the first doped layer have opposite polarities after doping; forming a first passivation layer on the first intermediate; printing a first electrode paste on the first passivation layer above the first electrode region to obtain a second intermediate; sintering the second intermediate; wherein, during the sintering process, the first electrode paste burns through the first passivation layer and melts the first doped source layer, thereby forming a first co-doped region within the first doped layer in the first electrode region, co-doped with the doping elements of the first doped layer, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. Implementing this invention can improve the fill factor, short-circuit current, and conversion efficiency of solar cells.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more particularly to a solar cell, its preparation method, cell module, and photovoltaic system. Background Technology

[0002] In traditional tunneling oxide passivated contact (TOPCon) structures, a doped polysilicon layer is typically fabricated on the tunneling oxide layer to achieve selective carrier transport and form a composite passivation structure with the tunneling oxide layer. After electrode fabrication, the electrode burns through the passivation layer and contacts the doped polysilicon layer. However, the contact resistance at this point is high, resulting in significant current loss and low conversion efficiency. A common solution is to increase the doping concentration of the polysilicon layer; however, increasing the doping concentration often leads to increased parasitic absorption and greater lattice distortion, which also reduces conversion efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a solar cell and a method for preparing the same, which can reduce contact resistance and improve conversion efficiency.

[0004] Another technical problem that the present invention needs to solve is to provide a battery assembly.

[0005] Another technical problem that the present invention needs to solve is to provide a photovoltaic system.

[0006] To address the above problems, this invention discloses a method for preparing a solar cell, comprising: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; wherein, the first doped layer has a first electrode region for contacting a first electrode; A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate; wherein the doping element of the first doped source layer has the opposite polarity to the doped element of the first layer. A first passivation layer is formed on the first intermediate; wherein the first passivation layer covers the first doped layer and the first doped source layer; A first electrode paste is printed on a first passivation layer above the first electrode region to obtain a second intermediate. The second intermediate is sintered; wherein, during the sintering process, the first electrode slurry burns through the first passivation layer and melts the first doping source layer to form the doping element of the first doping layer, the doping element of the first doping source layer, and the first co-doped region of the metal co-doped in the first electrode slurry within the first doping layer of the first electrode region.

[0007] As an improvement to the above technical solution, the step of forming a first doped source layer on the first doped layer in the first electrode region to obtain the first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the first preset region to obtain a second intermediate.

[0008] As an improvement to the above technical solution, the step of forming a first doped source layer on the first doped layer in the first electrode region to obtain the first intermediate includes: The first tunneling layer and the first doped layer in the first preset region are removed to expose the silicon substrate in the first preset region; wherein, the silicon substrate in the first preset region is provided with a second electrode region for contacting the second electrode; A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on a silicon substrate in the second electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the silicon substrate after doping. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on a first passivation layer above the second electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode paste burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping element of the silicon substrate, the doping element of the second doping source layer, and the second co-doped region of the metal co-doped in the second electrode paste within the silicon substrate of the second electrode region.

[0009] As an improvement to the above technical solution, the step of forming a first doped source layer on the first doped layer in the first electrode region to obtain the first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A first inner expansion layer is formed on a silicon substrate in a first predetermined region, wherein the doping polarity of the first inner expansion layer is opposite to that of the silicon substrate; wherein the first inner expansion layer is provided with a fourth electrode region for contacting a second electrode. A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the first inner expansion layer of the fourth electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the same polarity as the doping element of the silicon substrate after doping. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the fourth electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the first inner expansion layer, the doping elements of the second doping source layer, and the fourth co-doped region of metal co-doped in the second electrode slurry within the first inner expansion layer of the fourth electrode region.

[0010] As an improvement to the above technical solution, the step of forming a first doped source layer on the first doped layer in the first electrode region to obtain the first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A second tunneling layer and a second doped layer are sequentially formed on a silicon substrate in the first preset region and on the first doped layer; wherein the polarities of the first doped layer and the second doped layer are opposite; the second doped layer is provided with a third electrode region for contacting the second electrode; Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form a first doped source layer, thereby obtaining a first intermediate. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the third electrode region to obtain a second intermediate. The silicon substrate includes a first surface and a second surface disposed opposite to each other, and both the first doped layer and the second doped layer are disposed on the first surface.

[0011] As an improvement to the above technical solution, the step of forming a first doped source layer on the first doped layer in the first electrode region to obtain the first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A second tunneling layer and a second doped layer are sequentially formed on a silicon substrate in the first preset region and on the first doped layer; wherein the polarities of the first doped layer and the second doped layer are opposite; the second doped layer is provided with a third electrode region for contacting the second electrode; Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form the first doped source layer; A second doped source layer is formed on the second doped layer in the third electrode region to obtain a first intermediate; wherein the polarity of the doping element in the second doped source layer is opposite to that of the doping element in the second doped layer. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the third electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the second doping layer, the doping elements of the second doping source layer, and the third co-doped region of metal co-doping in the second electrode slurry in the second doping layer of the third electrode region. The silicon substrate includes a first surface and a second surface disposed opposite to each other, and both the first doped layer and the second doped layer are disposed on the first surface.

[0012] As an improvement to the above technical solution, the step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A second inner expansion layer is formed on the second surface of the silicon substrate; wherein the polarity of the second inner expansion layer is opposite to that of the silicon substrate; the second inner expansion layer is provided with a fourth electrode region for contacting the second electrode; A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the fourth electrode region to obtain a second intermediate.

[0013] As an improvement to the above technical solution, the step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A second inner expansion layer is formed on the second surface of the silicon substrate, the second inner expansion layer having a polarity opposite to that of the silicon substrate; wherein the second inner expansion layer has a fourth electrode region for contacting the second electrode; A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the second inner expansion layer in the fourth electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the second inner expansion layer after doping. The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the fourth electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the second passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the second inner expansion layer, the doping elements of the second doping source layer, and the fourth co-doped region of metal co-doped in the second electrode slurry in the second inner expansion layer of the fourth electrode region.

[0014] As an improvement to the above technical solution, the step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; A second tunneling layer and a second doped layer are sequentially formed on the second surface of the silicon substrate; wherein the second doped layer has a third electrode region for contacting the second electrode; The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the third electrode region to obtain a second intermediate.

[0015] As an improvement to the above technical solution, the step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; A second tunneling layer and a second doped layer are sequentially formed on the second surface of the silicon substrate; wherein the second doped layer has a third electrode region for contacting the second electrode; The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the second doped layer in the third electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the second doped layer after doping. The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the third electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the second passivation layer and melts the second doping source layer during the sintering process, so as to form the doping element of the second doping layer, the doping element of the second doping source layer, and the third co-doped region of metal co-doped in the second electrode slurry within the second doping layer of the third electrode region.

[0016] As an improvement to the above technical solution, the silicon substrate is N-type monocrystalline silicon or P-type monocrystalline silicon; and / or The first doped layer is a doped polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, Al, P, As, Sb or Bi; and / or The doping element of the first doped source layer is one or more of B, Ga, In, Al, P, As, Sb, or Bi; and / or The first electrode paste comprises Ag and / or Al.

[0017] As an improvement to the above technical solution, the doping element of the second doped source layer is one or more of B, Ga, In, Al, P, As, Sb, or Bi; and / or The second electrode slurry comprises Ag and / or Al.

[0018] As an improvement to the above technical solution, the doping element of the second doped layer is one or more of B, Ga, In, Al, P, As, Sb or Bi.

[0019] As an improvement to the above technical solution, the first electrode slurry is sintered to form the first electrode; The width of the first co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the first co-doped region is either continuously distributed or discontinuously distributed.

[0020] As an improvement to the above technical solution, the second electrode slurry is sintered to form the second electrode; The width of the second co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the second co-doped region is either continuously or discontinuously distributed.

[0021] As an improvement to the above technical solution, the second electrode slurry is sintered to form the second electrode; The width of the fourth co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the fourth co-doped region is either continuously or discontinuously distributed.

[0022] As an improvement to the above technical solution, the second electrode slurry is sintered to form the second electrode; The width of the third co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the third co-doped region is either continuously or discontinuously distributed.

[0023] As an improvement to the above technical solution, the doping concentration of the first doped layer is 5×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The doping concentration of the second doped layer is 2×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0024] As an improvement to the above technical solution, the doping concentration of the silicon substrate in the second electrode region is 5×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 .

[0025] As an improvement to the above technical solution, the doping concentration of the first inner extension layer in the fourth electrode region is 5×10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

[0026] As an improvement to the above technical solution, the doping concentration of the second inner extension layer in the fourth electrode region is 5×10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

[0027] As an improvement to the above technical solution, the first tunneling layer is a silicon oxide layer; and / or The first passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0028] As an improvement to the above technical solution, the second tunneling layer is a silicon oxide layer.

[0029] Accordingly, the present invention also discloses a solar cell prepared by the above-described method for preparing a solar cell.

[0030] Accordingly, the present invention also discloses a battery assembly comprising the aforementioned solar cell.

[0031] Accordingly, the present invention also discloses a photovoltaic system comprising the above-described battery assembly or the above-described solar cell.

[0032] Implementing this invention has the following beneficial effects: In a method for fabricating a solar cell according to an embodiment of the present invention, a first doped source layer is formed on a first doped layer, wherein the doping element of the source layer has the opposite polarity to that of the doped element in the first doped layer. Then, during the subsequent sintering of the first electrode paste, a first co-doped region is formed within the first doped layer in the first electrode region, containing the doping elements of the first doped layer, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. This first co-doped region contains a large number of doped elements, which can form more active charge carriers within the first doped layer, thereby enhancing the conductivity of the first doped layer, reducing the contact resistance, and ultimately improving the short-circuit current, fill factor, and conversion efficiency of the solar cell. Attached Figure Description

[0033] Figure 1 This is a flowchart of the method for preparing the solar cell in Example 1; Figure 2 This is a schematic cross-sectional view of the solar cell in Example 2; Figure 3 This is a top view of the back of the solar cell in Example 2; Figure 4 This is a flowchart of the method for preparing the solar cell in Example 2; Figure 5 This is a flowchart of the method for preparing the solar cell in Example 3; Figure 6 This is a schematic cross-sectional view of the solar cell in Example 3; Figure 7 This is a top view of the back of the solar cell in Example 3; Figure 8 This is a flowchart of the method for preparing the solar cell in Example 4; Figure 9 This is a schematic cross-sectional view of the solar cell in Example 4; Figure 10 This is a top view of the back of the solar cell in Example 4; Figure 11 This is a flowchart of the method for preparing the solar cell in Example 5; Figure 12 This is a schematic cross-sectional view of the solar cell in Example 5; Figure 13This is a top view of the back of the solar cell in Example 5; Figure 14 This is a flowchart of the method for preparing the solar cell in Example 6; Figure 15 This is a schematic cross-sectional view of the solar cell in Example 6; Figure 16 This is a top view of the back of the solar cell in Example 6; Figure 17 This is a flowchart of the method for preparing the solar cell in Example 7; Figure 18 This is a schematic cross-sectional view of the solar cell in Example 7; Figure 19 This is a top view of the back of the solar cell in Example 7; Figure 20 This is a top view of the front structure of the solar cell in Example 7; Figure 21 This is a flowchart of the method for preparing the solar cell in Example 8; Figure 22 This is a schematic cross-sectional view of the solar cell in Example 8; Figure 23 This is a top view of the back of the solar cell in Example 8; Figure 24 This is a top view of the front structure of the solar cell in Example 8. Detailed Implementation

[0034] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0035] Example 1 Please see Figure 1 , Figure 2 This embodiment provides a method for preparing a solar cell, which includes the following steps: S110: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S120: A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate; S130: A first passivation layer is formed on the first intermediate; S140: Print the first electrode paste on the first passivation layer above the first electrode region to obtain the second intermediate; S150: Sinter the second intermediate.

[0036] The first doped layer 310 includes a first electrode region 311 for contacting the first electrode 510. The dopant elements in the first doped source layer and the dopant elements in the first doped layer 310 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer, forming a first co-doped region 610 within the first doped layer 310 in the first electrode region 311, co-doped with the dopant elements of the first doped layer 310, the dopant elements of the first doped source layer, and the metal in the first electrode paste. The first co-doped region 610 contains a large number of dopant elements, which can form more active charge carriers within the first doped layer 310, thereby enhancing the conductivity of the first doped layer 310, reducing the contact resistance, and ultimately improving the short-circuit current, fill factor, and conversion efficiency of the solar cell.

[0037] Specifically, in step S110, the silicon substrate 100 can be P-type single-crystal silicon or N-type single-crystal silicon, but is not limited thereto. When the silicon substrate 100 is N-type single-crystal silicon, the doping element can be one or more of phosphorus (P), bismuth (Bi), antimony (Sb), and arsenic (As), but is not limited thereto. When the silicon substrate 100 is P-type single-crystal silicon, the doping element can be one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In), but is not limited thereto. In terms of thickness, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0038] Specifically, in step S110, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0039] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, in some embodiments, the first tunneling layer 210 is a silicon oxide layer.

[0040] Specifically, in step S110, the first doped layer 310 can be formed by LPCVD or PECVD. More specifically, an intrinsic amorphous silicon layer can be grown by PECVD first, and then annealed, crystallized, and diffused to obtain the first doped layer 310. Alternatively, a doped amorphous silicon layer can be grown by PECVD first, and then annealed and crystallized to obtain the first doped layer 310. Alternatively, an intrinsic polycrystalline silicon layer can be grown by LPCVD first, and then diffused to obtain the first doped layer 310. Alternatively, a doped polycrystalline silicon layer can be grown in situ by PECVD to obtain the first doped layer 310, but these methods are not limited to these.

[0041] The first doped layer 310 is disposed on the first tunneling layer 210, and more specifically, on the side of the first tunneling layer 210 facing away from the first surface 110. Specifically, depending on the type of solar cell, the first doped layer 310 may completely or partially cover the first surface 110. For example, when the solar cell is a TOPCon cell, the first doped layer 310 may completely cover the first surface 110; when the solar cell is a TBC cell, the first doped layer 310 may partially cover the first surface 110. It should be noted that "completely covered" here means substantially completely covered; for example, there may be areas around the silicon substrate 100 that are only covered by a conventional passivation layer and not by the first doped layer 310.

[0042] The first doped layer 310 may be a doped polycrystalline silicon layer, a doped amorphous silicon layer, or a doped microcrystalline silicon layer, but is not limited thereto. More specifically, the first doped layer 310 may be an N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, an N-type amorphous silicon layer, a P-type microcrystalline silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is an N-type polycrystalline silicon layer or a P-type polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, Al, P, As, Sb, or Bi.

[0043] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 If the doping concentration is too low, the introduction of heterogeneous dopant elements into the first doped source layer can easily lead to a decrease in carrier selectivity, affecting the selective transport capability of carriers. If the doping concentration is too high, it can easily form more defects, reducing the passivation quality. For example, the doping concentration of the first doped layer 310 is 2 × 10⁻⁶. 19 cm -3 4×10 19 cm -3 6×10 19 cm -3 8×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 Or 4×10 20 cm -3 However, this is not the only possibility. Preferably, in some embodiments, the doping concentration of the first doped layer 310 is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 .

[0044] Specifically, in step S120, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a borosilicate glass layer (BSG) or a phosphosilicate glass layer (PSG), which can be formed through a diffusion process. The first doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited thereto. Preferably, in some embodiments, the first doped source layer includes a doped polycrystalline silicon layer, formed by PECVD or LPCVD. Based on this, the fabrication process of the first doped source layer can be integrated with the fabrication of other battery structure layers, improving fabrication efficiency. The doping element of the first doped source layer is one or more of B, Ga, In, Al, P, As, Sb, or Bi, but is not limited thereto.

[0045] Specifically, in step S130, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0046] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0047] Specifically, in step S140, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0048] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Ag and / or Al.

[0049] Specifically, in step S140, the second intermediate is sintered in a sintering furnace. After sintering, it can be sorted and tested to obtain a solar cell.

[0050] Specifically, the solar cells prepared by the preparation method of this embodiment can be TOPCon cells, POLO cells, HPBC cells, TBC cells, etc., but are not limited to these.

[0051] Preferably, please refer to Figure 3In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed along the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0052] Preferably, please refer to Figure 3 In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0053] Example 2 Please see Figure 2 , Figure 4 This embodiment provides a method for preparing a solar cell, which includes the following steps: S211: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S212: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; S213: A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate; S214: A first passivation layer is formed on the first intermediate; S215: Print the first electrode paste on the first passivation layer above the first electrode region; S216: Print the second electrode paste on the first passivation layer above the first preset region to obtain the second intermediate; S217: Sinter the second intermediate.

[0054] The first doped layer 310 includes a first electrode region 311 for contacting the first electrode 510. The dopant elements in the first doped source layer and the dopant elements in the first doped layer 310 have opposite polarities. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer, forming a first co-doped region 610 within the first doped layer 310 in the first electrode region 311. This co-doped region 610 contains a large number of dopant elements, which can form more activated charge carriers within the first doped layer 310, thereby enhancing the conductivity of the first doped layer 310, reducing the contact resistance, and ultimately improving the short-circuit current, fill factor, and conversion efficiency of the solar cell.

[0055] Specifically, in step S211, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0056] Specifically, in step S211, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0057] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0058] Specifically, in step S211, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the first doped layer 310 is P.

[0059] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0060] Specifically, in step S212, the first tunneling layer 210 and the first doped layer 310 of the first preset region 112 can be removed by photolithography, laser etching, or wet etching to expose part of the first surface 110 of the silicon substrate 100 for later formation of the second electrode 520.

[0061] Specifically, in some implementations, in step S212, a portion of the silicon substrate 100 within the first preset region 112 may be removed to prevent the doping elements in the first doped layer 310 from abnormally diffusing into the silicon substrate 100 and affecting the contact between the second electrode 520 and the silicon substrate 100.

[0062] Specifically, in step S213, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a borosilicate glass layer (BSG) or a phosphosilicate glass layer (PSG), which can be formed through a diffusion process. The first doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the first doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the first doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0063] The doping element of the first doped source layer is one or more of B, Ga, In, and Al, but is not limited to these. Preferably, the doping element of the first doped source layer is B.

[0064] Specifically, in step S214, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0065] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0066] The first passivation layer 410 covers the silicon substrate 100, which includes the first doped layer 310, the first doped source layer, and the first preset region 112.

[0067] Preferably, in some embodiments, step S214 further includes the step of forming an antireflection layer and / or a passivation layer on the second surface 120 of the silicon substrate 100.

[0068] Specifically, in step S215, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0069] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Ag.

[0070] Specifically, in step S216, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0071] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Al.

[0072] Specifically, in step S217, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain a solar cell.

[0073] Preferably, please refer to Figure 3 In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0074] Preferably, please refer to Figure 3 In some embodiments, the width of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0075] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figure 2 , Figure 3As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a first passivation layer 410, a first electrode 510, and a second electrode 520 are disposed on a first surface 110 (i.e., the back side) of the silicon substrate 100. The first surface 110 of the silicon substrate 100 includes a first region 111 and a first predetermined region 112 alternately distributed along a second direction. The first tunneling layer 210, the first doped layer 310, and the first electrode 510 are disposed within the first region 111, and the second electrode 520 is disposed within the first predetermined region 112. The first doped layer 310 has a first electrode region 311 for forming the first electrode 510. The first electrode region 311 contains doping elements from a first doped source layer, doping elements from the first doped layer 310, and a first co-doped region 610 co-doped with metals from the first electrode paste.

[0076] Example 3 Please see Figure 5 , Figure 6 This embodiment provides a method for preparing a solar cell, which includes the following steps: S221: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S222: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; S223: A first doped source layer is formed on the first doped layer in the first electrode region; S224: A second doped source layer is formed on the silicon substrate in the second electrode region to obtain the first intermediate; S225: A first passivation layer is formed on the first intermediate; S226: Print the first electrode paste on the first passivation layer above the first electrode region; S227: Print the second electrode paste on the first passivation layer above the second electrode region to obtain the second intermediate; S228: Sinter the second intermediate.

[0077] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510, and the silicon substrate 100 of the first preset region 112 has a second electrode region 113 for contacting the second electrode 520. The doping elements of the first doped source layer and the doping elements of the first doped layer 310 have opposite polarities after doping, and the doping elements of the second doped source layer and the doping elements of the silicon substrate 100 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer to form a first co-doped region 610 within the first doped layer 310 of the first electrode region 311, consisting of the doping elements of the first doped layer 310, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. During the sintering process, the second electrode paste burns through the first passivation layer 410 and melts the second doped source layer to form a second co-doped region 620 within the silicon substrate 100 of the second electrode region 113, consisting of the doping elements of the silicon substrate 100, the doping elements of the second doped source layer, and the metal co-doped in the second electrode paste. The first co-doped region 610 and the second co-doped region 620 contain a large number of dopants, which can form more active charge carriers in the first doped layer 310 and the silicon substrate 100, respectively. This enhances the conductivity of the first doped layer 310 and the silicon substrate 100, reduces the contact resistance, and thus improves the short-circuit current, fill factor and conversion efficiency of the solar cell.

[0078] Specifically, in step S221, the silicon substrate 100 is P-type single-crystal silicon. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0079] Specifically, in step S221, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0080] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0081] Specifically, in step S221, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the first doped layer 310 is P.

[0082] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0083] Specifically, in step S222, the first tunneling layer 210 and the first doped layer 310 of the first preset region 112 can be removed by photolithography, laser etching, or wet etching to expose part of the first surface 110 of the silicon substrate 100 for later formation of the second doped source layer and the second electrode 520.

[0084] Specifically, in some implementations, in step S222, a portion of the silicon substrate 100 within the first preset region 112 may be removed to prevent the doping elements in the first doped layer 310 from abnormally diffusing into the silicon substrate 100 and affecting the contact between the second electrode 520 and the silicon substrate 100.

[0085] Specifically, in step S223, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a borosilicate glass (BSG) layer, which can be formed through a diffusion process. The first doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the first doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the first doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0086] The doping element of the first doped source layer is one or more of B, Ga, In, and Al, but is not limited to these. Preferably, the doping element of the first doped source layer is B.

[0087] Specifically, in step S224, the second doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The second doped source layer can also be a borosilicate glass layer (BSG) or a phosphosilicate glass layer (PSG), which can be formed through a diffusion process. The second doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the second doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the second doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0088] The doping element of the second doped source layer is one or more of P, As, Sb, or Bi, but is not limited thereto. Preferably, the doping element of the second doped source layer is P.

[0089] Specifically, in step S225, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0090] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0091] The first passivation layer 410 covers the first doped layer 310, the first doped source layer, the silicon substrate 100 of the first preset region 112, and the second doped source layer.

[0092] Preferably, in some embodiments, step S225 further includes the step of forming an antireflection layer and / or a passivation layer on the second surface 120 of the silicon substrate 100.

[0093] Specifically, in step S226, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0094] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Ag.

[0095] Specifically, in step S227, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0096] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Al.

[0097] Specifically, in step S228, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain a solar cell.

[0098] Preferably, please refer to Figure 7In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0099] Preferably, please refer to Figure 7 In some embodiments, the second co-doped region 620 is continuously or discontinuously distributed in the first direction. Preferably, the second co-doped region 620 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0100] Preferably, please refer to Figure 7 In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0101] Preferably, please refer to Figure 7 In some embodiments, the width of the second co-doped region 620 (in the second direction) is 20% to 80% of the width of the second electrode 520, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the second co-doped region 620 is 20% to 60% of the width of the second electrode 520; based on this range, the conversion efficiency of the solar cell can be improved.

[0102] Preferably, in some embodiments, the doping concentration of the silicon substrate 100 within the second electrode region 113 is 5 × 10⁻⁶. 17 cm -3 ~5×10 19 cm -3 Based on this, co-doping can effectively improve conversion efficiency while ensuring carrier selectivity.

[0103] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figure 6 , Figure 7As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a first passivation layer 410, a first electrode 510, and a second electrode 520 are disposed on a first surface 110 (i.e., the back side) of the silicon substrate 100. The first surface 110 of the silicon substrate 100 includes a first region 111 and a first predetermined region 112 alternately distributed along a second direction. The first tunneling layer 210, the first doped layer 310, and the first electrode 510 are disposed within the first region 111, and the second electrode 520 is disposed within the first predetermined region 112. The first doped layer 310 has a first electrode region 311 for forming the first electrode 510. The first electrode region 311 contains doping elements from a first doped source layer, doping elements from the first doped layer 310, and a first co-doped region 610 co-doped with metals from the first electrode paste. A second electrode region 113 for forming a second electrode 520 is provided on the silicon substrate 100 of the first preset region 112. The second electrode region 113 contains doping elements of the second doped source layer, doping elements of the silicon substrate 100, and a second co-doped region 620 of metal co-doped in the second electrode paste.

[0104] Example 4 Please see Figure 8 , Figure 9 This embodiment provides a method for preparing a solar cell, which includes the following steps: S231: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S232: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; S233: A first inner expansion layer is formed on a silicon substrate in a first preset region; S234: A first doped source layer is formed on the first doped layer in the first electrode region; S235: A second doped source layer is formed on the first inner expansion layer in the second electrode region to obtain a first intermediate; S236: A first passivation layer is formed on the first intermediate; S237: Print the first electrode paste on the first passivation layer above the first electrode region; S238: Print the second electrode paste on the first passivation layer above the second electrode region to obtain the second intermediate; S239: Sinter the second intermediate.

[0105] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510, and the first inner expansion layer 330 has a fourth electrode region 331 for contacting the second electrode 520. The doping elements of the first doped source layer and the doping elements of the first doped layer 310 have opposite polarities after doping, while the doping elements of the second doped source layer have the same polarity as the doping elements of the silicon substrate 100 after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer to form a first co-doped region 610 within the first doped layer 310 of the first electrode region 311, consisting of the doping elements of the first doped layer 310, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. During the sintering process, the second electrode paste burns through the first passivation layer 410 and melts the second doped source layer to form a fourth co-doped region 640 within the first inner expansion layer 330 of the fourth electrode region 331, consisting of the doping elements of the first inner expansion layer 330, the doping elements of the second doped source layer, and the metal co-doped in the second electrode paste. The first co-doped region 610 and the fourth co-doped region 640 contain a large number of doped elements, which can form more activated charge carriers in the first doped layer 310 and the first inner expansion layer 330, respectively. This enhances the conductivity of the first doped layer 310 and the first inner expansion layer 330, reduces the contact resistance, and thus improves the short-circuit current, fill factor and conversion efficiency of the solar cell.

[0106] Specifically, in step S231, the silicon substrate 100 is N-type single-crystal silicon. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0107] Specifically, in step S231, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0108] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0109] Specifically, in step S231, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the first doped layer 310 is P.

[0110] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0111] Specifically, in step S232, the first tunneling layer 210 and the first doped layer 310 of the first preset region 112 can be removed by photolithography etching process, laser etching, or wet etching process to expose part of the first surface 110 of the silicon substrate 100 for later formation of the first inner expansion layer 330, the second doped source layer, and the second electrode 520.

[0112] Specifically, in some implementations, in step S232, a portion of the silicon substrate 100 within the first preset region 112 may be removed to prevent the doping elements in the first doped layer 310 from abnormally diffusing into the silicon substrate 100 and affecting the formation of the first inner expansion layer 330.

[0113] Specifically, in step S233, the first inner expansion layer 330 can be formed through processes such as diffusion or laser doping, but is not limited to these. The doping element of the first inner expansion layer 330 is one or more of B, Ga, In, and Al, but is not limited to these. Preferably, the doping element of the first inner expansion layer 330 is B. The doping concentration of the first inner expansion layer 330 is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 An example is 6×10. 19 cm -3 8×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 4.5×10 20 cm -3 However, it is not limited to this. Preferably, the doping concentration of the first inner extension layer 330 of the fourth electrode region 331 is 5 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

[0114] Specifically, in step S234, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a borosilicate glass (BSG) layer, which can be formed through a diffusion process. The first doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing and inkjet printing, but is not limited to these. Preferably, in some embodiments, the first doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the first doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0115] The doping element of the first doped source layer is one or more of B, Ga, In, and Al, but is not limited to these. Preferably, the doping element of the first doped source layer is B.

[0116] Preferably, in some embodiments, in step S233, a doped silicon paste can be formed first on the silicon substrate 100 of the first preset region 112 and the first doped layer 310 of the first electrode region 311 by screen printing process, and then the first inner expansion layer 330 is formed by laser processing; while the doped silicon paste on the first electrode region 311 directly serves as the first doping source layer.

[0117] Specifically, in step S235, the second doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The second doped source layer can also be a borosilicate glass layer (BSG) or a phosphosilicate glass layer (PSG), which can be formed through a diffusion process. The second doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the second doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the second doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0118] The doping element of the second doped source layer is one or more of P, As, Sb, or Bi, but is not limited thereto. Preferably, the doping element of the second doped source layer is P.

[0119] Specifically, in step S236, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0120] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0121] The first passivation layer 410 covers the first doped layer 310, the first doped source layer, the silicon substrate 100 of the first preset region 112, the first inner expansion layer 330, and the second doped source layer.

[0122] Preferably, in some embodiments, step S236 further includes the step of forming an antireflection layer and / or a passivation layer on the second surface 120 of the silicon substrate 100.

[0123] Specifically, in step S237, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0124] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Ag.

[0125] Specifically, in step S238, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0126] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Al.

[0127] Specifically, in step S239, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain a solar cell.

[0128] Preferably, please refer to Figure 10 In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0129] Preferably, please refer to Figure 10 In some embodiments, the fourth co-doped region 640 is continuously or discontinuously distributed in the first direction. Preferably, the fourth co-doped region 640 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0130] Preferably, please refer to Figure 10In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0131] Preferably, please refer to Figure 10 In some embodiments, the width (in the second direction) of the fourth co-doped region 640 is 20% to 80% of the width of the second electrode 520, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the fourth co-doped region 640 is 20% to 60% of the width of the second electrode 520; based on this range, the conversion efficiency of the solar cell can be improved.

[0132] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figure 9 , Figure 10 As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a first passivation layer 410, a first electrode 510, and a second electrode 520 are disposed on a first surface 110 (back side) of the silicon substrate 100. The first surface 110 of the silicon substrate 100 includes a first region 111 and a first predetermined region 112 alternately distributed along a second direction. The first tunneling layer 210, the first doped layer 310, and the first electrode 510 are disposed within the first region 111, and the second electrode 520 is disposed within the first predetermined region 112. The first doped layer 310 has a first electrode region 311 for forming the first electrode 510. The first electrode region 311 contains doping elements from a first doped source layer, doping elements from the first doped layer 310, and a first co-doped region 610 co-doped with metals from the first electrode paste. A first inner expansion layer 330 is formed on the silicon substrate 100 of the first preset region 112. The first inner expansion layer 330 is provided with a fourth electrode region 331 for forming the second electrode 520. The fourth electrode region 331 is formed with doping elements of the second doping source layer, doping elements of the silicon substrate 100, and a fourth co-doped region 640 of metal co-doped in the second electrode paste.

[0133] Example 5 Please see Figure 11 , Figure 12This embodiment provides a method for preparing a solar cell, which includes the following steps: S311: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S312: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; S313: A second tunneling layer 220 and a second doped layer are sequentially formed on the silicon substrate and the first doped layer in the first preset region; S314: Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form a first doped source layer and obtain a first intermediate; S315: A first passivation layer is formed on the first intermediate; S316: Print the first electrode paste on the first passivation layer above the first electrode region; S317: Print the second electrode paste on the first passivation layer above the third electrode region to obtain the second intermediate; S318: Sinter the second intermediate.

[0134] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510. The dopant elements of the first doped source layer and the dopant elements of the first doped layer 310 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer, forming a first co-doped region 610 within the first doped layer 310 in the first electrode region 311, co-doped with the dopant elements of the first doped layer 310, the dopant elements of the first doped source layer, and the metal in the first electrode paste. The first co-doped region 610 contains a large number of dopant elements, which can form more activated charge carriers within the first doped layer 310, thereby enhancing the conductivity of the first doped layer 310, reducing the contact resistance, and ultimately improving the short-circuit current, fill factor, and conversion efficiency of the solar cell.

[0135] Specifically, in step S311, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0136] Specifically, in step S311, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0137] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0138] Specifically, in step S311, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, or a P-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is a P-type polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, or Al. More preferably, the doping element of the first doped layer 310 is B.

[0139] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0140] Specifically, in step S312, the first tunneling layer 210 and the first doped layer 310 of the first preset region 112 can be removed by photolithography, laser etching, or wet etching to expose part of the first surface 110 of the silicon substrate 100 for later formation of the second tunneling layer 220, the second doped layer 320, and the second electrode 520.

[0141] Specifically, in some implementations, in step S312, a portion of the silicon substrate 100 within the first preset region 112 may be removed.

[0142] Specifically, in step S313, the second tunneling layer 220 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited thereto. Preferably, in some embodiments, the second tunneling layer 220 is formed by thermal oxidation.

[0143] The second tunneling layer 220 is disposed on the first surface 110, and may be a stack formed of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the second tunneling layer 220 is a silicon oxide layer.

[0144] Specifically, in step S313, the second doped layer 320 can be formed by LPCVD or PECVD, but is not limited thereto. The second doped layer 320 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the second doped layer 320 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the second doped layer 320 is P.

[0145] The doping concentration of the second doped layer 320 is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 For example, 2×10 20 cm -3 4×10 20 cm -3 6×10 20 cm -3 Or 8×10 20 cm -3 However, it is not limited to this. Preferably, the doping concentration of the second doped layer 320 is 2 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0146] Specifically, in step S314, the second tunneling layer 220 and the second doped layer 320 in the second preset region can be removed by photolithography, laser etching, or wet etching, but are not limited thereto. Preferably, in some embodiments, in step S313, a mask layer is first formed, then the second preset region is selectively etched to form the second tunneling layer 220 and the second doped layer 320. Finally, in step S314, the mask layer and the second tunneling layer 220 and the second doped layer 320 above the mask layer are removed to form the first doped source layer.

[0147] Specifically, in step S315, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0148] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0149] The first passivation layer 410 covers the first doped layer 310, the first doped source layer, the silicon substrate 100 of the first preset region 112, and the second doped layer 320.

[0150] Preferably, in some embodiments, step S315 further includes the step of forming an antireflection layer and / or a passivation layer on the second surface 120 of the silicon substrate 100.

[0151] Specifically, in step S316, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0152] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Al.

[0153] Specifically, in step S317, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0154] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Ag.

[0155] Specifically, in step S318, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain a solar cell.

[0156] Preferably, please refer to Figure 13 In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0157] Preferably, please refer to Figure 13In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0158] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figure 12 , 13 As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a second tunneling layer 220, a second doped layer 320, a first passivation layer 410, a first electrode 510, and a second electrode 520 are disposed on a first surface 110 (i.e., the back side) of the silicon substrate 100. The first surface 110 of the silicon substrate 100 includes a first region 111 and a first predetermined region 112 alternately distributed along a second direction. The first tunneling layer 210, the first doped layer 310, and the first electrode 510 are disposed within the first region 111, while the second tunneling layer 220, the second doped layer 320, and the second electrode 520 are disposed within the first predetermined region 112. The first doped layer 310 has a first electrode region 311 for forming the first electrode 510. The first electrode region 311 contains doping elements from a first doped source layer, doping elements from the first doped layer 310, and a first co-doped region 610 co-doped with metals from a first electrode paste. The second doped layer 320 has a third electrode region 321 for forming the second electrode 520.

[0159] Example 6 Please see Figure 14 , Figure 15 This embodiment provides a method for preparing a solar cell, which includes the following steps: S321: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; S322: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; S323: A second tunneling layer and a second doped layer are sequentially formed on the silicon substrate and the first doped layer in the first preset region; S324: Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form the first doped source layer; S325: A second doped source layer is formed on the second doped layer in the third electrode region to obtain the first intermediate; S326: A first passivation layer is formed on the first intermediate; S327: Print the first electrode paste on the first passivation layer above the first electrode region; S328: Print the second electrode paste on the first passivation layer above the third electrode region to obtain the second intermediate; S329: Sinter the second intermediate.

[0160] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510, and the second doped layer 320 has a third electrode region 321 for contacting the second electrode 520. The doping elements of the first doped source layer and the first doped layer 310 have opposite polarities after doping, and the doping elements of the second doped source layer and the second doped layer 320 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer to form a first co-doped region 610 within the first doped layer 310 of the first doped layer 310, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. During the sintering process, the second electrode paste burns through the first passivation layer 410 and melts the second doped source layer to form a third co-doped region 630 within the second doped layer 320 of the third electrode region 321, the doping elements of the second doped layer 320, the doping elements of the second doped source layer, and the metal co-doped in the second electrode paste. The first co-doped region 610 and the third co-doped region 630 contain a large number of doped elements, which can form more activated charge carriers in the first doped layer 310 and the second doped layer 320, respectively. This enhances the conductivity of the first doped layer 310 and the second doped layer 320, reduces the contact resistance, and thus improves the short-circuit current, fill factor and conversion efficiency of the solar cell.

[0161] Specifically, in step S321, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0162] Specifically, in step S321, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0163] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0164] Specifically, in step S321, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, or a P-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is a P-type polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, or Al. More preferably, the doping element of the first doped layer 310 is B.

[0165] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0166] Specifically, in step S322, the first tunneling layer 210 and the first doped layer 310 of the first preset region 112 can be removed by photolithography, laser etching, or wet etching to expose part of the first surface 110 of the silicon substrate 100 for later formation of the second tunneling layer 220, the second doped layer 320, and the second electrode 520.

[0167] Specifically, in some implementations, in step S322, a portion of the silicon substrate 100 within the first preset region 112 may be removed.

[0168] Specifically, in step S323, the second tunneling layer 220 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the second tunneling layer 220 is formed by thermal oxidation.

[0169] The second tunneling layer 220 is disposed on the first surface 110, and may be a stack formed of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the second tunneling layer 220 is a silicon oxide layer.

[0170] Specifically, in step S323, the second doped layer 320 can be formed by LPCVD or PECVD, but is not limited thereto. The second doped layer 320 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the second doped layer 320 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the second doped layer 320 is P.

[0171] The doping concentration of the second doped layer 320 is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 For example, 2×10 20 cm -3 4×10 20 cm -3 6×10 20 cm -3 Or 8×10 20 cm -3 However, it is not limited to this. Preferably, the doping concentration of the second doped layer 320 is 2 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0172] Specifically, in step S324, the second tunneling layer 220 and the second doped layer 320 in the second preset region can be removed by photolithography, laser etching, or wet etching, but are not limited thereto. Preferably, in some embodiments, in step S313, a mask layer is first formed, then the second preset region is selectively etched to form the second tunneling layer 220 and the second doped layer 320. Finally, in step S324, the mask layer and the second tunneling layer 220 and the second doped layer 320 above the mask layer are removed to form the first doped source layer.

[0173] Specifically, in step S325, the second doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The second doped source layer can also be a borosilicate glass layer (BSG) or a phosphosilicate glass layer (PSG), which can be formed through a diffusion process. The second doped source layer can also be a doped silicon slurry layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the second doped source layer is a doped silicon slurry layer, which can be formed through a screen printing process. Based on this, the fabrication process of the second doped source layer can be effectively simplified, and the fabrication efficiency can be improved.

[0174] The doping element of the second doped source layer is one or more of B, Ga, In, and Al, but is not limited to these. Preferably, the doping element of the second doped source layer is B.

[0175] Specifically, in step S326, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0176] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially.

[0177] The first passivation layer 410 covers the first doped layer 310, the first doped source layer, the silicon substrate 100 of the first preset region 112, the second doped layer 320, and the second doped source layer.

[0178] Preferably, in some embodiments, step S326 further includes the step of forming an antireflection layer and / or a passivation layer on the second surface 120 of the silicon substrate 100.

[0179] Specifically, in step S327, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0180] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Al.

[0181] Specifically, in step S328, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0182] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Ag.

[0183] Specifically, in step S329, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain the solar cell.

[0184] Preferably, please refer to Figure 16In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0185] Preferably, please refer to Figure 16 In some embodiments, the third co-doped region is continuously or discontinuously distributed in the first direction. Preferably, the third co-doped region is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0186] Preferably, please refer to Figure 16 In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0187] Preferably, please refer to Figure 16 In some embodiments, the width of the third co-doped region (in the second direction) is 20% to 80% of the width of the second electrode 520, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the third co-doped region is 20% to 60% of the width of the second electrode 520. Based on this range, it can be ensured that the second doped layer 320 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0188] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figure 15 , Figure 16As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a second tunneling layer 220, a second doped layer 320, a first passivation layer 410, a first electrode 510, and a second electrode 520 are disposed on a first surface 110 of the silicon substrate 100. The first surface 110 of the silicon substrate 100 includes a first region 111 and a first predetermined region 112 alternately distributed along a second direction. The first tunneling layer 210, the first doped layer 310, and the first electrode 510 are disposed within the first region 111, while the second tunneling layer 220, the second doped layer 320, and the second electrode 520 are disposed within the first predetermined region 112. A first electrode region 311 for forming the first electrode 510 is provided on the first doped layer 310. The first electrode region 311 contains doping elements from a first doped source layer, doping elements from the first doped layer 310, and a first co-doped region 610 co-doped with metals from a first electrode paste. The second doped layer 320 has a third electrode region 321 for forming the second electrode 520. The third electrode region 321 contains the doping elements of the second doped source layer, the doping elements of the second doped layer 320, and a third co-doped region 630 of the metal co-doped in the second electrode paste.

[0189] Example 7 Please see Figure 17 , Figure 18 This embodiment provides a method for preparing a solar cell, which includes the following steps: S411: A second inner extension layer is formed on the second surface of a silicon substrate; S412: A first tunneling layer and a first doped layer are sequentially formed on the first surface of a silicon substrate; S413: A first doped source layer is formed on the first doped layer in the first electrode region; S414: A second doped source layer is formed on the second inner extension layer in the fourth electrode region to obtain the first intermediate; S415: A second passivation layer is formed on the side where the second surface of the first intermediate is located; S416: A first passivation layer is formed on the side where the first surface of the first intermediate is located; S417: Print the first electrode paste on the first passivation layer above the first electrode region; S418: Print the second electrode paste on the second passivation layer above the fourth electrode region to obtain the second intermediate; S419: Sinter the second intermediate.

[0190] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510, and the second inner expansion layer 340 has a fourth electrode region 331 for contacting the second electrode 520. The doping elements of the first doped source layer and the doping elements of the first doped layer 310 have opposite polarities after doping, and the doping elements of the second doped source layer and the doping elements of the second inner expansion layer 340 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer to form a first co-doped region 610 within the first doped layer 310 of the first electrode region 311, consisting of the doping elements of the first doped layer 310, the doping elements of the first doped source layer, and the metal co-doped in the first electrode paste. During the sintering process, the second electrode paste burns through the second passivation layer 420 and melts the second doped source layer to form a fourth co-doped region 640 within the second inner expansion layer 340 of the fourth electrode region 331, consisting of the doping elements of the second inner expansion layer 340, the doping elements of the second doped source layer, and the metal co-doped in the second electrode paste. The first co-doped region 610 and the fourth co-doped region 640 contain a large number of dopants, which can form more active charge carriers in the first doped layer 310 and the second inner expansion layer 340, respectively. This enhances the conductivity of the first doped layer 310 and the second inner expansion layer 340, reduces the contact resistance, and thus improves the short-circuit current, fill factor and conversion efficiency of the solar cell.

[0191] Specifically, in step S411, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0192] Specifically, in step S411, the second inner expansion layer 340 can be formed by diffusion, but is not limited thereto. Specifically, the doping element of the second inner expansion layer 340 is one or more of B, Ga, In, Al, P, As, Sb, or Bi, but is not limited thereto. Preferably, the doping element of the second inner expansion layer 340 is B, Ga, In, or Al, more preferably B. The doping concentration of the second inner expansion layer 340 within the fourth electrode region 331 is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3。 For example, 7×10 19 cm -3 9×10 19 cm -3 1×10 20 cm -3 Or 3×10 20 cm -3 However, it is not limited to this. Preferably, it is 5×10. 19 cm -3 ~3×1020 cm -3 .

[0193] Specifically, in step S412, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0194] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0195] Specifically, in step S412, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is an N-type polycrystalline silicon layer, and its doping element is one or more of P, As, Sb, or Bi. More preferably, the doping element of the first doped layer 310 is P.

[0196] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0197] Specifically, in step S413, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a borosilicate glass (BSG) layer, which can be formed through a diffusion process. The first doped source layer can also be a doped silicon paste layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the first doped source layer is a doped silicon paste layer, which can be formed through a printing process, simplifying the fabrication process.

[0198] Specifically, in step S414, the second doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The second doped source layer can also be a phosphosilicate glass (PSG) layer, which can be formed through a diffusion process. The second doped source layer can also be a doped silicon paste layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the second doped source layer is a doped silicon paste layer, which can be formed through a printing process, simplifying the fabrication process.

[0199] Specifically, in step S415, the second passivation layer 420 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the second passivation layer 420 is formed by PECVD.

[0200] The second passivation layer 420 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the second passivation layer 420 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially. The second passivation layer 420 covers the second inner expansion layer 340.

[0201] Specifically, in step S416, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0202] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially. The first passivation layer 410 covers the first doped layer 310 and the first doped source layer.

[0203] Specifically, in step S417, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0204] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Ag.

[0205] Specifically, in step S418, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0206] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Al.

[0207] Specifically, in step S419, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain the solar cell.

[0208] Preferably, please refer to Figure 19 In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0209] Preferably, please refer to Figure 20 In some embodiments, the fourth co-doped region 640 is continuously or discontinuously distributed in the first direction. Preferably, the second doped source layer is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0210] Preferably, please refer to Figure 19 In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0211] Preferably, please refer to Figure 20 In some embodiments, the width (in the second direction) of the fourth co-doped region 640 is 20% to 80% of the width of the second electrode 520, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the fourth co-doped region 640 is 20% to 60% of the width of the second electrode 520. Based on this range, it can be ensured that the second doped layer 320 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0212] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figures 18-20As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a first passivation layer 410, and a first electrode 510 are disposed on a first surface 110 (i.e., the back side) of the silicon substrate 100. A second inner expansion layer 340, a second passivation layer 420, and a second electrode 520 are disposed on a second surface 120 (i.e., the front side) of the silicon substrate 100. A first electrode region 311 for forming the first electrode 510 is disposed on the first doped layer 310. The first electrode region 311 contains doped elements of the first doped source layer, doped elements of the first doped layer 310, and a first co-doped region 610 co-doped with metal from the first electrode paste. A fourth electrode region 331 for forming the second electrode 520 is disposed on the second inner expansion layer 340. The fourth electrode region 331 contains doped elements of the second doped source layer, doped elements of the second inner expansion layer 340, and a fourth co-doped region 640 co-doped with metal from the second electrode paste.

[0213] Example 8 Please see Figure 21 , Figure 22 This embodiment provides a method for preparing a solar cell, which includes the following steps: S511: A first tunneling layer and a first doped layer are sequentially formed on the first surface of a silicon substrate; S512: A second tunneling layer and a second doped layer are sequentially formed on the second surface of a silicon substrate; S513: A first doped source layer is formed on the first doped layer in the first electrode region; S514: A second doped source layer is formed on the second doped layer in the third electrode region to obtain the first intermediate; S515: A second passivation layer is formed on the side where the second surface of the first intermediate is located; S516: A first passivation layer is formed on the side where the first surface of the first intermediate is located; S517: Print the first electrode paste on the first passivation layer above the first electrode region; S518: Print the second electrode paste on the second passivation layer above the third electrode region to obtain the second intermediate; S519: Sinter the second intermediate.

[0214] The first doped layer 310 has a first electrode region 311 for contacting the first electrode 510, and the second doped layer 320 has a third electrode region 321 for contacting the second electrode 520. The dopant elements in the first doped source layer and the dopant elements in the first doped layer 310 have opposite polarities after doping, and the dopant elements in the second doped source layer and the dopant elements in the second doped layer 320 have opposite polarities after doping. During the sintering process of the second intermediate, the first electrode paste burns through the first passivation layer 410 and melts the first doped source layer to form a first co-doped region 610 within the first doped layer 310 of the first electrode region 311, consisting of the dopant elements of the first doped layer 310, the dopant elements of the first doped source layer, and the metal co-doped in the first electrode paste. During the sintering process, the second electrode paste burns through the second passivation layer 420 and melts the second doped source layer to form a third co-doped region 630 within the second doped layer 320 of the third electrode region 321, consisting of the dopant elements of the second doped layer 320, the dopant elements of the second doped source layer, and the metal co-doped in the second electrode paste. The first co-doped region 610 and the third co-doped region 630 contain a large number of doped elements, which can form more activated charge carriers in the first doped layer 310 and the second doped layer 320, respectively. This enhances the conductivity of the first doped layer 310 and the second doped layer 320, reduces the contact resistance, and thus improves the short-circuit current, fill factor and conversion efficiency of the solar cell.

[0215] Specifically, in step S511, the silicon substrate 100 may be P-type monocrystalline silicon or N-type monocrystalline silicon, but is not limited thereto. In the thickness direction, the silicon substrate 100 includes a first surface 110 and a second surface 120 disposed opposite to each other.

[0216] Specifically, in step S511, the first tunneling layer 210 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the first tunneling layer 210 is formed by thermal oxidation.

[0217] The first tunneling layer 210 is disposed on the first surface 110, and may be a stack of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the first tunneling layer 210 is a silicon oxide layer.

[0218] Specifically, in step S511, the first doped layer 310 can be formed by LPCVD or PECVD, but is not limited thereto. The first doped layer 310 is a P-type polycrystalline silicon layer, a P-type amorphous silicon layer, or a P-type microcrystalline silicon layer, but is not limited thereto. Preferably, the first doped layer 310 is a P-type polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, or Al. More preferably, the doping element of the first doped layer 310 is B.

[0219] The doping concentration of the first doped layer 310 is 1×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 Preferably, it is 5×10 19 cm -3 ~5×10 20 cm -3 .

[0220] Specifically, in step S512, the second tunneling layer 220 can be formed by thermal oxidation, LPCVD, or PECVD, but is not limited to these methods. Preferably, in some embodiments, the second tunneling layer 220 is formed by thermal oxidation.

[0221] The second tunneling layer 220 is disposed on the second surface 120, and may be a stack formed of one or at least two of the following: silicon oxide layer, aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic amorphous silicon layer, silicon carbide layer, and magnesium fluoride layer, but is not limited thereto. Preferably, the second tunneling layer 220 is a silicon oxide layer.

[0222] Specifically, in step S512, the second doped layer 320 can be formed by LPCVD or PECVD, but is not limited thereto. The second doped layer 320 is an N-type polycrystalline silicon layer, an N-type amorphous silicon layer, or an N-type microcrystalline silicon layer, but is not limited thereto. Preferably, the second doped layer 320 is an N-type polycrystalline silicon layer, and its doping element is P, As, Sb, or Bi, but is not limited thereto. More preferably, the doping element of the second doped layer 320 is P.

[0223] The doping concentration of the second doped layer 320 is 1×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 For example, 2×10 20 cm -3 4×10 20 cm -3 6×10 20 cm -3 Or 8×10 20 cm -3 However, it is not limited to this. Preferably, the doping concentration of the second doped layer 320 is 2 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

[0224] Specifically, in step S513, the first doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The first doped source layer can also be a phosphosilicate glass (PSG) layer, which can be formed through a diffusion process. The first doped source layer can also be a doped silicon paste layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the first doped source layer is a doped silicon paste layer, which can be formed through a printing process, simplifying the fabrication process.

[0225] Specifically, in step S514, the second doped source layer can be a doped crystalline silicon layer or a doped amorphous silicon layer, prepared using conventional thin-film fabrication processes. The second doped source layer can also be a borosilicate glass (BSG) layer, which can be formed through a diffusion process. The second doped source layer can also be a doped silicon paste layer, which can be formed through processes such as screen printing or inkjet printing, but is not limited to these. Preferably, in some embodiments, the second doped source layer is a doped silicon paste layer, which can be formed through a printing process, simplifying the fabrication process.

[0226] Specifically, in step S515, the second passivation layer 420 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the second passivation layer 420 is formed by PECVD.

[0227] The second passivation layer 420 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the second passivation layer 420 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially. The second passivation layer 420 covers the second doped layer 320 and the second doped source layer.

[0228] Specifically, in step S516, the first passivation layer 410 can be formed by PECVD, LPCVD, MOCVD, PVD, or ALD, but is not limited to these methods. Preferably, in some embodiments, the first passivation layer 410 is formed by PECVD.

[0229] The first passivation layer 410 is a stacked structure formed by one or more of the following: silicon nitride layer, aluminum oxide layer, silicon oxide layer, and silicon oxynitride layer, but is not limited thereto. Preferably, in some embodiments, the first passivation layer 410 includes an aluminum oxide layer and a silicon nitride layer stacked sequentially. The first passivation layer 410 covers the first doped layer 310 and the first doped source layer.

[0230] Specifically, in step S517, the first electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the first electrode paste is printed using a screen printing process.

[0231] The metal in the first electrode paste may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the first electrode paste is Al.

[0232] Specifically, in step S518, the second electrode paste can be printed using processes such as screen printing and inkjet printing, but is not limited to these methods. Preferably, in some embodiments, the second electrode paste is printed using a screen printing process.

[0233] The metal in the second electrode slurry may be one or more of Cu, Ag, Al, Au, and Ni, but is not limited thereto. Preferably, the metal in the second electrode slurry is Ag.

[0234] Specifically, in step S519, the second intermediate is sintered in a sintering furnace. After sintering, the first electrode slurry forms the first electrode 510, and the second electrode slurry forms the second electrode 520. After sintering, sorting and testing can be performed to obtain the solar cell.

[0235] Preferably, please refer to Figure 22 In some embodiments, the first co-doped region 610 is continuously or discontinuously distributed in the first direction. Preferably, the first co-doped region 610 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0236] Preferably, please refer to Figure 23 In some embodiments, the third co-doped region 630 is continuously or discontinuously distributed along the extension direction (i.e., the second direction) of the third electrode region 321. Preferably, the third co-doped region 630 is discontinuously distributed, for example, in the form of multiple spaced strip structures or lattice structures, thereby reducing manufacturing costs while ensuring the doping effect.

[0237] Preferably, please refer to Figure 23 In some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 80% of the width of the first electrode 510, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width (in the second direction) of the first co-doped region 610 is 20% to 60% of the width of the first electrode 510. Based on this range, it can be ensured that the first doped layer 310 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0238] Preferably, please refer to Figure 24In some embodiments, the width (in the second direction) of the third co-doped region 630 is 20% to 80% of the width of the second electrode 520, exemplarily 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, or 80%, but not limited thereto. Preferably, in some embodiments, the width of the third co-doped region 630 is 20% to 60% of the width of the second electrode 520. Based on this range, it can be ensured that the second doped layer 320 has good carrier selectivity, reducing carrier recombination, thereby improving the conversion efficiency of the solar cell.

[0239] Accordingly, this embodiment also discloses a solar cell, the specific structure of which is as follows: Figures 22-24 As shown, it includes a silicon substrate 100. A first tunneling layer 210, a first doped layer 310, a first passivation layer 410, and a first electrode 510 are disposed on a first surface 110 (i.e., the back side) of the silicon substrate 100. A second tunneling layer 220, a second doped layer 320, a second passivation layer 420, and a second electrode 520 are disposed on a second surface 120 (i.e., the front side) of the silicon substrate 100. A first electrode region 311 for forming the first electrode 510 is formed in the first electrode region 311, containing doping elements of the first doped source layer, doping elements of the first doped layer 310, and a first co-doped region 610 co-doped with metal from the first electrode paste. A third electrode region 321 for forming the second electrode 520 is formed in the second doped layer 320, containing doping elements of the second doped source layer, doping elements of the second doped layer 320, and a third co-doped region 630 co-doped with metal from the second electrode paste.

[0240] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of the present invention to facilitate a specific and detailed understanding of the technical solution of the present invention, but should not be construed as limiting the scope of protection of the invention patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that, include: A first tunneling layer and a first doped layer are sequentially formed on a silicon substrate; wherein, the first doped layer has a first electrode region for contacting a first electrode; A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate; wherein the doping element of the first doped source layer has the opposite polarity to the doped element of the first layer. A first passivation layer is formed on the first intermediate; wherein the first passivation layer covers the first doped layer and the first doped source layer; A first electrode paste is printed on a first passivation layer above the first electrode region to obtain a second intermediate. The second intermediate is sintered; wherein, during the sintering process, the first electrode slurry burns through the first passivation layer and melts the first doping source layer to form the doping element of the first doping layer, the doping element of the first doping source layer, and the first co-doped region of the metal co-doped in the first electrode slurry within the first doping layer of the first electrode region.

2. The method for preparing a solar cell as described in claim 1, characterized in that, The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A first doped source layer is formed on the first doped layer in the first electrode region to obtain a first intermediate. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the first preset region to obtain a second intermediate.

3. The method for preparing a solar cell as described in claim 1, characterized in that, The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: The first tunneling layer and the first doped layer in the first preset region are removed to expose the silicon substrate in the first preset region; wherein, the silicon substrate in the first preset region is provided with a second electrode region for contacting the second electrode; A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on a silicon substrate in the second electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the silicon substrate after doping. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on a first passivation layer above the second electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode paste burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping element of the silicon substrate, the doping element of the second doping source layer, and the second co-doped region of the metal co-doped in the second electrode paste within the silicon substrate of the second electrode region.

4. The method for preparing a solar cell as described in claim 1, characterized in that, The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A first inner expansion layer is formed on a silicon substrate in a first predetermined region, wherein the doping polarity of the first inner expansion layer is opposite to that of the silicon substrate; wherein the first inner expansion layer is provided with a fourth electrode region for contacting a second electrode. A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the first inner expansion layer of the fourth electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the same polarity as the doping element of the silicon substrate after doping. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the fourth electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the first inner expansion layer, the doping elements of the second doping source layer, and the fourth co-doped region of metal co-doped in the second electrode slurry within the first inner expansion layer of the fourth electrode region.

5. The method for preparing a solar cell as described in claim 1, characterized in that, The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A second tunneling layer and a second doped layer are sequentially formed on a silicon substrate in the first preset region and on the first doped layer; wherein the polarities of the first doped layer and the second doped layer are opposite; the second doped layer is provided with a third electrode region for contacting the second electrode; Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form a first doped source layer, thereby obtaining a first intermediate. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the third electrode region to obtain a second intermediate. The silicon substrate includes a first surface and a second surface disposed opposite to each other, and both the first doped layer and the second doped layer are disposed on the first surface.

6. The method for preparing a solar cell as described in claim 1, characterized in that, The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: Remove the first tunneling layer and the first doped layer in the first preset region to expose the silicon substrate in the first preset region; A second tunneling layer and a second doped layer are sequentially formed on a silicon substrate in the first preset region and on the first doped layer; wherein the polarities of the first doped layer and the second doped layer are opposite; the second doped layer is provided with a third electrode region for contacting the second electrode; Remove the second tunneling layer and the second doped layer in the second preset region on the first doped layer, and retain only the second tunneling layer and the second doped layer on the first doped layer in the first electrode region to form the first doped source layer; A second doped source layer is formed on the second doped layer in the third electrode region to obtain a first intermediate; wherein the polarity of the doping element in the second doped source layer is opposite to that of the doping element in the second doped layer. The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the first passivation layer above the third electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the first passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the second doping layer, the doping elements of the second doping source layer, and the third co-doped region of metal co-doping in the second electrode slurry in the second doping layer of the third electrode region. The silicon substrate includes a first surface and a second surface disposed opposite to each other, and both the first doped layer and the second doped layer are disposed on the first surface.

7. The method for preparing a solar cell as described in claim 1, characterized in that, The step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A second inner expansion layer is formed on the second surface of the silicon substrate; wherein the polarity of the second inner expansion layer is opposite to that of the silicon substrate; the second inner expansion layer is provided with a fourth electrode region for contacting the second electrode; A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the fourth electrode region to obtain a second intermediate.

8. The method for preparing a solar cell as described in claim 1, characterized in that, The step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A second inner expansion layer is formed on the second surface of the silicon substrate, the second inner expansion layer having a polarity opposite to that of the silicon substrate; wherein the second inner expansion layer has a fourth electrode region for contacting the second electrode; A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the second inner expansion layer in the fourth electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the second inner expansion layer after doping. The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the fourth electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the second passivation layer and melts the second doping source layer during the sintering process, so as to form the doping elements of the second inner expansion layer, the doping elements of the second doping source layer, and the fourth co-doped region of metal co-doped in the second electrode slurry in the second inner expansion layer of the fourth electrode region.

9. The method for preparing a solar cell as described in claim 1, characterized in that, The step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; A second tunneling layer and a second doped layer are sequentially formed on the second surface of the silicon substrate; wherein the second doped layer has a third electrode region for contacting the second electrode; The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the third electrode region to obtain a second intermediate.

10. The method for preparing a solar cell according to claim 1, characterized in that, The step of sequentially forming a first tunneling layer and a first doped layer on a silicon substrate includes: A first tunneling layer and a first doped layer are sequentially formed on the first surface of the silicon substrate; A second tunneling layer and a second doped layer are sequentially formed on the second surface of the silicon substrate; wherein the second doped layer has a third electrode region for contacting the second electrode; The step of forming a first doped source layer on a first doped layer in the first electrode region to obtain a first intermediate includes: A first doped source layer is formed on the first doped layer in the first electrode region; A second doped source layer is formed on the second doped layer in the third electrode region to obtain a first intermediate; wherein the doping element of the second doped source layer has the opposite polarity to the doping element of the second doped layer after doping. The step of forming the first passivation layer on the first intermediate includes: A second passivation layer is formed on the side where the second surface of the first intermediate is located; A first passivation layer is formed on one side of the first surface of the first intermediate; The step of printing a first electrode paste onto a first passivation layer above the first electrode region to obtain a second intermediate includes: Print the first electrode paste on the first passivation layer above the first electrode region; A second electrode paste is printed on the second passivation layer above the third electrode region to obtain a second intermediate. In the step of sintering the second intermediate, the second electrode slurry burns through the second passivation layer and melts the second doping source layer during the sintering process, so as to form the doping element of the second doping layer, the doping element of the second doping source layer, and the third co-doped region of metal co-doped in the second electrode slurry within the second doping layer of the third electrode region.

11. The method for preparing a solar cell according to any one of claims 1 to 10, characterized in that, The silicon substrate is N-type monocrystalline silicon or P-type monocrystalline silicon; and / or The first doped layer is a doped polycrystalline silicon layer, and its doping element is one or more of B, Ga, In, Al, P, As, Sb or Bi; and / or The doping element of the first doped source layer is one or more of B, Ga, In, Al, P, As, Sb, or Bi; and / or The first electrode paste comprises Ag and / or Al.

12. The method for preparing a solar cell according to any one of claims 3, 4, 6, 8 or 10, characterized in that, The doping element of the second doped source layer is one or more of B, Ga, In, Al, P, As, Sb, or Bi; and / or The second electrode slurry comprises Ag and / or Al.

13. The method for preparing a solar cell according to any one of claims 5, 6, 9 or 10, characterized in that, The doping element of the second doped layer is one or more of B, Ga, In, Al, P, As, Sb or Bi.

14. The method for preparing a solar cell according to any one of claims 1 to 10, characterized in that, The first electrode is formed by sintering the first electrode slurry. The width of the first co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the first co-doped region is either continuously distributed or discontinuously distributed.

15. The method for preparing a solar cell as described in claim 3, characterized in that, The second electrode is formed after the slurry is sintered. The width of the second co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the second co-doped region is either continuously or discontinuously distributed.

16. The method for preparing a solar cell as described in claim 4 or 8, characterized in that, The second electrode is formed after the slurry is sintered. The width of the fourth co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the fourth co-doped region is either continuously or discontinuously distributed.

17. The method for preparing a solar cell as described in claim 6 or 10, characterized in that, The second electrode is formed after the slurry is sintered. The width of the third co-doped region in the second direction is 20% to 60% of the width of the second electrode in the second direction; and / or Along the first direction, the third co-doped region is either continuously or discontinuously distributed.

18. The method for preparing a solar cell according to any one of claims 5, 6, 9 or 10, characterized in that, The doping concentration of the first doped layer is 5×10 19 cm -3 ~5×10 20 cm -3 The doping concentration of the second doped layer is 2×10⁻⁶. 20 cm -3 ~1×10 21 cm -3 .

19. The method for preparing a solar cell as described in claim 3, characterized in that, The doping concentration of the silicon substrate in the second electrode region is 5 × 10⁻⁶. 17 cm -3 ~5×10 19 cm -3 .

20. The method for preparing a solar cell according to claim 4, characterized in that, The doping concentration of the first inner layer in the fourth electrode region is 5 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

21. The method for preparing a solar cell as described in claim 8, characterized in that, The doping concentration of the second inner layer in the fourth electrode region is 5 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 .

22. The method for preparing a solar cell according to claim 1, characterized in that, The first tunneling layer is a silicon oxide layer; and / or The first passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked sequentially.

23. The method for preparing a solar cell according to any one of claims 5, 6, 9 or 10, characterized in that, The second tunneling layer is a silicon oxide layer.

24. A solar cell, characterized in that, It is prepared by the method of any one of claims 1 to 23.

25. A battery assembly, characterized in that, Including the solar cell as described in claim 24.

26. A photovoltaic system, characterized in that, This includes the battery assembly as described in claim 25, or the solar cell as described in claim 24.

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