Semiconductor device structure and method of fabricating the same

Abstract

The application relates to a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a semiconductor layer, a trench extending from the surface of the semiconductor layer to the interior of the semiconductor layer, a channel layer separated from the semiconductor layer by the trench, and the trench surrounding the channel layer. The channel layer comprises a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer being smaller than that of the second sub-channel layer. The first direction is from the top of the trench to the bottom of the trench. The semiconductor device structure further comprises a gate dielectric layer surrounding the channel layer, the thickness of the gate dielectric layer surrounding the first sub-channel layer being greater than that of the gate dielectric layer surrounding the second sub-channel layer. The semiconductor device structure further comprises a gate electrode located on the surface of the gate dielectric layer away from the channel layer and surrounding the gate dielectric layer. The semiconductor device structure further comprises a source region located in the semiconductor layer exposed by the bottom of the trench, and a drain region located on the side of the first sub-channel layer away from the second sub-channel layer. The semiconductor device structure has good voltage resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] As semiconductor device dimensions continue to shrink, gate channel lengths are decreasing, significantly reducing the ability of traditional planar transistors to control the electric field in the channel region, leading to severe degradation of short-channel effects. This has led to the development of Gate-All-Around FETs (GAAFETs), which enhance gate control over the channel by having the gate completely surround the channel.

[0003] However, in the actual fabrication and application of GAAFETs, due to the constraints of device miniaturization design and structural forming process, the thickness of the gate oxide layer between the all-around gate and the channel is continuously compressed and thinned, resulting in a reduction in the device's withstand voltage capability. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device structure with high voltage resistance and its fabrication method.

[0005] In a first aspect, this application provides a semiconductor device structure, including:

[0006] A semiconductor layer having trenches extending from its surface to its interior, the trenches isolating a channel layer within the semiconductor layer, the trenches surrounding the channel layer; the channel layer includes a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer being smaller than the width of the second sub-channel layer; the first direction extends from the top of the trench to the bottom of the trench.

[0007] A gate dielectric layer surrounds the channel layer; the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer;

[0008] A gate is located on the surface of the gate dielectric layer away from the channel layer and surrounds the gate dielectric layer;

[0009] The source region is located within the semiconductor layer exposed at the bottom of the trench;

[0010] The leak area is located on the side of the first sub-channel layer away from the second sub-channel layer.

[0011] In one embodiment, the semiconductor device structure further includes:

[0012] A drift layer is located between the drain region and the channel layer, and is in contact with both the drain region and the channel layer;

[0013] The ion doping concentration in the drain region is greater than that in the source region.

[0014] In one embodiment, along the first direction, the ratio of the length of the first sub-channel layer to the length of the second sub-channel layer is 3:1 to 7:1.

[0015] In one embodiment, there are multiple trenches and multiple channel layers; the multiple channel layers are arranged at intervals along a second direction, and each channel layer is surrounded by trenches; each channel layer is surrounded by a gate dielectric layer and a gate in sequence; each first sub-channel layer has a drain region on the side away from the second sub-channel layer integrally connected to it; and each channel layer has a source region in the semiconductor layer exposed at the bottom of the trenches on opposite sides.

[0016] The second direction is perpendicular to the first direction.

[0017] Secondly, this application also provides a method for fabricating a semiconductor device structure, comprising:

[0018] Provides a semiconductor layer;

[0019] A trench extending from the surface to the interior of the semiconductor layer is formed therein, the trench isolating a channel layer within the semiconductor layer, the trench surrounding the channel layer; the channel layer includes a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer being smaller than the width of the second sub-channel layer; the first direction extends from the top of the trench to the bottom of the trench;

[0020] A gate dielectric layer and a gate electrode are formed around the periphery of the channel layer; the gate dielectric layer surrounds the channel layer, and the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer; the gate electrode is located on the surface of the gate dielectric layer away from the channel layer and surrounds the gate dielectric layer;

[0021] A source region is formed within the semiconductor layer at the bottom of the trench, and a drain region is formed on the side of the first sub-channel layer away from the second sub-channel layer.

[0022] In one embodiment, forming a trench extending from the surface to the interior of the semiconductor layer includes:

[0023] A patterned mask layer is formed on the surface of the semiconductor layer;

[0024] The semiconductor layer is etched based on the patterned mask layer to form a first sub-trench extending from its surface to its interior within the semiconductor layer. The first sub-trench isolates a first initial sub-channel layer within the semiconductor layer and surrounds the first initial sub-channel layer.

[0025] A dielectric mask layer is formed on the sidewall of the first sub-trench;

[0026] Based on the patterned mask layer and the dielectric mask layer, the semiconductor layer is etched to form a second sub-trench at the bottom of the first sub-trench, which is connected to the first sub-trench. The width of the second sub-trench is smaller than the width of the first sub-trench. The second sub-trench isolates a second initial sub-channel layer that is integrally connected to the first initial sub-channel layer within the semiconductor layer. The width of the second initial sub-channel layer is larger than the width of the first initial sub-channel layer.

[0027] In one embodiment, a gate dielectric layer and a gate are formed around the periphery of the channel layer, including:

[0028] A gate dielectric material layer is formed on the surface of the dielectric mask layer, the sidewalls of the second sub-trench, and the bottom.

[0029] A gate material layer is formed on the surface of the gate dielectric material layer, and the gate material layer fills the trench;

[0030] Remove the gate material layer, gate dielectric material layer, dielectric mask layer, and patterned mask layer located on the first initial sub-channel layer;

[0031] The dielectric mask layer, gate dielectric material layer, and gate material layer located within the trench are removed by etch-back; the retained dielectric mask layer and gate dielectric material layer are the gate dielectric layer; the top of the gate dielectric layer and the top of the retained gate material layer are lower than the top of the trench;

[0032] An isolation trench is formed within the gate material layer retained in the trench, the isolation trench penetrating the gate material layer along the first direction, and the retained gate material layer is the gate.

[0033] In one embodiment, the thickness of the dielectric mask layer is 10 angstroms to 100 angstroms, and the thickness of the gate dielectric material layer is 1 angstrom to 10 angstroms.

[0034] In one embodiment, after etching back and removing portions of the dielectric mask layer, gate dielectric material layer, and gate material layer located within the trench, and before forming an isolation trench within the gate material layer remaining in the trench, the method further includes:

[0035] Ion implantation is performed on the upper part of the first initial sub-channel layer to transform the upper part of the first initial sub-channel layer into a drift layer; the retained first initial sub-channel layer is the first sub-channel layer, and the second initial sub-channel layer is the second sub-channel layer.

[0036] In one embodiment, a source region is formed within the semiconductor layer at the bottom of the trench, and a drain region is formed on the side of the first sub-channel layer away from the second sub-channel layer, including:

[0037] Ion implantation is performed on the side of the semiconductor layer at the bottom of the trench and the first sub-channel layer away from the second sub-channel layer to form the source region and the drain region.

[0038] An unexpected effect of this application is:

[0039] In the semiconductor device structure provided in this embodiment, a first sub-trench and a second sub-trench are formed by etching the semiconductor layer twice. The first sub-trench surrounds the first sub-channel layer, and the second sub-trench surrounds the second sub-channel layer. A gate dielectric layer and a gate are formed on the periphery of the channel layer. The width of the first sub-trench is greater than the width of the second sub-trench. The wider sub-trench can accommodate a thicker gate dielectric layer, which makes the thickness of the gate dielectric layer surrounding the first sub-channel layer in the first sub-trench greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer in the second sub-trench. That is, the thickness of the gate dielectric layer near the drain region is increased, which can improve the breakdown voltage of the device and enhance the device's withstand voltage performance.

[0040] In this embodiment, when a drift layer is formed on the drain side of the semiconductor device structure, the gate material layer a is used as a barrier layer for ion implantation, which can save on the photomask.

[0041] The semiconductor device structure provided in this embodiment has a drift layer formed on the drain side, and the ion doping type of the drift layer is the same as that of the drain region. This results in the ion doping concentration of the drain region being greater than that of the source region. In addition, the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than that surrounding the second sub-channel layer, forming a quasi-laterally diffused metal oxide semiconductor (LDMOS) structure. By adjusting the doping concentration of the drift layer and the thickness of the gate dielectric layer, the voltage can be basically exhausted in the drift region, avoiding electric field spikes in the device junction region, which can further improve the device's breakdown voltage performance. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device structure provided in one embodiment;

[0044] Figure 2 A cross-sectional schematic diagram of a semiconductor device structure provided for another embodiment;

[0045] Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor device structure according to one embodiment.

[0046] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S202 of the semiconductor device structure fabrication method provided in one embodiment;

[0047] Figure 5 This is a schematic cross-sectional view of the intermediate structure in step S203 of a method for fabricating a semiconductor device structure provided in an embodiment.

[0048] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S203 of the semiconductor device structure fabrication method provided in one embodiment;

[0049] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S204 of the semiconductor device structure fabrication method provided in one embodiment;

[0050] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S301 of the method for fabricating a semiconductor device structure according to an embodiment;

[0051] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S303 of the semiconductor device structure fabrication method provided in one embodiment;

[0052] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S304 of the semiconductor device structure fabrication method provided in one embodiment;

[0053] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S400 of the method for fabricating a semiconductor device structure according to an embodiment.

[0054] Explanation of reference numerals in the attached figures:

[0055] 100 - Semiconductor layer, 101 - First sub-channel layer, 101a - First initial sub-channel layer, 102 - Second sub-channel layer, 200 - Gate dielectric layer, 201 - Dielectric mask layer, 201a - Dielectric mask material layer, 202 - Gate dielectric material layer, 300 - Gate, 300a - Gate material layer, 400 - Source region, 500 - Drain region, 600 - Drift layer, 700 - Substrate, 800 - Patterned mask layer, 901 - First sub-trench, 902 - Second sub-trench, 1000 - Isolation trench. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," or "directly connected to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0061] In one embodiment, this application provides a semiconductor device structure, such as... Figure 1 As shown, it may include a semiconductor layer 100, a gate dielectric layer 200, a gate 300, a source region 400, and a drain region 500.

[0062] The semiconductor layer 100 has trenches extending from its surface to its interior, the trenches isolating a channel layer within the semiconductor layer 100, and the trenches surround the channel layer. The remaining portion of the semiconductor layer 100 can be used as a well region for a semiconductor device structure, and the semiconductor layer 100 has a first conductivity type. The semiconductor layer material can be any suitable semiconductor material known in the art, including, for example, III-V compound semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), IV compound semiconductors such as silicon carbide (SiC), II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and IV semiconductors such as silicon (Si) and germanium (Ge).

[0063] The trench layer includes a first sub-trench layer 101 and a second sub-trench layer 102 integrally connected along a first direction, wherein the width of the first sub-trench layer 101 is smaller than the width of the second sub-trench layer 102. The first direction extends from the top of the trench to the bottom of the trench.

[0064] The gate dielectric layer 200 surrounds the channel layer, wherein the thickness of the gate dielectric layer 200 surrounding the first sub-channel layer 101 is greater than the thickness of the gate dielectric layer 200 surrounding the second sub-channel layer 102. The gate dielectric layer material can be any suitable gate dielectric material known in the art, for example, it can be composed of SiO2 or a material with a dielectric constant greater than SiO2, including oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc.

[0065] Gate 300 is located on the surface of gate dielectric layer 200 away from the channel layer and surrounds gate dielectric layer 200. The gate material can be any suitable gate material known in the art, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi. x Combinations of Ni3Si, Pt, Ru, W, and various conductive materials.

[0066] The source region 400 is located within the semiconductor layer 100 exposed at the bottom of the trench. The source region 400 has a second conductivity type. The second conductivity type is the opposite of the first conductivity type, which is either N-type or P-type, and the second conductivity type is either N-type or P-type.

[0067] Drain region 500 is located on the side of the first sub-channel layer 101 away from the second sub-channel layer 102. Drain region 500 has a second conductivity type.

[0068] In this embodiment, by setting the channel layer to a stepped shape, consisting of a first sub-channel layer 101 and a second sub-channel layer 102 integrally connected along a first direction, and the width of the first sub-channel layer 101 being smaller than the width of the second sub-channel layer 102, the thickness of the gate dielectric layer 200 surrounding the first sub-channel layer 101 after the gate dielectric layer 200 is formed is greater than the thickness of the gate dielectric layer 200 surrounding the second sub-channel layer 102. That is, a thicker gate dielectric layer 200 is formed on the side near the drain region 500, thereby improving the withstand voltage performance of the device.

[0069] In one embodiment, such as Figure 1 As shown, the semiconductor device structure also includes a drift layer 600. The drift layer 600 is located between the drain region 500 and the channel layer, and is in contact with both the drain region 500 and the channel layer. The drift layer has a second conductivity type.

[0070] Furthermore, the ion doping concentration of the drain region 500 is greater than that of the source region 400. The ion doping concentration of the drain region 500 can be approximated as the sum of the ion doping concentration of the drift layer 600 and the ion doping concentration of the source region 400.

[0071] In this embodiment, by setting a drift layer 600 on top of the channel layer, the ion doping concentration of the drain region 500 is greater than that of the source region 400, forming an asymmetric drain region 500 and source region 400. Combined with the fact that the thickness of the gate dielectric layer 200 surrounding the first sub-channel layer 101 is greater than that surrounding the gate dielectric layer 200 of the second sub-channel layer 102, a LDMOS-like structure is formed. By adjusting the doping concentration of the drift layer 600 and the thickness of the gate dielectric layer 200, the voltage can be essentially exhausted in the drift layer 600, avoiding electric field spikes in the device junction region and further improving the device's breakdown voltage performance.

[0072] In one embodiment, along the first direction, the ratio of the length of the first sub-channel layer 101 to the length of the second sub-channel layer 102 is 3:1 to 7:1. For example, the ratio of the length of the first sub-channel layer 101 to the length of the second sub-channel layer 102 can be 3:1, 5:1, or 7:1.

[0073] In this embodiment, the ratio of the length of the first sub-channel layer 101 to the length of the second sub-channel layer 102 is set to 3:1 to 7:1. This can prevent the drain region 500 from being too far from the gate 300, resulting in a longer carrier transport path and affecting the device switching speed. At the same time, it can also prevent the drain region 500 from being too close to the gate 300, which would lead to insufficient high-voltage buffer area in the thick gate dielectric layer 200 and a decrease in the device's withstand voltage performance. Furthermore, it can prevent the gate-drain parasitic capacitance from increasing.

[0074] In one embodiment, such as Figure 2 As shown, there are multiple trenches and multiple trench layers. The multiple trench layers are arranged at intervals along a second direction, and each trench layer is surrounded by trenches. The second direction is perpendicular to the first direction, and the second direction can be any direction in a plane perpendicular to the first direction.

[0075] Each channel layer is surrounded by a gate dielectric layer 200 and a gate 300. Each first sub-channel layer 101 has a drain region 500 on the side away from the second sub-channel layer 102 that is integrally connected to it, and each semiconductor layer 100 exposed at the bottom of the trench on opposite sides of each channel layer has a source region 400.

[0076] Based on the same inventive concept, this application also provides a method for fabricating the semiconductor device structure provided in any of the above embodiments, such as... Figure 3 As shown, it includes the following S100-S400.

[0077] S100 provides a semiconductor layer.

[0078] S200, a trench extending from the surface to the interior of the semiconductor layer is formed in the semiconductor layer, the trench isolates a channel layer in the semiconductor layer, and the trench surrounds the channel layer; the channel layer includes a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer is smaller than the width of the second sub-channel layer.

[0079] S300, a gate dielectric layer and a gate are formed on the periphery of the channel layer; the gate dielectric layer surrounds the channel layer, and the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer; the gate is located on the surface of the gate dielectric layer away from the channel layer and surrounds the gate dielectric layer.

[0080] S400, a source region is formed in the semiconductor layer at the bottom of the trench, and a drain region is formed on the side of the first sub-channel layer away from the second sub-channel layer.

[0081] Figures 4 to 11 The following are schematic cross-sectional views illustrating various stages in the fabrication process of the semiconductor device structure provided in the embodiments of this application. Figures 4 to 11 The method for fabricating the semiconductor device structure provided in the embodiments of this application will be described.

[0082] In S100, a semiconductor layer 100 is provided, such as Figure 4 As shown. The semiconductor layer 100 may be formed on the substrate 700. The substrate material may be any suitable substrate material known in the art.

[0083] In S200, trenches extending from the surface to the interior of the semiconductor layer 100 are formed within it, such as... Figures 4 to 7 As shown.

[0084] In this step, S201, a patterned mask layer is formed on the surface of the semiconductor layer.

[0085] like Figure 4 As shown, a patterned mask layer 800 is formed on the surface of the semiconductor layer 100.

[0086] S202, based on patterned mask layer etching of semiconductor layer to form first sub-trench extending from its surface to its interior within semiconductor layer.

[0087] like Figure 4 As shown, a semiconductor layer 100 is etched based on a patterned mask layer 800 to form a first sub-trench 901 extending from its surface to its interior within the semiconductor layer 100. The first sub-trench 901 isolates a first initial sub-channel layer 101a within the semiconductor layer 100, and the first sub-trench 901 surrounds the first initial sub-channel layer 101a.

[0088] S203, a dielectric mask layer is formed on the sidewall of the first sub-trench.

[0089] like Figure 5 As shown, a dielectric mask material layer 201a is first formed on the inner wall of the first sub-trench 901 and the surface of the patterned mask layer 800 using a deposition process, such as... Figure 6 As shown, the dielectric mask material layer 201a at the bottom of the first sub-trench 901 is etched. During the etching process, the dielectric mask material layer 201a on the surface of the patterned mask layer 800 will inevitably be etched away. The dielectric mask material layer 201a remaining on the sidewall of the first sub-trench 901 is the dielectric mask layer 201. The dielectric mask layer 201 is made of the same material as the gate dielectric layer 200.

[0090] In this step, the thickness of the deposited dielectric mask layer 201 must not be too thin to avoid damage to the first initial sub-channel layer 101a by subsequent etching processes. For example, the thickness of the dielectric mask layer 201 is 10 angstroms to 100 angstroms, such as 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms or values ​​between these values.

[0091] S204, based on the patterned mask layer and the dielectric mask layer, the semiconductor layer is etched to form a second sub-trench at the bottom of the first sub-trench that is connected to the first sub-trench.

[0092] like Figure 7 As shown, the patterned mask layer 800 and the dielectric mask layer 201 are used as masks to etch the semiconductor layer 100 to form a second sub-trench 902 at the bottom of the first sub-trench 901 that is connected to the first sub-trench 901.

[0093] The width of the second sub-trench 902 is smaller than the width of the first sub-trench 901. The second sub-trench 902 isolates a second initial sub-channel layer integrally connected to the first initial sub-channel layer 101a within the semiconductor layer 100. The width of the second initial sub-channel layer is larger than the width of the first initial sub-channel layer 101a. The second initial sub-channel layer is the second sub-channel layer 102.

[0094] In S300, a gate dielectric layer and a gate electrode are formed around the channel layer, such as Figures 8 to 11 As shown.

[0095] In this step, S301, a gate dielectric material layer is formed on the surface of the dielectric mask layer, the sidewalls of the second sub-trench, and the bottom.

[0096] like Figure 8 As shown, a gate dielectric material layer 202 is formed on the surface of the dielectric mask layer 201, the sidewalls of the second sub-trench 902, and the bottom using a deposition process. Exemplarily, the thickness of the gate dielectric material layer 202 is 1 angstrom to 10 angstroms, for example, 1 angstrom, 3 angstroms, 5 angstroms, 7 angstroms, 9 angstroms, 10 angstroms, or values ​​between these.

[0097] S302, a gate material layer is formed on the surface of the gate dielectric material layer, and the gate material layer fills the trench.

[0098] A gate material layer 300a is formed on the surface of the gate dielectric material layer 202 using a deposition process, and the gate material layer 300a fills the trench.

[0099] S303, remove the gate material layer, gate dielectric material layer, dielectric mask layer and patterned mask layer located on the first initial sub-channel layer.

[0100] like Figure 9 As shown, etching or polishing processes can be used to remove the gate material layer 300a, gate dielectric material layer 202, dielectric mask layer 201 and patterned mask layer 800 located on the first initial sub-channel layer 101a, exposing the first initial sub-channel layer 101a.

[0101] S304, etching back to remove the dielectric mask layer, gate dielectric material layer and gate material layer located in the trench.

[0102] like Figure 10 As shown, an etching process, such as dry etching, is used to remove part of the dielectric mask layer, gate dielectric material layer 202, and gate material layer 300a within the trench. The remaining dielectric mask layer 201 and gate dielectric material layer 202 constitute the gate dielectric layer 200. The top of the gate dielectric layer 200 and the top of the remaining gate material layer are lower than the top of the trench and higher than the bottom of the first sub-trench 901.

[0103] In this step, in the first direction, the ratio of the length of the gate dielectric material layer in the first sub-trench 901 to the length of the gate dielectric material layer in the second sub-trench 902 is 3:1 to 7:1. Thus, the ratio of the lengths of the subsequently formed first sub-channel layer 101 and second sub-channel layer 102 in the first direction is also 3:1 to 7:1. This ensures that the distance between the subsequently formed drain region 500 and the gate 300 is appropriate, avoiding the drain region 500 being too far from the gate 300, resulting in a longer carrier transport path and affecting the device switching speed. At the same time, it avoids the drain region 500 being too close to the gate 300, which would lead to insufficient high-voltage buffer area of ​​the thicker gate dielectric layer 200 and a decrease in the device's withstand voltage performance, and also avoids an increase in gate-drain parasitic capacitance.

[0104] S305, an isolation trench is formed in the gate material layer retained in the trench.

[0105] like Figure 11 As shown, an etching process, such as dry etching, is used to etch the gate material layer 300a retained in the trench, forming an isolation trench 1000. The isolation trench 1000 penetrates the gate material layer along a first direction, and the retained gate material layer is the gate 300.

[0106] Specifically, after S304 and before S305, ion implantation is performed on the upper part of the first initial sub-channel layer 101a to transform the upper part of the first initial sub-channel layer 101a into a drift layer 600.

[0107] like Figure 11 As shown, ion implantation is performed on the upper part of the first initial sub-channel layer 101a to transform the upper part of the first initial sub-channel layer 101a into a drift layer 600. The retained first initial sub-channel layer 101a is the first sub-channel layer 101, and the second initial sub-channel layer is the second sub-channel layer 102.

[0108] In this step, the retained gate material layer 300a can be used as a barrier layer for ion implantation to save on the photomask.

[0109] S400, a source region 400 is formed in the semiconductor layer 100 at the bottom of the trench, and a drain region 500 is formed on the side of the first sub-channel layer 101 away from the second sub-channel layer 102.

[0110] like Figure 11 As shown, an ion implantation process can be used to form a source region 400 in the semiconductor layer 100 at the bottom of the trench, and a drain region 500 can be formed on the side of the first sub-channel layer 101 away from the second sub-channel layer 102.

[0111] In this step, ion implantation can be performed simultaneously on the semiconductor layer 100 at the bottom of the trench and the side of the first sub-channel layer 101 away from the second sub-channel layer 102, or ion implantation can be performed separately on the semiconductor layer 100 at the bottom of the trench and the side of the first sub-channel layer 101 away from the second sub-channel layer 102, to form the source region 400 and the drain region 500.

[0112] An unexpected effect of this embodiment is:

[0113] In the semiconductor device structure provided in this embodiment, a first sub-trench 901 and a second sub-trench 902 are formed by etching the semiconductor layer 100 twice. The first sub-trench 901 surrounds the first sub-channel layer 101, and the second sub-trench 902 surrounds the second sub-channel layer 102. A gate dielectric layer 200 and a gate 300 are formed on the periphery of the channel layer. The width of the first sub-trench 901 is greater than the width of the second sub-trench 902. A wider sub-trench can accommodate a thicker gate dielectric layer, which makes the thickness of the gate dielectric layer surrounding the first sub-channel layer 101 in the first sub-trench 901 greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer 102 in the second sub-trench 902. That is, the thickness of the gate dielectric layer near the drain region 500 is increased, which can improve the breakdown voltage of the device and enhance the device's withstand voltage performance.

[0114] In this embodiment, when a drift layer 600 is formed on one side of the drain region 500, the gate material layer 300a is used as a barrier layer for ion implantation, which can save on photomasks.

[0115] The semiconductor device structure provided in this embodiment has a drift layer 600 formed on one side of the drain region 500, and the ion doping type of the drift layer 600 is the same as that of the drain region 500, so that the ion doping concentration of the drain region 500 is greater than that of the source region 400. Combined with the fact that the thickness of the gate dielectric layer 200 surrounding the first sub-channel layer 101 is greater than the thickness of the gate dielectric layer 200 surrounding the second sub-channel layer 102, a LDMOS-like structure is formed. By adjusting the doping concentration of the drift layer 600 and the thickness of the gate dielectric layer 200, the voltage can be basically exhausted in the drift region, avoiding electric field spikes in the device junction region, which can further improve the device's voltage withstand performance.

[0116] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A semiconductor device structure, characterized in that, include: A semiconductor layer having trenches extending from its surface to its interior, the trenches isolating a channel layer within the semiconductor layer, the trenches surrounding the channel layer; the channel layer includes a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer being smaller than the width of the second sub-channel layer; the first direction extends from the top of the trench to the bottom of the trench. A gate dielectric layer surrounds the channel layer; the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer; A gate is located on the surface of the gate dielectric layer away from the channel layer and surrounds the gate dielectric layer; The source region is located within the semiconductor layer exposed at the bottom of the trench; The leak area is located on the side of the first sub-channel layer away from the second sub-channel layer.

2. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure also includes: A drift layer is located between the drain region and the channel layer, and is in contact with both the drain region and the channel layer; The ion doping concentration in the drain region is greater than that in the source region.

3. The semiconductor device structure according to claim 1, characterized in that, Along the first direction, the ratio of the length of the first sub-channel layer to the length of the second sub-channel layer is 3:1 to 7:

1.

4. The semiconductor device structure according to any one of claims 1 to 3, characterized in that, The number of trenches and the number of channel layers are both multiple; the multiple channel layers are arranged at intervals along the second direction, and each channel layer is surrounded by trenches; each channel layer is surrounded by a gate dielectric layer and a gate in sequence; each first sub-channel layer has a drain region on the side away from the second sub-channel layer integrally connected to it; each channel layer has a source region in the semiconductor layer exposed at the bottom of the trench on opposite sides. The second direction is perpendicular to the first direction.

5. A method for fabricating a semiconductor device structure, characterized in that, include: Provides a semiconductor layer; A trench extending from the surface to the interior of the semiconductor layer is formed therein, the trench isolating a channel layer within the semiconductor layer, the trench surrounding the channel layer; the channel layer includes a first sub-channel layer and a second sub-channel layer integrally connected along a first direction, the width of the first sub-channel layer being smaller than the width of the second sub-channel layer; the first direction extends from the top of the trench to the bottom of the trench; A gate dielectric layer and a gate electrode are formed around the periphery of the channel layer; the gate dielectric layer surrounds the channel layer, and the thickness of the gate dielectric layer surrounding the first sub-channel layer is greater than the thickness of the gate dielectric layer surrounding the second sub-channel layer; the gate electrode is located on the surface of the gate dielectric layer away from the channel layer and surrounds the gate dielectric layer; A source region is formed within the semiconductor layer at the bottom of the trench, and a drain region is formed on the side of the first sub-channel layer away from the second sub-channel layer.

6. The method according to claim 5, characterized in that, Forming trenches extending from the surface to the interior within the semiconductor layer, including: A patterned mask layer is formed on the surface of the semiconductor layer; The semiconductor layer is etched based on the patterned mask layer to form a first sub-trench extending from its surface to its interior within the semiconductor layer. The first sub-trench isolates a first initial sub-channel layer within the semiconductor layer and surrounds the first initial sub-channel layer. A dielectric mask layer is formed on the sidewall of the first sub-trench; Based on the patterned mask layer and the dielectric mask layer, the semiconductor layer is etched to form a second sub-trench at the bottom of the first sub-trench that is connected to the first sub-trench. The width of the second sub-trench is smaller than the width of the first sub-trench. The second sub-trench isolates a second initial sub-channel layer that is integrally connected to the first initial sub-channel layer within the semiconductor layer. The width of the second initial sub-channel layer is larger than the width of the first initial sub-channel layer.

7. The method according to claim 6, characterized in that, A gate dielectric layer and a gate are formed around the periphery of the channel layer, including: A gate dielectric material layer is formed on the surface of the dielectric mask layer, the sidewalls of the second sub-trench, and the bottom. A gate material layer is formed on the surface of the gate dielectric material layer, and the gate material layer fills the trench; Remove the gate material layer, gate dielectric material layer, dielectric mask layer, and patterned mask layer located on the first initial sub-channel layer; The dielectric mask layer, gate dielectric material layer, and gate material layer located within the trench are removed by etch-back; the retained dielectric mask layer and gate dielectric material layer are the gate dielectric layer; the top of the gate dielectric layer and the top of the retained gate material layer are lower than the top of the trench; An isolation trench is formed within the gate material layer retained in the trench, the isolation trench penetrating the gate material layer along the first direction, and the retained gate material layer is the gate.

8. The method according to claim 7, characterized in that, The thickness of the dielectric mask layer is 10 angstroms to 100 angstroms, and the thickness of the gate dielectric material layer is 1 angstrom to 10 angstroms.

9. The method according to claim 7, characterized in that, After the dielectric mask layer, gate dielectric material layer, and gate material layer located within the trench are removed by etch-back, and before an isolation trench is formed within the gate material layer remaining in the trench, the process further includes: Ion implantation is performed on the upper part of the first initial sub-channel layer to transform the upper part of the first initial sub-channel layer into a drift layer; the retained first initial sub-channel layer is the first sub-channel layer, and the second initial sub-channel layer is the second sub-channel layer.

10. The method according to any one of claims 5 to 9, characterized in that, A source region is formed within the semiconductor layer at the bottom of the trench, and a drain region is formed on the side of the first sub-channel layer away from the second sub-channel layer, including: Ion implantation is performed on the side of the semiconductor layer at the bottom of the trench and the first sub-channel layer away from the second sub-channel layer to form the source region and the drain region.

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