Test circuit and chip
By introducing a first logic circuit, a second logic circuit, and a gating circuit into the chip, parallel testing of multiple circuits under test is achieved, solving the problem of increased testing time in existing technologies and improving testing efficiency and reliability.
Patent Information
- Application Number
- CN202611106240.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-24
- Publication Date
- 2026-08-25
AI Technical Summary
In existing technologies, the test outputs of multiple identical IP cores need to be completed serially, which increases the test time and cannot meet the rapid testing requirements of large-scale integrated chips, resulting in low test efficiency.
The output signals of multiple circuits under test are processed by the first logic circuit and the second logic circuit. Parallel testing is achieved through the first gating circuit. The faulty circuit is identified by the inverted expected signal, reducing the need for one-to-one comparison.
It enables parallel testing of multiple circuits under test, significantly improving testing efficiency. It eliminates the need to compare the output of each circuit under test individually, and can quickly identify faulty circuits.
Smart Images
Figure CN122632050A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and in particular to a test circuit and chip. Background Technology
[0002] In chip design, to achieve functional reuse, multiple identical IP cores are typically integrated on-chip, and these need to be tested to ensure proper functioning. Currently, the JTAG (Joint Test Action Group) interface is often used to test the IP, with test vectors input through a single TDI (Test Data In) port and test results output through a single TDO (Test Data Out) port.
[0003] To improve testing efficiency, multiple test inputs with the same IP can share the TDI port to achieve parallel input via broadcast. However, since JTAG only has one TDO port, the test outputs of multiple IPs need to be sequentially selected by a MUX (Multiplexer) to shift out the results one by one and compare them with the expected value.
[0004] Therefore, IP testing can only achieve parallel input, while the output still needs to be completed serially. The test time increases significantly with the number of IP cores, making parallel testing impossible and resulting in low test efficiency, which is difficult to meet the rapid testing needs of large-scale integrated chips. Summary of the Invention
[0005] The main objective of this invention is to provide a test circuit and chip that aims to improve the efficiency of IP testing.
[0006] To achieve the above objectives, this invention proposes a test circuit applied to a chip. The chip includes multiple circuits under test (DUTs), whose input terminals are used to receive test signals. The DUTs process the test signals and output corresponding logic signals. The test circuit includes: A first logic circuit, wherein the input terminal of the first logic circuit is used to connect to the output terminals of multiple circuits under test, and the first logic circuit is used to output a first signal when the parameters of multiple logic signals are all the same, and is also used to output a second signal when at least two of the parameters of multiple logic signals are different. The second logic circuit has an input terminal for receiving the desired signal and an output of the inverted desired signal after inverting the desired signal. A first gating circuit has a first input terminal connected to the output terminal of the second logic circuit, a second input terminal of the first gating circuit used to connect to the output terminal of one of the circuits under test, an output terminal of the first gating circuit used to connect to a test instrument, a controlled terminal of the first gating circuit connected to the output terminal of the first logic circuit, and the first gating circuit is used to output the logic signal received by the second input terminal to the test instrument when receiving the first signal, and is also used to output the inverted desired signal received by the first input terminal to the test instrument when receiving the second signal.
[0007] In one embodiment, the first logic circuit includes: The first AND gate circuit has multiple input terminals that are connected one-to-one to the output terminals of multiple circuits under test. The first AND gate circuit is used to output 1 when the parameters of multiple logic signals are all 1, and also to output 0 when any one of the parameters of multiple logic signals is 0. An inverting circuit and a second AND gate circuit are provided. The multiple input terminals of the inverting circuit are used to connect one-to-one with the output terminals of multiple circuits under test. The multiple output terminals of the inverting circuit are connected to the multiple input terminals of the second AND gate circuit. The inverting circuit is used to invert multiple logic signals and output them to the second AND gate circuit. The second AND gate circuit is used to output 1 when all parameters of the multiple inverted logic signals are 1, and also to output 0 when any one of the parameters of the multiple inverted logic signals is 0. An OR gate circuit, wherein the first input terminal of the OR gate circuit is connected to the output terminal of the first AND gate circuit, the second input terminal of the OR gate circuit is connected to the output terminal of the second AND gate circuit, and the output terminal of the OR gate circuit is connected to the controlled terminal of the first gating circuit; The first signal is 1, and the second signal is 0.
[0008] In one embodiment, the first AND gate circuit includes: Multiple first AND gates are connected in series. Among the multiple first AND gates connected in series, the input terminals that are not connected to the output terminals of adjacent first AND gates are used to be connected to the output terminals of multiple circuits under test one by one. In a series of first AND gates connected in sequence, the output of the last first AND gate is connected to the first input of the OR gate circuit.
[0009] In one embodiment, the inverting circuit includes: Multiple inverters, with the input terminals of the multiple inverters connected one-to-one with the output terminals of multiple circuits under test; The second AND gate circuit includes: Multiple second AND gates are connected in series. The input terminals of the second AND gates that are not connected to the output terminals of the adjacent second AND gates are connected to the output terminals of the multiple inverters in a one-to-one correspondence. Among the multiple second AND gates connected in series, the output terminal of the last second AND gate is connected to the second input terminal of the OR gate circuit.
[0010] In one embodiment, the second logic circuit includes: An inverter, the input of which is used to receive the desired signal, and the output of which is connected to the first input of the first gating circuit.
[0011] In one embodiment, the test circuit further includes: The second gating circuit has one input terminal connected to the output terminal of the first gating circuit, and the remaining input terminals of the second gating circuit are used to connect to the output terminals of multiple circuits under test one by one. The output terminal of the second gating circuit is used to connect to the test equipment. The controlled terminal of the second gating circuit is used to connect to an external control signal. The second gating circuit is used to select the transmission path between any of its input terminals and the test equipment according to the external control signal.
[0012] The present invention also proposes a chip comprising multiple circuits under test and the test circuit described in any of the above claims.
[0013] The test circuit of this invention includes a first logic circuit, a second logic circuit, and a first gating circuit. Multiple circuits under test (DUTs) are used to process test signals and output corresponding logic signals. When all DUTs are normal, the parameters of the multiple logic signals are the same. At this time, the first logic circuit outputs a first signal to the controlled terminal of the first gating circuit to control the first gating circuit to output the logic signal of one of the DUTs to the test equipment. Since all DUTs are normal at this time, when the test equipment compares the logic signal with the expected signal (the signal output after processing the test signal when the DUT is normal), it will determine that the logic signal is the same as the expected signal and output the result that all DUTs are normal.
[0014] When at least two of the parameters of multiple logic signals are different, it indicates that at least one circuit under test is malfunctioning. At this time, the first logic circuit outputs a second signal to the controlled terminal of the first gating circuit to control the first gating circuit to transmit the inverted expected signal to the test machine. Since the inverted expected signal and the expected signal are different, the test machine outputs the result that at least one test circuit has failed.
[0015] With this configuration, compared to existing technologies, the test circuit of this invention enables parallel testing of the output results of multiple circuits under test. It can determine whether multiple circuits under test are faulty without comparing the output of each circuit under test one by one, which significantly improves the efficiency of IP testing. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a circuit structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the present invention; Figure 3 This is a schematic diagram of a circuit structure according to another embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of another embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit structure of another embodiment of the present invention.
[0018] Explanation of icon numbers: 10. First logic circuit; 11. First AND gate circuit; 12. Inverting circuit; 13. Second AND gate circuit; 14. OR gate circuit; 20. Second logic circuit; 30. First gating circuit; 40. Second gating circuit.
[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0021] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0023] In chip design, to achieve functional reuse, multiple identical IP cores are typically integrated on-chip, and these need to be tested to ensure proper functioning. Currently, the JTAG (Joint Test Action Group) interface is often used to test the IP, with test vectors input through a single TDI (Test Data In) port and test results output through a single TDO (Test Data Out) port.
[0024] To improve testing efficiency, multiple test inputs with the same IP can share the TDI port to achieve parallel input via broadcast. However, since JTAG only has one TDO port, the test outputs of multiple IPs need to be sequentially selected by a MUX (Multiplexer) to shift out the results one by one and compare them with the expected value.
[0025] Therefore, IP testing can only achieve parallel input, while the output still needs to be completed serially. The test time increases significantly with the number of IP cores, making parallel testing impossible and resulting in low test efficiency, which is difficult to meet the rapid testing needs of large-scale integrated chips.
[0026] To address the aforementioned technical problems, this invention proposes a test circuit applied to a chip. The chip includes multiple circuits under test (DUTs), whose input terminals are used to receive test signals. The DUTs process the test signals and output corresponding logic signals. In one embodiment, reference is made to… Figure 1 The test circuit includes: The first logic circuit 10 has an input terminal for connecting to the output terminals of multiple circuits under test. The first logic circuit 10 is used to output a first signal when the parameters of multiple logic signals are all the same, and also to output a second signal when at least two of the parameters of multiple logic signals are different. The second logic circuit 20 has an input terminal for receiving a desired signal and is used to invert the desired signal and output an inverted desired signal. A first gating circuit 30 has a first input terminal connected to the output terminal of the second logic circuit 20, a second input terminal of the first gating circuit 30 for connecting to the output terminal of one of the circuits under test, an output terminal of the first gating circuit 30 for connecting to a test instrument, a controlled terminal of the first gating circuit 30 connected to the output terminal of the first logic circuit 10, and the first gating circuit 30 is used to output the logic signal received by the second input terminal to the test instrument when receiving the first signal, and is also used to output the inverted desired signal received by the first input terminal to the test instrument when receiving the second signal.
[0027] It should be noted that the multiple circuits under test are multiple internally identical IP cores. Each IP core includes multiple registers. One part of the registers is used to receive control signals input to the IP core and shift and write the corresponding values through the input port. Another part of the registers is used to latch the test results output by the IP core and shift and output its value to the input terminal of the first logic circuit 10 through the output port for testing.
[0028] Understandably, when multiple circuits under test (DUTs) are functioning normally, the parameters of multiple logic signals are identical. In this case, the first logic circuit 10 outputs a first signal to the first gating circuit 30, causing the first gating circuit 30 to output any one of the logic signals to the test equipment. The test equipment compares the logic signal with the expected signal (the signal output after processing the test signal when the DUT is functioning normally). If the logic signal and the expected signal are identical, it determines that all DUTs are functioning normally. Understandably, since the parameters of multiple logic signals are identical when all DUTs are functioning normally, only one logic signal needs to be output to the test equipment for verification. The test equipment does not need to read the logic signals of multiple DUTs one by one, significantly improving the efficiency of IP testing.
[0029] When at least one circuit under test fails, at least two of the parameters of multiple logic signals are different. At this time, the first logic circuit 10 outputs a second signal to the controlled terminal of the first gating circuit 30 to control the first gating circuit 30 to transmit the inverted expected signal to the test machine. Since the inverted expected signal and the expected signal are different, the test machine can determine that at least one test circuit has failed.
[0030] In one embodiment, reference Figure 2 The first logic circuit 10 includes: The first AND gate circuit 11 has multiple input terminals that are connected to the output terminals of multiple circuits under test in a one-to-one correspondence. The first AND gate circuit 11 is used to output 1 when the parameters of multiple logic signals are all 1, and also to output 0 when any one of the parameters of multiple logic signals is 0. The inverter circuit 12 and the second AND gate circuit 13 are configured such that the multiple input terminals of the inverter circuit 12 are connected to the output terminals of multiple circuits under test one by one, and the multiple output terminals of the inverter circuit 12 are connected to the multiple input terminals of the second AND gate circuit 13. The inverter circuit 12 is used to invert multiple logic signals and output them to the second AND gate circuit 13. The second AND gate circuit 13 is used to output 1 when all parameters of the multiple inverted logic signals are 1, and also to output 0 when any one of the parameters of the multiple inverted logic signals is 0. OR gate circuit 14, the first input terminal of OR gate circuit 14 is connected to the output terminal of the first AND gate circuit 11, the second input terminal of OR gate circuit 14 is connected to the output terminal of the second AND gate circuit 13, and the output terminal of OR gate circuit 14 is connected to the controlled terminal of the first gating circuit 30; wherein, the first signal is 1 and the second signal is 0.
[0031] The first AND gate circuit 11 and the second AND gate circuit 13 can both be implemented using multi-input AND gates. The multi-input AND gate outputs 1 only when all input logic signals are 1, and outputs 0 when any input logic signal is 0. The inverter circuit 12 can be implemented using multiple inverters to invert multiple logic signals. The OR gate circuit 14 can be implemented using at least one OR gate.
[0032] When multiple logic signals are identical, for example, all are 1, the first AND gate 11 outputs 1, and the inverter 12 outputs multiple 0s to the second AND gate 13, causing the second AND gate 13 to output 0. Alternatively, the OR gate 14, upon receiving both 1 and 0, outputs 1 to the controlled terminal of the first gating circuit 30, causing the first gating circuit 30 to output the logic signal received at its second input terminal to the test equipment. When at least two of the inverted logic signals are different, for example, one logic signal is 0 and the rest are 1, both the first AND gate 11 and the second AND gate 13 output 0. Alternatively, the OR gate 14, upon receiving two 0s, outputs 0 to the controlled terminal of the first gating circuit 30, causing the first gating circuit 30 to output the inverted desired signal received at its first input terminal to the test equipment.
[0033] In another embodiment, the first logic circuit 10 can be implemented using only a multi-input AND gate. When all the logic signals at all inputs are 1, the multi-input AND gate outputs 1 to the controlled terminal of the first gating circuit 30, so that the first gating circuit 30 outputs the logic signal received at its second input terminal to the test equipment. When any one of the logic signals at all inputs is 0, the multi-input AND gate outputs 0 to the controlled terminal of the first gating circuit 30, so that the first gating circuit 30 outputs the inverted desired signal received at its first input terminal to the test equipment.
[0034] It should be noted that the expected signal is the signal output after processing the test signal when the circuit under test is normal. This signal is used by the testing equipment to compare the logic signals to determine if multiple circuits under test are faulty. The second logic circuit 20 is used to invert the expected signal and output an inverted expected signal. Its implementation includes, but is not limited to, inverters, NOT gates, or CMOS inverters. For example, see reference... Figure 4 The second logic circuit 20 is implemented using an inverter. As can be seen from the above embodiment, when at least one of the multiple circuits under test is faulty, at least two of the multiple logic signals are different. At this time, the first logic circuit 10 outputs a second signal to the first gating circuit 30, so that the first gating circuit 30 outputs an inverted expected signal to the test instrument, so that the test instrument recognizes that the inverted expected signal is different from the expected signal, and outputs the result that at least one of the multiple circuits under test is faulty.
[0035] In this embodiment, the first gating circuit 30 is used to output the logic signal received at the second input terminal or the inverted expected signal received at the first input terminal to the test instrument. Its implementation methods include, but are not limited to, a two-to-one selector or a multiplexer.
[0036] In summary, the test circuit of this invention includes a first logic circuit 10, a second logic circuit 20, and a first gating circuit 30. Multiple circuits under test (DUTs) are used to process test signals and output corresponding logic signals. When multiple DUTs are all normal, the parameters of multiple logic signals are the same. At this time, the first logic circuit 10 outputs a first signal to the controlled terminal of the first gating circuit 30 to control the first gating circuit 30 to output the logic signal of one of the DUTs to the test equipment. Since multiple DUTs are all normal at this time, when the test equipment compares the logic signal with the expected signal (the signal output after processing the test signal when the DUT is normal), it will determine that the logic signal is the same as the expected signal and output the result that multiple DUTs are normal.
[0037] When at least two of the parameters of multiple logic signals are different, it indicates that at least one circuit under test is malfunctioning. At this time, the first logic circuit 10 outputs a second signal to the controlled terminal of the first gating circuit 30 to control the first gating circuit 30 to transmit the inverted expected signal to the test machine. Since the inverted expected signal and the expected signal are different, the test machine outputs the result that at least one test circuit has failed.
[0038] With this configuration, compared to existing technologies, the test circuit of this invention enables parallel testing of the output results of multiple circuits under test. It can determine whether multiple circuits under test are faulty without comparing the output of each circuit under test one by one, which significantly improves the efficiency of IP testing.
[0039] In one embodiment of the present invention, reference is made to... Figure 3 The first AND gate circuit 11 includes: Multiple first AND gates A1 connected in series, and the input terminals of the multiple first AND gates A1 connected in series are used to be connected to the output terminals of multiple circuits under test one by one; In a series of first AND gates A1 connected in sequence, the output terminal of the last first AND gate A1 is connected to the first input terminal of the OR gate circuit 14.
[0040] In this embodiment, when multiple logic signals are identical, for example, all are 1, multiple first AND gates A1 all output 1, so that the first AND gate A1 at the end outputs 1 to the first input terminal of the OR gate circuit 14. When at least two logic signals have different parameters, for example, one logic signal has a parameter of 0 and the parameters of the remaining logic signals are all 1, the first AND gate A1 connected to logic signal 0 outputs 0, so that all subsequent first AND gates A1 output 0, and finally the first AND gate A1 at the end outputs 0 to the first input terminal of the OR gate circuit 14.
[0041] In one embodiment of the present invention, reference is made to... Figure 3The inverting circuit 12 includes: Multiple inverters, with the input terminals of the multiple inverters connected one-to-one with the output terminals of multiple circuits under test; The second AND gate circuit 13 includes: Multiple second AND gates A2 are connected in series. Among the multiple second AND gates A2 connected in series, the input terminal that is not connected to the output terminal of the adjacent second AND gate A2 is connected to the output terminal of the multiple inverters one by one. Among the multiple second AND gates A2 connected in series, the output terminal of the second AND gate A2 at the end is connected to the second input terminal of the OR gate circuit 14.
[0042] In this embodiment, when the parameters of multiple logic signals are all the same, for example, all are 0, multiple inverters output 1 to multiple second AND gates A2 connected in series, so that the multiple second AND gates A2 output 1 to the second input terminal of OR gate circuit 14. When the parameters of at least two logic signals are different, for example, one logic signal is 0 and the rest are 1, the multiple second AND gates A2 connected in series receive one logic signal 1 and multiple logic signals 0 respectively, so that the multiple second AND gates A2 output 0, and finally the second input terminal of OR gate circuit 14 receives 0.
[0043] In one embodiment of the present invention, reference is made to... Figure 5 The test circuit further includes: The second gating circuit 40 has one input terminal connected to the output terminal of the first gating circuit 30. The remaining input terminals of the second gating circuit 40 are used to connect to the output terminals of multiple circuits under test one by one. The output terminal of the second gating circuit 40 is used to connect to the test equipment. The controlled terminal of the second gating circuit 40 is used to connect to an external control signal. The second gating circuit 40 is used to select the transmission path between any of its input terminals and the test equipment according to the external control signal.
[0044] In this embodiment, the second gating circuit 40 can be implemented using a multiplexer or a multiplexer to output the signal received at one of the input terminals to the test equipment.
[0045] It should be noted that when the user determines that at least one circuit under test is faulty, the external control signal output controls the second gating circuit 40 to send the logic signals output by the multiple circuits under test to the test equipment one by one, so that the test equipment compares the logic signal output by each circuit under test with the expected signal. When the logic signal is inconsistent with the expected signal, it is determined that the circuit under test corresponding to the logic signal is faulty.
[0046] Understandably, the second gating circuit 40 sends the signal output by the first gating circuit 30 to the test equipment by default, so that the test equipment can first determine whether there is a fault in multiple circuits under test.
[0047] With this configuration, the present invention can accurately locate the faulty circuit under test by switching the second gating circuit 40 one by one after determining that there is a faulty circuit under test, thereby improving the reliability and observability of the test.
[0048] The present invention also proposes a chip comprising multiple circuits under test and a test circuit as described above.
[0049] It is worth noting that since the chip of the present invention is based on the above-described test circuit, the embodiments of the chip of the present invention include all the technical solutions of all the embodiments of the above-described test circuit, and the technical effects achieved are exactly the same, so they will not be repeated here.
[0050] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A test circuit applied to a chip, the chip including multiple circuits under test (DUTs), the input terminals of the multiple DUTs being used to receive test signals, the DUTs being used to process the test signals and output corresponding logic signals, characterized in that, The test circuit includes: A first logic circuit, wherein the input terminal of the first logic circuit is used to connect to the output terminals of multiple circuits under test, and the first logic circuit is used to output a first signal when the parameters of multiple logic signals are all the same, and is also used to output a second signal when at least two of the parameters of multiple logic signals are different. The second logic circuit has an input terminal for receiving the desired signal and an output of the inverted desired signal after inverting the desired signal. A first gating circuit has a first input terminal connected to the output terminal of the second logic circuit, a second input terminal of the first gating circuit used to connect to the output terminal of one of the circuits under test, an output terminal of the first gating circuit used to connect to a test instrument, a controlled terminal of the first gating circuit connected to the output terminal of the first logic circuit, and the first gating circuit is used to output the logic signal received by the second input terminal to the test instrument when receiving the first signal, and is also used to output the inverted desired signal received by the first input terminal to the test instrument when receiving the second signal.
2. The test circuit as described in claim 1, characterized in that, The first logic circuit includes: The first AND gate circuit has multiple input terminals that are connected one-to-one to the output terminals of multiple circuits under test. The first AND gate circuit is used to output 1 when the parameters of multiple logic signals are all 1, and also to output 0 when any one of the parameters of multiple logic signals is 0. An inverting circuit and a second AND gate circuit are provided. The multiple input terminals of the inverting circuit are used to connect one-to-one with the output terminals of multiple circuits under test. The multiple output terminals of the inverting circuit are connected to the multiple input terminals of the second AND gate circuit. The inverting circuit is used to invert multiple logic signals and output them to the second AND gate circuit. The second AND gate circuit is used to output 1 when all parameters of the multiple inverted logic signals are 1, and also to output 0 when any one of the parameters of the multiple inverted logic signals is 0. An OR gate circuit, wherein the first input terminal of the OR gate circuit is connected to the output terminal of the first AND gate circuit, the second input terminal of the OR gate circuit is connected to the output terminal of the second AND gate circuit, and the output terminal of the OR gate circuit is connected to the controlled terminal of the first gating circuit; The first signal is 1, and the second signal is 0.
3. The test circuit as described in claim 2, characterized in that, The first AND gate circuit includes: Multiple first AND gates are connected in series. Among the multiple first AND gates connected in series, the input terminals that are not connected to the output terminals of adjacent first AND gates are used to be connected to the output terminals of multiple circuits under test one by one. In a series of first AND gates connected in sequence, the output of the last first AND gate is connected to the first input of the OR gate circuit.
4. The test circuit as described in claim 2, characterized in that, The inverting circuit includes: Multiple inverters, with the input terminals of the multiple inverters connected one-to-one with the output terminals of multiple circuits under test; The second AND gate circuit includes: Multiple second AND gates are connected in series. The input terminals of the second AND gates that are not connected to the output terminals of the adjacent second AND gates are connected to the output terminals of the multiple inverters in a one-to-one correspondence. Among the multiple second AND gates connected in series, the output terminal of the last second AND gate is connected to the second input terminal of the OR gate circuit.
5. The test circuit as described in claim 1, characterized in that, The second logic circuit includes: An inverter, the input of which is used to receive the desired signal, and the output of which is connected to the first input of the first gating circuit.
6. The test circuit as described in any one of claims 1 to 5, characterized in that, The test circuit also includes: The second gating circuit has one input terminal connected to the output terminal of the first gating circuit, and the remaining input terminals of the second gating circuit are used to connect to the output terminals of multiple circuits under test one by one. The output terminal of the second gating circuit is used to connect to the test equipment. The controlled terminal of the second gating circuit is used to connect to an external control signal. The second gating circuit is used to select the transmission path between any of its input terminals and the test equipment according to the external control signal.
7. A chip, characterized in that, It includes multiple circuits under test and a test circuit as described in any one of claims 1 to 6.