Electronic device

Abstract

The present disclosure provides an electronic device, characterized in that comprising: a first substrate comprising a cavity, the cavity having a first bottom surface; a photonic crystal grain disposed in the cavity and having a second bottom surface facing the first bottom surface; a connecting member disposed between the first bottom surface and the second bottom surface; and a first waveguide disposed corresponding to the photonic crystal grain and receiving an optical signal from the photonic crystal grain; wherein the roughness of the first bottom surface of the first substrate is different from the roughness of the second bottom surface of the photonic crystal grain.

Description

Technical Field

[0001] This disclosure relates to an electronic device, specifically an electronic device having photonic chips and / or waveguides. Background Technology

[0002] In recent years, with the continuous development of technology, technologies such as artificial intelligence and cloud computing, which require high-density and high-performance chips, have grown rapidly. In addition to testing the manufacturer's process technology, the high density and high performance of chips are prone to drawbacks such as overheating of electronic devices.

[0003] Traditional electronic devices that rely solely on electrical signal transmission are gradually failing to meet market demands. Optical signals, on the other hand, offer advantages over electrical signals, such as wider bandwidth, faster transmission speed, lower power consumption, and better anti-interference capabilities. Therefore, integrating optical signal transmission components with electronic devices remains a direction that requires ongoing research.

[0004] Therefore, there is an urgent need to provide an electronic device that can meet market demand. Summary of the Invention

[0005] This disclosure provides an electronic device, characterized in that it comprises: a first substrate including a cavity having a first bottom surface; a photonic chip disposed in the cavity and having a second bottom surface facing the first bottom surface; a connector disposed between the first bottom surface and the second bottom surface; and a first waveguide disposed corresponding to the photonic chip and receiving an optical signal from the photonic chip; wherein the roughness of the first bottom surface of the first substrate is different from the roughness of the second bottom surface of the photonic chip.

[0006] This disclosure also provides an electronic device, characterized in that it comprises: a second substrate including a first through-hole and a first side surface surrounding the first through-hole; an insulating layer disposed on the second substrate and including a second through-hole and a second side surface surrounding the second through-hole, wherein, in a top view of the electronic device, the first through-hole and the second through-hole overlap; an active layer disposed on the insulating layer and including a third waveguide and a photoelectric converter optically coupled to the third waveguide; a semiconductor die disposed on the active layer and electrically connected to the photoelectric converter; and a conductive element electrically connected to the semiconductor die and including a first portion and a second portion, the first portion being disposed in the first through-hole and the second portion being disposed in the second through-hole; wherein the roughness of the first side surface of the second substrate is different from the roughness of the second side surface of the insulating layer.

[0007] This disclosure also provides an electronic device, characterized in that it comprises: a first substrate including a cavity; a photonic chip disposed in the cavity of the first substrate; a first waveguide disposed corresponding to the photonic chip and receiving an optical signal from the photonic chip; a second substrate disposed on the first substrate; a semiconductor chip disposed on the second substrate; and a third waveguide disposed between the second substrate and the semiconductor chip and receiving the optical signal through the first waveguide. Attached Figure Description

[0008] Figure 1A A cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure is shown;

[0009] Figure 1B It shows Figure 1A A cross-sectional view of line segment A-A';

[0010] Figure 2A A cross-sectional schematic diagram of a portion of an electronic device according to another embodiment of the present disclosure is shown;

[0011] Figure 2B It shows Figure 2A Enlarged view of part of the image;

[0012] Figure 3 A cross-sectional schematic diagram of a portion of an electronic device according to another embodiment of the present disclosure is shown;

[0013] Figure 4A A schematic cross-sectional view of a portion of the first waveguide according to an embodiment of the present disclosure is shown;

[0014] Figure 4B A top view schematic diagram of a portion of the third waveguide according to an embodiment of the present disclosure is shown;

[0015] Figure 4C It shows Figure 4A A cross-sectional view of line segment B-B';

[0016] Figure 4D It shows Figure 4B A cross-sectional view of line segment C-C';

[0017] Figure 5 A cross-sectional schematic diagram of a portion of an electronic device according to another embodiment of the present disclosure is shown;

[0018] Figure 6A and Figure 6B They are shown respectively Figure 5 A cross-sectional schematic diagram of line segment D-D' in different implementation forms.

[0019] Figure label:

[0020] 1. First substrate;

[0021] 1s1 upper surface;

[0022] 1s² lower surface;

[0023] 11. Cavity;

[0024] 11s1 First bottom surface;

[0025] 11s2 sidewall;

[0026] 12 First waveguide;

[0027] 12A Part 1;

[0028] 12B Part 2;

[0029] 12S First curve segment;

[0030] 12s1 on one side;

[0031] 12s2 on the other side;

[0032] 13. Perforation;

[0033] 2. Photonic grains;

[0034] 2s1 Second bottom surface;

[0035] 2s2 top surface;

[0036] 21. Basal layer;

[0037] 22. Insulation layer;

[0038] 23. Circuit layer;

[0039] 24 Second waveguide;

[0040] 25. Chamfered structure;

[0041] 31. Connecting parts;

[0042] 32 optical layers;

[0043] 4. Second substrate;

[0044] 4s1 First side surface;

[0045] 4s², 5s² upper surfaces;

[0046] 4s3, 5s3 lower surface;

[0047] 41 First perforation;

[0048] 5. Insulation layer;

[0049] 5s1 Second side surface;

[0050] 51 Second perforation;

[0051] 6. Active layer;

[0052] 61. Third waveguide;

[0053] 61S Second curve segment;

[0054] 62. Photoelectric converter;

[0055] 7. Semiconductor grains;

[0056] 71. Basal layer;

[0057] 72. Inner connection layer;

[0058] 73. Dielectric layer;

[0059] 74 Connecting pads;

[0060] 8. Conductive components;

[0061] 8A Part 1;

[0062] 8B Part Two;

[0063] 9. Optical transmission elements;

[0064] 91. Light transmission medium;

[0065] 92 Lenses;

[0066] 93 Reflection Units;

[0067] CL circuit layer;

[0068] CL1, CL1' Conducting units;

[0069] CL2 connector pad;

[0070] CL3 dielectric layer;

[0071] EIC1 First Semiconductor Die;

[0072] EIC2 second semiconductor die;

[0073] EL encapsulation layer;

[0074] F1 Filler material;

[0075] F2 is another filler material;

[0076] P1, P2, P3, P4 pads;

[0077] PI photonic interposer;

[0078] RDL1 First Rerouting Layer;

[0079] RDL2 Second Rerouting Layer;

[0080] RDL3 Third Routing Layer;

[0081] RDL4 is the fourth rewiring layer.

[0082] S-shaped barrier structure;

[0083] H1 First Altitude;

[0084] H2 Second Height;

[0085] H3 Third Height;

[0086] H4, fourth altitude;

[0087] R1 is the first radius of curvature;

[0088] R2 is the second radius of curvature;

[0089] T1 is the first thickness;

[0090] T2 Second Thickness;

[0091] T3 thickness;

[0092] W1, W2, W5 widths;

[0093] W3 is the first width;

[0094] W4 is the second width;

[0095] X and Y directions;

[0096] Z-normal direction. Detailed Implementation

[0097] The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of this disclosure.

[0098] It should be noted that, unless otherwise specified herein, the use of the word "a" element is not limited to having a single element, but may include one or more of the elements. Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and claims to modify elements of a claim does not itself imply or represent any prior ordinal number for that claimed element, nor does it represent the order of one claimed element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely for the purpose of clearly distinguishing one claimed element with a given name from another claimed element with the same name.

[0099] Throughout this disclosure, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Therefore, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0100] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of these terms is implied. Furthermore, the phrases "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0101] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure is made. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0102] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element to another in the figures. It is understood that if the apparatus in the figures is flipped upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view, and this component can be above or below the other component, depending on the orientation of the apparatus.

[0103] In this disclosure, any two values ​​or directions used for comparison may have a certain degree of error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first and second values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0104] In this disclosure, the thickness, length, width, or distance and angle between components can be measured using an optical microscope (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain cross-sectional images of the structure, and the thickness, length, width, or distance and angle between components can be measured. Furthermore, the roughness of the structure can be obtained by using a scanning electron microscope to obtain cross-sectional images of the structure, and by arithmetic mean roughness (Ra) or ten-point mean roughness (Rz).

[0105] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0106] Figure 1A A cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure is shown. Figure 1B It shows Figure 1A A cross-sectional diagram of line segment A-A'.

[0107] In one embodiment of this disclosure, such as Figure 1AAs shown, the electronic device may include: a first substrate 1 including a cavity 11 having a first bottom surface 11s1; a photonic chip 2 disposed in the cavity 11 and having a second bottom surface 2s1 facing the first bottom surface 11s1; a connector 31 disposed between the first bottom surface 11s1 and the second bottom surface 2s1; and a first waveguide 12 disposed corresponding to the photonic chip 2 and receiving an optical signal from the photonic chip 2.

[0108] More in detail, such as Figure 1A As shown, the first substrate 1 includes an upper surface 1s1 and a lower surface 1s2 opposite to the upper surface 1s1. A cavity 11 is formed by a recess in the upper surface 1s1 of the first substrate 1, i.e., the cavity 11 is formed by a first bottom surface 11s1 and a sidewall 11s2 connected to both the first bottom surface 11s1 and the upper surface 1s1 of the first substrate 1. The photonic chip 2 has a second bottom surface 2s1 and a top surface 2s2 opposite to the second bottom surface 2s1, wherein, when the photonic chip 2 is disposed in the cavity 11 of the first substrate 1, the top surface 2s2 of the photonic chip 2 is approximately coplanar with the upper surface 1s1 of the first substrate 1. The photonic chip 2 can be fixed in the cavity 11 of the first substrate 1 by a connector 31, so that the optical signal provided by the photonic chip 2 can be stably transmitted to the first waveguide 12. In this disclosure, the roughness of the first bottom surface 11s1 of the cavity 11 of the first substrate 1 may differ from the roughness of the second bottom surface 2s1 of the photonic chip 2. For example, the roughness of the first bottom surface 11s1 of the cavity 11 of the first substrate 1 may be greater than the roughness of the second bottom surface 2s1 of the photonic chip 2. This increases the contact area between the connector 31 and the first bottom surface 11s1, thereby improving the fixation effect of the photonic chip 2. In one embodiment of this disclosure, the cavity 11 is a recessed structure that does not penetrate the first substrate 1 and is defined by the sidewall of the first substrate 1.

[0109] In one embodiment of this disclosure, such as Figure 1A As shown, the first substrate 1 may selectively include a plurality of through holes 13 as needed, and conductive material may be selectively disposed in the through holes 13, but this disclosure is not limited thereto. In this disclosure, the material of the first substrate 1 may include glass, silicon, silicon carbide, ceramic, resin, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the first substrate 1 may be a glass substrate. In this disclosure, the material of the first waveguide 12 may include glass, silicon, plastic, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the refractive index of the first waveguide 12 may be greater than the refractive index of the first substrate 1. In this disclosure, the material of the connector 31 includes an adhesive material, such as acrylic, epoxy resin, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the first waveguide 12 is a medium for transmitting optical signals.

[0110] In this disclosure, "photonic die 2" refers to a die containing a photonic integrated circuit (PIC), for example... Figure 1A As shown, the photonic chip 2 may include a substrate layer 21; a circuit layer 23 disposed on the substrate layer 21; an insulating layer 22 disposed between the substrate layer 21 and the circuit layer 23; and a second waveguide 24 disposed on the insulating layer 22 and used to transmit optical signals to the first waveguide 12. That is, in this disclosure, the optical signal provided by the photonic chip 2 can be transmitted to the first waveguide 12 through the second waveguide 24. Figure 1A The structure of the photonic chip 2 shown is exemplary and can be adjusted as needed. Although not shown in the figure, the photonic chip 2 may also include other components. In one embodiment of this disclosure, such as Figure 1A As shown, in a cross-section, the photonic chip 2 may include a chamfered structure 25, which can reduce defects caused by collisions between the photonic chip 2 and the cavity 11, thereby improving the reliability of the photonic chip 2. The "chamfered structure" refers, for example, to a non-right-angled or acute-angled corner or a curved corner of the photonic chip 2 in the cross-sectional view. In this disclosure, the material of the substrate layer 21 may include silicon, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), silicon germanium (SiGe), diamond, quartz, ceramic, or glass, but this disclosure is not limited thereto. In this disclosure, the material of the insulating layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the circuit layer 23 may include wires, pads, drive circuits, other suitable components, or combinations thereof. Suitable components may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, diodes, transistors, etc., but this disclosure is not limited thereto. In this disclosure, the material of the second waveguide 24 may include glass, silicon, plastic, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the second waveguide 24 is a medium for transmitting optical signals.

[0111] In one embodiment of this disclosure, such as Figure 1AAs shown, the electronic device may further include an optical layer 32 disposed between the first waveguide 12 and the second waveguide 24. In this disclosure, the optical layer 32 is made of a material with high transmittance to optical signals, thereby reducing the influence of the optical layer 32 on the optical signals. Suitable materials include transparent organic materials, such as polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyether polyol (POP), polymethyl methacrylate (PMMA), cycloolefin polymer (COP), rubber, UV-curable adhesive (UV adhesive), optically clear adhesive (OCA), optically clear resin (OCR), acrylic resin, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the optical layer 32 may selectively have adhesive properties, thereby strengthening the fixation of the photonic crystal 2 in the cavity 11. The term "high transmittance" may, for example, mean a transmittance of optical signals greater than 70%, greater than 80%, or greater than 90%, but this disclosure is not limited thereto. In one embodiment of this disclosure, the transmittance of optical signals by the optical layer 32 may be greater than or equal to the transmittance of optical signals by the connector 31. In one embodiment of this disclosure, the adhesiveness of the optical layer 32 may be less than or equal to the adhesiveness of the connector 31.

[0112] In one embodiment of this disclosure, such as Figure 1AAs shown in a cross-sectional view, the first waveguide 12 has a side 12s1 adjacent to the lower surface 1s2 of the first substrate 1 and another side 12s2 away from the lower surface 1s2 of the first substrate 1, that is, one side 12s1 of the first waveguide 12 is closer to the lower surface 1s2 of the first substrate 1 than the other side 12s2. The height of the connector 31 to the first bottom surface 11s1 of the cavity 11 can be a first height H1; the height of one side 12s1 of the first waveguide 12 to the first bottom surface 11s1 of the cavity 11 can be a second height H2; the height of the other side 12s2 of the first waveguide 12 to the first bottom surface 11s1 of the cavity 11 can be a third height H3; the height of the second waveguide 24 to the first bottom surface 11s1 of the cavity 11 can be a fourth height H4, wherein the first height H1 is less than the second height H2, the second height H2 is less than the fourth height H4, and the fourth height H4 is less than the third height H3. The "first height H1" refers, for example, in a cross-sectional view, the distance between the top surface of the connector 31 and the first bottom surface 11s1 of the cavity 11 along the normal direction Z of the first substrate 1. The "fourth height H4" refers, for example, in a cross-sectional view, the distance between the top surface of the second waveguide 24 and the first bottom surface 11s1 of the cavity 11 along the normal direction Z of the first substrate 1.

[0113] In one embodiment of this disclosure, the second height H2, the third height H3, and the fourth height H4 may satisfy the following formula:

[0114] [H2+(H3-H2) / 4]≦H4≦[H3-(H3-H2) / 4]

[0115] H2 is the second altitude, H3 is the third altitude, and H4 is the fourth altitude.

[0116] In one embodiment of this disclosure, such as Figure 1A As shown, the first waveguide 12 can be embedded in the first substrate 1. The first waveguide 12 can be formed by modifying a specific area inside the first substrate 1 by irradiating it with laser light; therefore, as... Figure 1B As shown, the cross-section of the first waveguide 12 may be, for example, elliptical (or circular) and includes a first portion 12A and a second portion 12B, the second portion 12B surrounding the first portion 12A, wherein the refractive index of the first portion 12A is greater than the refractive index of the second portion 12B. In another embodiment of this disclosure, the first waveguide 12 may be disposed on the first substrate 1, but this disclosure is not limited thereto.

[0117] Figure 2A A cross-sectional schematic diagram of a portion of an electronic device according to another embodiment of this disclosure is shown. Figure 2B It shows Figure 2A A magnified view of a portion of the image.

[0118] In one embodiment of this disclosure, such as Figure 2A and Figure 2B As shown, the electronic device may include: a second substrate 4, including a first through-hole 41 and a first side surface 4s1 surrounding the first through-hole 41; an insulating layer 5 disposed on the second substrate 4 and including a second through-hole 51 and a second side surface 5s1 surrounding the second through-hole 51, wherein, in the top view direction of the electronic device (e.g., the Z direction normal to the second substrate 4), the first through-hole 41 and the second through-hole 51 overlap; an active layer 6 disposed on the insulating layer 5 and including a third waveguide 61 and a photoelectric converter 62 optically coupled to the third waveguide 61; a semiconductor die 7 disposed on the active layer 6 and electrically connected to the photoelectric converter 62; and a conductive element 8 electrically connected to the semiconductor die 7 and including a first portion 8A and a second portion 8B, the first portion 8A being disposed in the first through-hole 41 and the second portion 8B being disposed in the second through-hole 51.

[0119] More in detail, such as Figure 2A and Figure 2B As shown, the second substrate 4 includes an upper surface 4s2 and a lower surface 4s3 opposite to the upper surface 4s2. An insulating layer 5 is disposed between the second substrate 4 and the active layer 6. For example, the insulating layer 5 can contact the second substrate 4 and the active layer 6 respectively, wherein the insulating layer 5 includes an upper surface 5s2 and a lower surface 5s3 opposite to the upper surface 5s2. A first through-hole 41 penetrates the second substrate 4, and a second through-hole 51 penetrates the insulating layer 5. The first through-hole 41 and the second through-hole 51 can communicate with each other. The semiconductor die 7 may include: a base layer 71; an interconnect layer 72; a dielectric layer 73, wherein the interconnect layer 72 is disposed between the base layer 71 and the dielectric layer 73; and a plurality of connection pads 74 disposed in the dielectric layer 73. A first portion 8A of the conductive element 8 is disposed in the first through-hole 41, and a second portion 8B of the conductive element 8 is disposed in the second through-hole 51, and the first portion 8A and the second portion 8B are connected. The first part 8A of the conductive element 8 can extend and be disposed on the lower surface 4s3 of the second substrate 4 and electrically connected to a pad P1, and the second part 8B of the conductive element 8 can extend and be disposed on the upper surface 5s2 of the insulating layer 5.

[0120] In one embodiment of this disclosure, such as Figure 2AAs shown, the electronic device may further include a circuit layer CL disposed between the semiconductor die 7 and the conductive element 8, wherein the semiconductor die 7 is electrically connected to the conductive element 8 through the circuit layer CL. More specifically, the circuit layer CL may include a plurality of conductive units CL1 disposed on the conductive element 8; a plurality of connection pads CL2 disposed on and electrically connected to the plurality of conductive units CL1; and a dielectric layer CL3, wherein the conductive units CL1 and the connection pads CL2 are disposed in the dielectric layer CL3. In this disclosure, the connection pads CL2 of the circuit layer CL are electrically connected to the connection pads 74 of the semiconductor die 7, and at least one of the conductive units CL1 of the circuit layer CL is electrically connected to the conductive element 8, thereby enabling electrical signals to be transmitted between the semiconductor die 7 and the connection pads P1 through the circuit layer CL and the conductive element 8. Another conductive unit CL1 of the circuit layer CL (e.g., conductive unit CL1') can be electrically connected to the photoelectric converter 62 and the semiconductor die 7, respectively, so that optical signals and / or electrical signals are converted by the photoelectric converter 62 and transmitted between the semiconductor die 7 and the third waveguide 61. More specifically, for example, the photoelectric converter 62 can convert the optical signal provided by the third waveguide 61 into an electrical signal and transmit it to the semiconductor die 7 through another conductive unit CL1 (e.g., conductive unit CL1') and the connecting pad CL2, or the electrical signal provided by the semiconductor die 7 can be transmitted to the photoelectric converter 62 through the connecting pad CL2 and another conductive unit CL1 (e.g., conductive unit CL1'), and the photoelectric converter 62 converts the electrical signal into an optical signal and transmits it to the third waveguide 61. In this disclosure, the second substrate 4, the insulating layer 5, the active layer 6, and the circuit layer CL can be formed as a photonic interposer PI, wherein the semiconductor die 7 is disposed on the photonic interposer PI.

[0121] In one embodiment of this disclosure, such as Figure 2A and Figure 2B As shown, the roughness of the first side surface 4s1 of the second substrate 4 is different from the roughness of the second side surface 5s1 of the insulating layer 5. For example, the roughness of the first side surface 4s1 of the second substrate 4 is greater than the roughness of the second side surface 5s1 of the insulating layer 5. The roughness of the side surface affects the adhesion effect of the component and / or the signal transmission efficiency. Increasing the roughness of the side surface can improve the adhesion effect of the component, while decreasing the roughness of the side surface can improve the signal transmission efficiency. Therefore, when the roughness of the first side surface 4s1 and the second side surface 5s1 meets the above-mentioned limitations, the adhesion effect of the conductive component 8 and / or the signal transmission efficiency can be improved.

[0122] In one embodiment of this disclosure, such as Figure 2A and Figure 2BAs shown, in a cross-section, the width W2 of the second through-hole 51 of the insulating layer 5 is smaller than the width W1 of the first through-hole 41 of the second substrate 4. The "width of the through-hole" refers, for example, to the maximum dimension measured at the interface between the insulating layer 5 and the second substrate 4 in the cross-section. In one embodiment of this disclosure, as... Figure 2A As shown, in the top view of the electronic device (e.g., in the Z direction normal to the second substrate 4), the third waveguide 61 does not overlap with the second through-hole 51. In one embodiment of this disclosure, as... Figure 2A As shown, in the top view of the electronic device (e.g., in the Z direction, the normal direction of the second substrate 4), the third waveguide 61 does not overlap with the first through hole 41.

[0123] In one embodiment of this disclosure, such as Figure 2A As shown, the electronic device may include multiple semiconductor chips 7, which are electrically insulated from each other through an encapsulation layer EL, and each semiconductor chip 7 is electrically connected to a corresponding conductive element 8 through a circuit layer CL.

[0124] In this disclosure, the material of the second substrate 4 may include glass, silicon, silicon carbide, ceramic, resin, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In one embodiment of this disclosure, the second substrate 4 may be a silicon substrate. In this disclosure, the materials of the insulating layer 5 and the encapsulation layer EL may each include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the material of the third waveguide 61 may include silicon, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), silicon germanium (SiGe), diamond, quartz, ceramic, glass, plastic, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the photoelectric converter 62 includes elements capable of performing photoelectric conversion. In this disclosure, the material of the base layer 71 is as described above and will not be repeated here. In this disclosure, the inner connection layer 72 may include wires, pads, driving circuitry, other suitable elements, or combinations thereof. Suitable components may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, diodes, transistors, etc., but this disclosure is not limited thereto. In this disclosure, the materials of dielectric layer 73 and dielectric layer CL3 may each comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, semiconductor die 7 may comprise a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), memory, a logic die, or combinations thereof, but this disclosure is not limited thereto. In this disclosure, the materials of the connecting pad 74, the conductive element 8, the conductive unit CL1, and the connecting pad CL2 may each comprise a metallic material, a metal oxide material, an alloy thereof, or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (AZO), but this disclosure is not limited thereto.

[0125] Figure 3 A cross-sectional schematic diagram of a portion of an electronic device according to another embodiment of this disclosure is shown. Figure 3 electronic devices and Figure 1A and Figure 2A Similar, except for the following differences.

[0126] In one embodiment of this disclosure, such as Figure 3As shown, the electronic device includes: a first substrate 1 containing a cavity 11; a photonic chip 2 disposed in the cavity 11 of the first substrate 1; a first waveguide 12 disposed corresponding to the photonic chip 2 and receiving an optical signal from the photonic chip 2; a second substrate 4 disposed on the first substrate 1; a semiconductor chip 7 disposed on the second substrate 4; and a third waveguide 61 disposed between the second substrate 4 and the semiconductor chip 7 and receiving the optical signal through the first waveguide 12.

[0127] In this disclosure, the local structure and features of components such as the first substrate 1, the photonic crystal 2, and the first waveguide 12 can be referred to Figure 1A and Figure 1B The partial structure and features of components such as the second substrate 4, semiconductor die 7, and third waveguide 61 can be referenced from the disclosure. Figure 2A and Figure 2B The details described herein will not be repeated here. In one embodiment of this disclosure, the first substrate 1 is a glass substrate, and the second substrate 4 is a silicon substrate. In one embodiment of this disclosure, for light with wavelengths from 650 nm to 900 nm, the transmittance of the first substrate 1 may be greater than that of the second substrate 4. In one embodiment of this disclosure, the refractive index of the third waveguide 61 may be greater than that of the first waveguide 12.

[0128] In one embodiment of this disclosure, such as Figure 3 As shown, the electronic device may further include an optical transmission element 9, disposed on the first substrate 1 and used to transmit an optical signal from the first waveguide 12 to the third waveguide 61. That is, the optical signal provided by the photonic chip 2 can be transmitted to the first waveguide 12 via the second waveguide 24, and then the optical signal is transmitted to the third waveguide 61 via the optical transmission element 9. More specifically, the optical transmission element 9 may include an optical transmission medium 91, a lens 92, and a reflection unit 93. The lens 92 can be used to focus the optical signal provided by the first waveguide 12 and transmit it through the optical transmission medium 91 to the reflection unit 93. The reflection unit 93 can reflect the optical signal to the third waveguide 61. In this disclosure, the optical transmission medium 91 is a material that can provide optical signal transmission, such as air, vacuum, optical fiber, or other suitable material. In this disclosure, the lens 92 may be, for example, a convex lens, but this disclosure is not limited thereto. In this disclosure, the reflection unit 93 may be, for example, a mirror, but this disclosure is not limited thereto.

[0129] In one embodiment of this disclosure, such as Figure 3As shown, the electronic device may further include: a first redistribution layer RDL1; a second redistribution layer RDL2 disposed on the first redistribution layer RDL1, wherein a first substrate 1 is disposed on the second redistribution layer RDL2; a third redistribution layer RDL3 disposed on the first substrate 1; and a fourth redistribution layer RDL4 disposed on the third redistribution layer RDL3, wherein a second substrate 4 is disposed on the fourth redistribution layer RDL4. The circuits in the first redistribution layer RDL1 can be electrically connected to the circuits in the second redistribution layer RDL2, and the circuits in the third redistribution layer RDL3 can be electrically connected to the circuits in the fourth redistribution layer RDL4. Furthermore, the circuits in the second redistribution layer RDL2 can be electrically connected to the circuits in the third redistribution layer RDL3 through conductive material disposed in the through-holes 13 of the first substrate 1, so as to transmit signals from one side of the first substrate 1 to the other side. In one embodiment of this disclosure, the conductive element 8 can be electrically connected to the circuits in the fourth redistribution layer RDL4 through a pad P1. In one embodiment of this disclosure, the circuitry in the first multilayer RDL1 can be electrically connected to a pad P2 to transmit signals to an external component (not shown). In this disclosure, the first multilayer RDL1, the second multilayer RDL2, the third multilayer RDL3, and the fourth multilayer RDL4 can each be selectively multilayered and may include circuit structures formed by the alternating stacking of wires and insulating layers.

[0130] In one embodiment of this disclosure, such as Figure 3 As shown, the electronic device may further include: a first semiconductor die EIC1 disposed on a third redistribution layer RDL3, wherein the first semiconductor die EIC1 is electrically connected to the photonic die 2 via circuitry on the third redistribution layer RDL3; and a second semiconductor die EIC2 disposed on a fourth redistribution layer RDL4, wherein the first semiconductor die EIC1 and the second semiconductor die EIC2 are electrically connected. More specifically, the first semiconductor die EIC1 may be electrically connected to circuitry on the third redistribution layer RDL3 via a pad P3, and the second semiconductor die EIC2 may be electrically connected to the first semiconductor die EIC1 via another pad P4. In this disclosure, the first semiconductor die EIC1 and the second semiconductor die EIC2 may each include a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), memory, a logic chip, or a combination thereof, but this disclosure is not limited thereto.

[0131] In this disclosure, an electrical signal can be applied to the first semiconductor die EIC1 and / or the second semiconductor die EIC2. The electrical signal is transmitted to the photonic die 2 via the circuit on the third redistribution layer RDL3. The photonic die 2 converts the received electrical signal into a corresponding optical signal, thereby providing an optical signal. The optical signal can be transmitted sequentially through the first waveguide 12, the optical transmission element 9, and the third waveguide 61 to the photoelectric converter 62. The photoelectric converter 62 can convert the optical signal into another electrical signal and provide it to the semiconductor die 7, thereby realizing signal transmission. Since optical signals have advantages such as fast transmission speed and low power loss, the electronic device of this disclosure can improve transmission efficiency and / or reduce transmission energy loss by using the photonic die 2 for photoelectric signal conversion, thereby improving problems such as poor transmission efficiency and / or overheating of the electronic device.

[0132] In one embodiment of this disclosure, such as Figure 3 As shown, the electronic device may further include: a filling material F1 disposed on the third wiring layer RDL3 and surrounding the first semiconductor die EIC1. The filling material F1 may also be disposed in the gap between the first semiconductor die EIC1 and the third wiring layer RDL3 to improve the reliability of the first semiconductor die EIC1 being fixed on the third wiring layer RDL3. Similarly, as Figure 3 As shown, the electronic device may further include: another filler material F2, disposed on the fourth redistribution layer RDL4 and surrounding the second semiconductor die EIC2. The other filler material F2 may also be disposed in the gap between the second semiconductor die EIC2 and the fourth redistribution layer RDL4 to improve the reliability of the second semiconductor die EIC2 being fixed on the fourth redistribution layer RDL4. In this disclosure, filler material F1 and the other filler material F2 may each comprise a thermosetting resin, such as epoxy resin, but this disclosure is not limited thereto.

[0133] In one embodiment of this disclosure, such as Figure 3 As shown, the electronic device may further include: a barrier structure S disposed on the fourth redistribution layer RDL4 and surrounding another filler material F2, the barrier structure S being used to limit the placement of the other filler material F2. More specifically, the other filler material F2 may be applied to the fourth redistribution layer RDL4 in liquid or semi-liquid form, and the other filler material F2 may be confined within the area formed by the barrier structure S. Through capillary action, the other filler material F2 may fill the gap between the second semiconductor die EIC2 and the fourth redistribution layer RDL4. The other filler material F2 is then cured to fix the second semiconductor die EIC2 onto the fourth redistribution layer RDL4. In this disclosure, the material of the barrier structure S may include silicon oxide, silicon nitride, silicon oxynitride, resin, photoresist, other suitable materials, or combinations thereof, but this disclosure is not limited thereto.

[0134] Other features of the first waveguide 12 and the third waveguide 61 will be described in detail below.

[0135] Figure 4A A cross-sectional schematic diagram of a part of the first waveguide of an embodiment of the present disclosure is shown. Figure 4B A top-view schematic diagram of a part of the third waveguide of an embodiment of the present disclosure is shown. Figure 4C Shows Figure 4A A cross-sectional schematic diagram of the line segment B-B'. Figure 4D Shows Figure 4B A cross-sectional schematic diagram of the line segment C-C'. Among them, Figure 4A and Figure 4B are Figure 3 Partial enlarged views. In addition, for the convenience of description, some elements are omitted in the figure.

[0136] In an embodiment of the present disclosure, as Figure 4A and Figure 4B shown, the first waveguide 12 includes a first curved segment 12S, and the third waveguide 61 includes a second curved segment 61S. Among them, a first curvature radius R1 of the first curved segment 12S is greater than a second curvature radius R2 of the second curved segment 61S. In an embodiment of the present disclosure, a first curvature of the first curved segment 12S is less than a second curvature of the second curved segment 61S.

[0137] In an embodiment of the present disclosure, as Figure 4C and Figure 4D shown, in a cross-sectional view, the first waveguide 12 has a first width W3 and a first thickness T1, and the third waveguide 61 has a second width W4 and a second thickness T2. Among them, the first width W3 is greater than the second width W4, and the first thickness T1 is greater than the second thickness T2. In an embodiment of the present disclosure, the ratio of the second width W4 to the first width W3 may be greater than 0 and less than or equal to 0.5 (i.e., 0 < W4 / W3 ≤ 0.5), but the present disclosure is not limited thereto. The "width" refers to, for example, the maximum lateral dimension of the component in the cross-sectional view. The "thickness" refers to, for example, the maximum dimension of the component along the normal direction Z of the substrate (such as the first substrate 1 or the second substrate 4) in the cross-sectional view.

[0138] Figure 5 A cross-sectional schematic diagram of a part of an electronic device of another embodiment of the present disclosure is shown. Figure 6A and Figure 6B respectively show Figure 5 Cross-sectional schematic diagrams of different embodiments of the line segment D-D'. Among them, Figure 5 The electronic device of Figure 3 is similar, except for the following differences.

[0139] In an embodiment of the present disclosure, as Figure 5As shown, the first waveguide 12 of the electronic device can be disposed on the first substrate 1. More specifically, in one embodiment, as Figure 6A shown, the first waveguide 12 can be directly disposed on the first substrate 1, that is, the first waveguide 12 can be in direct contact with the upper surface 1s1 of the first substrate 1, and the third redistribution layer RDL3 can be disposed on the first waveguide 12. In another embodiment, as Figure 6B shown, the first waveguide 12 can be disposed on the first substrate 1 and also disposed in the third redistribution layer RDL3, that is, the first waveguide 12 will not be in direct contact with the upper surface 1s1 of the first substrate 1, and wires and / or insulating layers, etc. in the third redistribution layer RDL3 can be included between the first waveguide 12 and the upper surface 1s1 of the first substrate 1. In this embodiment, the width W5 of the first waveguide 12 can be greater than the second width W4 of the third waveguide 61 (as Figure 4D shown), and the thickness T3 of the first waveguide 12 can be greater than the second thickness T2 of the third waveguide 61 (as Figure 4D shown). In an embodiment of the present disclosure, the ratio of the second width W4 to the width W5 can be greater than 0 and less than or equal to 0.5 (i.e., 0 < W4 / W5 ≤ 0.5), but the present disclosure is not limited thereto.

[0140] In an embodiment of the present disclosure, as Figure 5 shown, the light conduction element 9 can include a light conduction medium 91 and two reflection units 93, and the reflection units 93 can transmit the optical signal to the third waveguide 61 through reflection. More specifically, the optical signal provided by the photon die 2 can be transmitted to the first waveguide 12 through the second waveguide 24, and then the optical signal is transmitted to the third waveguide 61 via the light conduction element 9.

[0141] In the present disclosure, other features of the electronic device can be as Figure 3 described, and will not be elaborated herein.

[0142] In the present disclosure, by disposing the photon die and / or waveguide in the electronic device, the electronic device can be used to transmit optical signals, thereby improving problems such as poor transmission efficiency and / or overheating of the electronic device.

[0143] The above specific embodiments should be construed as merely illustrative and not limiting the remainder of the present disclosure in any way.

Claims

1. An electronic device, characterized in that, Include: A first substrate includes a cavity having a first bottom surface; A photonic crystal is disposed in the cavity and has a second bottom surface facing the first bottom surface; A connector is disposed between the first bottom surface and the second bottom surface; and A first waveguide is provided corresponding to the photonic chip and receives an optical signal from the photonic chip; The roughness of the first bottom surface of the first substrate is different from the roughness of the second bottom surface of the photonic crystal.

2. The electronic device according to claim 1, characterized in that, The roughness of the first bottom surface of the first substrate is greater than the roughness of the second bottom surface of the photonic crystal.

3. The electronic device according to claim 1, characterized in that, The first waveguide is embedded in the first substrate.

4. The electronic device according to claim 1, characterized in that, The height of the connector to the first bottom surface of the cavity is less than the height of the first waveguide to the first bottom surface of the cavity.

5. The electronic device according to claim 1, characterized in that, The photonic chip also includes a second waveguide for transmitting the optical signal to the first waveguide.

6. The electronic device according to claim 5, characterized in that, It also includes an optical layer disposed between the first waveguide and the second waveguide.

7. The electronic device according to claim 1, characterized in that, The first waveguide is disposed on the first substrate.

8. The electronic device according to claim 1, characterized in that, In one cross-section, the photonic grain contains a chamfered structure.

9. An electronic device, characterized in that, Include: A second substrate includes a first through hole and a first side surface surrounding the first through hole; An insulating layer is disposed on the second substrate and includes a second through hole and a second side surface surrounding the second through hole, wherein, in the top view of the electronic device, the first through hole overlaps with the second through hole; An active layer is disposed on the insulating layer and includes a third waveguide and a photoelectric converter optically coupled to the third waveguide; A semiconductor die is disposed on the active layer and electrically connected to the photoelectric converter; and A conductive element electrically connected to the semiconductor die and comprising a first portion and a second portion, the first portion being disposed in the first through-hole and the second portion being disposed in the second through-hole; The roughness of the first side surface of the second substrate is different from the roughness of the second side surface of the insulating layer.

10. The electronic device according to claim 9, characterized in that, The roughness of the first side surface of the second substrate is greater than the roughness of the second side surface of the insulating layer.

11. The electronic device according to claim 9, characterized in that, In a cross-section, the width of the second perforation in the insulating layer is smaller than the width of the first perforation in the second substrate.

12. The electronic device according to claim 9, characterized in that, From the top view of the electronic device, the third waveguide does not overlap with the second perforation.

13. The electronic device according to claim 9, characterized in that, The insulating layer is in contact with the second substrate and the active layer.

14. An electronic device, characterized in that, Include: A first substrate, comprising a cavity; A photonic crystal is disposed in the cavity of the first substrate; A first waveguide is provided corresponding to the photonic chip and receives an optical signal from the photonic chip; A second substrate is disposed on the first substrate; A semiconductor die is disposed on the second substrate; and A third waveguide is disposed between the second substrate and the semiconductor die and receives the optical signal through the first waveguide.

15. The electronic device according to claim 14, characterized in that, The first width of the first waveguide is greater than the second width of the third waveguide.

16. The electronic device according to claim 15, characterized in that, The ratio of the second width to the first width is greater than 0 and less than or equal to 0.

5.

17. The electronic device according to claim 14, characterized in that, The first thickness of the first waveguide is greater than the second thickness of the third waveguide.

18. The electronic device according to claim 14, characterized in that, The first waveguide includes a first curved segment, the third waveguide includes a second curved segment, and a first radius of curvature of the first curved segment is greater than a second radius of curvature of the second curved segment.

19. The electronic device according to claim 14, characterized in that, For light with wavelengths from 650 nm to 900 nm, the transmittance of the first substrate is greater than that of the second substrate.

20. The electronic device according to claim 14, characterized in that, The first substrate is a glass substrate, and the second substrate is a silicon substrate.

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