Optoelectronic co-packaging structure and method of forming the same

Abstract

The application discloses an optoelectronic co-encapsulation structure and a forming method thereof. The optoelectronic co-encapsulation structure comprises: a photonic chip interposer structure, comprising: a photonic chip, a plurality of metal bumps protruding on a second active surface of the photonic chip, and a plurality of optical ports in the second active surface on one side of the plurality of metal bumps; a plastic encapsulation layer covering the photonic chip, a first surface of the plastic encapsulation layer exposing the metal bumps and the optical ports; a first redistribution layer located on part of the first surface, the first redistribution layer being electrically connected with the metal bumps and exposing the optical ports; and an electronic chip assembly structure, the electronic chip assembly structure comprising: an electronic chip, a first active surface of the electronic chip having a circuit layer; a diamond heat conduction sheet bonded to a first back surface of the electronic chip; the electronic chip assembly structure being bonded to the photonic chip interposer structure; and a heat sink attached to a surface of the diamond heat conduction sheet away from the electronic chip. The heat dissipation efficiency of the electronic chip is improved, and the performance of the photonic chip is improved.

Description

Technical Field

[0001] This application relates to the field of advanced packaging, and in particular to an optoelectronic co-packaging structure and a method for forming the same. Background Technology

[0002] Co-Packaged Optics (CPO) is an advanced optoelectronic integration technology that directly integrates a light engine or photonic integrated circuit (PIC) with an electronic integrated circuit (EIC) within the same package.

[0003] Currently, advanced packaging technology, Fan-Out Wafer-Level Packaging (FOWLP), is commonly used to fabricate optoelectronic co-package structures. However, the electronic chips in this co-package structure have high power and generate significant heat. The heat generated by the electronic chips is conducted to the photonic chips, which can significantly affect their performance. Summary of the Invention

[0004] The purpose of this application is to provide an optoelectronic co-packaging structure and a method for forming the same, so as to improve the heat dissipation efficiency of electronic chips and thus enhance the performance of photonic chips.

[0005] To achieve the above objectives, this application first provides a method for forming an optoelectronic co-packaging structure, including:

[0006] At least one electronic chip assembly structure is provided, each of the electronic chip assembly structures comprising: an electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; and a diamond thermal conductive sheet bonded to the first back surface of the electronic chip. A photonic chip interposer structure is provided, comprising: a photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a protective layer located on a portion of the second active surface and covering the optical port; a molding compound layer encapsulating the photonic chip, the molding compound layer including a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps and the protective layer on the surface away from the second active surface; and a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bumps and exposing the protective layer. The wiring layer in the at least one electronic chip component structure is bonded to the first wiring layer of the photonic chip interposer structure. A heat sink is provided, and the heat sink is attached to the surface of the diamond thermal conductive sheet away from the electronic chip through a thermal interface material layer.

[0007] In some embodiments of this application, the thickness of the diamond heat-conducting sheet is 0.1mm-0.5mm.

[0008] In some embodiments of this application, the material of the diamond heat-conducting sheet is single-crystal diamond or polycrystalline diamond, wherein the thermal conductivity of the single-crystal diamond is in the range of 1800 W / (m·K)-2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond is in the range of 800 W / (m·K)-1500 W / (m·K).

[0009] In some embodiments of this application, the diamond thermal conductive sheet is bonded to the first back side of the electronic chip via a metal bonding layer.

[0010] In some embodiments of this application, the thickness of the metal bonding layer is less than or equal to 100 nm; The material of the metal bonding layer is one or more of Ti, Cu, W, and Au.

[0011] In some embodiments of this application, the number of electronic chip component structures is one or more; When there are multiple electronic chip component structures, the electronic chips in different electronic chip component structures may have the same or different functions. When there are multiple electronic chip assembly structures, a diamond heat-conducting sheet is bonded to the first back side of the electronic chip in each electronic chip assembly structure.

[0012] In some embodiments of this application, bonding the wiring layer in the at least one electronic chip component structure to the first rewiring layer of the photonic chip interposer structure includes: A first bonding layer is formed on the surface of the circuit layer in the electronic chip assembly structure that is away from the first active surface; A second bonding layer is formed on the surface of the first redistribution layer in the photonic chip interposer structure that is away from the photonic chip; The first bonding layer is bonded to the second bonding layer.

[0013] In some embodiments of this application, the circuit layer includes a dielectric layer and a metal circuit layer located within the dielectric layer; The first bonding layer includes a first bonding dielectric layer and a first bonding metal layer located in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the metal circuit layer.

[0014] In some embodiments of this application, the materials of the dielectric layer and the first bonding dielectric layer are inorganic materials, and the materials of the metal circuit layer and the first bonding metal layer are conductive metal materials.

[0015] In some embodiments of this application, the first redistribution layer includes a first dielectric layer and a first metal wiring layer located within the first dielectric layer; The second bonding layer includes a second bonding dielectric layer and a second bonding metal layer located in the second bonding dielectric layer, wherein the second bonding metal layer is electrically connected to the first metal wiring layer.

[0016] In some embodiments of this application, the materials of the first dielectric layer and the second bonding dielectric layer are organic materials, and the materials of the first metal wiring layer and the second bonding metal layer are conductive metal materials.

[0017] In some embodiments of this application, the formation process of the electronic chip assembly structure includes: A first wafer is provided, the first wafer including a plurality of electronic chip regions and a first dicing region located between the electronic chip regions; Several electronic devices are formed in the electronic chip area on the front side of the first wafer; A circuit layer is formed on the front side of the first wafer, and the circuit layer is electrically connected to the plurality of electronic devices; A first bonding layer is formed on the circuit layer; A first carrier plate is bonded to the surface of the first bonding layer that is away from the first wafer; A metal bonding layer is formed on the back side of the first wafer; The metal bonding layer, the circuit layer, and the first wafer are cut along the first dicing zone; After the cutting is performed, a diamond thermal conductive sheet is bonded to the surface of the metal bonding layer of each electronic chip area away from the first wafer. After bonding the diamond thermal conductive sheet, the first carrier plate is removed to form a plurality of discrete electronic chip component structures.

[0018] In some embodiments of this application, the photonic chip interposer structure further includes: A plurality of metal pillars are located in the molding layer, and the first and second surfaces of the molding layer expose the two end surfaces of the metal pillars, respectively. One end surface of the metal pillar is electrically connected to the first redistribution layer. The second wiring layer is located on the second surface of the molding layer and the second back surface of the photonic chip, and the second wiring layer is electrically connected to the other end surface of the metal pillar. A solder bump is located on the surface of the second wiring layer away from the photonic chip, and the solder bump is electrically connected to the second wiring layer.

[0019] In some embodiments of this application, the second redistribution layer includes a second dielectric layer and a second metal wiring layer located within the second dielectric layer; The material of the second dielectric layer includes organic materials, and the material of the second metal wiring layer includes conductive metal materials.

[0020] In some embodiments of this application, the formation process of the photonic chip interposer structure includes: A photonic chip is provided, the photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a protective layer located on a portion of the second active surface and covering the optical port; Provide a second carrier board; A second wiring layer is formed on the surface of the second carrier board; A plurality of metal pillars are formed on the surface of the second redistribution layer away from the second carrier board; The second back side of the photonic chip is attached to the surface of the second redistribution layer that is away from the second substrate. A molding compound layer is formed on the surface of the second redistribution layer away from the second substrate, covering the photonic chip and the metal pillar. The first surface of the molding compound layer exposes the surface of the metal pillar and the protective layer away from the second active surface of the photonic chip, and the surface of the metal bump away from the second redistribution layer. A first redistribution layer is formed on a portion of the first surface of the molding layer, the first redistribution layer being electrically connected to the metal bump and exposing the protective layer; Remove the second carrier board and form a solder bump on the surface of the second redistribution layer away from the photonic chip.

[0021] In some embodiments of this application, the photonic chip further has a groove penetrating a portion of the second active surface, and the sidewall of the groove exposes the optical port; The protective layer fills the groove and covers the optical port, and the surface of the protective layer is higher than the surface of the second active surface.

[0022] In some embodiments of this application, the formation process of the photonic chip includes: A second wafer is provided, the second wafer comprising a plurality of photonic chip regions and a second dicing region located between the photonic chip regions; Photonic devices and optical ports are formed in the photonic chip region on the front side of the second wafer; A groove is formed in a second wafer on one side of the optical aperture, and the sidewall of the groove exposes the optical aperture; A protective layer covering the optical port is formed in the groove and on the surface of part of the photonic chip area; After the protective layer is formed, a plurality of raised metal bumps are formed on the second active surface; After forming several metal bumps, the second wafer is cut along the second dicing zone to form several discrete photonic chips.

[0023] In some embodiments of this application, the material of the protective layer includes photoresist; The formation of the protective layer includes a spin coating process, an exposure process, and a development process.

[0024] In some embodiments of this application, after bonding the wiring layer in the at least one electronic chip component structure to the first redistribution layer of the photonic chip interposer structure, the method further includes: A slitting process is performed to cut away part of the protective layer in the groove, as well as the molding layer and photonic chip away from the outside of the groove, while the remaining protective layer in the groove still covers the optical port; After the offset cutting process, the remaining protective layer in the groove is removed to expose the optical aperture.

[0025] In some embodiments of this application, the process of removing the remaining protective layer in the groove includes: selectively rinsing the protective layer with a protective layer removal liquid to remove the protective layer.

[0026] In some embodiments of this application, after exposing the optical port, the method further includes: installing an optical coupling component corresponding to the position of the optical port on one side of the photonic chip.

[0027] In some embodiments of this application, the material of the thermal interface material layer includes nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

[0028] This application also provides an optoelectronic co-packaging structure, including: A photonic chip interposer structure includes: a photonic chip, comprising a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a molding compound covering the photonic chip, the molding compound comprising a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps and the optical port; and a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bumps and exposing the optical port. At least one electronic chip assembly structure, each of the electronic chip assembly structures comprising: an electronic chip, the electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; a diamond thermal conductive sheet, the diamond thermal conductive sheet being bonded to the first back surface of the electronic chip; the circuit layer in the at least one electronic chip assembly structure being bonded to a first redistribution layer of the photonic chip interposer structure; A heat sink is attached to the surface of the diamond thermally conductive sheet away from the electronic chip via a thermal interface material layer.

[0029] In some embodiments of this application, the thickness of the diamond heat-conducting sheet is 0.1mm-0.5mm.

[0030] In some embodiments of this application, the material of the diamond heat-conducting sheet is single-crystal diamond or polycrystalline diamond, wherein the thermal conductivity of the single-crystal diamond is in the range of 1800 W / (m·K)-2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond is in the range of 800 W / (m·K)-1500 W / (m·K).

[0031] In some embodiments of this application, the diamond thermal conductive sheet is bonded to the first back side of the electronic chip via a metal bonding layer; The thickness of the metal bonding layer is less than or equal to 100 nm; The material of the metal bonding layer is one or more of Ti, Cu, W, and Au.

[0032] In some embodiments of this application, the number of electronic chip component structures is one or more; When there are multiple electronic chip component structures, the electronic chips in different electronic chip component structures may have the same or different functions. When there are multiple electronic chip assembly structures, a diamond heat-conducting sheet is bonded to the first back side of the electronic chip in each electronic chip assembly structure.

[0033] In some embodiments of this application, it also includes: The first bonding layer located on the surface of the circuit layer in the electronic chip assembly structure that is away from the first active surface; A second bonding layer located on the surface of the first redistribution layer in the photonic chip interposer structure, away from the photonic chip; The first bonding layer is bonded to the second bonding layer.

[0034] In some embodiments of this application, the circuit layer includes a dielectric layer and a metal circuit layer located within the dielectric layer; The first bonding layer includes a first bonding dielectric layer and a first bonding metal layer located in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the metal circuit layer; The dielectric layer and the first bonding dielectric layer are made of inorganic materials, while the metal circuit layer and the first bonding metal layer are made of conductive metal materials.

[0035] In some embodiments of this application, the first redistribution layer includes a first dielectric layer and a first metal wiring layer located within the first dielectric layer; The second bonding layer includes a second bonding dielectric layer and a second bonding metal layer located in the second bonding dielectric layer, wherein the second bonding metal layer is electrically connected to the first metal wiring layer; The first dielectric layer and the second bonding dielectric layer are made of organic materials, and the first metal wiring layer and the second bonding metal layer are made of conductive metal materials.

[0036] In some embodiments of this application, the photonic chip interposer structure further includes: A plurality of metal pillars are located in the molding layer, and the first and second surfaces of the molding layer expose the two end surfaces of the metal pillars, respectively. One end surface of the metal pillar is electrically connected to the first redistribution layer. The second wiring layer is located on the second surface of the molding layer and the second back surface of the photonic chip, and the second wiring layer is electrically connected to the other end surface of the metal pillar. A solder bump is located on the surface of the second wiring layer away from the photonic chip, and the solder bump is electrically connected to the second wiring layer.

[0037] In some embodiments of this application, the photonic chip also has a groove penetrating a portion of the second active surface and a portion of the side surface of the photonic chip, with the sidewall of the groove exposing the optical port.

[0038] In some embodiments of this application, an optical coupling component is also included, which is mounted on the side of the photonic chip and corresponds to the position of the optical port.

[0039] In some embodiments of this application, the material of the thermal interface material layer includes nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

[0040] The beneficial effects of this application are: This application discloses an optoelectronic co-packaging structure and its forming method. The forming method includes: providing at least one electronic chip assembly structure, each of the electronic chip assembly structures including: an electronic chip, the electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; a diamond thermal conductive sheet, the diamond thermal conductive sheet being bonded to the first back surface of the electronic chip; and providing a photonic chip interposer structure, the photonic chip interposer structure including: a photonic chip, the photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and a portion of the second active surface on one side of the plurality of metal bumps having a... The device includes: an optical port; a protective layer located on a portion of the second active surface and covering the optical port; a molding compound layer encapsulating the photonic chip, the molding compound layer including a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bump and the surface of the protective layer away from the second active surface; a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bump and exposing the protective layer; bonding the wiring layer in the at least one electronic chip assembly structure to the first redistribution layer of the photonic chip interposer structure; and providing a heat sink, the heat sink being mounted to the surface of the diamond thermally conductive sheet away from the electronic chip via a thermal interface material layer.

[0041] In the aforementioned formation method of this application, since the wiring layer in the at least one electronic chip assembly structure is bonded to the first rewiring layer of the photonic chip interposer structure, that is, the electronic chip in the electronic chip assembly structure is located outside the molding compound (above the photonic chip), most of the photonic chip is encapsulated in the molding compound, and the molding compound exposes the optical port of the photonic chip. Furthermore, since a diamond thermal conductive sheet is bonded to the first back side (the surface away from the photonic chip) of the electronic chip, the diamond thermal conductive sheet has a very high thermal conductivity (greater than or equal to 800 kJ / m²). With a heat dissipation capacity of W / (m·K), the diamond heat sink can effectively and rapidly dissipate the heat generated by the electronic chip, thereby quickly reducing the junction temperature of the electronic chip and improving the efficiency of heat dissipation. Simultaneously, the heat dissipated by the diamond heat sink is transferred to the heat sink through the thermal interface material layer, preventing the heat generated by the electronic chip from being conducted to the photonic chip itself within the photonic chip's interposer structure. This protects the photonic chip from the effects of temperature changes and high temperatures, improving its performance and reliability (e.g., preventing wavelength drift) and reducing power consumption (e.g., eliminating the need to increase the photonic chip's drive current). Furthermore, since the diamond heat sink is bonded to the first back side of the electronic chip, it reduces gaps and holes at the contact surface between the diamond heat sink and the first back side of the electronic chip, thereby reducing interfacial thermal resistance and improving heat transfer efficiency.

[0042] Furthermore, the protective layer is located on a portion of the second active surface and covers the optical port. During the encapsulation process, the protective layer can prevent dust particles, metal debris, or chemical solvents from entering the optical port, avoiding contamination of the optical port, ensuring the integrity of the optical port, and thus reducing the light scattering loss of the optical port. In addition, the protective layer can also absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and welding) in the subsequent encapsulation process, thereby preventing the optical port from developing microcracks or breaking and avoiding damage to the optical port. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0044] Figure 1 This is a schematic diagram of the process for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the electronic chip assembly structure provided in the method for forming the optoelectronic co-packaging structure in some embodiments of this application; Figure 3 This document provides a schematic diagram of the first wafer and the structure after forming the circuit layer in a method for forming an optoelectronic co-packaging structure provided in some embodiments of this application. Figure 4 This is a schematic diagram of the structure after the first bonding layer is formed in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure after bonding the first carrier plate in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure after the formation of the first metal bonding layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the structure after cutting along the first cutting zone in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 8 This is a schematic diagram of the structure after bonding a diamond thermal conductive sheet in the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 9This is a schematic diagram of the structure after removing the first carrier plate in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 10 This is a schematic diagram of the photonic chip intermediary layer structure provided in the method for forming the optoelectronic co-packaging structure in some embodiments of this application; Figure 11 This is a schematic diagram of the photonic chip structure provided in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 12 This is a schematic diagram of the second wafer and the structure after forming the groove in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 13 This is a schematic diagram of the structure after forming a protective layer and metal bumps in the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 14 This is a schematic diagram of the structure after cutting along the second cutting zone in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 15 This is a schematic diagram of the structure after providing a second carrier board and forming a second redistribution layer and metal pillars in the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 16 This is a schematic diagram of the structure after the photonic chip is mounted in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 17 This is a schematic diagram of the structure after forming the molding layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 18 This is a schematic diagram of the structure after temporary bonding of a third carrier plate in the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application; Figure 19 This is a schematic diagram of the structure after forming the welding protrusion in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 20 This is a schematic diagram of the structure after temporary bonding of the fourth carrier plate in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 21 This is a schematic diagram of the structure after forming the first redistribution layer and the second bonding layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 22 This is a schematic diagram of the structure after bonding the wiring layer of at least one electronic chip component structure to the first wiring layer of the photonic chip intermediary layer structure in the method of forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 23This is a schematic diagram of the structure after the offset cutting process in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 24 This is a schematic diagram of the structure after removing the fourth carrier plate in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 25 This is a schematic diagram of the structure after removing the protective layer in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 26 This is a schematic diagram of the structure after the optical coupling component is installed in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application; Figure 27 This is a schematic diagram of the structure after the heat sink is attached in the method for forming the optoelectronic co-packaging structure provided in some embodiments of this application.

[0045] Explanation of reference numerals in the attached figures: Photonic chip 100; second wafer 101a; substrate 101; passivation layer 102; metal bump 103; optical port 104; groove 105; protective layer 106; molding layer 107; metal pillar 108; first redistribution layer 109; first dielectric layer 110; first metal wiring layer 111; second bonding dielectric layer 112; second bonding metal layer 113; second redistribution layer 114; second dielectric layer 115; second metal wiring layer 116; solder bump 117; adhesive layer 118; optical coupling assembly 119; optical coupling adhesive 120; Electronic chip 200; first wafer 200a; circuit layer 201; dielectric layer 202; metal circuit layer 201a; first bonding dielectric layer 203; first bonding metal layer 204; diamond thermal conductive sheet 205; bonding metal layer 206; thermal interface material layer 207; heat sink 208; First carrier 301; first temporary bonding layer 301a; second carrier 302; third carrier 303; fourth carrier 304; fourth temporary bonding layer 304a; Second active surface 11; Second back surface 12; Photonic chip region 13; Second dicing region 14; Offset process 15; First active surface 21; First back surface 22; Electronic chip region 23; First dicing region 24; Electronic chip assembly structure 31; Photonic chip interposer structure 32. Detailed Implementation

[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects, and is not necessarily used to describe a specific order or sequence.

[0049] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0050] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with the other component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or electrical coupling, or they can be in electrical contact or electrical coupling through an intermediate component.

[0051] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0052] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0053] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0054] It is understood that in some of the accompanying drawings of this application, adjacent films with the same processing material are drawn as connected to make them resemble the actual structure.

[0055] The existing optoelectronic co-packaging structure is made using fan-out wafer-level packaging technology. The electronic chip is buried in the molding compound, and the photonic chip is located on the surface of the molding compound above the electronic chip. The photonic chip is electrically connected to the electronic chip through corresponding wiring layers. Electronic chips operate at high power and generate significant heat. Because they are embedded in a plastic encapsulation layer and lack heat dissipation channels, the heat generated by the electronic chips cannot be dissipated effectively and promptly. This heat is conducted to photonic chips through the plastic encapsulation layer. Photonic chips (such as silicon-based or InP-based photonic chips) are highly sensitive to heat. Their performance, power consumption, and reliability are significantly affected by temperature changes. For example, the resonant wavelength of the ring modulator (such as a micro-ring resonator) in a silicon-based photonic chip will drift with temperature (at a rate greater than 0.1 nm / ℃), leading to signal detuning and increased bit error rate, which affects the performance and reliability of the photonic chip. Similarly, the output power and wavelength of InP photonic chips also change with temperature. At higher temperatures (such as 80℃), a higher drive current is required to maintain the predetermined power (such as 20mW) output, increasing the power consumption of the photonic chip.

[0056] Therefore, embodiments of this application provide an optoelectronic co-packaging structure and a method for forming the same. Figure 1 This is a flowchart illustrating the method for forming an optoelectronic co-packaging structure provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the optoelectronic co-packaging structure includes the following steps: Step S101: Provide at least one electronic chip component structure, each of the electronic chip component structures comprising: an electronic chip, the electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; and a diamond thermal conductive sheet, the diamond thermal conductive sheet being bonded to the first back surface of the electronic chip; Step S102: Provide a photonic chip interposer structure, the photonic chip interposer structure comprising: a photonic chip, the photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a protective layer located on a portion of the second active surface and covering the optical port; a molding compound layer covering the photonic chip, the molding compound layer including a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps and the protective layer on the surface away from the second active surface; and a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bumps and exposing the protective layer; Step S103: Bond the wiring layer in the at least one electronic chip component structure to the first wiring layer of the photonic chip interposer structure. Step S104: Provide a heat sink and attach the heat sink to the surface of the diamond thermal conductive sheet away from the electronic chip through a thermal interface material layer.

[0057] The method for forming the optoelectronic co-packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0058] First, refer to Figure 1 In conjunction with references Figure 2 In step S101, at least one electronic chip assembly structure 31 is provided. Each electronic chip assembly structure 31 includes: an electronic chip 200, the electronic chip 200 including a first active surface 21 and a first back surface 22 disposed opposite to each other, the first active surface 21 having a circuit layer 201; and a diamond thermal conductive sheet 205, the diamond thermal conductive sheet 205 being bonded to the first back surface 22 of the electronic chip 200.

[0059] The electronic chip assembly structure 31 is part of an optoelectronic co-package structure. The main structure of the electronic chip assembly structure 31 is an electronic integrated circuit (EIC) 200. In some embodiments, the electronic chip 200 serves as an optical engine for electro-optic modulation driving, photoelectric signal transimpedance amplification, signal equalization, and clock recovery. In other embodiments, in addition to electro-optic modulation driving, photoelectric signal transimpedance amplification, signal equalization, and clock recovery, the electronic chip 200 can also be used for data exchange, packet forwarding, routing scheduling, protocol processing, and outputting high-speed low-voltage electrical signals (serial signals, parallel signals, or SerDes electrical signals).

[0060] In one specific example, the electronic chip 200 may include an electronic driver chip and / or a transimpedance amplifier chip (TIA). The electronic driver chip receives high-speed, low-voltage electrical signals, amplifies the amplitude, shapes the waveform, and outputs a driving signal (driving voltage or driving current) to drive the optical modulator and laser in the subsequently provided photonic chip. The transimpedance amplifier chip (TIA) amplifies the weak photocurrent output by the detector in the photonic chip, performs signal equalization and clock recovery, achieving seamless matching and low-noise switching between high-speed electrical and optical signals. It also manages local power supply and impedance matching, reducing optoelectronic interconnect losses and delays. In another specific example, the electronic chip 200 may also include a switching chip or a main power chip. The switching chip or main power chip is used for data switching, packet forwarding, routing scheduling, and protocol processing. It outputs high-speed, low-voltage electrical signals to the electronic driver chip and receives the amplified electrical signals from the transimpedance amplifier chip (TIA) for data decoding, shaping, and switching scheduling.

[0061] In some embodiments, the provided electronic chip component structure 31 may be one or more, and each electronic chip component structure 31 may contain one electronic chip 200. In some embodiments, when there are multiple provided electronic chip component structures 31, the electronic chips 200 in different electronic chip component structures 31 may have different or the same functions. In other embodiments, when there are multiple provided electronic chip component structures 31, some of the electronic chips 200 in a number of electronic chip component structures 31 may have the same function, while some of the electronic chips 200 in a number of electronic chip component structures 31 may have different functions.

[0062] In one specific example, the number of provided electronic chip component structures 31 is two, and the electronic chips 200 in the two electronic chip component structures 31 have different functions. The electronic chip 200 in one electronic chip component structure 31 is an electronic driver chip, and the electronic chip 200 in the other electronic chip component structure 31 is a transimpedance amplifier chip (TIA).

[0063] The electronic chip 200 includes a first active surface 21 and a first back surface 22 disposed opposite to each other, and the first active surface 21 has a circuit layer 201. In some embodiments, the first active surface 21 may also have a plurality of electronic devices (not shown in the figure), and the circuit layer 201 is electrically connected to the plurality of electronic devices to form an integrated circuit with a specific function, which is the function of the electronic chip 200 described above.

[0064] In some embodiments, the electronic device includes one or more of diodes, transistors, resistors, capacitors, and inductors. The circuit layer 201 may include a dielectric layer 202 and a metal circuit layer 201a located within the dielectric layer 202. The dielectric layer 202 may be a single layer or multiple layers, and correspondingly, the metal circuit layer 201a may also be a single layer or multiple layers. In a specific embodiment, when the dielectric layer 202 has multiple layers and the corresponding metal circuit layer 201a has multiple layers, each dielectric layer 202 has one layer of the metal circuit layer 201a, and there is an electrical connection between adjacent metal circuit layers 201a. In some examples, the dielectric layer 202 is made of an inorganic material, specifically including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide). The metal circuit layer 201a is made of a conductive metal material, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0065] The first back surface 22 of the electronic chip 200 is bonded with a diamond thermal conductive sheet 205. After the circuit layer 201 in the at least one electronic chip component structure 31 is subsequently bonded to the first redistribution layer 109 of the photonic chip interposer structure 32 (see reference) Figure 22 and Figure 27Because the diamond heatsink 205 has a very high thermal conductivity (greater than or equal to 800 W / (m·K)), it can greatly and rapidly dissipate the heat generated by the electronic chip 200, thereby quickly reducing the junction temperature of the electronic chip 200 and improving the efficiency of heat dissipation. Simultaneously, the heat dissipated by the diamond heatsink 205 is transferred to the heat sink 208 through the thermal interface material layer 207 (see reference). Figure 27 The heat generated by the electronic chip 200 is released through the photonic chip interposer structure 32, thus preventing the heat generated by the electronic chip 200 from being conducted to the photonic chip 100 within the photonic chip interposer structure 32. This protects the photonic chip 100 from temperature changes and high temperatures, thereby improving the performance and reliability of the photonic chip 100 (e.g., preventing the resonant wavelength of the photonic chip 100 from drifting) and reducing the power consumption of the photonic chip (e.g., eliminating the need to increase the driving current of the photonic chip 100). Furthermore, since the diamond heat-conducting sheet 205 is bonded to the first back surface 22 of the electronic chip 200, gaps and holes at the contact surface or bonding interface between the diamond heat-conducting sheet 205 and the first back surface 22 of the electronic chip 200 are reduced, thereby reducing interface thermal resistance and improving heat transfer efficiency.

[0066] In some embodiments, the thickness of the diamond heat-conducting sheet 205 is 0.1mm-0.5mm, and specifically, the thickness can be 0.1mm, 0.2mm, 0.3mm, 0.4mm, or 0.5mm. The material of the diamond heat-conducting sheet 205 is single-crystal diamond or polycrystalline diamond, wherein the thermal conductivity of the single-crystal diamond ranges from 1800 W / (m·K) to 2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond ranges from 800 W / (m·K) to 1500 W / (m·K).

[0067] In some embodiments, the diamond thermal conductive sheet 205 is bonded to the first back surface 22 of the electronic chip 200 via a bonding metal layer 206. Using a bonding metal layer 206 for bonding further reduces the gaps and holes at the contact surface between the diamond thermal conductive sheet 205 and the first back surface 22 of the electronic chip 200, thereby further reducing the interfacial thermal resistance and further improving the efficiency of heat transfer. In one specific embodiment, the thickness of the bonding metal layer 206 is less than or equal to 100 nm; the material of the bonding metal layer 206 is one or more of Ti, Cu, W, and Au. The bonding metal layer 206 is relatively thin and uses a metal with high thermal conductivity that can covalently bond with diamond, greatly reducing or eliminating gaps or holes at the bonding interface between the diamond heat-conducting sheet 205 and the first back surface 22 of the electronic chip 200, resulting in extremely low interfacial thermal resistance (less than 0.08 cm⁻¹) between the diamond heat-conducting sheet 205 and the first back surface 22 of the electronic chip 200. 2(·K / W), further improving the heat dissipation efficiency of the electronic chip 200.

[0068] In some embodiments, continue to refer to Figure 2 The surface of the circuit layer 201 in the electronic chip assembly structure 31, away from the first active surface 21, also has a first bonding layer (203 and 204). The first bonding layer is used for subsequent bonding with a second bonding layer (112 and 113) on the surface of the first redistribution layer 109 in the photonic chip interposer structure 32, away from the photonic chip 100 (see reference). Figure 22 Mixed bonding is performed.

[0069] In some embodiments, the first bonding layer includes a first bonding dielectric layer 203 and a first bonding metal layer 204 located in the first bonding dielectric layer 203, wherein the first bonding metal layer 204 is electrically connected to the metal circuit layer 201a. The material of the first bonding dielectric layer 203 is an inorganic material, specifically including silicon oxide or silicon oxycarbide (SiCN), and the material of the first bonding metal layer 204 is a conductive metallic material, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0070] In a specific example, the material of the first bonding dielectric layer 203 is silicon carbonitride (SiCN), and the material of the first bonding metal layer 204 is Cu. Since the coefficient of thermal expansion of the first bonding metal layer 204 is greater than that of the first bonding dielectric layer 203, in order to improve the bonding strength during subsequent hybrid bonding, in some embodiments, the surface of the first bonding metal layer 204 has a dish-shaped recess with a depth of 2nm-5nm.

[0071] It should be noted that when there are multiple electronic chip assembly structures 31, the first back surface 22 of the electronic chip 200 in each electronic chip assembly structure 31 is bonded with a diamond heat-conducting sheet 205.

[0072] The following embodiments, in conjunction with the appendix Figure 3 -Appendix Figure 9 right Figure 2 The formation process of the electronic chip component structure 31 shown is described in detail.

[0073] In some embodiments, the formation process of the electronic chip assembly structure 31 includes: refer to Figure 3A first wafer 200a is provided, the first wafer 200a including a plurality of electronic chip regions 23 and a first dicing region 24 located between the electronic chip regions 23. The plurality of electronic chip regions 23 may be arranged in an array. The electronic chip regions 23 are used to form electronic chips. The first dicing region 24 is used for subsequent dicing. In one example, the material of the first wafer 200a is silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds.

[0074] Continue to refer to Figure 3 A plurality of electronic devices are formed in the electronic chip area 23 on the front side of the first wafer 200a; a circuit layer 201 is formed on the front side of the first wafer 200a, and the circuit layer 201 is electrically connected to the plurality of electronic devices.

[0075] In some embodiments, the electronic device includes one or more of diodes, transistors, resistors, capacitors, and inductors. The circuit layer 201 may include a dielectric layer 202 and a metal circuit layer 201a located within the dielectric layer 202. The dielectric layer 202 may be a single layer or multiple layers, and correspondingly, the metal circuit layer 201a may also be a single layer or multiple layers. In a specific embodiment, when the dielectric layer 202 has multiple layers and the corresponding metal circuit layer 201a has multiple layers, each dielectric layer 202 has one layer of the metal circuit layer 201a, and there is an electrical connection between adjacent metal circuit layers 201a.

[0076] refer to Figure 4 A first bonding layer is formed on the circuit layer 201. The first bonding layer includes a first bonding dielectric layer 203 and a first bonding metal layer 204 located in the first bonding dielectric layer 203.

[0077] refer to Figure 5 A first carrier plate 301 is bonded to the surface of the first bonding layer away from the first wafer 200a. The first carrier plate 301 is used to support the first wafer 200a and protect the first bonding layer and the circuit layer 201 in subsequent processes.

[0078] In some embodiments, the material of the first carrier plate 301 includes glass or silicon.

[0079] In some embodiments, the first carrier 301 is bonded to the surface of the first bonding layer away from the first wafer 200a via a first temporary bonding layer 301a. The material of the first temporary bonding layer 301a can be a heat-sensitive adhesive or a photosensitive adhesive. When the first carrier 301 needs to be removed later, the first temporary bonding layer 301a can be removed by heating the first temporary bonding layer 301a (heat-sensitive adhesive) or by irradiating the first temporary bonding layer 301a (photosensitive adhesive) with light to debond it.

[0080] refer to Figure 6 A metal bonding layer 206 is formed on the back side of the first wafer 200a.

[0081] In some embodiments, the thickness of the bonding metal layer 206 is less than or equal to 100 nm; the material of the bonding metal layer 206 is one or more of Ti, Cu, W, and Au, and the process for forming the bonding metal layer 206 includes sputtering.

[0082] In some embodiments, before forming the metal bonding layer 206, the back side of the first wafer 200a is thinned.

[0083] refer to Figure 7 The metal bonding layer 206, the circuit layer 201 and the first wafer 200a are cut along the first cutting area 24 to form a plurality of electronic chips 200. refer to Figure 8 After the cutting is performed, a diamond thermal conductive sheet 205 is bonded to the surface of the metal bonding layer 206 of each electronic chip region 23 away from the first wafer 200a.

[0084] A diamond thermal conductive sheet 205 is bonded to the surface of the metal bonding layer 206 in each electronic chip region 23 away from the first wafer 200a, using a low-temperature metal atom diffusion bonding process. The temperature range of the low-temperature metal atom diffusion bonding process is 150℃--250℃, and the time range is 1-3h. Furthermore, the temperature control in the low-temperature metal atom diffusion bonding process employs a stepped heating and natural cooling method. For example, the temperature is initially raised to a first temperature (range: 140℃-160℃, specifically 140℃, 150℃, or 160℃) within a first time period (range: 20 min - 40 min, specifically 20 min, 30 min, or 40 min), and held at this temperature for a second time period (range: 20 min - 40 min, specifically 20 min, 30 min, or 40 min). Then, the temperature is raised to a second temperature, which is higher than the first temperature (range: 190℃-210℃, specifically 190℃, 200℃, or 210℃), and held at this temperature for a third time period (range: 20 min - 40 min, specifically 20 min, 30 min, or 40 min). (Or 40 min); then raise the temperature to a third temperature, which is higher than the second temperature (the second temperature range is 240℃-260℃, specifically 240℃, 250℃, or 260℃), and maintain the third temperature for a fourth time (the fourth time range is 0.9h-1.1h, specifically 0.9h, 1h, or 1.1h); then allow it to cool naturally to room temperature, ending the bonding process. Through the aforementioned low-temperature metal atom diffusion bonding process, covalent bonds are formed between the diamond heat-conducting sheet 205 and the metal bonding layer 206. The bonding interface between the two forms a transition layer containing C elements and metal elements from the metal bonding layer (such as a WC transition layer, CuC transition layer, or TiC transition layer), eliminating gaps or pores at the bonding interface and reducing interfacial thermal resistance.

[0085] refer to Figure 9 After bonding the diamond heat-conducting sheet 205, the first carrier plate 301 is removed to form a plurality of discrete electronic chip component structures 31.

[0086] The aforementioned steps improve the batch production efficiency of the electronic chip assembly structure 31 with bonded diamond heat-conducting sheets 205. Furthermore, since diamond, the material of the diamond heat-conducting sheet 205, is a naturally occurring superhard material, its cutting and grinding techniques are challenging. Currently, the only way to produce the diamond heat-conducting sheet 205 is to first laser-cut the diamond material and then grind the edges. Therefore, in the aforementioned steps, the metal bonding layer 206, the circuit layer 201, and the first wafer 200a are first cut along the first cutting area 24 to form several electronic chips 200. Then, a diamond heat-conducting sheet 205 is bonded to the surface of the metal bonding layer 206 in each electronic chip area 23, away from the first wafer 200a, to reduce the difficulty of the process.

[0087] Next, continue to refer to Figure 1 In conjunction with references Figure 10 In step S102, a photonic chip interposer structure 32 is provided, comprising: a photonic chip 100, the photonic chip 100 including a second active surface 11 and a second back surface 12 disposed opposite to each other, the second active surface 11 having a plurality of raised metal bumps 103, and an optical port 104 in the second active surface 11 on one side of the plurality of metal bumps 103; a protective layer 106 located on a portion of the second active surface 11 and covering the optical port 104; a molding compound 107 covering the photonic chip 100, the molding compound 107 including a first surface and a second surface disposed opposite to each other, the first surface exposing the surface of the metal bumps 103 and the protective layer 106 away from the second active surface 11; and a first redistribution layer 109 located on a portion of the first surface, the first redistribution layer 109 being electrically connected to the metal bumps 103 and exposing the protective layer 106.

[0088] The photonic chip interposer structure 32 serves as the subsequent optoelectronic co-packaging structure. The main structure within the photonic chip interposer structure 32 is the photonic chip 100.

[0089] In some embodiments, the photonic chip 100 is mainly used in the optoelectronic co-package structure for electro-optical conversion (emission): converting the high-speed electrical signal sent by the electronic chip 200 into an optical signal (modulation) and transmitting it to the optical fiber outside the optoelectronic co-package structure; and for optoelectronic conversion (reception): converting the optical signal transmitted in the optical fiber outside the optoelectronic co-package structure into an electrical signal (detection) and transmitting it to the optoelectronic co-package structure. In other embodiments, the photonic chip 100 is also used for optical domain processing, such as waveguide routing, multiplexing / demultiplexing, optical coupling / beam splitting, and optical switching.

[0090] The photonic chip 100 includes a second active surface 11 and a second back surface 12 disposed opposite to each other, and the second active surface 11 has a plurality of raised metal bumps 103. In some embodiments, the second active surface may have a photonic device (not shown) and an optical port 104.

[0091] The metal bump 103 is used for the photonic chip 100 and the electronic chip 200 (see reference). Figure 27 Electrical signals are transmitted between them. The number of the metal bumps 103 is multiple.

[0092] In some embodiments, the photonic devices include optical waveguides (for confining and transmitting optical signals), high-speed modulators (for loading electrical signals onto light), photodetectors (PDs) (for converting optical signals into electrical signals), and passive devices (including optical beam splitters, combiners, isolators, and polarization controllers). The metal bumps 103 are electrically connected to some of the photonic devices. Through the metal bumps 103, electrical signals output from the electronic chip 200 can be transmitted to the corresponding photonic devices, or electrical signals generated by the corresponding photonic devices can be transmitted to the electronic chip 200.

[0093] The optical port 104, also known as the optical coupling port, serves as the optical interface between the photonic chip 100 and external optical coupling components (such as fiber optic connectors). It solves the mode matching problem between the "in-chip waveguide" and the "external optical interface," reducing coupling loss. Specifically, in some embodiments, the optical port 104 is used to couple optical signals from the external optical fiber into the photonic chip 100, and also to couple optical signals from the photonic chip 100 out to the external optical fiber. The optical port 104 is also used for matching the fiber mode field of the external optical fiber with the waveguide mode field of the waveguide in the photonic chip 100, reducing optical coupling loss, and for directional transmission, optical path alignment, and fixation of the optical path between the waveguide in the photonic chip 100 and the external optical fiber.

[0094] In some embodiments, the number of optical ports 104 may be one or more. The optical ports 104 are located at the edge of the photonic chip 100. The optical ports 104 include edge couplers (EG).

[0095] In some embodiments, the photonic chip 100 includes a substrate 101 and a passivation layer 102 located on the front side of the substrate 101. The substrate 101 is made of Si or InP, and the passivation layer 102 is made of one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The photonic device (not shown) and the optical port 104 are formed on the front side of the substrate 101. The passivation layer 102 covers the photonic device, exposing the optical port 104.

[0096] The protective layer 106 is located on a portion of the second active surface 11 and covers the optical port 104. The protective layer 106 is subsequently subjected to a cutting process 15 (see reference 23-). Figure 25 After removal, the protective layer 106 can prevent dust particles, metal debris or chemical solvents from entering the optical port 104 during subsequent packaging processes, avoid contamination of the optical port 104, ensure the integrity of the optical port 104, and thus reduce the light scattering loss of the optical port 104; and the protective layer 105 can also absorb the mechanical stress (such as the pressure and / or thermal stress generated during grinding, cleaning, and welding) during subsequent packaging processes, thereby preventing the optical port 104 from developing microcracks or breaking, and avoiding damage to the optical port 104.

[0097] In some embodiments, the material of the protective layer 106 includes photoresist; forming the protective layer 106 includes a spin coating process, an exposure process, and a development process. This makes the formation process of the protective layer 106 simple, the formation location accurate, and the removal process simple.

[0098] In some embodiments, the photonic chip 100 further has a groove 105 that penetrates a portion of the second active surface 11, and the sidewall of the groove 105 exposes the optical port 104; The protective layer 106 fills the groove 105 and covers the optical port 104, and the surface of the protective layer 106 is higher than the surface of the second active surface 11.

[0099] The molding compound 107 encapsulates the photonic chip 100. The molding compound 107 includes a first surface and a second surface disposed opposite to each other. The first surface exposes the surfaces of the metal bumps 103 and the protective layer 106 that are away from the second active surface 11. In one example, the first surface may be flush with the surfaces of the metal bumps 103 and the protective layer 106 that are away from the second active surface 11.

[0100] In some embodiments, the material of the molding layer 107 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, with or without fillers; or it may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol, with fillers. The filler may be inorganic or organic.

[0101] The first rewiring layer 109 is located on a portion of the first surface of the molding layer 107, and the first rewiring layer 109 is electrically connected to the metal bump 103 and exposes the protective layer 106.

[0102] In some embodiments, the first redistribution layer 109 includes a first dielectric layer 110 and a first metal wiring layer 111 located within the first dielectric layer 110. The first dielectric layer 110 may be a single-layer or multi-layer structure, and correspondingly, the first metal wiring layer 111 may be a single-layer or multi-layer structure. The material of the first dielectric layer is an organic material, specifically a photosensitive epoxy resin, a photosensitive polyimide resin (PI), a photosensitive benzocyclobutene resin (BCB), or a photosensitive polybenzoxazole resin (PBO). The material of the first metal wiring layer 111 is a conductive metal material, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0103] In some embodiments, the surface of the first redistribution layer 109 in the photonic chip interposer structure 32, away from the photonic chip 100, further includes a second bonding layer (112 and 113). This second bonding layer is used to subsequently bond with the first bonding layer (203 and 204) on the surface of the circuit layer 201 in the electronic chip assembly structure 31, away from the first active surface 21 (see reference). Figure 22 Mixed bonding is performed.

[0104] In some embodiments, the second bonding layer includes a second bonding dielectric layer 112 and a second bonding metal layer 113 located in the second bonding dielectric layer 112, wherein the second bonding metal layer 113 is electrically connected to the first metal wiring layer 111. In one example, the material of the second bonding dielectric layer 112 is an organic material, specifically including photosensitive polyimide resin (PI) or photosensitive benzocyclobutene resin (BCB), and the material of the second bonding metal layer 113 is a conductive metal material, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0105] Since the coefficient of thermal expansion of the second bonding dielectric layer 112 of the organic material is greater than that of the second bonding metal layer 113, in order to improve the bonding strength during subsequent hybrid bonding, in some embodiments, the surface of the second bonding metal layer 113 away from the first redistribution layer 109 is higher than the surface of the second bonding dielectric layer 112 away from the first redistribution layer 109.

[0106] In some embodiments, continue to refer to Figure 10 The photonic chip interposer structure 32 further includes: A plurality of metal pillars 108 are located in the molding layer 107, and the first and second surfaces of the molding layer 107 expose the two end surfaces of the metal pillars 108 respectively. One end surface of the metal pillars 108 is electrically connected to the first redistribution layer 109. The second wiring layer 114 is located on the second surface of the molding layer 107 and the second back surface 12 of the photonic chip 100. The second wiring layer 114 is electrically connected to the other end surface of the metal pillar 108. A solder bump 117 is located on the surface of the second redistribution layer 114 away from the photonic chip 100, and the solder bump 117 is electrically connected to the second redistribution layer 114.

[0107] In some embodiments, the second redistribution layer 114 includes a second dielectric layer 115 and a second metal wiring layer 116 located in the second dielectric layer 115; The material of the second dielectric layer 115 includes organic materials, specifically photosensitive epoxy resin, photosensitive polyimide resin (PI), photosensitive benzocyclobutene resin (BCB), or photosensitive polybenzoxazole resin (PBO). The material of the second metal wiring layer 116 includes conductive metal materials, specifically including one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0108] The metal pillars 108 are used for transmitting electrical signals between the first redistribution layer 109 and the second metal wiring layer 116. In some embodiments, there may be multiple metal pillars 108, and the material of the metal pillars 108 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0109] In some embodiments, the weld protrusion 117 comprises a solder ball or a metal protrusion and a solder ball located on the top surface of the metal protrusion. In one example, the metal protrusion is made of one or more of copper, aluminum, nickel, tin, tungsten, platinum, titanium, chromium, tantalum, gold, silver, titanium nitride, tantalum nitride, and tungsten nitride, and the solder ball is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0110] The following embodiments, in conjunction with the appendix Figure 11 Appendix Figure 15 -Appendix Figure 21 right Figure 10The formation process of the photonic chip interposer structure 32 shown is described in detail.

[0111] In some embodiments, the formation process of the photonic chip interposer structure 32 includes: refer to Figure 11 A photonic chip 100 is provided, the photonic chip 100 includes a second active surface 11 and a second back surface 12 disposed opposite to each other, the second active surface 11 has a plurality of raised metal bumps 103, and an optical port 104 is provided in the second active surface 11 on one side of the plurality of metal bumps 103; a protective layer 106 is located on a portion of the second active surface 11 and covers the optical port 104.

[0112] refer to Figure 15 A second carrier board 302 is provided; a second redistribution layer 114 is formed on the surface of the second carrier board 302; and a plurality of metal pillars 108 are formed on the surface of the second redistribution layer 114 away from the second carrier board 302.

[0113] The material of the second carrier plate 302 includes glass or silicon.

[0114] In some embodiments, the second redistribution layer 114 includes a second dielectric layer 115 and a second metal wiring layer 116 located within the second dielectric layer 115; the material of the second dielectric layer 115 includes a photosensitive organic material, and the material of the second metal wiring layer 116 includes a conductive metal material. The second dielectric layer 115 can be a single layer or multiple layers, and correspondingly, the second metal wiring layer 116 can also be a single layer or multiple layers.

[0115] Taking the formation of a second dielectric layer 115 and a second metal wiring layer 116 as an example, the formation process of the second dielectric layer 115 and the second metal wiring layer 116 includes: forming a second dielectric layer 115 on the surface of the second carrier 302 using a spin coating process; exposing and developing the second dielectric layer 115 to form a plurality of openings in the second dielectric layer 115 that expose a portion of the surface of the second carrier; and forming the second metal wiring layer 116 in the openings and on a portion of the surface of the second dielectric layer 115 outside the openings.

[0116] In some embodiments, the metal pillar 108 may be formed by an electroplating process.

[0117] refer to Figure 16 The second back surface 12 of the photonic chip 100 is attached to the surface of the second redistribution layer 114 that is away from the second carrier 302.

[0118] In some embodiments, the second back surface 12 of the photonic chip 100 is attached to the surface of the second redistribution layer 114 away from the second carrier 302 via an adhesive layer 118. After the photonic chip is attached, the surface of the metal bump 103 on the photonic chip 100 away from the second redistribution layer 114 is flush with the surface of the metal pillar 108 away from the second redistribution layer 114.

[0119] refer to Figure 17 A molding layer 107 is formed on the surface of the second redistribution layer 114 away from the second carrier 302, covering the photonic chip 100 and the metal pillar 108. The first surface of the molding layer 107 exposes the surface of the metal pillar 108 and the second active surface 11 of the protective layer 106 away from the photonic chip 100, and exposes the surface of the metal bump 103 away from the second redistribution layer 114.

[0120] The molding compound 107 is formed using an injection molding process. During injection molding, a specific fixture is required, meaning that the injection process must avoid the optical port 104 and the protective layer 106 (the top surface of the protective layer 106 will not form molding compound material during the injection molding process). After the injection molding process, a thinning process can be used to thin the molding compound away from the second redistribution layer 114, so that the remaining first surface of the molding compound 107 exposes the surfaces of the metal pillars 108 and the protective layer 106 away from the second active surface 11 of the photonic chip 100, as well as the surface of the metal bumps 103 away from the second redistribution layer 114.

[0121] refer to Figure 18 The third carrier 303 is temporarily bonded to the first surface of the molding layer 107 (or the surface away from the second redistribution layer 114).

[0122] refer to Figure 19 Remove the second carrier board to expose the back side of the second redistribution layer 114 away from the photonic chip 100, and form a solder bump 117 on the surface of the second redistribution layer 114 away from the photonic chip 100.

[0123] refer to Figure 20 A fourth carrier plate 304 is temporarily bonded to one side surface of the second redistribution layer 114 where the solder protrusion 117 is formed. In one example, the fourth carrier plate 304 is bonded to the side surface of the second redistribution layer 114 where the solder protrusion 117 is formed via a fourth temporary bonding layer 304a.

[0124] refer to Figure 21Remove the third carrier board to expose the first surface of the molding layer 107. Form a first redistribution layer 109 on a portion of the first surface of the molding layer 107. The first redistribution layer 109 is electrically connected to the metal bump 103 and exposes the protective layer 106. Form a second bonding layer (112 and 113) on the surface of the first redistribution layer 109 away from the molding layer 107.

[0125] The aforementioned steps improve the fabrication efficiency of the photonic chip interposer structure 32, and the optical port 104 will not be damaged during the fabrication process due to the protection of the protective layer 106.

[0126] The following embodiments, in conjunction with the appendix Figure 12 -Appendix Figure 14 right Figure 11 The formation process of the photonic chip 100 shown is described in detail.

[0127] In some embodiments, the formation process of the photonic chip 100 includes: refer to Figure 12 A second wafer 101a is provided, the second wafer 101a including a plurality of photonic chip regions 13 and a second dicing region 14 located between the photonic chip regions 13. The plurality of photonic chip regions 13 may be arranged in an array. The photonic chip regions 13 are used to form photonic chips. The second dicing region 14 is used for subsequent dicing. In one example, the material of the second wafer 101a includes Si or InP. Continue to refer to Figure 12 A photonic device (not shown) and an optical port 104 are formed in the photonic chip region 13 on the front side of the second wafer 101a; a passivation layer 102 is formed covering the photonic device, and the passivation layer 102 exposes the optical port 104.

[0128] In some embodiments, the photonic device includes an optical waveguide (for confining and conducting optical signals), a high-speed modulator (for loading electrical signals onto light), a photodetector (PD) (for converting optical signals into electrical signals), and passive devices (including optical beam splitters, combiners, isolators, and polarization controllers). The photolithography includes an edge coupler (EG). Continue to refer to Figure 12 A groove 105 is formed in a second wafer 101a on one side of the optical port 104, and the sidewall of the groove 105 exposes the optical port 104. In one example, the groove 105 is located in the photonic chip region 13 and is close to the edge of the photonic chip region 13.

[0129] In some embodiments, the process of forming the groove 105 includes an etching process.

[0130] refer to Figure 13 A protective layer 106 is formed in the groove 105 and on the surface of part of the photonic chip region 13 to cover the optical port 105.

[0131] In some embodiments, the material of the protective layer 106 includes photoresist; forming the protective layer 106 includes a spin coating process, an exposure process, and a development process. Specifically, a photoresist layer is formed in the groove 105 and on the surface of the passivation layer 102 using a spin coating process, and the photoresist layer is cured; the photoresist layer is exposed, baked after exposure, and developed, retaining the photoresist in the groove 105 and covering the aperture 104 as a protective layer, and removing the photoresist in other areas; after development, a hard bake is performed.

[0132] Continue to refer to Figure 13 After the protective layer 106 is formed, a plurality of raised metal bumps 103 are formed on the second active surface 11. In one example, the process of forming the metal bumps 103 includes electroplating.

[0133] refer to Figure 14 After forming several metal bumps 103, the second wafer 101a is cut along the second cutting channel area 14 to form several discrete photonic chips 100.

[0134] The aforementioned steps enable the mass production of photonic chips 100, improving the production efficiency of photonic chips 100, and the optical port 104 will not be damaged during the production process due to the protection of the protective layer.

[0135] Next, continue to refer to Figure 1 In conjunction with references Figure 22 In step S103, the circuit layer 201 in the at least one electronic chip component structure 31 is bonded to the first redistribution layer 109 of the photonic chip interposer structure 32.

[0136] In some embodiments, one or more circuit layers 201 in the electronic chip component structure 31 are bonded to the first redistribution layer 109 of the photonic chip interposer structure 32. In one example, circuit layers 201 in two electronic chip component structures 31 are bonded to the first redistribution layer 109 of the photonic chip interposer structure 32.

[0137] In some embodiments, bonding the circuit layer 201 in the at least one electronic chip assembly structure 31 to the first redistribution layer 109 of the photonic chip interposer structure 32 includes: a first bonding layer (203 and 204) on the circuit layer 201 of the electronic chip assembly structure 31 and a second bonding layer (112 and 113) on the first redistribution layer 109 of the photonic chip interposer structure 32 are mixed-bonded. Specifically, the first bonding dielectric layer 203 in the first bonding layer is bonded to the corresponding second bonding dielectric layer 112 in the second bonding layer, and the first bonding metal layer 204 in the first bonding layer is bonded to the corresponding second bonding metal layer 113 in the second bonding layer. Using mixed bonding can increase the interconnect density and shorten the interconnect distance.

[0138] In some embodiments, prior to hybrid bonding, the surfaces of the first bonding layers (203 and 204) and the second bonding layers (112 and 113) are activated to improve the bonding strength between the first and second bonding layers during and after hybrid bonding. Specifically, for the first bonding layers (203 and 204), the surface is first bombarded with Ar / H2 plasma, followed by chemical wet surface activation with ammonia (NH3-H2O), resulting in the surfaces of the first bonding medium layer 203 (inorganic material) and the first bonding metal layer 204 being rich in hydroxyl dangling bonds (-OH). For the second bonding layers (112 and 113), the surface is first bombarded with Ar / H2 plasma, followed by citric acid catalytic activation, reducing the metal oxides on the surface of the second bonding metal layer 113 and enriching the surface of the second bonding medium layer 112 (organic material) with polymer functional groups (-COOH). In some embodiments, during hybrid bonding, since the first bonding metal layer 204 has a concave structure relative to the bonding surface and the second bonding metal layer 113 has a protruding structure relative to the bonding surface, when the first bonding metal layer 204 and the second bonding metal layer 113 come into contact and align, they form an interlocking structure similar to a "mortise and tenon". During subsequent bonding, the metals at the interface between the first bonding metal layer 204 and the second bonding metal layer 113 slowly diffuse and bond, and the polymer functional groups (-COOH) on the surface of the second bonding medium layer 112 combine with the hydroxyl dangling bonds (-OH) on the surface of the first bonding medium layer 203; the bonding interface material expands according to its coefficient of thermal expansion (CTE), resulting in a closed state of the overall interface with a "mortise and tenon" interlocking structure, achieving high-quality hybrid bonding. In some embodiments, reference... Figure 23 and Figure 24 After bonding the circuit layer 201 in the at least one electronic chip component structure 31 to the first redistribution layer 109 of the photonic chip interposer structure 32, the method further includes: A slitting process 15 is performed to cut and remove part of the protective layer 106 in the groove 105, as well as the molding layer 107 and photonic chip 100 (and the second redistribution layer 114) of the groove 105 away from the outside of the photolithography. The remaining protective layer 106 in the groove 105 still covers the optical port 104.

[0139] Before the offset cutting process 15, since the protective layer 106 is always filled in the groove 105 and covers the optical port, the protective layer 106 and the groove 105 have a large contact area, so that the protective layer 106 is firmly adhered to the surrounding side walls and bottom of the groove 105. During the aforementioned encapsulation process, the protective layer 106 will not fall off, detach or delaminate, thereby better protecting the optical port. After bonding the circuit layer 201 in the at least one electronic chip component structure 31 to the first redistribution layer 109 of the photonic chip interposer structure 32, since most of the packaging process has been completed, a dicing process 15 is performed to cut and remove part of the protective layer 106 in the groove 105, as well as the molding layer 107 of the groove 105 away from the photolithography outer side and the photonic chip 100 (and the second redistribution layer 114), so that one side of the photonic chip 100 exposes the protective layer 106, which facilitates the subsequent removal of the protective layer 106. After removing the protective layer, one side of the photonic chip 100 exposes the optical port, which facilitates the installation of the optical coupling component 119 (reference) corresponding to the photolithography position on one side of the photonic chip 100. Figure 26 ).

[0140] In some embodiments, continue to refer to Figure 24 After the offset cutting process 15, the fourth carrier 304 and the fourth temporary bonding layer 304a are removed. When the fourth carrier 304 is removed, after the offset cutting process 15, part of the protective layer 106 in the groove 105, as well as the molding layer 107 and photonic chip 100 (and the second redistribution layer 114) of the groove 105 away from the outside of the photolithography are cut off and removed together with the fourth carrier.

[0141] In one embodiment, reference Figure 25 After the offset cutting process, the remaining protective layer 106 in the groove 105 is removed (see reference). Figure 24 ), so as to expose the light port 104.

[0142] In one embodiment, the process of removing the remaining protective layer 106 in the groove includes selectively rinsing the protective layer 106 with a protective layer removal solution to remove the protective layer 106. In one example, the removal solution is a photoresist removal solution.

[0143] In one embodiment, reference Figure 26After exposing the optical port 104, the device further includes: mounting an optical coupling component 119 on one side of the photonic chip 100, corresponding to the position of the optical port 104. In one example, the optical coupling component 119 includes an optical fiber coupling component, which is mounted on one side of the photonic chip 100 via optical coupling adhesive 120, with the optical fiber in the optical coupling component 119 facing the optical port 104.

[0144] Next, continue to refer to Figure 1 In conjunction with references Figure 27 In step S104, a heat sink 208 is provided, and the heat sink 208 is attached to the surface of the diamond thermal conductive sheet 205 away from the electronic chip 200 through a thermal interface material layer 207.

[0145] In some embodiments, the material of the thermal interface material layer 207 includes a metal with high thermal conductivity, specifically including nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

[0146] The heat sink 208 is used to release the heat conducted to it by the diamond heat-conducting plate 205. Specifically, the heat conducted to the heat sink 208 by the diamond heat-conducting plate 205 can be released by air cooling or liquid cooling.

[0147] The heat sink 208 is formed of a material with high thermal conductivity. In some embodiments, the material with high thermal conductivity includes metals (e.g., copper, aluminum, gold, nickel, steel, or stainless steel) or carbon-containing materials (e.g., graphite, graphene, or carbon nanotubes). In other embodiments, reference continues to this section. Figure 27 To improve heat dissipation efficiency, the back of the heat sink can be designed with a structure that increases or maximizes contact with the cooling medium (e.g., a corrugated structure or a "wing" structure).

[0148] This application also provides an optoelectronic co-packaging structure, see reference. Figure 27 ,include: A photonic chip interposer structure 32 includes: a photonic chip 100, which includes a second active surface 11 and a second back surface 12 disposed opposite to each other. The second active surface 11 has a plurality of raised metal bumps 103, and an optical port 104 is provided in the second active surface 11 on one side of the plurality of metal bumps 103; a molding compound 107 covering the photonic chip 100, which includes a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps 103 and the optical port 104; and a first redistribution layer 109 located on a portion of the first surface, which is electrically connected to the metal bumps 103 and exposes the optical port 104. At least one electronic chip assembly structure 31, each of the electronic chip assembly structures 31 comprising: an electronic chip 200, the electronic chip 200 including a first active surface 21 and a first back surface 22 disposed opposite to each other, the first active surface 21 having a circuit layer 201; a diamond thermal conductive sheet 205, the diamond thermal conductive sheet 205 being bonded to the first back surface 22 of the electronic chip 200; the circuit layer 201 in the at least one electronic chip assembly structure 31 being bonded to a first redistribution layer 109 of the photonic chip interposer structure 32. Heat sink 208 is attached to the surface of the diamond thermal conductive sheet 205 away from the electronic chip 200 via a thermal interface material layer 207.

[0149] In some embodiments, the thickness of the diamond heat-conducting sheet 205 is 0.1mm-0.5mm.

[0150] In some embodiments, the diamond heat-conducting sheet 205 is made of single-crystal diamond or polycrystalline diamond, wherein the thermal conductivity of the single-crystal diamond is in the range of 1800 W / (m·K)-2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond is in the range of 800 W / (m·K)-1500 W / (m·K).

[0151] In some embodiments, the diamond thermal conductive sheet 205 is bonded to the first back surface 22 of the electronic chip 200 via a bonding metal layer 206; The thickness of the bonding metal layer 206 is less than or equal to 100 nm; The bonding metal layer 206 is made of one or more of Ti, Cu, W, and Au.

[0152] In some embodiments, the number of electronic chip component structures 31 is one or more; When there are multiple electronic chip component structures 31, the electronic chips 200 in different electronic chip component structures 31 may have the same or different functions. When there are multiple electronic chip assembly structures 31, a diamond heat-conducting sheet 205 is bonded to the first back surface 22 of the electronic chip 200 in each electronic chip assembly structure 31.

[0153] In some embodiments, it also includes: The first bonding layer located on the surface of the circuit layer 201 in the electronic chip assembly structure 31 that is away from the first active surface 21; The second bonding layer located on the surface of the first redistribution layer 109 in the photonic chip interposer structure 32, away from the photonic chip 100; The first bonding layer is bonded to the second bonding layer.

[0154] In some embodiments, the circuit layer 201 includes a dielectric layer and a metal circuit layer 201a located in the dielectric layer; The first bonding layer includes a first bonding dielectric layer 203 and a first bonding metal layer 204 located in the first bonding dielectric layer 203, wherein the first bonding metal layer 204 is electrically connected to the metal line layer 201a. The dielectric layer and the first bonding dielectric layer 203 are made of inorganic materials, while the metal circuit layer 201a and the first bonding metal layer 204 are made of conductive metal materials.

[0155] In some embodiments, the first redistribution layer 109 includes a first dielectric layer 110 and a first metal wiring layer 111 located in the first dielectric layer 110; The second bonding layer includes a second bonding dielectric layer 112 and a second bonding metal layer 113 located in the second bonding dielectric layer 112, wherein the second bonding metal layer 113 is electrically connected to the first metal wiring layer 111. The first dielectric layer 110 and the second bonding dielectric layer 112 are made of organic materials, and the first metal wiring layer 111 and the second bonding metal layer 113 are made of conductive metal materials.

[0156] In some embodiments, the photonic chip interposer structure 32 further includes: A plurality of metal pillars 108 are located in the molding layer 107, and the first and second surfaces of the molding layer 107 expose the two end surfaces of the metal pillars 108 respectively. One end surface of the metal pillars 108 is electrically connected to the first redistribution layer 109. The second wiring layer 114 is located on the second surface of the molding layer 107 and the second back surface 12 of the photonic chip 100. The second wiring layer 114 is electrically connected to the other end surface of the metal pillar 108. A solder bump 117 is located on the surface of the second redistribution layer 114 away from the photonic chip 100, and the solder bump 117 is electrically connected to the second redistribution layer 114.

[0157] In some embodiments, the photonic chip 100 further has a groove 105 that penetrates a portion of the second active surface 11 and a portion of the side surface of the photonic chip 100, with the sidewall of the groove 105 exposed to the optical port 104.

[0158] In some embodiments, it further includes: an optical coupling component 119, which is mounted on the side of the photonic chip 100 and corresponds to the position of the optical port 104.

[0159] In some embodiments, the material of the thermal interface material layer 206 includes nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

[0160] It should be noted that the same or similar limitations or descriptions in this embodiment (optoelectronic co-packaging structure) as those in the foregoing embodiment (method for forming optoelectronic co-packaging structure) will not be repeated in this embodiment. Please refer to the corresponding limitations or descriptions in the foregoing embodiments for details.

[0161] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0162] It should be noted that, unless otherwise specified, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0163] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming an optoelectronic co-packaging structure, characterized in that, include: At least one electronic chip assembly structure is provided, each of the electronic chip assembly structures comprising: an electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; and a diamond thermal conductive sheet bonded to the first back surface of the electronic chip. A photonic chip interposer structure is provided, comprising: a photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a protective layer located on a portion of the second active surface and covering the optical port; a molding compound layer encapsulating the photonic chip, the molding compound layer including a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps and the protective layer on the surface away from the second active surface; and a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bumps and exposing the protective layer. The wiring layer in the at least one electronic chip component structure is bonded to the first wiring layer of the photonic chip interposer structure. A heat sink is provided, and the heat sink is attached to the surface of the diamond thermal conductive sheet away from the electronic chip through a thermal interface material layer.

2. The method for forming the optoelectronic co-packaging structure according to claim 1, characterized in that, The thickness of the diamond heat-conducting sheet is 0.1mm-0.5mm.

3. The method for forming the optoelectronic co-packaging structure according to claim 1 or 2, characterized in that, The material of the diamond heat-conducting sheet is single-crystal diamond or polycrystalline diamond. The thermal conductivity of the single-crystal diamond is in the range of 1800 W / (m·K)-2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond is in the range of 800 W / (m·K)-1500 W / (m·K).

4. The method for forming the optoelectronic co-packaging structure according to claim 1, characterized in that, The diamond thermal conductive sheet is bonded to the first back side of the electronic chip via a metal bonding layer.

5. The method for forming the optoelectronic co-packaging structure according to claim 4, characterized in that, The thickness of the metal bonding layer is less than or equal to 100 nm; The material of the metal bonding layer is one or more of Ti, Cu, W, and Au.

6. The method for forming the optoelectronic co-packaging structure according to claim 1, characterized in that, The number of electronic chip component structures is one or more; When there are multiple electronic chip component structures, the electronic chips in different electronic chip component structures may have the same or different functions. When there are multiple electronic chip assembly structures, the diamond heat-conducting sheet is bonded to the first back side of the electronic chip in each electronic chip assembly structure.

7. The method for forming the optoelectronic co-packaging structure according to claim 1 or 6, characterized in that, Bonding the wiring layer in the at least one electronic chip component structure to the first rewiring layer of the photonic chip interposer structure includes: A first bonding layer is formed on the surface of the circuit layer in the electronic chip assembly structure that is away from the first active surface; A second bonding layer is formed on the surface of the first redistribution layer in the photonic chip interposer structure that is away from the photonic chip; The first bonding layer is bonded to the second bonding layer.

8. The method for forming an optoelectronic co-packaging structure according to claim 7, characterized in that, The circuit layer includes a dielectric layer and a metal circuit layer located within the dielectric layer; The first bonding layer includes a first bonding dielectric layer and a first bonding metal layer located in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the metal circuit layer.

9. The method for forming an optoelectronic co-packaging structure according to claim 8, characterized in that, The dielectric layer and the first bonding dielectric layer are made of inorganic materials, and the metal circuit layer and the first bonding metal layer are made of conductive metal materials.

10. The method for forming an optoelectronic co-packaging structure according to claim 7, characterized in that, The first rewiring layer includes a first dielectric layer and a first metal wiring layer located in the first dielectric layer; The second bonding layer includes a second bonding dielectric layer and a second bonding metal layer located in the second bonding dielectric layer, wherein the second bonding metal layer is electrically connected to the first metal wiring layer.

11. The method for forming an optoelectronic co-packaging structure according to claim 10, characterized in that, The first dielectric layer and the second bonding dielectric layer are made of organic materials, and the first metal wiring layer and the second bonding metal layer are made of conductive metal materials.

12. The method for forming an optoelectronic co-packaging structure according to claim 7, characterized in that, The formation process of the electronic chip assembly structure includes: A first wafer is provided, the first wafer including a plurality of electronic chip regions and a first dicing region located between the electronic chip regions; Several electronic devices are formed in the electronic chip area on the front side of the first wafer; A circuit layer is formed on the front side of the first wafer, and the circuit layer is electrically connected to the plurality of electronic devices; A first bonding layer is formed on the circuit layer; A first carrier plate is bonded to the surface of the first bonding layer that is away from the first wafer; A metal bonding layer is formed on the back side of the first wafer; The metal bonding layer, the circuit layer, and the first wafer are cut along the first dicing zone; After the cutting is performed, a diamond thermal conductive sheet is bonded to the surface of the metal bonding layer of each electronic chip area away from the first wafer. After bonding the diamond thermal conductive sheet, the first carrier plate is removed to form a plurality of discrete electronic chip component structures.

13. The method for forming an optoelectronic co-packaging structure according to claim 7, characterized in that, The photonic chip interposer structure also includes: A plurality of metal pillars are located in the molding layer, and the first and second surfaces of the molding layer expose the two end surfaces of the metal pillars, respectively. One end surface of the metal pillar is electrically connected to the first redistribution layer. The second wiring layer is located on the second surface of the molding layer and the second back surface of the photonic chip, and the second wiring layer is electrically connected to the other end surface of the metal pillar. A solder bump is located on the surface of the second wiring layer away from the photonic chip, and the solder bump is electrically connected to the second wiring layer.

14. The method for forming an optoelectronic co-packaging structure according to claim 13, characterized in that, The second redistribution layer includes a second dielectric layer and a second metal wiring layer located within the second dielectric layer; The material of the second dielectric layer includes organic materials, and the material of the second metal wiring layer includes conductive metal materials.

15. The method for forming an optoelectronic co-packaging structure according to claim 13, characterized in that, The formation process of the photonic chip interposer structure includes: A photonic chip is provided, the photonic chip including a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a protective layer located on a portion of the second active surface and covering the optical port; Provide a second carrier board; A second wiring layer is formed on the surface of the second carrier board; A plurality of metal pillars are formed on the surface of the second redistribution layer away from the second carrier board; The second back side of the photonic chip is attached to the surface of the second redistribution layer that is away from the second substrate. A molding compound layer is formed on the surface of the second redistribution layer away from the second substrate, covering the photonic chip and the metal pillar. The first surface of the molding compound layer exposes the surface of the metal pillar and the protective layer away from the second active surface of the photonic chip, and the surface of the metal bump away from the second redistribution layer. A first redistribution layer is formed on a portion of the first surface of the molding layer, the first redistribution layer being electrically connected to the metal bump and exposing the protective layer; Remove the second carrier board and form a solder bump on the surface of the second redistribution layer away from the photonic chip.

16. The method for forming an optoelectronic co-packaging structure according to claim 15, characterized in that, The photonic chip also has a groove that penetrates a portion of the second active surface, and the sidewall of the groove exposes the light port; The protective layer fills the groove and covers the optical port, and the surface of the protective layer is higher than the surface of the second active surface.

17. The method for forming an optoelectronic co-packaging structure according to claim 16, characterized in that, The formation process of the photonic chip includes: A second wafer is provided, the second wafer comprising a plurality of photonic chip regions and a second dicing region located between the photonic chip regions; Photonic devices and optical ports are formed in the photonic chip region on the front side of the second wafer; A groove is formed in a second wafer on one side of the optical aperture, and the sidewall of the groove exposes the optical aperture; A protective layer covering the optical port is formed in the groove and on the surface of part of the photonic chip area; After the protective layer is formed, a plurality of raised metal bumps are formed on the second active surface; After forming several metal bumps, the second wafer is cut along the second dicing zone to form several discrete photonic chips.

18. The method for forming an optoelectronic co-packaging structure according to claim 17, characterized in that, The material of the protective layer includes photoresist; The formation of the protective layer includes a spin coating process, an exposure process, and a development process.

19. The method for forming an optoelectronic co-packaging structure according to claim 16, characterized in that, After bonding the wiring layer in the at least one electronic chip component structure to the first rewiring layer of the photonic chip interposer structure, the method further includes: A slitting process is performed to cut away part of the protective layer in the groove, as well as the molding layer and photonic chip away from the outside of the groove, while the remaining protective layer in the groove still covers the optical port; After the offset cutting process, the remaining protective layer in the groove is removed to expose the optical aperture.

20. The method for forming an optoelectronic co-packaging structure according to claim 19, characterized in that, The process of removing the remaining protective layer in the groove includes: selectively rinsing the protective layer with a protective layer removal solution to remove the protective layer.

21. The method for forming an optoelectronic co-packaging structure according to claim 19, characterized in that, After exposing the optical port, the method further includes: installing an optical coupling component corresponding to the position of the optical port on one side of the photonic chip.

22. The method for forming an optoelectronic co-packaging structure according to claim 1, characterized in that, The thermal interface material layer includes materials such as nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

23. A photoelectric co-packaging structure, characterized in that, include: A photonic chip interposer structure includes: a photonic chip, comprising a second active surface and a second back surface disposed opposite to each other, the second active surface having a plurality of raised metal bumps, and an optical port in the second active surface on one side of the plurality of metal bumps; a molding compound covering the photonic chip, the molding compound including a first surface and a second surface disposed opposite to each other, the first surface exposing the metal bumps and the optical port; and a first redistribution layer located on a portion of the first surface, the first redistribution layer being electrically connected to the metal bumps and exposing the optical port. At least one electronic chip assembly structure, each of the electronic chip assembly structures comprising: an electronic chip, the electronic chip including a first active surface and a first back surface disposed opposite to each other, the first active surface having a circuit layer; a diamond thermal conductive sheet, the diamond thermal conductive sheet being bonded to the first back surface of the electronic chip; the circuit layer in the at least one electronic chip assembly structure being bonded to a first redistribution layer of the photonic chip interposer structure; A heat sink is attached to the surface of the diamond thermally conductive sheet away from the electronic chip via a thermal interface material layer.

24. The optoelectronic co-packaging structure according to claim 23, characterized in that, The thickness of the diamond heat-conducting sheet is 0.1mm-0.5mm.

25. The optoelectronic co-packaging structure according to claim 23 or 24, characterized in that, The material of the diamond heat-conducting sheet is single-crystal diamond or polycrystalline diamond. The thermal conductivity of the single-crystal diamond is in the range of 1800 W / (m·K)-2400 W / (m·K), and the thermal conductivity of the polycrystalline diamond is in the range of 800 W / (m·K)-1500 W / (m·K).

26. The optoelectronic co-packaging structure according to claim 23, characterized in that, The diamond thermal conductive sheet is bonded to the first back side of the electronic chip via a metal bonding layer; The thickness of the metal bonding layer is less than or equal to 100 nm; The material of the metal bonding layer is one or more of Ti, Cu, W, and Au.

27. The optoelectronic co-packaging structure according to claim 23, characterized in that, The number of electronic chip component structures is one or more; When there are multiple electronic chip component structures, the electronic chips in different electronic chip component structures may have the same or different functions. When there are multiple electronic chip assembly structures, the diamond heat-conducting sheet is bonded to the first back side of the electronic chip in each electronic chip assembly structure.

28. The optoelectronic co-packaging structure according to claim 23 or 27, characterized in that, Also includes: The first bonding layer located on the surface of the circuit layer in the electronic chip assembly structure that is away from the first active surface; A second bonding layer located on the surface of the first redistribution layer in the photonic chip interposer structure, away from the photonic chip; The first bonding layer is bonded to the second bonding layer.

29. The optoelectronic co-packaging structure according to claim 28, characterized in that, The circuit layer includes a dielectric layer and a metal circuit layer located within the dielectric layer; The first bonding layer includes a first bonding dielectric layer and a first bonding metal layer located in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the metal circuit layer; The dielectric layer and the first bonding dielectric layer are made of inorganic materials, and the metal circuit layer and the first bonding metal layer are made of conductive metal materials.

30. The optoelectronic co-packaging structure according to claim 28, characterized in that, The first rewiring layer includes a first dielectric layer and a first metal wiring layer located in the first dielectric layer; The second bonding layer includes a second bonding dielectric layer and a second bonding metal layer located in the second bonding dielectric layer, wherein the second bonding metal layer is electrically connected to the first metal wiring layer; The first dielectric layer and the second bonding dielectric layer are made of organic materials, and the first metal wiring layer and the second bonding metal layer are made of conductive metal materials.

31. The optoelectronic co-packaging structure according to claim 23, characterized in that, The photonic chip interposer structure also includes: A plurality of metal pillars are located in the molding layer, and the first and second surfaces of the molding layer expose the two end surfaces of the metal pillars, respectively. One end surface of the metal pillar is electrically connected to the first redistribution layer. The second wiring layer is located on the second surface of the molding layer and the second back surface of the photonic chip, and the second wiring layer is electrically connected to the other end surface of the metal pillar. A solder bump is located on the surface of the second wiring layer away from the photonic chip, and the solder bump is electrically connected to the second wiring layer.

32. The optoelectronic co-packaging structure according to claim 23, characterized in that, The photonic chip also has a groove that penetrates a portion of the second active surface and a portion of the side surface of the photonic chip, with the sidewall of the groove exposed at the light port.

33. The optoelectronic co-packaging structure according to claim 32, characterized in that, Also includes: An optical coupling component is mounted on the side of the photonic chip and corresponds to the position of the optical port.

34. The optoelectronic co-packaging structure according to claim 23, characterized in that, The thermal interface material layer includes materials such as nano-silver, titanium, tungsten, gold silicon, germanium gold, or gold tin.

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