Display substrate and display device

Abstract

The application provides a display substrate and a display device. The display substrate comprises a substrate, a plurality of sub-pixels and a plurality of power signal lines. The plurality of sub-pixels are arranged in multiple rows and multiple columns. The size of the sub-pixel in the row direction is a first size, the size of the sub-pixel in the column direction is a second size, and the first size is greater than the second size. The sub-pixel comprises a first electrode and a second electrode arranged oppositely, and liquid crystal molecules between the first electrode and the second electrode. The plurality of power signal lines extend along the column direction. Two first electrodes adjacent in the row direction are connected by the power signal line, and two first electrodes adjacent in the column direction are connected by the power signal line. The display device comprises the display substrate.

Description

[0001] This application is a divisional application of patent application number 202310748299.8 (the original application was filed on June 21, 2023, and the invention was entitled "Display Substrate and Display Device"). Technical Field

[0002] This application relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] With the continuous development of display technology, display devices such as mobile phones, laptops, and televisions have become necessities in people's work and life. LCD displays, due to their advantages such as high brightness, vibrant colors, and wide viewing angles, have become the mainstream display devices. Currently, LCD displays suffer from the problem of low pixel aperture ratio. Summary of the Invention

[0004] This application provides a display substrate and a display device.

[0005] According to a first aspect of the embodiments of this application, a display substrate is provided. The display substrate includes: Substrate; The substrate contains a plurality of sub-pixels arranged in multiple rows and columns. The sub-pixels have a first dimension in the row direction and a second dimension in the column direction, wherein the first dimension is larger than the second dimension. Each sub-pixel includes a first electrode and a second electrode disposed opposite to each other, and liquid crystal molecules located between the first electrode and the second electrode. Multiple power signal lines extend along the column direction; two adjacent first electrodes in the row direction are connected by the power signal lines, and two adjacent first electrodes in the column direction are connected by the power signal lines.

[0006] In one embodiment, among two second electrodes connected to the same power signal line and adjacent in the row direction, in the row direction, the distance from one of the second electrodes to the portion of the power signal line extending along the column direction is a first distance, and the distance from the other second electrode to the portion extending along the column direction is a second distance, wherein the first distance is different from the second distance.

[0007] In one embodiment, the power signal line includes alternating first sub-signal lines and second sub-signal lines, wherein the dimension of the first sub-signal line in the column direction is greater than the dimension of the second sub-signal line in the column direction.

[0008] In one embodiment, the second sub-signal line extends along the column direction; the two second electrodes that are adjacent in the column direction and located on either side of the center of the second sub-signal line are equidistant from the center of the second sub-signal line.

[0009] In one embodiment, the display substrate further includes a first signal line extending along the row direction, and a second sub-signal line extending along the column direction; the orthographic projection of the second sub-signal line on the substrate overlaps with the orthographic projection of a first signal line on the substrate; the opposite ends of the second sub-signal line are respectively connected to the first sub-signal line, and the orthographic projections of the opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projection of the first signal line on the substrate.

[0010] In one embodiment, the first sub-signal line includes a first segment, a second segment, and a third segment connected in sequence. The first segment extends along the row direction, the second segment extends along the column direction, and the third segment is located on opposite sides of the first segment. The ends of the first segment and the third segment that are away from the second segment are respectively connected to the second sub-signal line.

[0011] In one embodiment, among two second electrodes connected to the same power signal line and adjacent in the row direction, the distance from one second electrode to the second segment is different from the distance from the other second electrode to the second segment in the row direction.

[0012] In one embodiment, among two second electrodes connected to the same power signal line and adjacent in the column direction, in the row direction, the distance from one second electrode to the second segment is different from the distance from the other second electrode to the second segment.

[0013] In one embodiment, the first sub-signal line includes a fourth segment and a fifth segment connected together, the fourth segment extending along the row direction and the fifth segment extending along the column direction, and the end of the fourth segment opposite to the fifth segment and the end of the fifth segment opposite to the fourth segment being connected to the second sub-signal line.

[0014] In one embodiment, among two second electrodes connected to the same power signal line and adjacent in the row direction, the distance from one second electrode to the fifth segment is different from the distance from the other second electrode to the fifth segment in the row direction.

[0015] In one embodiment, in two sub-pixels connected to the same power signal line and adjacent in the column direction, in the row direction, the distance from one of the second electrodes to the fifth segment is different from the distance from the other second electrode to the fifth segment.

[0016] In one embodiment, the first sub-signal line includes a connected sixth segment and a seventh segment, the sixth segment extending along the row direction and located on one side of the seventh segment, the seventh segment extending along the column direction; the opposite ends of the seventh segment are respectively connected to the second sub-signal line.

[0017] In one embodiment, among two second electrodes connected to the same power signal line and adjacent in the row direction, the distance from one second electrode to the seventh segment is different from the distance from the other second electrode to the seventh segment in the row direction.

[0018] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer located on the side of the first metal conductive layer opposite to the substrate, wherein the first sub-signal line is located on the first metal conductive layer and the second sub-signal line is located on the second metal conductive layer.

[0019] In one embodiment, the display substrate further includes an insulating layer located between the first metal conductive layer and the second metal conductive layer, the insulating layer having through holes, through which the first sub-signal line and the second sub-signal line are connected; The display substrate further includes a light-shielding layer located on the side of the sub-pixel away from the substrate. The light-shielding layer has a plurality of openings. The orthographic projection of one of the openings on the substrate falls within the orthographic projection of the second electrode on the substrate. The orthographic projection of the through-hole on the substrate falls within the edge region of the orthographic projection of the second electrode on the substrate and is located within the orthographic projection of the light-shielding layer on the substrate.

[0020] In one embodiment, the first electrode is connected to the first sub-signal line, or the first electrode is connected to the second sub-signal line.

[0021] In one embodiment, the display substrate includes a first metal conductive layer and a second metal conductive layer located on the side of the first metal conductive layer facing away from the substrate. The power signal line includes a first portion extending along the column direction and a second portion extending along the row direction. The first portion is located in the second metal conductive layer. The second portion is located in the first metal conductive layer or disposed in the same layer as the first electrode. The second portion connects two adjacent first electrodes located in the same row. The second portion is located between the second metal conductive layer and the substrate. The display substrate further includes an insulating layer located between the second portion and the second metal conductive layer. The insulating layer has vias, and the first portion and the second portion are connected through the vias.

[0022] In one embodiment, the display substrate further includes a plurality of first signal lines extending along the row direction and a plurality of second signal lines extending along the column direction; the orthographic projections of the second signal lines and the power signal lines on the substrate are located between the orthographic projections of two adjacent columns of the sub-pixels on the substrate.

[0023] In one embodiment, the display substrate further includes a plurality of spacers; The spacers are surrounded at least on both sides by the orthogonal projections of the power signal lines on the substrate; multiple spacers located between adjacent columns of sub-pixels are distributed on both sides of the power signal lines; or... The power signal line includes a portion extending along the column direction, and the orthographic projection of the plurality of spacers located between two adjacent columns of sub-pixels on the substrate is located on the same side of the orthographic projection of the adjacent portions extending along the column direction on the substrate; or, The spacer is located on the side of the power signal line away from the substrate, and the orthographic projection of the spacer on the substrate overlaps with the orthographic projection of the power signal line on the substrate.

[0024] In one embodiment, the display substrate further includes a pixel driving circuit, which includes driving transistors; The orthographic projections of two adjacent driving transistors on the substrate in the column direction are located on opposite sides of the orthographic projections of adjacent power signal lines on the substrate; or, the orthographic projections of two adjacent driving transistors on the substrate in the column direction are located on the same side of the orthographic projections of adjacent power signal lines on the substrate.

[0025] In one embodiment, the display substrate includes a display area and a border area, the sub-pixel is located in the display area, the display substrate also includes a wire located in the border area, the wire being electrically connected to the power signal line and the driver chip respectively; the display substrate also includes a metal conductive layer, the wire being located in the metal conductive layer.

[0026] In one embodiment, the display substrate further includes a light-shielding layer located on the side of the sub-pixel opposite to the substrate, the light-shielding layer having a plurality of openings, wherein the orthographic projection of one of the openings on the substrate falls within the orthographic projection of a second electrode on the substrate; the display substrate further includes a plurality of first signal lines extending along the row direction; The power signal line includes a segment located between two adjacent apertures in the row direction and extending along the column direction, wherein the minimum distance between the edge of the orthographic projection of the segment extending along the column direction onto the substrate and the edge of the orthographic projection of the adjacent aperture onto the substrate ranges from 4 μm to 8 μm; and / or, The first electrode is located on the side of the first signal line facing away from the substrate, and the display substrate further includes an insulating layer located between the first signal line and the first electrode; in the column direction, the distance between the edge of the orthographic projection of the first signal line on the substrate and the edge of the orthographic projection of the second electrode on the substrate ranges from 3 μm to 5 μm; and / or, The orthographic projection of the first signal line on the substrate falls within the orthographic projection of the light-shielding layer on the substrate; the distance between the orthographic projection of the first signal line on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate extending along the row direction is in the range of 6μm~11μm.

[0027] According to a second aspect of the present application, a display device is provided, the display device including the display substrate described above.

[0028] The display substrate and display device provided in this application embodiment, by setting the power signal line to extend along the column direction, can avoid the problem of light leakage caused by the step difference in different areas of the power signal line when the power signal line extends along the row direction and a portion of the power signal line overlaps with the first electrode in the film layer stacking direction, resulting in poor anchoring of liquid crystal molecules in the area where the power signal line has a step difference. In other words, extending the power signal line along the column direction can improve this problem. Therefore, the opening of the light-emitting area of ​​the sub-pixel in the light-shielding layer on the side of the sub-pixel away from the substrate can be set to be larger, thereby increasing the pixel aperture ratio of the display substrate and thus improving the light efficiency of the display substrate. Attached Figure Description

[0029] Figure 1This is a partial structural schematic diagram of a display substrate provided in an exemplary embodiment of this application; Figure 2 This is a partial schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment of this application; Figure 3 This is a partial schematic diagram of multiple film layers of a display substrate provided in another exemplary embodiment of this application; Figure 4 This is a partial schematic diagram of multiple film layers of a display substrate provided in another exemplary embodiment of this application; Figure 5 This is a partial schematic diagram of the first metal conductive layer of a display substrate provided in an exemplary embodiment of this application; Figure 6 This is a partial schematic diagram of the first metal conductive layer and the first electrode superimposed on a display substrate provided in an exemplary embodiment of this application; Figure 7 This is a partial schematic diagram of the stacked first metal conductive layer, first electrode, and second metal conductive layer of a display substrate provided in an exemplary embodiment of this application; Figure 8 yes Figure 2 The image shows a cross-sectional view of the display substrate taken along section AA. Figure 9 yes Figure 2 The image shows a cross-sectional view of a display substrate cut along the BB line. Figure 10 yes Figure 2 The image shows another cross-sectional view of the display substrate cut along BB. Figure 11 This is a partial schematic diagram of the first electrode of a display substrate provided in an exemplary embodiment of this application; Figure 12 This is a partial schematic diagram of the first metal conductive layer and the first electrode superimposed on a display substrate provided in an exemplary embodiment of this application; Figure 13 This is a partial schematic diagram of the stacked first metal conductive layer, first electrode, and second metal conductive layer of a display substrate provided in an exemplary embodiment of this application; Figure 14 yes Figure 3 The image shows a cross-sectional view of the display substrate taken along the CC direction; Figure 15 This is a partial schematic diagram of multiple film layers of a display substrate provided in another exemplary embodiment of this application; Figure 16 This is a partial schematic diagram of multiple film layers of a display substrate provided in another exemplary embodiment of this application; Figure 17 This is a partial schematic diagram of multiple film layers of a display substrate provided in another exemplary embodiment of this application. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0031] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0032] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0033] This application provides a display substrate and a display device. The display substrate and display device of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0034] This application provides a display substrate. For example... Figure 1 As shown, the display substrate includes a substrate 10 and a plurality of sub-pixels 20 located on the substrate 10. The plurality of sub-pixels 20 are arranged in multiple rows and columns. The size of the sub-pixels 20 in the row direction X is a first size d1, and the size of the sub-pixels 20 in the column direction Y is a second size d2. The first size d1 is greater than the second size d2.

[0035] like Figures 2 to 4As shown, the sub-pixel includes a first electrode 21 and a second electrode 22 disposed opposite to each other. The sub-pixel 20 also includes liquid crystal molecules located between the first electrode 21 and the second electrode 22. The display substrate also includes a plurality of power signal lines 30, which extend along the column direction Y; two adjacent first electrodes 21 in the row direction X are connected by the power signal lines 30, and two adjacent first electrodes 21 in the column direction Y are connected by the power signal lines 30. The term "power signal lines 30 extending along the column direction Y" means that the power signal lines 30 extend entirely along the column direction Y, but the power signal lines 30 may include a portion extending along the row direction X.

[0036] The display substrate provided in this application embodiment, by setting the power signal line to extend along the column direction, can avoid the problem of light leakage caused by the step difference in different areas of the power signal line when the power signal line extends along the row direction and a portion of the power signal line overlaps with the first electrode in the film layer stacking direction, resulting in poor anchoring of liquid crystal molecules in the area where the power signal line has a step difference. In other words, extending the power signal line along the column direction can improve this problem. Therefore, the opening of the light-emitting area of ​​the sub-pixel in the light-shielding layer on the side of the sub-pixel away from the substrate can be set to be larger, thereby increasing the pixel aperture ratio of the display substrate and thus improving the light efficiency of the display substrate.

[0037] In one embodiment, the display substrate further includes a plurality of pixel driving circuits, wherein the pixel driving circuits of the display substrate correspond one-to-one with the sub-pixels, and each pixel driving circuit is used to drive the corresponding sub-pixel.

[0038] In one embodiment, such as Figure 1 As shown, the display substrate also includes multiple scan signal lines (Gates) extending along the row direction X and multiple data signal lines (Data) extending along the column direction. Subpixels in the same row are connected to the same scan signal line (Gate), and the scan signal line (Gate) can be located between two adjacent rows of subpixels. The number of data signal lines (Data) can be the same as the number of rows of subpixels, and the data signal lines (Data) can be located between two adjacent columns of subpixels. Since the size of the subpixel 20 in the row direction X is larger than its size in the column direction Y, when the size of the display substrate in the row direction X is fixed, the number of columns of subpixels in the display substrate can be reduced, thereby reducing the number of data signal lines (Data), and consequently reducing the number of driver chips used to provide signals to the data signal lines (Data), thus reducing the cost of the display substrate.

[0039] In one embodiment, such as Figures 1 to 3As shown, data signal lines Data are provided on opposite sides of each column of sub-pixels. In the column direction Y, the pixel driving circuits corresponding to two adjacent sub-pixels 20 are connected to different data signal lines Data. To avoid liquid crystal molecule polarization, during display, the signal of one of the two adjacent data signal lines Data is greater than the signal of the power signal line 30, and the signal of the other data signal line Data is less than the signal of the power signal line 30. This arrangement ensures that in the column direction, one pixel driving circuit receives a data signal greater than the signal of the power signal line 30, and the other pixel driving circuit receives a data signal less than the signal of the power signal line 30. Simultaneously, in the row direction, one pixel driving circuit receives a data signal greater than the signal of the power signal line 30, and the other pixel driving circuit receives a data signal less than the signal of the power signal line 30, thus improving the display uniformity and display effect of the display substrate.

[0040] In one embodiment, multiple subpixels in the display substrate are divided into multiple pixel units, and each pixel unit may include multiple subpixels with different emission colors. Multiple subpixels of the same pixel unit may be arranged along the column direction Y, and each subpixel of the same pixel unit is connected to a different scan signal line (Gate). Multiple subpixels located in the same row may have the same emission color.

[0041] In one embodiment, the display substrate may include three sub-pixels with different emission colors, such as a red emission sub-pixel, a green emission sub-pixel, and a blue emission sub-pixel. A pixel unit may include three sub-pixels with different emission colors.

[0042] In one embodiment, the substrate 10 can be a flexible substrate or a rigid substrate. The flexible substrate may be made of one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials, including epoxy resin, triazine, silicone resin, or polyimide. The rigid substrate includes any of the following: glass substrate, quartz substrate, sapphire substrate, ceramic substrate, etc.; or any of the following semiconductor substrates: single-crystal semiconductor substrates or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium, SOI (Silicon on Insulator) substrates, etc.

[0043] In one embodiment, the first electrode 21 is a cathode, the second electrode 22 is an anode, and the power signal line is a low-level power signal line. In some embodiments, the second electrode 22 may have multiple strip-shaped slits.

[0044] In one embodiment, both the first electrode 21 and the second electrode 22 may be made of transparent conductive materials. Examples of transparent conductive materials include indium zinc oxide and indium tin oxide.

[0045] In one embodiment, such as Figures 2 to 4 As shown, the pixel driving circuit includes a driving transistor 70, which includes a gate electrode 71, a first electrode 72, and a second electrode 73. The first electrode 72 and the second electrode 73 may be located on the side of the gate electrode 71 facing away from the substrate. One of the first electrode 72 and the second electrode 73 may be a source electrode, and the other may be a drain electrode; for example, the first electrode 72 may be the source electrode, and the second electrode 73 may be the drain electrode. The pixel driving circuit may also include an active layer, which may be located between the gate electrode 71 and the substrate. The second electrode 22 of the sub-pixel is connected to the first electrode 72 of the corresponding driving transistor 70.

[0046] In one embodiment, such as Figures 5 to 7 As shown, the display substrate includes a first metal conductive layer 91 located on a substrate and a second metal conductive layer 92 located on the side of the first metal conductive layer 91 facing away from the substrate. The display substrate also includes an insulating layer located between the first metal conductive layer 91 and the second metal conductive layer 92.

[0047] In one embodiment, the second electrode 22 is located on the side of the second metal conductive layer 92 away from the substrate, and the display substrate further includes an insulating material layer located between the second metal conductive layer 92 and the second electrode 22.

[0048] In one embodiment, such as Figure 5 As shown, the gate electrode 71 and the scan signal line Gate are located in the first metal conductive layer 91, and the gate electrode 71 is connected to the scan signal line Gate.

[0049] In one embodiment, such as Figure 6 As shown, the first electrode 72, the second electrode 73, and the data signal line Data are located in the second metal conductive layer 92.

[0050] In one embodiment, such as Figure 7 As shown, the insulating material layer has multiple through holes 82, and the second electrode 22 can be electrically connected to the first electrode 72 through the through holes 82.

[0051] In one embodiment, the display substrate further includes a light-shielding layer and a color filter layer located on the side of the sub-pixel facing away from the substrate. The light-shielding layer has multiple openings. For example... Figures 2 to 4As shown, the orthographic projection of one of the openings 50 on the substrate falls within the orthographic projection of one of the second electrodes 22 on the substrate. Each opening corresponds one-to-one with a first electrode, and the orthographic projection of each opening on the substrate falls within the orthographic projection of the corresponding second electrode on the substrate. The color filter layer includes a plurality of color filter portions, at least a portion of which is located within one of the openings.

[0052] In one embodiment, the display substrate can be obtained by assembling an array substrate and a color filter substrate. The array substrate includes a substrate, a first conductive metal layer, a second conductive metal layer, and a first electrode. The color filter substrate may include a second electrode, a light-shielding layer, and a color filter layer. During the assembly process, a sealant is applied to one of the color filter substrate and the array substrate, while liquid crystal material is added to the other; subsequently, the color filter substrate and the array substrate are assembled to obtain the display substrate.

[0053] In one embodiment, such as Figures 2 to 4 As shown, among two second electrodes 22 connected to the same power signal line 30 and adjacent in the row direction, in the row direction X, the distance from one second electrode 22 to the portion of the power signal line 30 extending along the column direction Y is a first distance, and the distance from the other second electrode 22 to the portion extending along the column direction Y is a second distance, wherein the first distance and the second distance are different. With this arrangement, at least a portion of the data signal line Data located between two columns can be positioned between the power signal line 30 and a column of sub-pixels farther away from it.

[0054] In one embodiment, such as Figures 2 to 4 As shown, the power signal line 30 includes alternating first sub-signal lines 31 and second sub-signal lines 32. The first sub-signal line 31 has a dimension d3 in the column direction Y, and the second sub-signal line 32 has a dimension d4 in the column direction Y, where d3 is greater than d4. In the same power signal line 30, the opposite ends of the first sub-signal line 31 are respectively connected to the adjacent second sub-signal line 32, and the opposite ends of the second sub-signal line 32 are respectively connected to the adjacent first sub-signal line 31.

[0055] In one embodiment, such as Figures 2 to 4 As shown, the second sub-signal line 32 extends along the column direction Y; the two second electrodes 22, which are adjacent in the column direction Y and located on either side of the center of the second sub-signal line 32, are equidistant from the center of the second sub-signal line 32. For example Figure 2In the example shown, of the two second electrodes 22 located on both sides of the center of the second sub-signal line 32, the distance from one second electrode 22 to the center of the second sub-signal line 32 is d5, and the distance from the other second electrode 22 to the center of the second sub-signal line 32 is d6, and d5 and d6 are equal.

[0056] In one embodiment, such as Figures 2 to 4 As shown, the display substrate further includes a first signal line 41 extending along the row direction X, and a second sub-signal line 32 extending along the column direction Y; the orthographic projection of the second sub-signal line 32 on the substrate overlaps with the orthographic projection of one of the first signal lines 41 on the substrate; the opposite ends of the second sub-signal line 32 are respectively connected to the first sub-signal line 31, and the orthographic projections of the opposite ends of the second sub-signal line 32 on the substrate are located on opposite sides of the orthographic projection of the first signal line 41 on the substrate. The orthographic projection of the first sub-signal line 31 on the substrate is located between the orthographic projections of two adjacent first signal lines 41 on the substrate. In some embodiments, the first signal line 41 is a scan signal line (Gate).

[0057] In one embodiment, such as Figures 2 to 4 As shown, the display substrate further includes a plurality of second signal lines 42 extending along the column direction; the orthographic projections of the second signal lines 42 and the power signal lines 30 on the substrate are both located between the orthographic projections of two adjacent columns of sub-pixels on the substrate. In some embodiments, the second signal lines 42 are data signal lines.

[0058] In one embodiment, such as Figure 2 As shown, the first sub-signal line 31 includes a first segment 311, a second segment 312, and a third segment 313 connected sequentially. The first segment 311 extends along the row direction X, the second segment 312 extends along the column direction Y, and the third segment 313 is located on opposite sides of the first segment 311. The ends of the first segment 311 and the third segment 313 opposite to the second segment 312 are connected to the second sub-signal line 32. This arrangement facilitates the connection between the first sub-signal line 31 and the second sub-signal line 32, and also facilitates the connection between the first sub-signal line 31 and two adjacent first electrodes 21 in the row direction X. Figure 2 In the embodiment shown, the angle between the extension direction of the third segment 313 and the extension direction of the second segment 312 is an acute angle.

[0059] In one embodiment, such as Figure 2As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent in the row direction X, the distance from one second electrode 22 to the second segment 312 is different from the distance from the other second electrode 22 to the second segment 312 in the row direction X.

[0060] In one embodiment, such as Figure 2 As shown, among two second electrodes connected to the same power signal line 30 and adjacent in the column direction Y, the distance from one second electrode 22 to the second segment 312 in the row direction X is different from the distance from the other second electrode 22 to the second segment 312. With this configuration, the power signal line 30 is zigzag-shaped, allowing two adjacent driving transistors 70 in the column direction to be positioned on opposite sides of the power signal line 30, thereby placing two adjacent driving transistors 70 on opposite sides of the data signal line Data, thus improving the display uniformity of the display substrate.

[0061] In one embodiment, such as Figure 3 As shown, the first sub-signal line 31 includes a fourth segment 314 and a fifth segment 315 connected together. The fourth segment 314 extends along the row direction X, and the fifth segment 315 extends along the column direction Y. The ends of the fourth segment 314 and the fifth segment 315 that are opposite to the fifth segment 315 are connected to the second sub-signal line 32. This arrangement facilitates the connection between the first sub-signal line 31 and the second sub-signal line 32, and also facilitates the connection between the first sub-signal line 31 and two adjacent first electrodes 21 in the row direction X. Simultaneously, it allows the power signal line 30 to be in a zigzag shape, facilitating the placement of two adjacent driving transistors 70 in the column direction on opposite sides of the power signal line 30, and also allowing two adjacent driving transistors 70 to be placed on opposite sides of the data signal line Data, thereby improving the display uniformity of the display substrate.

[0062] In one embodiment, such as Figure 3 As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent in the row direction X, the distance from one of the second electrodes 22 to the fifth segment 315 is different from the distance from the other second electrode 22 to the fifth segment 315 in the row direction X.

[0063] In one embodiment, such as Figure 3 As shown, in two sub-pixels connected to the same power signal line 30 and adjacent in the column direction Y, in the row direction X, the distance from one of the second electrodes 22 to the fifth segment 315 is different from the distance from the other second electrode 22 to the fifth segment 315. This arrangement helps the power signal line 30 to have a zigzag shape.

[0064] In one embodiment, such as Figure 4 As shown, the first sub-signal line 31 includes a connected sixth segment 316 and a seventh segment 317. The sixth segment 316 extends along the row direction X and is located on one side of the seventh segment 317. The seventh segment 317 extends along the column direction Y. The opposite ends of the seventh segment 317 are respectively connected to the second sub-signal line 32. This configuration allows the sixth segment 316 and the seventh segment 317 to be connected to different first electrodes 21 of two adjacent first electrodes 21 in the row direction, facilitating the connection of the first sub-signal line 31 to the two adjacent first electrodes 21 in the row direction X, and also facilitating the connection of the first sub-signal line 31 to the second sub-signal line 32.

[0065] In one embodiment, such as Figure 4 As shown, among the two second electrodes 22 connected to the same power signal line 30 and adjacent in the row direction X, the distance from one of the second electrodes 22 to the seventh segment 317 is different from the distance from the other second electrode 22 to the seventh segment 317 in the row direction X.

[0066] In one embodiment, such as Figures 5 to 7 As shown, the first sub-signal line 31 is located on the first metal conductive layer 91, and the second sub-signal line 32 is located on the second metal conductive layer 92. That is, the first sub-signal line 31 is located on the same layer as the gate electrode 71, and the second sub-signal line 32 is located on the same layer as the first electrode 72 and the second electrode 73. With this configuration, in the same power signal line 30, the second sub-signal line 32 can connect two adjacent first sub-signal lines 31 together while avoiding short circuit between the second sub-signal line 32 and the scan signal line Gate; and since both the first sub-signal line 31 and the second sub-signal line 32 are made of metal, the resistance of the power signal line 30 is relatively small, which helps to improve the consistency of the voltage levels of each first electrode 21.

[0067] In one embodiment, such as Figure 6 and Figure 7 As shown, the insulating layer located between the first metal conductive layer 91 and the second metal conductive layer 92 is provided with a plurality of through holes 81, and the first sub-signal line 31 and the second sub-signal line 32 are connected through the through holes 81. Specifically, one end of the second sub-signal line 32 is connected to the first sub-signal line 31 through one of the through holes 81, and the other end is connected to the first sub-signal line 31 through one of the through holes 81.

[0068] In one embodiment, such as Figure 7As shown, the orthographic projection of the via 81 on the substrate falls on the edge region of the orthographic projection of the second electrode 22 on the substrate, and is located within the orthographic projection of the light-shielding layer on the substrate. By placing the via 81 in the edge region of the second electrode 22 and covering it with the light-shielding layer, the impact on the aperture ratio of the sub-pixel can be reduced.

[0069] In one embodiment, such as Figure 7 As shown, the orthographic projection of the through-hole 82 in the insulating material layer onto the substrate falls on the edge region of the orthographic projection of the second electrode 22 onto the substrate, and is located within the orthographic projection of the light-shielding layer onto the substrate. By placing the through-hole 82 in the edge region of the second electrode 22 and covering it with the light-shielding layer, the through-hole 82 can be prevented from affecting the display effect of the display substrate.

[0070] In one embodiment, such as Figures 5 to 7 As shown, when forming the array substrate of the display substrate, a first metal conductive layer 91 is first formed; then an insulating layer is formed on the side of the first metal conductive layer 91 facing away from the substrate; subsequently, a second metal conductive layer 92 is formed on the insulating layer, and a second sub-signal line 32 located on the second metal conductive layer 92 is connected to the first sub-signal line 31 located on the first metal conductive layer 91 through a through-hole 81 formed in the insulating layer; then a first electrode 21 is formed, and the first electrode 21 overlaps with the second sub-signal line 32. The array substrate and the color filter substrate are then assembled into a single unit. Figure 2 The display substrate shown.

[0071] If the first electrode is formed before the first metal conductive layer during the formation of the display substrate, to avoid short circuits between the first electrode and the scan signal line Gate located on the first metal conductive layer, the distance from the first electrode to the scan signal line Gate in the column direction must be greater than or equal to 7 μm. In this embodiment, since an insulating layer is provided between the first electrode 21 and the scan signal line Gate located on the first metal conductive layer 91, there is no risk of short circuit between the first electrode 21 and the scan signal line Gate. The distance between the first electrode 21 and the scan signal line Gate in the column direction can be set to be smaller, thereby increasing the area of ​​the opening in the light-shielding layer and effectively improving the aperture ratio of the sub-pixel.

[0072] In one example, the power signal line includes a segment (i.e., the second segment 312) located between two adjacent openings 50 in the row direction X and extending along the column direction Y. Figure 8As shown, the minimum distance between the edge of the orthographic projection of the second segment 312 on the substrate 10 and the edge of the orthographic projection of the adjacent aperture 50 on the substrate 10 is x1, where x1 ranges from 4μm to 8μm. This setting avoids x1 being too small, which could cause the second segment 312 to be exposed and result in reflections due to alignment misalignment when the array substrate and color filter substrate are aligned, and also avoids x1 being too large, which could affect the aperture ratio of the sub-pixels. In some embodiments, x1 can be 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, etc.

[0073] In one embodiment, such as Figure 8 As shown, the orthographic projection of the first electrode 21 on the substrate 10 overlaps with the orthographic projection of the second segment 312 on the substrate 10, and the edge of the orthographic projection of the second segment on the substrate 10 is located inside the edge of the orthographic projection of the first electrode 21 on the substrate 10. The minimum distance between the edge of the orthographic projection of the first electrode 21 on the substrate 10 and the edge of the orthographic projection of the second segment 312 on the substrate 10 is x2, and x2 ranges from 1.5μm to 3μm. This configuration ensures that even if there is a misalignment between the first electrode 21 and the first sub-signal line 31, there is still an overlapping area between the first electrode and the second segment in the film stacking direction, thus facilitating the connection between the first electrode and the first sub-signal line. In some embodiments, x2 can be 1.5μm, 2.0μm, 2.5μm, 3.0μm, etc.

[0074] In one embodiment, such as Figure 9 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the adjacent aperture 50 on the substrate 10 is x3, and the range of x3 is 6μm to 11μm. This setting avoids the problem of light leakage from the side viewing angle caused by the range of x3 being too small, and also avoids the problem of the range of x3 being too large, which would affect the aperture ratio of the sub-pixels. In some embodiments, x3 can be 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, etc.

[0075] In one instance, such as Figure 9 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x4, where x4 ranges from 3μm to 5μm. This configuration reduces the impact on the aperture ratio of the sub-pixels while ensuring that the signal of the first signal line 41 does not interfere with the signal of the first electrode 21. In some embodiments, x4 can be 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc.

[0076] It should be noted that the above numerical range was determined when the liquid crystal molecules in the display substrate are positive liquid crystal molecules.

[0077] In another embodiment, when the liquid crystal molecules are negative liquid crystal molecules, such as Figure 10 As shown, in the column direction, the distance between the edge of the orthogonal projection of the first signal line 41 on the substrate 10 and the edge of the orthogonal projection of the adjacent opening 50 on the substrate 10 is x5, and the range of x5 is 3μm to 5μm. When the liquid crystal molecules are negative liquid crystal molecules, there is no light leakage problem in the row direction, so x5 can be set to be relatively small.

[0078] Furthermore, such as Figure 10 As shown, the edge of the orthogonal projection of the opening 50 of the light-shielding layer 51 onto the substrate 10, extending along the column direction Y, is located outside the orthogonal projection of the corresponding first electrode 21 onto the substrate 10. That is, when the liquid crystal molecules are negative liquid crystal molecules, the area where the opening 50 is enlarged is mostly a non-light-emitting area. However, due to the alignment deviation between the color filter substrate and the array substrate during cell assembly, the light-shielding layer 51 can be prevented from covering the effective light-emitting area of ​​the sub-pixel after cell assembly, which helps to improve the aperture ratio of the sub-pixel.

[0079] In one embodiment, such as Figures 11 to 13 As shown, in forming the array substrate of the display substrate, a first electrode 21 is first formed; then a first metal conductive layer 91 is formed, and a first sub-signal line 31 located on the first metal conductive layer overlaps with the first electrode 21; then an insulating layer is formed on the side of the first metal conductive layer 91 facing away from the substrate; then a second metal conductive layer 92 is formed on the insulating layer, and a second sub-signal line 32 located on the second metal conductive layer 92 is connected to the first sub-signal line 31 located on the first metal conductive layer 91 through a through-hole 81 opened in the insulating layer. The array substrate and the color filter substrate are then assembled into a single unit. Figure 3 The display substrate shown.

[0080] Furthermore, such as Figure 14 As shown, in the column direction, the distance between the edge of the orthographic projection of the first signal line 41 on the substrate 10 and the edge of the orthographic projection of the first electrode 21 on the substrate 10 is x6, where x6 ranges from 5μm to 7μm. This arrangement prevents conductive material from falling into the gap between the first signal line 41 and the first electrode 21 during their formation, thus avoiding a short circuit. In some embodiments, x6 can be 5μm, 5.5μm, 6μm, 6.5μm, 7μm, etc.

[0081] In another embodiment, such as Figure 15 and Figure 16As shown, the power signal line 30 includes a first portion 33 extending along the column direction Y and a second portion 34 extending along the row direction X. The first portion 33 is located in the second metal conductive layer 92; the second portion 34 is located in the first metal conductive layer 91 or is disposed in the same layer as the first electrode 21, and the second portion 34 connects two adjacent first electrodes 21 located in the same row. The second portion 34 is located between the second metal conductive layer 92 and the substrate. The display substrate also includes an insulating layer located between the second portion 34 and the second metal conductive layer 92, and the insulating layer is provided with a via 83, through which the first portion 33 and the second portion 34 are connected. Figure 15 In the embodiment shown, the second part 34 is located on the first metal conductive layer 91, and the first electrode 21 can overlap with the second part 34. Figure 16 In the illustrated embodiment, the second portion 34 is disposed on the same layer as the first electrode 21 and formed simultaneously in the same process step. This arrangement, where the portion of the power signal line 30 extending along the column direction Y is integrally formed on the same layer, helps reduce the resistance of the power signal line 30 and improves the consistency of the voltage level signal of the first electrode 21 compared to a solution where different regions of the power signal line extending along the column direction Y are located on different layers and connected by vias.

[0082] In one embodiment, such as Figures 2 to 4 , Figure 15 and Figure 16 As shown, the display substrate also includes a plurality of spacers 62. The spacers 62 allow the color filter substrate and the array substrate to maintain a fixed distance.

[0083] In one embodiment, such as Figure 2 , Figure 4 , Figure 15 and Figure 16 As shown, the display substrate further includes multiple support portions 61, and the orthographic projection of a spacer 62 on the substrate lies within the orthographic projection of a support portion 61 on the substrate. The support portions 61 and spacers 62 can correspond one-to-one. The support portion 61 can be located on the second metal conductive layer 92 and is connected to the data signal line Data.

[0084] In one embodiment, such as Figure 2 As shown, at least two sides of the orthographic projection of the spacer 62 on the substrate are surrounded by the orthographic projection of the power signal line 30 on the substrate; a plurality of the spacers 62 located between two adjacent columns of sub-pixels are distributed on both sides of the power signal line 30. Figure 2 In the embodiment shown, the spacer 62 is surrounded on both sides by the second sub-signal line 32 and the first segment 311.

[0085] In another embodiment, such as Figure 3 As shown, the spacer 62 is located on the side of the power signal line 30 away from the substrate, and the orthographic projection of the spacer 62 on the substrate overlaps with the orthographic projection of the power signal line 30 on the substrate. Figure 3 In the illustrated embodiment, the orthographic projection of the spacer 62 onto the substrate 10 overlaps with the orthographic projection of the power signal line 30 onto the substrate, and partially overlaps with the orthographic projection of the data signal line Data onto the substrate. This eliminates the need for a support portion to support the spacer 62, helping to reduce the distance between adjacent columns of sub-pixels.

[0086] In yet another embodiment, such as Figure 4 , Figure 15 and Figure 16 As shown, the power signal line 30 includes a portion extending along the column direction. The orthographic projections of the plurality of spacers 62 located between two adjacent columns of sub-pixels on the substrate are located on the same side of the orthographic projections of the adjacent portions extending along the column direction on the substrate. The power signal line adjacent to a spacer refers to the power signal line with the smallest distance from the spacer, where both the power signal line and the spacer are located between the aforementioned two adjacent columns of sub-pixels.

[0087] In one embodiment, such as Figure 2 and Figure 3 As shown, the orthographic projections of two adjacent driving transistors 70 in the column direction Y onto the substrate are located on opposite sides of the orthographic projections of adjacent power signal lines 30 onto the substrate. In another embodiment, as... Figure 4 , Figure 14 and Figure 15 As shown, the orthographic projections of two adjacent driving transistors 70 on the substrate in the column direction Y are located on the same side of the orthographic projections of adjacent power signal lines 30 on the substrate. The power signal line 30 adjacent to the driving transistor 70 refers to the power signal line 30 with the smallest distance from the driving transistor 70 in the row direction X.

[0088] In one embodiment, such as Figure 2 , Figure 3 and Figure 16 As shown, the orthographic projections of two adjacent driving transistors 70 in the column direction Y onto the substrate are located on opposite sides of the orthographic projections of adjacent data signal lines Data onto the substrate. In another embodiment, as... Figure 4 and Figure 14As shown, the orthographic projections of two adjacent driving transistors 70 on the substrate in the column direction Y are located on the same side of the orthographic projection of the adjacent data signal line Data on the substrate. Here, the data signal line Data adjacent to the driving transistor 70 refers to the data signal line Data with the smallest distance from the driving transistor 70 in the row direction X.

[0089] In one embodiment, such as Figure 17 As shown, the display substrate includes a display area 101 and a border area 102, with the sub-pixels located in the display area 101. The display substrate also includes conductive lines 63 located in the border area 102, which are electrically connected to the power signal line 30 and the driver chip, respectively. The display substrate further includes a metal conductive layer, with the conductive lines 63 located within this layer. The conductive lines 63 can transmit the power signal provided by the driver chip to the power signal line 30.

[0090] Furthermore, conductor 63 is located on the first conductive metal layer 91, and the first sub-signal line 31 of the power signal line 30 is also located on the first conductive metal layer 91. Conductor 63 is connected to the first sub-signal line 31. With this configuration, the power signal line 30 does not need to be connected to conductor 63 through a via in the insulating layer, which helps improve the signal uniformity of the first electrode. Moreover, conductor 63 and data signal line Data are located on different metal layers, and the portion of data signal line Data extending to the frame area 102 will not intersect with conductor 63, allowing for more flexible placement of conductor 63.

[0091] This application also provides a display device, which includes the display substrate described in any of the above embodiments.

[0092] In some embodiments, the display device further includes a housing, in which a display substrate is embedded.

[0093] The display device provided in this application embodiment can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0094] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0095] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0096] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that, The display substrate includes: Substrate; A plurality of sub-pixels are located on the substrate, the plurality of sub-pixels are arranged in multiple rows and multiple columns, the size of the sub-pixel in the row direction is a first size, the size of the sub-pixel in the column direction is a second size, and the first size is larger than the second size; Multiple power signal lines extend along the column direction; The power signal line includes alternating first sub-signal lines and second sub-signal lines; the first sub-signal line includes a first segment, a second segment and a third segment connected in sequence, the first segment extends along the row direction, the second segment extends along the column direction, and the third segment is located on opposite sides of the first segment. Multiple first signal lines extend along the row direction; the first signal lines are scan signal lines, and the scan signal lines are located between two adjacent rows of sub-pixels; the orthographic projection of the second sub-signal line on the substrate overlaps with the orthographic projection of one of the scan signal lines on the substrate; The substrate comprises a first conductive metal layer, an insulating layer on the side of the first conductive metal layer away from the substrate, and a second conductive metal layer on the side of the insulating layer away from the substrate; a first sub-signal line is located on the first conductive metal layer; a second sub-signal line is electrically connected to two adjacent first sub-signal lines through two first vias in the insulating layer, and in a direction perpendicular to the substrate, the end of the first segment overlaps with one of the first vias; the orthographic projections of the two vias corresponding to the same second sub-signal line on the substrate are located on opposite sides of the orthographic projection of a scan signal line on the substrate along the column direction; Multiple second signal lines extend along the column direction, and the second signal lines are data signal lines; Multiple support portions are provided to support spacers; the support portions are connected to the data signal lines and are all located in the second metal conductive layer; in the row direction, the width of the support portion is greater than the width of the data signal line; the third section is disposed adjacent to the support portion; among the three adjacent second sub-signal lines of the same power signal line, two non-adjacent second sub-signal lines are located on one side of the data signal line, and the other second sub-signal line is located on the other side of the data signal line, and the orthographic projections of the three adjacent second sub-signal lines on the substrate overlap with the orthographic projections of the three adjacent scan signal lines on the substrate. Multiple pixel driving circuits, each including multiple driving transistors, wherein two adjacent driving transistors in the column direction are disposed on opposite sides of the data signal line.

2. The display substrate according to claim 1, characterized in that, The sub-pixel includes a second electrode. In two adjacent second electrodes in the row direction, in the row direction, the distance from one second electrode to the portion of the power signal line extending along the column direction is a first distance, and the distance from the other second electrode to the portion extending along the column direction is a second distance. The first distance is different from the second distance.

3. The display substrate according to claim 1, characterized in that, The dimension of the first sub-signal line in the column direction is greater than the dimension of the second sub-signal line in the column direction.

4. The display substrate according to claim 3, characterized in that, The sub-pixel includes a second electrode, and the second sub-signal line extends along the column direction; the two second electrodes that are adjacent in the column direction and located on both sides of the center of the second sub-signal line are equidistant from the center of the second sub-signal line.

5. The display substrate according to claim 3, characterized in that, The two opposite ends of the second sub-signal line are respectively connected to the first sub-signal line, and the orthographic projections of the two opposite ends of the second sub-signal line on the substrate are located on opposite sides of the orthographic projections of the first signal line on the substrate.

6. The display substrate according to any one of claims 3 to 5, characterized in that, The end of the first segment away from the second segment and the end of the third segment away from the second segment are respectively connected to the second sub-signal line.

7. The display substrate according to claim 6, characterized in that, The sub-pixel includes a second electrode, wherein in two adjacent second electrodes in the row direction, the distance from one second electrode to the second segment is different from the distance from the other second electrode to the second segment in the row direction.

8. The display substrate according to claim 6, characterized in that, The sub-pixel includes a second electrode, wherein in two adjacent second electrodes in the column direction, in the row direction, the distance from one second electrode to the second segment is different from the distance from the other second electrode to the second segment.

9. The display substrate according to claim 1, characterized in that, The orthographic projection of the second signal line and the power signal line on the substrate is located between the orthographic projections of two adjacent columns of the sub-pixels on the substrate.

10. The display substrate according to claim 1, characterized in that, The display substrate also includes multiple spacers; The spacer is surrounded on at least two sides by the orthogonal projection of the power signal line on the substrate.

11. The display substrate according to claim 1, characterized in that, The display substrate includes a display area and a border area. The sub-pixels are located in the display area. The display substrate also includes wires located in the border area. The wires are electrically connected to the power signal line and the driver chip, respectively. The display substrate also includes a metal conductive layer. The wires are located in the metal conductive layer.

12. The display substrate according to claim 1, characterized in that, The sub-pixel includes a second electrode, and the display substrate further includes a light-shielding layer located on the side of the sub-pixel away from the substrate. The light-shielding layer has a plurality of openings, and the orthographic projection of one of the openings on the substrate falls within the orthographic projection of one of the second electrodes on the substrate. The power signal line includes a segment located between two adjacent openings in the row direction and extending along the column direction, wherein the minimum distance between the edge of the orthographic projection of the segment extending along the column direction on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate is in the range of 4μm to 8μm. And / or, The sub-pixel includes a first electrode located on the side of the first signal line away from the substrate. The display substrate also includes an insulating layer between the first signal line and the first electrode. In the column direction, the distance between the edge of the orthogonal projection of the first signal line on the substrate and the edge of the orthogonal projection of the first electrode on the substrate is in the range of 3μm to 5μm. And / or, The orthographic projection of the first signal line on the substrate falls within the orthographic projection of the light-shielding layer on the substrate; the distance between the orthographic projection of the first signal line on the substrate and the edge of the orthographic projection of the adjacent opening on the substrate extending along the row direction is in the range of 6μm~11μm.

13. The display substrate according to claim 1, wherein the display substrate further comprises a light-shielding layer located on the side of the sub-pixel opposite to the substrate, the light-shielding layer having a plurality of openings; the spacing between two adjacent openings in a direction passing through the support portion and parallel to the extension direction of the scan signal line is a first spacing, and the spacing between two adjacent openings in a direction passing through the data signal line and parallel to the extension direction of the scan signal line is a second spacing, wherein the first spacing is greater than the second spacing.

14. The display substrate according to claim 13, wherein the edge of the opening includes a zigzag line in the extending direction of the data signal line.

15. The display substrate according to claim 1, 13 or 14, wherein the driving transistor includes a gate electrode, a first electrode and a second electrode, and further includes a second electrode connected to the first electrode through a second via; the second electrode includes a center line parallel to the extension direction of the scan signal line, the center line being equidistant from two opposite edges of the second electrode along the extension direction of the data signal line; the second via is closer to the center line than one of the edges.

16. The display substrate according to claim 15, wherein the sub-pixel includes a second electrode, the second electrode includes a plurality of electrode strips arranged along the extension direction of the scan signal line, and the plurality of electrode strips of a sub-pixel include electrode strips with two different extension directions, and both extension directions intersect with the extension direction of the scan signal line.

17. The display substrate according to claim 1, further comprising a first electrode, the first electrode being connected to the power signal line.

18. A display device, characterized in that, The display device includes the display substrate according to any one of claims 1 to 17.

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