Detection circuit, detection chip, system on chip and electronic device

Abstract

The present disclosure relates to a detection circuit, a detection chip, a system on chip and an electronic device. The detection circuit comprises a periodic signal generation circuit, the periodic signal generation circuit receives a reference clock signal, and is configured to generate a periodic signal and a trigger signal according to the reference clock signal; a synchronous signal generation circuit, the synchronous signal generation circuit is electrically connected with the periodic signal generation circuit, receives the reference clock signal and a to-be-detected clock signal, and is configured to perform synchronous processing on the periodic signal according to the reference clock signal and the to-be-detected clock signal to generate a first synchronous signal; and a clock interruption judgment circuit, the clock interruption judgment circuit is electrically connected with the periodic signal generation circuit and the synchronous signal generation circuit, and is configured to determine whether the to-be-detected clock signal is abnormally interrupted according to the periodic signal and the first synchronous signal in response to receiving the trigger signal. The detection circuit of the present disclosure realizes flexible configuration of detection time, and avoids the problem of difficult timing convergence of the reference clock signal.

Description

Technical Field

[0001] This disclosure relates to the field of detection technology, and in particular to a detection circuit, a detection chip, a system-on-a-chip, and an electronic device. Background Technology

[0002] Clock interruptions can cause timing errors in chips, leading to data errors, logic anomalies, and incorrect operational results. In severe cases, it can even cause chip malfunction. Therefore, detecting clock interruptions is crucial for ensuring normal chip operation. Currently, circuits used for clock interruption detection have inflexible detection time configurations and suffer from high reference clock signal frequencies, resulting in convergence difficulties. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a detection circuit, a detection chip, a system-on-a-chip, and an electronic device.

[0004] According to a first aspect of this disclosure, a detection circuit is provided, the detection circuit comprising: A periodic signal generation circuit receives a reference clock signal and is used to generate a periodic signal and a trigger signal based on the reference clock signal. A synchronization signal generation circuit is electrically connected to the periodic signal generation circuit and receives the reference clock signal and the clock signal to be detected. The synchronization signal generation circuit is used to perform synchronization processing on the periodic signal according to the reference clock signal and the clock signal to be detected to generate a first synchronization signal. A clock interruption determination circuit is electrically connected to both the periodic signal generation circuit and the synchronization signal generation circuit. The clock interruption determination circuit is used to determine whether the clock signal to be detected is abnormally interrupted based on the periodic signal and the first synchronization signal in response to receiving the trigger signal.

[0005] In this embodiment, the trigger signal used to trigger detection is generated based on a reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, so the frequency of the reference clock signal can be set according to requirements, realizing flexible configuration of the detection time and avoiding the problem of difficulty in timing convergence of the reference clock signal.

[0006] In some embodiments of this disclosure, the periodic signal generation circuit includes: A counting unit receives the reference clock signal and is electrically connected to both the synchronization signal generation circuit and the clock interrupt determination circuit. The counting unit is used for: In response to the fact that the count value of the counting unit has not reached the counting threshold, the count value is increased by a preset value every time one cycle of the reference clock signal is elapsed; In response to the count value reaching the count threshold and passing one cycle of the reference clock signal, the count value is cleared to zero, the level of the cycle signal is flipped, and the trigger signal is generated.

[0007] In this embodiment, the duration of one cycle of the detection operation is the product of the duration of one cycle of the reference clock signal and the ratio of the counting threshold to a preset value plus one. The frequency of the reference clock signal and the counting threshold are configurable, thus the cycle of the detection operation is configurable, meeting different detection time requirements and improving detection flexibility.

[0008] In some embodiments of this disclosure, the ratio of the counting threshold to the preset value plus one is greater than or equal to the ratio of the maximum delay of the first synchronization signal relative to the periodic signal to the duration of one period of the reference clock signal when the clock signal to be detected is not interrupted.

[0009] In this embodiment, by setting the ratio of the counting threshold to a preset value plus one, which is greater than or equal to the ratio of the maximum delay of the first synchronization signal relative to the periodic signal to the duration of one period of the reference clock signal when the clock signal to be detected is not interrupted, abnormal detection function of the detection circuit can be avoided.

[0010] In some embodiments of this disclosure, in response to the count value not reaching the count threshold, the count value is incremented by the preset value at each rising edge or each falling edge of the reference clock signal.

[0011] In this embodiment, the count value change is triggered at the same type of edge of the reference clock signal, thus avoiding the influence of the duty cycle of the reference clock signal.

[0012] In some embodiments of this disclosure, the synchronization signal generation circuit includes: A first synchronization unit is electrically connected to the periodic signal generation circuit and receives the clock signal to be detected. The first synchronization unit is used to perform synchronization processing on the periodic signal according to the clock signal to be detected to generate a second synchronization signal. The second synchronization unit is electrically connected to the first synchronization unit and receives the reference clock signal. The second synchronization unit is used to perform synchronization processing on the second synchronization signal according to the reference clock signal to generate the first synchronization signal.

[0013] In this embodiment, after two synchronization processes, whether the clock signal to be detected is interrupted can be reflected in the first synchronization signal. At the same time, the first synchronization signal, the periodic signal and the trigger signal are all in the same clock domain, which can be used to determine whether the clock is abnormally interrupted.

[0014] In some embodiments of this disclosure, the first synchronization unit samples the periodic signal at a first preset number of rising or falling edges of the clock signal to be detected to generate the second synchronization signal. Wherein, the first preset quantity is an integer greater than or equal to 2.

[0015] In this embodiment, the periodic signal is sampled at multiple edges of the same type of clock signal to be detected for synchronization processing, thus avoiding the influence of the duty cycle of the clock signal to be detected.

[0016] In some embodiments of this disclosure, the second synchronization unit samples the second synchronization signal at a second preset number of rising or falling edges adjacent to the reference clock signal to generate the first synchronization signal; Wherein, the second preset quantity is an integer greater than or equal to 2.

[0017] In this embodiment, the second synchronization signal is sampled at multiple edges of the same type of the reference clock signal for synchronization processing, thus avoiding the influence of the duty cycle of the reference clock signal.

[0018] In some embodiments of this disclosure, the clock interrupt determination circuit includes: The XOR unit is electrically connected to both the periodic signal generation circuit and the synchronization signal generation circuit. The XOR unit is used to perform an XOR operation on the periodic signal and the first synchronization signal to generate an XOR signal.

[0019] In this embodiment, the level of the XOR signal can be used to represent whether the level of the periodic signal at the same time is the same as the level of the first synchronization signal, so as to determine whether the clock signal to be detected is abnormally interrupted based on whether the periodic signal is synchronized to the first synchronization signal at the target time.

[0020] In some embodiments of this disclosure, the clock interrupt determination circuit further includes: The judgment unit is electrically connected to both the XOR unit and the periodic signal generation circuit. The judgment unit is used to determine whether the clock signal to be detected is abnormally interrupted based on the XOR signal in response to receiving the trigger signal.

[0021] In this embodiment, the judgment unit can determine whether the clock signal to be detected is abnormally interrupted based on the XOR signal when it is triggered. The judgment process is simple and highly stable.

[0022] In some embodiments of this disclosure, the level of the XOR signal includes a first level and a second level, wherein the second level is lower than the first level; The determination unit is used to determine that the clock signal to be detected is abnormally interrupted when the XOR signal is at the first level at the moment the trigger signal is received.

[0023] In this embodiment, the judgment unit can determine whether the clock signal to be detected is abnormally interrupted based on the level of the XOR signal when it is triggered. The judgment process is simple and highly stable.

[0024] In some embodiments of this disclosure, the abnormal interruption of the clock signal to be detected is defined as the duration of the interruption of the clock signal to be detected being greater than a preset duration threshold. The preset duration threshold is half the duration of one cycle of the periodic signal, minus the difference between the minimum delay duration of the first synchronization signal and the periodic signal when the clock signal to be detected is not interrupted.

[0025] In this embodiment, the preset duration threshold can be adjusted by adjusting the frequency of the periodic signal, thereby meeting the detection requirements of different clock abnormal interruptions.

[0026] In some embodiments of this disclosure, the clock interrupt determination circuit is further configured to output a clock abnormality signal in response to an abnormal interruption of the clock signal to be detected.

[0027] In this embodiment, the output clock anomaly signal can be used to determine the cause of the anomaly, improving the accuracy of diagnosis and maintenance.

[0028] According to a second aspect of this disclosure, a detection chip is provided, the detection chip including any of the detection circuits of the first aspect of this disclosure.

[0029] According to a third aspect of this disclosure, a system-on-a-chip (SoC) is provided, the SoC including the detection chip of the second aspect of this disclosure.

[0030] According to a fourth aspect of this disclosure, an electronic device is provided, the electronic device comprising a detection chip of the second aspect of this disclosure or a system-on-a-chip of the third aspect of this disclosure.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0033] Figure 1 This is a schematic diagram of the detection circuit according to an exemplary embodiment of the present disclosure; Figure 2 This is a schematic diagram of the detection circuit according to another exemplary embodiment of the present disclosure; Figure 3 This is a timing diagram illustrating the operation of the detection circuit when the clock signal to be detected is not interrupted, according to an exemplary embodiment of the present disclosure; Figure 4 This is a timing diagram illustrating the operation of the detection circuit in the event of an abnormal interruption of the clock signal to be detected, according to an exemplary embodiment of the present disclosure. Figure 5 This is a schematic diagram of the detection circuit according to another exemplary embodiment of the present disclosure; Figure 6 This is a schematic diagram of the detection circuit according to another exemplary embodiment of the present disclosure; Figure 7 This is a schematic diagram of the detection circuit according to another exemplary embodiment of the present disclosure; Figure 8 This is a schematic diagram of the detection circuit according to another exemplary embodiment of the present disclosure; Figure 9 This is a block diagram of an electronic device illustrated according to an exemplary embodiment of the present disclosure.

[0034] In the picture: 10 - Periodic signal generation circuit; 11 - Counting unit; 20 - Synchronization signal generation circuit; 21 - First synchronization unit; 22 - Second synchronization unit; 30 - Clock interrupt judgment circuit; 31 - XOR unit; 32 - Judgment unit; T1 - First time step; T2 - Second time step; T3 - Third time step; T4 - Fourth time step; T5 - Fifth time step; T6 - Sixth time step; T7 - ​​Seventh time step; T8 - Eighth time step; T9 - Ninth time step; T10 - Tenth time step; CLK_REF - Reference clock signal; CLK _MON - Clock signal to be detected; S_PER - Periodic signal; S_EN - Trigger signal; S_SYNC1 - First synchronization signal; S_SYNC2 - Second synchronization signal; S_XOR - XOR signal; VAL_CNT - Count value; 900 - Electronic device; 902 - Processing component; 904 - Memory; 906 - Power supply component; 908 - Multimedia component; 910 - Audio component; 912 - Input / output interface; 914 - Sensor component; 916 - Communication component; 920 - Processor. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims. It should also be understood that the term “and / or” as used herein refers to any or all possible combinations including one or more of the associated listed items.

[0036] Clock interruptions can cause timing errors in chips, leading to data errors, logic anomalies, and incorrect execution results. In severe cases, it can even cause chip malfunction. Therefore, detecting clock interruptions is crucial for ensuring normal chip operation. Currently, the detection time of circuits used for clock interruption detection is constrained by fixed capacitor discharge times or the fixed period of the clock signal being detected, limiting its flexibility and failing to meet the need for timely alarms for interruptions. Furthermore, the reference clock signal used by the timer in the detection circuit needs to be several times higher than the frequency of the clock signal being detected, resulting in a high reference clock signal frequency and difficulties in timing convergence.

[0037] Based on this, this disclosure provides a detection circuit. In the detection circuit, a periodic signal generation circuit generates a periodic signal and a trigger signal based on a reference clock signal. A synchronization signal generation circuit performs a synchronization operation on the periodic signal based on the reference clock signal and the clock signal to be detected to generate a first synchronization signal. A clock interruption judgment circuit responds to the received trigger signal and determines whether the clock signal to be detected has been abnormally interrupted based on the periodic signal and the first synchronization signal. The trigger signal used for trigger detection is generated based on the reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, thus allowing the frequency of the reference clock signal to be set according to requirements. This achieves flexible configuration of the detection time and avoids the problem of difficulty in timing convergence of the reference clock signal.

[0038] This disclosure provides a detection circuit, such as Figure 1As shown, the detection circuit includes a periodic signal generation circuit 10, a synchronization signal generation circuit 20, and a clock interruption determination circuit 30. The periodic signal generation circuit 10 receives a reference clock signal CLK_REF and generates a periodic signal S_PER and a trigger signal S_EN based on the reference clock signal CLK_REF. The synchronization signal generation circuit 20 is electrically connected to the periodic signal generation circuit 10 and receives the reference clock signal CLK_REF and the clock signal to be detected CLK_MON. The synchronization signal generation circuit 20 performs synchronization processing on the periodic signal S_PER based on the reference clock signal CLK_REF and the clock signal to be detected CLK_MON to generate a first synchronization signal S_SYNC1. The clock interruption determination circuit 30 is electrically connected to both the periodic signal generation circuit 10 and the synchronization signal generation circuit 20. In response to receiving the trigger signal S_EN, the clock interruption determination circuit 30 determines whether the clock signal to be detected CLK_MON has been abnormally interrupted based on the periodic signal S_PER and the first synchronization signal S_SYNC1.

[0039] For example, the periodic signal generation circuit 10 can count the periods of the reference clock signal CLK_REF. Before the count value reaches the counting threshold, the count value is increased by a preset value for each cycle of the reference clock signal. After the count value reaches the counting threshold and one cycle of the reference clock signal CLK_REF has elapsed, the level of the periodic signal S_PER is toggled, a trigger signal S_EN is generated, the count value is cleared to zero, and the next round of counting begins.

[0040] For example, the synchronization signal generation circuit 20 can first perform synchronization processing on the periodic signal S_PER according to the clock signal to be detected CLK_MON to generate a second synchronization signal S_SYNC2, and then perform synchronization processing on the second synchronization signal S_SYNC2 according to the reference clock signal CLK_REF to generate a first synchronization signal S_SYNC1. For instance, the synchronization signal generation circuit 20 samples the periodic signal S_PER at a first preset number of rising or falling edges adjacent to the clock signal to be detected CLK_MON to generate the second synchronization signal S_SYNC2. The first preset number is an integer greater than or equal to 2. The synchronization signal generation circuit 20 samples the second synchronization signal S_SYNC2 at a second preset number of rising or falling edges adjacent to the reference clock signal CLK_REF to generate the first synchronization signal S_SYNC1. The second preset number is an integer greater than or equal to 2. Understandably, the periodic signal S_PER is synchronized based on the clock signal CLK_MON to be detected. If the clock signal CLK_MON is abnormally interrupted, this abnormal interruption can be reflected in the generated second synchronization signal S_SYNC2, and further in the first synchronization signal S_SYNC1. During the abnormal interruption of the clock signal CLK_MON, the synchronization processing of the periodic signal S_PER is also interrupted, and the level of the second synchronization signal S_SYNC2 cannot change, but remains at a certain level. Consequently, the level of the first synchronization signal S_SYNC1 will also follow the level of the second synchronization signal S_SYNC2 and remain unchanged.

[0041] For example, the clock interrupt determination circuit 30 can perform an XOR operation on the periodic signal S_PER and the first synchronization signal S_SYNC1 to generate an XOR signal S_XOR. The level of the XOR signal S_XOR includes a first level and a second level, with the second level being lower than the first level. When the trigger signal S_EN is received, if the level of the XOR signal S_XOR is the first level, the clock interrupt determination circuit 30 can determine that the clock signal CLK_MON to be detected has been abnormally interrupted, causing the most recent toggle of the level of the periodic signal S_PER to fail to be synchronized to the first synchronization signal S_SYNC1 at the time the trigger signal S_EN is generated.

[0042] For example, to ensure the detection circuit functions correctly, the ratio of the count threshold to a preset value plus one can be set to be greater than or equal to the ratio of the maximum delay of the first synchronization signal S_SYNC1 relative to the periodic signal S_PER to the duration of one period of the reference clock signal CLK_REF, assuming the clock signal CLK_MON is not interrupted. This ensures that, assuming the clock signal CLK_MON is not interrupted, the most recent toggle of the periodic signal S_PER's level can be synchronized to the first synchronization signal S_SYNC1 at the time the trigger signal S_EN is generated.

[0043] In this embodiment, the trigger signal used to trigger detection is generated based on a reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, so the frequency of the reference clock signal can be set according to requirements, realizing flexible configuration of the detection time and avoiding the problem of difficulty in timing convergence of the reference clock signal.

[0044] In one embodiment, such as Figure 2 As shown, the periodic signal generation circuit 10 includes a counting unit 11. The counting unit 11 receives a reference clock signal CLK_REF and is electrically connected to both the synchronization signal generation circuit 20 and the clock interrupt judgment circuit 30. In response to the counting value of the counting unit 11 not reaching a counting threshold, the counting unit 11 increments the counting value by a preset value every cycle of the reference clock signal CLK_REF. In response to the counting value reaching the counting threshold and after one cycle of the reference clock signal CLK_REF, the counting value is cleared to zero, the level of the periodic signal S_PER is toggled, and a trigger signal S_EN is generated.

[0045] Figure 3 This is a timing diagram illustrating the operation of the detection circuit when the clock signal CLK_MON to be detected is not interrupted, according to one embodiment. Figure 4 This is a timing diagram illustrating the operation of the detection circuit in the event of an abnormal interruption of the clock signal CLK_MON to be detected, according to one embodiment.

[0046] For example, the count value can be Figure 3 and Figure 4 The counting value VAL_CNT has a counting threshold of 9 and a preset value of 1. Counting unit 11 increments the count value VAL_CNT by 1 every cycle of the reference clock signal CLK_REF if the count value VAL_CNT has not reached 9. If the count value VAL_CNT reaches 9 and one cycle of the reference clock signal CLK_REF has elapsed, the count value VAL_CNT is cleared to zero, the level of the cycle signal S_PER is toggled, and a trigger signal S_EN is generated. After the count value VAL_CNT is cleared to zero, the next round of counting begins. It is understandable that... Figure 3 and Figure 4 The counting threshold and preset value are just examples; the counting threshold and preset value can also be other values.

[0047] In this embodiment, the duration of one cycle of the detection operation is the product of the duration of one cycle of the reference clock signal and the ratio of the counting threshold to a preset value plus one. The frequency of the reference clock signal and the counting threshold are configurable, thus the cycle of the detection operation is configurable, meeting different detection time requirements and improving detection flexibility.

[0048] In one embodiment, the ratio of the counting threshold to the preset value plus one is greater than or equal to the ratio of the maximum delay of the first synchronization signal S_SYNC1 relative to the periodic signal S_PER to the duration of one cycle of the reference clock signal CLK_REF, provided that the clock signal to be detected CLK_MON is not interrupted.

[0049] If the ratio of the counting threshold to the preset value plus one is greater than or equal to the ratio of the maximum delay of the first synchronization signal S_SYNC1 relative to the periodic signal S_PER to the duration of one period of the reference clock signal CLK_REF, when the clock signal CLK_MON to be detected is not interrupted, the most recent toggle of the level of the periodic signal S_PER has been synchronized to the first synchronization signal S_SYNC1 when the trigger signal S_EN is generated, in the case that the clock signal CLK_MON to be detected is not interrupted. This avoids the detection circuit from mistakenly determining that the clock signal CLK_MON to be detected is abnormally interrupted.

[0050] Reference Figure 3 To explain, Figure 3 In this circuit, the synchronization signal generation circuit 20 can sample the periodic signal S_PER at two adjacent rising edges of the clock signal CLK_MON to be detected, generating a second synchronization signal S_SYNC2. The level of the periodic signal S_PER flips at the first time T1 and is synchronized to the second synchronization signal S_SYNC2 at the second time T2. The delay of the second synchronization signal S_SYNC2 relative to the periodic signal S_PER is the interval between the second time T2 and the first time T1. It can be understood that if the level of the periodic signal S_PER flips at the rising edge of the clock signal CLK_MON to be detected, it will cause metastability. Therefore, it is necessary to sample the periodic signal S_PER at two rising edges after that rising edge to generate the second synchronization signal S_SYNC2. In this case, the delay of the second synchronization signal S_SYNC2 relative to the periodic signal S_PER is the longest, which is the duration of two periods of the clock signal CLK_MON to be detected.

[0051] Figure 3In this circuit, the synchronization signal generation circuit 20 can sample the second synchronization signal S_SYNC2 at two adjacent rising edges of the reference clock signal CLK_REF to generate the first synchronization signal S_SYNC1. The level of the second synchronization signal S_SYNC2 flips at the second time T2 and is synchronized to the first synchronization signal S_SYNC1 at the third time T3. The delay of the first synchronization signal S_SYNC1 relative to the second synchronization signal S_SYNC2 is the interval between the third time T3 and the second time T2. It can be understood that if the level of the second synchronization signal S_SYNC2 flips at the rising edge of the reference clock signal CLK_REF, it will cause metastability. Therefore, it is necessary to sample the second synchronization signal S_SYNC2 at two rising edges after that rising edge to generate the first synchronization signal S_SYNC1. In this case, the delay of the first synchronization signal S_SYNC1 relative to the second synchronization signal S_SYNC2 is the longest, which is the duration of two cycles of the reference clock signal CLK_REF.

[0052] Based on the above, Figure 3 In this context, the maximum delay of the first synchronization signal S_SYNC1 relative to the periodic signal S_PER is the sum of the duration of two periods of the clock signal CLK_MON to be detected and the duration of two periods of the reference clock signal CLK_REF. If the ratio of the preset threshold to the preset value plus one is less than the ratio of the sum of the duration of two periods of the clock signal CLK_MON to the duration of two periods of the reference clock signal CLK_REF, and the duration of one period of the reference clock signal CLK_REF, even if... Figure 3 If the clock signal CLK_MON to be detected is not interrupted, the level of the periodic signal S_PER, even if it flips at the first time T1, cannot be synchronized to the first synchronization signal S_SYNC1 before the fourth time T4, when the level of the periodic signal S_PER will flip once. The clock interrupt detection circuit 30, responding to the received trigger signal S_EN at the fourth time T4, and based on the XOR signal S_XOR being at the first level, will mistakenly determine that the clock signal CLK_MON to be detected is abnormally interrupted.

[0053] In this embodiment, by setting the ratio of the counting threshold to a preset value plus one, which is greater than or equal to the ratio of the maximum delay of the first synchronization signal relative to the periodic signal to the duration of one period of the reference clock signal when the clock signal to be detected is not interrupted, abnormal detection function of the detection circuit can be avoided.

[0054] In one embodiment, in response to the count value not reaching the count threshold, the count value is increased by a preset value on each rising edge or each falling edge of the reference clock signal CLK_REF.

[0055] For example, refer to Figure 3 and Figure 4 In response to the count value VAL_CNT not reaching the count threshold, the count value VAL_CNT is incremented by a preset value on each rising edge of the reference clock signal CLK_REF.

[0056] For example, in response to the count value not reaching the count threshold, the count value is incremented by a preset value on each falling edge of the reference clock signal CLK_REF.

[0057] In this embodiment, the count value change is triggered at the same type of edge of the reference clock signal, thus avoiding the influence of the duty cycle of the reference clock signal.

[0058] In one embodiment, such as Figure 5 As shown, the synchronization signal generation circuit 20 includes a first synchronization unit 21 and a second synchronization unit 22. The first synchronization unit 21 is electrically connected to the periodic signal generation circuit 10 and receives a clock signal CLK_MON to be detected. The first synchronization unit 21 is used to synchronize the periodic signal S_PER according to the clock signal CLK_MON to generate a second synchronization signal S_SYNC2. The second synchronization unit 22 is electrically connected to the first synchronization unit 21 and receives a reference clock signal CLK_REF. The second synchronization unit 22 is used to synchronize the second synchronization signal S_SYNC2 according to the reference clock signal CLK_REF to generate a first synchronization signal S_SYNC1.

[0059] Understandably, the periodic signal S_PER is synchronized based on the clock signal CLK_MON to be detected. If the clock signal CLK_MON is abnormally interrupted, this abnormal interruption can be reflected in the generated second synchronization signal S_SYNC2, and further in the first synchronization signal S_SYNC1. During the abnormal interruption of the clock signal CLK_MON, the synchronization processing of the periodic signal S_PER is also interrupted, and the level of the second synchronization signal S_SYNC2 cannot change, but remains at a certain level. Consequently, the level of the first synchronization signal S_SYNC1 will also follow the level of the second synchronization signal S_SYNC2 and remain unchanged. However, by synchronizing the second synchronization signal S_SYNC2 with the reference clock signal CLK_REF to generate the first synchronization signal S_SYNC1, the first synchronization signal S_SYNC1 can be placed in the same clock domain (i.e., the clock domain of the reference clock signal CLK_REF) as the periodic signal S_PER and the trigger signal S_EN, thus enabling the determination of whether the clock is abnormally interrupted.

[0060] In this embodiment, after two synchronization processes, whether the clock signal to be detected is interrupted can be reflected in the first synchronization signal. At the same time, the first synchronization signal, the periodic signal and the trigger signal are all in the same clock domain, which can be used to determine whether the clock is abnormally interrupted.

[0061] In one embodiment, at a first preset number of rising or falling edges adjacent to the clock signal CLK_MON to be detected, the first synchronization unit 21 samples the periodic signal S_PER to generate a second synchronization signal S_SYNC2. The first preset number is an integer greater than or equal to 2.

[0062] For example, such as Figure 3 As shown, the clock signal CLK_MON to be detected was not interrupted. The first synchronization unit 21 can sample the periodic signal S_PER on two adjacent rising edges of the clock signal CLK_MON to generate the second synchronization signal S_SYNC2. The level of the periodic signal S_PER is synchronized to the second synchronization signal S_SYNC2 at the second time T2 after the flipping of the first time T1.

[0063] For example, such as Figure 4 As shown, the clock signal CLK_MON to be detected is abnormally interrupted. The first synchronization unit 21 can sample the periodic signal S_PER on two consecutive rising edges before and after the abnormal interruption of the clock signal CLK_MON to be detected, in order to generate the second synchronization signal S_SYNC2. The level of the periodic signal S_PER is toggled at the fifth time T5 and synchronized to the second synchronization signal S_SYNC2 at the sixth time T6.

[0064] Understandable Figure 3 and Figure 4 For example only, the first preset number can also be any other integer greater than 2. The first synchronization unit 21 can also sample the periodic signal S_PER on the falling edge of the clock signal CLK_MON adjacent to the first preset number of falling edges to generate the second synchronization signal S_SYNC2.

[0065] In this embodiment, the periodic signal is sampled at multiple edges of the same type of clock signal to be detected for synchronization processing, thus avoiding the influence of the duty cycle of the clock signal to be detected.

[0066] In one embodiment, at a second preset number of rising or falling edges adjacent to the reference clock signal CLK_REF, the second synchronization unit 22 samples the second synchronization signal S_SYNC2 to generate the first synchronization signal S_SYNC1. The second preset number is an integer greater than or equal to 2.

[0067] For example, such as Figure 3and Figure 4 As shown, the second synchronization unit 22 can sample the second synchronization signal S_SYNC2 on two adjacent rising edges of the reference clock signal CLK_REF to generate the first synchronization signal S_SYNC1. Figure 3 In the process, the level of the second synchronization signal S_SYNC2 is switched at the second time T2 and synchronized to the first synchronization signal S_SYNC1 at the third time T3. Figure 4 In the process, the level of the second synchronization signal S_SYNC2 flips at the sixth time T6 and is synchronized to the first synchronization signal S_SYNC1 at the seventh time T7.

[0068] Understandable Figure 3 and Figure 4 For example only, the second preset number can also be any other integer greater than 2. The second synchronization unit 22 can also sample the second synchronization signal S_SYNC2 on the falling edge of the reference clock signal CLK_REF adjacent to the second preset number to generate the first synchronization signal S_SYNC1.

[0069] In this embodiment, the second synchronization signal is sampled at multiple edges of the same type of the reference clock signal for synchronization processing, thus avoiding the influence of the duty cycle of the reference clock signal.

[0070] In one embodiment, such as Figure 6 As shown, the clock interrupt determination circuit 30 includes an XOR unit 31. The XOR unit 31 is electrically connected to both the periodic signal generation circuit 10 and the synchronization signal generation circuit 20. The XOR unit 31 is used to perform an XOR operation on the periodic signal S_PER and the first synchronization signal S_SYNC1 to generate an XOR signal S_XOR.

[0071] Because the first synchronization signal S_SYNC1 is obtained by synchronizing the periodic signal S_PER, the levels of both the first synchronization signal S_SYNC1 and the periodic signal S_PER can include both third and fourth levels. If, at the same time, both the level of the periodic signal S_PER and the first synchronization signal S_SYNC1 are at the third level or both are at the fourth level, the level of the XOR signal S_XOR can be the second level. If, at the same time, one of the level of the periodic signal S_PER and the first synchronization signal S_SYNC1 is at the third level and the other is at the fourth level, the level of the XOR signal S_XOR can be the first level. The second level is lower than the first level.

[0072] In this embodiment, the level of the XOR signal can be used to represent whether the level of the periodic signal at the same time is the same as the level of the first synchronization signal, so as to determine whether the clock signal to be detected is abnormally interrupted based on whether the periodic signal is synchronized to the first synchronization signal at the target time.

[0073] In one embodiment, such as Figure 7 As shown, the clock interrupt determination circuit 30 also includes a determination unit 32. The determination unit 32 is electrically connected to the XOR unit 31 and the periodic signal generation circuit 10. The determination unit 32 is used to determine whether the clock signal CLK_MON to be detected is abnormally interrupted based on the XOR signal S_XOR in response to receiving the trigger signal S_EN.

[0074] For example, in such Figure 3 At the fourth moment T4 shown, the judgment unit 32 can receive the trigger signal S_EN. At this time, the judgment unit 32 can determine that the clock signal CLK_MON to be detected has not been abnormally interrupted based on the level of the XOR signal S_XOR being the second level.

[0075] For example, in such Figure 4 At the eighth moment T8 shown, the judgment unit 32 can receive the trigger signal S_EN. At this time, the judgment unit 32 can determine that the clock signal CLK_MON to be detected is abnormally interrupted based on the level of the XOR signal S_XOR being the first level.

[0076] In this embodiment, the judgment unit can determine whether the clock signal to be detected is abnormally interrupted based on the XOR signal when it is triggered. The judgment process is simple and highly stable.

[0077] In one embodiment, the level of the XOR signal S_XOR includes a first level and a second level, wherein the second level is lower than the first level. The determination unit 32 is configured to determine that the clock signal CLK_MON to be detected is abnormally interrupted when the level of the XOR signal S_XOR is the first level at the moment the trigger signal S_EN is received.

[0078] For example, such as Figure 4 As shown, because the clock signal CLK_MON to be detected is abnormally interrupted between the ninth time T9 and the tenth time T10, at the eighth time T8, the level of the periodic signal S_PER has not yet been synchronized to the first synchronization signal S_SYNC1 after the flip of the fifth time T5. The level of the periodic signal S_PER is different from the level of the first synchronization signal S_SYNC1, and the XOR signal S_XOR is at the first level. The judgment unit 32 can determine that the clock signal CLK_MON to be detected is abnormally interrupted based on this.

[0079] In this embodiment, the judgment unit can determine whether the clock signal to be detected is abnormally interrupted based on the level of the XOR signal when it is triggered. The judgment process is simple and highly stable.

[0080] In one embodiment, an abnormal interruption of the clock signal CLK_MON to be detected is defined as an interruption of the clock signal CLK_MON to be detected for a duration exceeding a preset duration threshold. The preset duration threshold is half the duration of one cycle of the periodic signal S_PER, minus the difference between the minimum delay duration of the first synchronization signal S_SYNC1 and the periodic signal S_PER when the clock signal CLK_MON to be detected is not interrupted.

[0081] Reference Figure 3 To explain, if the level of the periodic signal S_PER does not flip at the rising edge of the clock signal CLK_MON to be detected, the periodic signal S_PER will be sampled by the two adjacent rising edges of the clock signal CLK_MON to be detected after the level of the periodic signal S_PER flips, generating the second synchronization signal S_SYNC2. The delay of the second synchronization signal S_SYNC2 relative to the periodic signal S_PRE is longer than the duration of one period of the clock signal CLK_MON to be detected, but shorter than the duration of two periods of the clock signal CLK_MON to be detected. If the level of the second synchronization signal S_SYNC2 does not flip at the rising edge of the reference clock signal CLK_REF, after the level of the second synchronization signal S_SYNC2 flips, the two adjacent rising edges of the reference clock signal CLK_REF sample the second synchronization signal S_SYNC2 to generate the first synchronization signal S_SYNC1. The delay of the first synchronization signal S_SYNC1 relative to the second synchronization signal S_SYNC2 is greater than the duration of one period of the reference clock signal CLK_REF, and less than the duration of two periods of the reference clock signal CLK_REF. Therefore, it can be concluded that, without interruption of the clock signal CLK_MON to be detected, the minimum delay of the first synchronization signal S_SYNC1 relative to the periodic signal S_PER is greater than the sum of the duration of one period of the clock signal CLK_MON to be detected and the duration of one period of the reference clock signal CLK_REF.

[0082] by Figure 4 Taking this as an example, the interval between the ninth time T9 and the tenth time T10 is greater than or equal to the sum of the duration of one cycle of the clock signal to be detected CLK_MON and the duration of one cycle of the reference clock signal CLK_REF. This causes the level of the periodic signal S_PER to fail to be synchronized to the first synchronization signal S_SYNC1 at the flip of the fifth time T5 at the eighth time T8. The level of the XOR signal S_XOR is the first level, and the clock interrupt judgment circuit 30 can detect the abnormal interruption of the clock signal to be detected CLK_MON.

[0083] It is understandable that if the duration of the interruption of the clock signal CLK_MON to be detected is less than or equal to the preset duration threshold, even if the clock signal CLK_MON to be detected is interrupted, at the moment the trigger signal S_EN is generated, the most recent flip of the level of the periodic signal S_PER has been synchronized to the first synchronization signal S_SYNC1, and the clock interrupt judgment circuit 30 cannot detect the interruption.

[0084] In this embodiment, the preset duration threshold can be adjusted by adjusting the frequency of the periodic signal, thereby meeting the detection requirements of different clock abnormal interruptions.

[0085] In one embodiment, the clock interrupt determination circuit 30 is further configured to output a clock abnormality signal in response to an abnormal interruption of the clock signal to be detected, CLK_MON.

[0086] In this embodiment, the output clock anomaly signal can be used to determine the cause of the anomaly, improving the accuracy of diagnosis and maintenance.

[0087] This disclosure provides a detection circuit, such as Figure 8As shown, the detection circuit includes a counting unit 11, a first synchronization unit 21, a second synchronization unit 22, an XOR unit 31, and a judgment unit 32. The counting unit 11 receives a reference clock signal CLK_REF. In response to the counting value of the counting unit 11 not reaching the counting threshold, the counting unit 11 increments the counting value by a preset value every cycle of the reference clock signal CLK_REF; in response to the counting value reaching the counting threshold and after one cycle of the reference clock signal CLK_REF, the counting value is cleared to zero, the level of the periodic signal S_PER is toggled, and a trigger signal S_EN is generated. The first synchronization unit 21 is electrically connected to the counting unit 11 and receives the clock signal to be detected CLK_MON. The first synchronization unit 21 performs synchronization processing on the periodic signal S_PER according to the clock signal to be detected CLK_MON to generate a second synchronization signal S_SYNC2. The second synchronization unit 22 is electrically connected to the first synchronization unit 21 and receives a reference clock signal CLK_REF. The second synchronization unit 22 is used to perform synchronization processing on the second synchronization signal S_SYNC2 according to the reference clock signal CLK_REF to generate the first synchronization signal S_SYNC1. The XOR unit 31 is electrically connected to both the counting unit 11 and the second synchronization unit 22. The XOR unit 31 is used to perform an XOR operation on the periodic signal S_PER and the first synchronization signal S_SYNC1 to generate an XOR signal S_XOR. The judgment unit 32 is electrically connected to both the XOR unit 31 and the counting unit 11. The judgment unit 32 is used to determine whether the clock signal CLK_MON to be detected is abnormally interrupted according to the XOR signal S_XOR in response to the received trigger signal S_EN. The judgment unit 32 is also used to output a clock abnormality signal in response to an abnormal interruption of the clock signal CLK_MON to be detected.

[0088] In this embodiment, the detection circuit uses pure digital logic, has no special process requirements, and is highly stable.

[0089] This disclosure provides a detection chip including any of the detection circuits described in the above embodiments. Because it includes the detection circuits described in the above embodiments, the trigger signal for initiating detection is generated based on a reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, thus allowing the frequency of the reference clock signal to be set according to requirements. This achieves flexible configuration of the detection time and avoids the problem of difficulty in timing convergence of the reference clock signal.

[0090] This disclosure provides a system-on-a-chip (SoC) including the detection chip described in the above embodiments. Because it includes the detection chip described in the above embodiments, the trigger signal for initiating detection is generated based on a reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, thus allowing the frequency of the reference clock signal to be set according to requirements. This achieves flexible configuration of the detection time and avoids the problem of difficulty in timing convergence of the reference clock signal.

[0091] This disclosure provides an electronic device including the detection chip or system-on-a-chip (SoC) described in the above embodiments. Because it includes the detection chip or SoC described in the above embodiments, the trigger signal for initiating detection is generated based on a reference clock signal. The frequency of the reference clock signal is not constrained by the clock signal to be detected, thus allowing the frequency of the reference clock signal to be set according to requirements. This achieves flexible configuration of the detection time and avoids the problem of difficulty in timing convergence of the reference clock signal.

[0092] In one exemplary embodiment, an electronic device is provided, such as a mobile phone, a laptop computer, a tablet computer, and a wearable device.

[0093] refer to Figure 9 As shown, the electronic device 900 may include one or more of the following components: processing component 902, memory 904, power supply component 906, multimedia component 908, audio component 910, input / output (I / O) interface 912, sensor component 914, and communication component 916.

[0094] Processing component 902 typically controls the overall operation of electronic device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 902 may include one or more processors 920 to execute instructions. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0095] Memory 904 is configured to store various types of data to support the operation of electronic device 900. Examples of this data include instructions for any application or method operating on electronic device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0096] Power supply component 906 provides power to various components of electronic device 900. Power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 900.

[0097] Multimedia component 908 includes a screen that provides an output interface between electronic device 900 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera module and / or a rear-facing camera module. When electronic device 900 is in an operating mode, such as shooting mode or video mode, the front-facing camera module and / or rear-facing camera module may receive external multimedia data. Each front-facing camera module and rear-facing camera module may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0098] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when electronic device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0099] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0100] Sensor assembly 914 includes one or more sensors for providing state assessments of various aspects of electronic device 900. For example, sensor assembly 914 may detect the on / off state of electronic device 900, the relative positioning of components such as the display and keypad of electronic device 900, changes in position of electronic device 900 or a component of electronic device 900, the presence or absence of user contact with electronic device 900, orientation or acceleration / deceleration of electronic device 900, and temperature changes of electronic device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0101] Communication component 916 is configured to facilitate wired or wireless communication between electronic device 900 and other terminals. Electronic device 900 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0102] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing terminals (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0103] In one exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions that can be executed by a processor 920 of an electronic device 900. For example, the non-transitory computer-readable storage medium may be a ROM, CD-ROM, magnetic tape, floppy disk, or optical data storage terminal, etc.

[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0105] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0106] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0107] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0108] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, when implementing each example, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained through appropriate means, in accordance with relevant laws and regulations. The specific methods of notification and / or authorization can vary depending on the actual situation and application scenario; the scope of the solution is not limited in this regard.

[0109] In this manual and the sample solutions, any processing of personal information will be conducted only under legal grounds (such as obtaining the consent of the data subject or being necessary for the performance of a contract) and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

Claims

1. A detection circuit, characterized in that, The detection circuit includes: A periodic signal generation circuit receives a reference clock signal and is used to generate a periodic signal and a trigger signal based on the reference clock signal. A synchronization signal generation circuit is electrically connected to the periodic signal generation circuit and receives the reference clock signal and the clock signal to be detected. The synchronization signal generation circuit is used to perform synchronization processing on the periodic signal according to the reference clock signal and the clock signal to be detected to generate a first synchronization signal. A clock interruption determination circuit is electrically connected to both the periodic signal generation circuit and the synchronization signal generation circuit. The clock interruption determination circuit is used to determine whether the clock signal to be detected is abnormally interrupted based on the periodic signal and the first synchronization signal in response to receiving the trigger signal.

2. The detection circuit according to claim 1, characterized in that, The periodic signal generation circuit includes: A counting unit receives the reference clock signal and is electrically connected to both the synchronization signal generation circuit and the clock interrupt determination circuit. The counting unit is used for: In response to the fact that the count value of the counting unit has not reached the counting threshold, the count value is increased by a preset value every time one cycle of the reference clock signal is elapsed; In response to the count value reaching the count threshold and passing one cycle of the reference clock signal, the count value is cleared to zero, the level of the cycle signal is flipped, and the trigger signal is generated.

3. The detection circuit according to claim 2, characterized in that, The ratio of the counting threshold to the preset value plus one is greater than or equal to the ratio of the maximum delay of the first synchronization signal relative to the periodic signal to the duration of one period of the reference clock signal when the clock signal to be detected is not interrupted.

4. The detection circuit according to claim 2, characterized in that, In response to the count value not reaching the count threshold, the count value is incremented by the preset value at each rising edge or each falling edge of the reference clock signal.

5. The detection circuit according to claim 1, characterized in that, The synchronization signal generation circuit includes: A first synchronization unit is electrically connected to the periodic signal generation circuit and receives the clock signal to be detected. The first synchronization unit is used to perform synchronization processing on the periodic signal according to the clock signal to be detected to generate a second synchronization signal. The second synchronization unit is electrically connected to the first synchronization unit and receives the reference clock signal. The second synchronization unit is used to perform synchronization processing on the second synchronization signal according to the reference clock signal to generate the first synchronization signal.

6. The detection circuit according to claim 5, characterized in that, At a first preset number of rising or falling edges of the clock signal to be detected, the first synchronization unit samples the periodic signal to generate the second synchronization signal. Wherein, the first preset quantity is an integer greater than or equal to 2.

7. The detection circuit according to claim 5, characterized in that, At a second preset number of rising or falling edges adjacent to the reference clock signal, the second synchronization unit samples the second synchronization signal to generate the first synchronization signal; Wherein, the second preset quantity is an integer greater than or equal to 2.

8. The detection circuit according to claim 1, characterized in that, The clock interrupt detection circuit includes: The XOR unit is electrically connected to both the periodic signal generation circuit and the synchronization signal generation circuit. The XOR unit is used to perform an XOR operation on the periodic signal and the first synchronization signal to generate an XOR signal.

9. The detection circuit according to claim 8, characterized in that, The clock interrupt detection circuit also includes: The judgment unit is electrically connected to both the XOR unit and the periodic signal generation circuit. The judgment unit is used to determine whether the clock signal to be detected is abnormally interrupted based on the XOR signal in response to receiving the trigger signal.

10. The detection circuit according to claim 9, characterized in that, The XOR signal level includes a first level and a second level, wherein the second level is lower than the first level; The determination unit is used to determine that the clock signal to be detected is abnormally interrupted when the XOR signal is at the first level at the moment the trigger signal is received.

11. The detection circuit according to any one of claims 1 to 10, characterized in that, The abnormal interruption of the clock signal to be detected is defined as the duration of the interruption of the clock signal to be detected being greater than a preset duration threshold. The preset duration threshold is half the duration of one cycle of the periodic signal, minus the difference between the minimum delay duration of the first synchronization signal and the periodic signal when the clock signal to be detected is not interrupted.

12. The detection circuit according to any one of claims 1 to 10, characterized in that, The clock interrupt detection circuit is also used to output a clock abnormality signal in response to an abnormal interruption of the clock signal to be detected.

13. A detection chip, characterized in that, The detection chip includes the detection circuit as described in any one of claims 1 to 12.

14. A system-on-a-chip, characterized in that, The system-on-a-chip includes the detection chip as described in claim 13.

15. An electronic device, characterized in that, The electronic device includes the detection chip as described in claim 13 or the system-on-a-chip as described in claim 14.

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