Method, medium and device for suppressing non-zero sequence third harmonic of three-phase four-wire inverter

Abstract

The application discloses a three-phase four-wire inverter non-zero sequence third harmonic suppression method, medium and equipment, and relates to the technical field of inverters; the method comprises the following steps: a resonant controller with a resonant frequency of (3k+1) times of a fundamental frequency is additionally connected in parallel in a positive sequence d-axis and q-axis voltage loop; the output of the resonant controller and an existing controller in the positive sequence d-axis and q-axis voltage loop is superposed, so as to generate a first d-axis driving instruction and a first q-axis driving instruction; and based on the first d-axis driving instruction and the first q-axis driving instruction, a first driving signal for suppressing negative sequence 3k order harmonics in inverter output voltage is generated. The medium and the equipment are used for implementing the above method. The application has the beneficial effects that by additionally connecting the resonant controller with the corresponding frequency in the positive sequence d-axis and q-axis voltage loop, the structural suppression blind area of the existing positive sequence dq-axis voltage loop for the negative sequence 3k order harmonics is accurately filled.

Description

Technical Field

[0001] This application relates to the field of inverter technology, and in particular to a method, medium and device for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter. Background Technology

[0002] Off-grid photovoltaic-storage power supply systems typically employ a three-phase four-wire inverter structure to directly adapt to single-phase / three-phase mixed loads. In medium-to-high power industrial and commercial applications, an inverter topology using a split capacitor on the DC bus and a neutral line drawn from the midpoint has become one of the preferred solutions. Its advantages include: the neutral line can be naturally drawn using the split capacitor, eliminating the need for an additional transformer, and it has the ability to handle unbalanced loads.

[0003] In off-grid operation mode, the inverter needs to act as an independent voltage source, requiring the output voltage to have good waveform quality under balanced and unbalanced, linear and nonlinear loads. Total harmonic distortion (THD) is typically used as the core indicator. To achieve this goal, precise control of the voltage loop is crucial. Currently, there are two main control frameworks: one is phase-by-phase control based on the ABC three-phase stationary coordinate system, where each phase voltage loop has an independently set proportional-resonant or (quasi-)resonant controller, with multiple (quasi-)resonant controllers for specific harmonics connected in parallel to suppress voltage distortion; the other is control based on the dq0 rotating coordinate system, which transforms the positive-sequence fundamental wave into a DC component using proportional-integral (PI) regulation, with the zero-sequence component independently controlled by the 0-axis channel, and the fundamental negative-sequence component appearing as a second-harmonic AC quantity on the positive-sequence dq axis.

[0004] For the dq0 control framework, in order to suppress voltage harmonics caused by unbalanced and nonlinear loads, the voltage loop of dq0 control is usually connected in parallel with multiple (quasi) resonant controllers to form a common multi (quasi) resonant configuration scheme. For example, a second (quasi) resonant controller is connected in parallel on the positive sequence dq axis to suppress the second harmonic component caused by the negative sequence of the fundamental frequency, and a sixth (quasi) resonant controller is connected in parallel to suppress the fifth and seventh harmonics; a first, third, fifth, and seventh (quasi) resonant controller is connected in parallel on the zero axis to handle the zero sequence harmonic.

[0005] However, in practice, it has been found that when a three-phase four-wire three-level inverter is subjected to an extremely unbalanced load (such as single-phase full load) under dq0 control, a significant third harmonic voltage still appears in the output voltage despite the specific harmonic suppression of the aforementioned (quasi-)resonant controller. This harmonic component is predominantly negative sequence, leading to THD deterioration. Therefore, the existing (quasi-resonant controller configuration cannot effectively suppress this negative-sequence third harmonic (which manifests as a fourth harmonic component in the positive-sequence dq system), exposing a harmonic suppression blind spot in existing technologies under such operating conditions. Currently, existing technologies generally assume that purely linear loads do not introduce more harmonics into the inverter output voltage. Therefore, the source of output voltage harmonics is implicitly attributed to switching dead time, PWM modulation, etc., without recognizing the unique self-generated harmonic mechanism of the three-level split capacitor topology under unbalanced linear loads. Summary of the Invention

[0006] One objective of this application is to provide a method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter that can solve at least one of the defects in the aforementioned background art.

[0007] Another object of this application is to provide a computer-readable storage medium for implementing the above-described method for suppressing non-zero-sequence third harmonics in a three-phase four-wire inverter.

[0008] Another object of this application is to provide an electronic device for implementing the above-described method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter.

[0009] To achieve at least one of the above objectives, one aspect of this application provides a method for suppressing non-zero sequence third harmonic in a three-phase four-wire inverter, applied to a dq0 control framework, comprising the following steps: adding resonant controllers with a resonant frequency of (3k+1) times the fundamental frequency in parallel to both the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop; superimposing the outputs of the added resonant controller in the positive sequence d-axis voltage loop and the existing controller to generate a first d-axis drive command; superimposing the outputs of the added resonant controller in the positive sequence q-axis voltage loop and the existing controller to generate a first q-axis drive command; and generating a first drive signal to suppress the negative sequence 3kth harmonic in the inverter output voltage based on the first d-axis drive command and the first q-axis drive command; wherein k represents a natural number and takes the value of an integer greater than or equal to 1.

[0010] Preferably, the controllers in the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop both include a proportional-integral controller, a resonant controller with a resonant frequency of 2 times the fundamental frequency, and a resonant controller with a resonant frequency of 6 times the fundamental frequency.

[0011] Preferably, when k is an integer greater than or equal to 2, a resonant controller with a resonant frequency of (3k-1) times the fundamental frequency is added in parallel to both the positive-sequence d-axis voltage loop and the positive-sequence q-axis voltage loop; the outputs of all the resonant controllers added to the positive-sequence d-axis voltage loop and the existing controller are superimposed to generate a second d-axis drive command; the outputs of all the resonant controllers added to the positive-sequence q-axis voltage loop and the existing controller are superimposed to generate a second q-axis drive command; based on the second d-axis drive command and the second q-axis drive command, a second drive signal is generated to suppress the positive and negative 3kth harmonics in the inverter output voltage.

[0012] Preferably, the resonant controller is an ideal resonant controller or a quasi-resonant controller.

[0013] Preferably, k is set to 1, so that a resonant controller with a resonant frequency of 4 times the fundamental frequency is added in parallel in both the positive sequence d-axis and q-axis voltage loops.

[0014] Preferably, while suppressing the 3kth harmonic through the added resonant controller, a feedforward compensation stage is also set up in parallel to compensate for the 3kth harmonic. Specifically, this includes the following process: real-time acquisition of the voltage signal of the split capacitor on the DC side of the inverter; extraction of the half-bus fundamental frequency ripple and the half-bus second harmonic ripple; construction of feedforward compensation components based on the extracted ripple signal and the ideal modulation wave signal; superposition of the obtained feedforward compensation components onto the modulation wave command of each phase to generate the final modulation wave after feedforward compensation; wherein, the feedforward compensation component of phase x... The calculation expression is as follows: ; In the formula, This represents the DC component of the inverter's DC bus voltage. This indicates the fundamental frequency ripple of the half-bus. This indicates a half-bus frequency harmonic ripple. This represents the ideal modulation wave corresponding to inverter x, where phase x is any one of phases a, b, and c.

[0015] Preferably, the activation and scheduling mechanism for the added resonant controller includes the following process: real-time detection of the three-phase load current of the inverter and calculation of the load imbalance; when the load imbalance is less than a preset imbalance threshold, the added resonant controller is disabled; when the load imbalance is greater than or equal to the preset imbalance threshold, the added resonant controller is enabled.

[0016] Preferably, when the added resonant controller is enabled, the gain coefficient of the resonant controller is dynamically adjusted according to the load imbalance, so that the gain coefficient increases with the increase of the load imbalance; wherein, the adjustment expression of the gain coefficient is as follows: ; In the formula, Indicates the gain coefficient. and These represent the preset minimum and maximum gain, respectively, and E represents the load imbalance. This indicates the preset imbalance threshold. This indicates the preset maximum load imbalance.

[0017] Another aspect of this application provides a computer-readable storage medium storing a computer program; when the computer program is executed by a processor, it implements the above-described method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter.

[0018] Another aspect of this application provides an electronic device, including a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the above-described method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter.

[0019] Compared with the prior art, the beneficial effects of this application are as follows: (1) This application is the first to add a resonant controller of the corresponding frequency in the positive d-axis and q-axis voltage loops under the dq0 control framework, which precisely fills the structural suppression blind zone of the existing positive dq-axis voltage loop for the negative 3k harmonic.

[0020] (2) This application only adds a resonant controller in parallel to the positive sequence d-axis and q-axis of the existing dq0 voltage loop, without changing the inverter main circuit topology, nor reconstructing the original fundamental positive sequence PI control and the existing resonant control loop. The implementation of the newly added resonant controller is completely consistent with the existing controller, which can meet the stringent off-grid requirements of industrial and commercial applications. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the traditional dq0 control framework for a three-phase four-wire inverter.

[0022] Figure 2 This is a schematic diagram of the working steps of this application.

[0023] Figure 3 This is a schematic diagram of the architecture of the d-axis voltage loop in this application. Detailed Implementation

[0024] The present application will now be further described in conjunction with specific embodiments. It should be noted that, in the description of this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0025] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.

[0026] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0028] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0029] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0030] To facilitate understanding of the technical solution of this application, the specific control process of the traditional dq0 control framework of a three-phase four-wire inverter, as well as the mechanism of the non-zero sequence third harmonic voltage appearing at the output of the inverter under unbalanced linear load, will be described in detail below.

[0031] like Figure 1 As shown, the traditional dq0 control framework employs a three-channel independent control structure in the dq0 rotating coordinate system, independently regulating the positive-sequence fundamental component (d-axis and q-axis) and zero-sequence component (0-axis) of the three-phase voltage. The control outputs of the three channels are converted into three-phase modulated waves after dq0 / ABC inverse transformation, which are then fed into the pulse width modulation module to generate drive signals. The overall control architecture can be divided into three parallel voltage loop channels: a d-axis voltage loop, a q-axis voltage loop, and a 0-axis voltage loop. The d-axis voltage loop controls the active component of the output voltage, achieving amplitude regulation; the q-axis voltage loop controls the reactive component of the output voltage, achieving phase regulation; and the 0-axis voltage loop controls the zero-sequence component of the output voltage, responsible for neutral point potential balance and zero-sequence voltage suppression.

[0032] For the d-axis voltage loop, the given voltage reference value V ref-d The d-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-dError calculation is performed to obtain an error signal. This error signal is then sent to the d-axis voltage controller, where it undergoes PI calculation to generate the initial adjustment amount for the d-axis voltage command. Simultaneously, a cascaded d-axis resonant module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal, such as the 2nd and 6th harmonics, to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. Based on the compensated error signal, the initial adjustment amount of the d-axis voltage command is superimposed and corrected to obtain the corrected d-axis voltage command. To prevent excessive output from the d-axis voltage controller, which could lead to modulation exceeding limits or system malfunction, the corrected d-axis voltage command is amplitude-limited to keep it within a safe range.

[0033] For the q-axis voltage loop, the given voltage reference value V ref-q The q-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-q Error calculation is performed to obtain an error signal. This error signal is then fed into the q-axis voltage controller, where it undergoes PI calculation to generate the initial adjustment amount for the q-axis voltage command. Simultaneously, a cascaded q-axis resonant module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal, such as the 2nd and 6th harmonics, to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. Based on the compensated error signal, the initial adjustment amount of the q-axis voltage command is superimposed and corrected to obtain the corrected q-axis voltage command. To prevent excessive output from the q-axis voltage controller from causing the modulation wave to exceed limits or the system to malfunction, the corrected q-axis voltage command is amplitude-limited to keep it within a safe range.

[0034] For the 0-axis voltage loop, the given voltage reference value V ref-0 The zero-axis component V extracted from the three-phase output voltage after ABC / dq0 transformation inv-0Error calculations are performed to obtain an error signal. This error signal is then fed into the zero-axis voltage controller, where a PI calculation generates the initial adjustment amount for the zero-axis voltage command. Simultaneously, a cascaded zero-axis resonant controller module composed of multiple parallel resonant controllers can compensate for specific harmonics in the error signal, such as the 1st, 3rd, 5th, and 7th harmonics, to suppress periodic harmonic distortion in the output voltage and reduce total harmonic distortion. The initial adjustment amount of the zero-axis voltage command is then superimposed and corrected based on the compensated error signal to obtain the corrected zero-axis voltage command. To prevent excessive output from the zero-axis voltage controller, which could lead to modulation exceeding limits or system malfunction, the corrected zero-axis voltage command is amplitude-limited, keeping it within a safe range. In some high-performance control scenarios, a current loop can be added to the output of each voltage loop in the dq0 control framework, using the voltage loop output as a reference value for the current loop, enabling a faster dynamic response.

[0035] In a three-phase four-wire three-level inverter operating under the aforementioned dq0 control framework and with an unbalanced linear load, the non-zero sequence third harmonic voltage at the output is mainly caused by the nonlinear coupling between the DC-side ripple and the asymmetric modulation wave under closed-loop control. This will be described in detail below.

[0036] Specifically, when the inverter carries a single-phase or two-phase unbalanced linear load, two types of voltage fluctuations appear simultaneously on the DC-side split capacitors: one is the half-bus fundamental frequency ripple, which is the charging and discharging effect of the neutral current on the upper and lower capacitors, causing the voltages of the upper and lower capacitors to produce fundamental frequency fluctuations of equal magnitude and opposite direction; the other is the total bus second harmonic ripple, which is the output power pulsation caused by the unbalanced load, causing the total bus voltage to produce second harmonic fluctuations. This fluctuation is evenly distributed to the upper and lower capacitors, forming a common-mode second harmonic ripple on the half-bus.

[0037] To maintain sinusoidal symmetry of the three-phase output voltage under severe load imbalance, considering the constant fluctuations in the half-bus voltage, the dq0 controller will inevitably output a large-amplitude fundamental zero-sequence modulation component on the 0-axis. This zero-sequence component superimposed on the positive-sequence dq-axis output causes severe asymmetry in the three-phase modulation waveform.

[0038] Furthermore, due to the nonlinear coupling between the modulation wave and DC ripple in PWM modulation, harmonic disturbances are generated at the output. To counteract these disturbances, the closed-loop controller must inject corresponding harmonic compensation components into the modulation wave in the reverse direction. Therefore, the steady-state modulation wave is not the ideal sine wave as conventionally assumed, but contains the fundamental zero-sequence component and low-order harmonic components excited by ripple coupling. This "self-distortion" is an inevitable result of closed-loop control and the intrinsic driving force behind the continued existence of harmonics.

[0039] The average output phase voltage of a three-phase four-wire inverter can be expressed as: .

[0040] In the formula, This represents the average phase voltage at the output terminal of the x-phase bridge arm of the inverter relative to the midpoint O of the DC-side split capacitor. This represents the instantaneous value of the modulation wave in phase x of the inverter. This represents the DC component of the inverter's DC bus voltage. This indicates a half-bus frequency harmonic ripple. This indicates the fundamental frequency ripple of the half-bus.

[0041] As can be seen from the above expression, there are two nonlinear coupling paths: Path 1, the modulated wave is directly multiplied by the second harmonic ripple of the half-bus, and more third harmonic components are generated through trigonometric identity transformation; Path 2, the absolute value of the modulated wave is multiplied by the fundamental frequency ripple of the half-bus, and even harmonics are introduced due to the absolute value operation, and then the third harmonic is generated by the fundamental frequency ripple.

[0042] It is important to know that, due to the asymmetry of the three-phase modulation wave, the third harmonic generated by the above path is necessarily asymmetrical among the three phases. According to the symmetrical component method, it contains positive sequence, negative sequence and zero sequence components.

[0043] In contrast, in a two-level split-capacitor three-phase four-wire topology, the average output phase voltage depends only on the linear product of the total bus voltage and the modulation ratio, and there is no absolute value coupling term as mentioned above. Therefore, capacitor voltage fluctuations in a two-level topology will not nonlinearly couple with the modulation wave. Simultaneously, due to the absence of this nonlinear disturbance source, the closed-loop modulation wave does not require additional harmonic compensation components to cancel such coupling, and the modulation waveform itself is closer to an ideal sine wave, further avoiding secondary coupling between modulation wave distortion and ripple. This explains the special nature of this problem in a three-level topology from both topological and control perspectives.

[0044] In the aforementioned conventional dq0 control framework, the zero-sequence third harmonic is effectively suppressed by the 0-axis third-order resonant controller; the positive-sequence third harmonic is mapped to twice the fundamental frequency in the positive-sequence dq coordinate system, which is incidentally suppressed by the second-order resonant controller used for fundamental negative-sequence suppression; the negative-sequence third harmonic is mapped to four times the fundamental frequency in the positive-sequence dq coordinate system, but the existing second-order and sixth-order resonant controllers do not cover this frequency, thus forming a structural suppression blind zone; this is the fundamental reason why the output voltage THD deteriorates under unbalanced linear loads and the third harmonic is dominated by the negative-sequence component.

[0045] It is important to understand that the above mechanism is universally applicable to higher harmonics. Specifically, the coupling of a DC-side ripple containing the fundamental frequency and second harmonic ripple with an asymmetric modulated wave containing the fundamental frequency and harmonic compensation components injected through a closed loop can generate a 3kth non-zero sequence harmonic (k=1, 2, 3...). Among these, the negative sequence 3kth harmonic maps to a frequency (3k+1) times the fundamental frequency in the positive sequence dq coordinate system, which generally exceeds the coverage range of traditional resonant controllers.

[0046] To address the aforementioned technical problems, one aspect of this application provides a method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter applied to the aforementioned dq0 control framework, such as... Figure 2 and Figure 3 As shown, one preferred embodiment includes the following steps: S100: A resonant controller with a resonant frequency of (3k+1) times the fundamental frequency is added in parallel to both the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop; where k represents a natural number.

[0047] It should be known that, as mentioned above, the positive sequence d-axis and q-axis voltage loops under the existing dq0 control framework are mainly equipped with a proportional-integral controller, a resonant controller with a resonant frequency of twice the fundamental frequency (i.e., a second-order resonant controller), and a resonant controller with a resonant frequency of six times the fundamental frequency (i.e., a sixth-order resonant controller).

[0048] However, according to the physical mechanism revealed above, in the non-zero sequence 3k harmonic generated under unbalanced linear load, the negative sequence 3k component is mapped to the positive sequence dq coordinate system at a frequency that is (3k+1) times the fundamental frequency. This frequency does not coincide with the resonant frequency of any of the existing controllers mentioned above, resulting in the harmonic component at this frequency being in a state of "no controller coverage".

[0049] Therefore, this step fills this blind spot directly from the frequency configuration level of the controller by adding a resonant controller with a resonant frequency of (3k+1) times the fundamental frequency, providing a hardware foundation for the subsequent precise adjustment of the voltage error at this frequency point to zero.

[0050] S200: The outputs of the newly added resonant controller in the positive sequence d-axis voltage loop and the existing controller are superimposed to generate the first d-axis drive command; the outputs of the newly added resonant controller in the positive sequence q-axis voltage loop and the existing controller are superimposed to generate the first q-axis drive command.

[0051] It should be understood that the added resonant controller is merely an independent operational module, and its output only represents the compensation amount for the (3k+1)th harmonic fundamental frequency component. If this compensation amount is not correctly superimposed on the output of the existing controller, the suppression information cannot be transmitted to the subsequent current inner loop and PWM modulation stage.

[0052] This step involves algebraically superimposing the output of the newly added resonant controller with the output of the existing controller, enabling the drive command to simultaneously carry multiple control objectives such as fundamental wave control, existing harmonic suppression, and newly added blind zone suppression.

[0053] S300: Based on the first d-axis drive command and the first q-axis drive command, generate a first drive signal to suppress the negative sequence 3k harmonics in the inverter output voltage.

[0054] It should be understood that the purpose of this step is to transform the d-axis and q-axis drive commands containing harmonic suppression information generated in step S200 into physical pulse signals that can drive the inverter switching transistors through a complete current inner loop control, coordinate transformation and PWM modulation link, so that the harmonic suppression commands can be truly executed in the power circuit.

[0055] Understandably, this application is the first to add a resonant controller of the corresponding frequency in the positive d-axis and q-axis voltage loops under the dq0 control framework, which precisely fills the structural suppression blind spot of the existing positive dq-axis voltage loop for the negative 3k harmonics.

[0056] This application only requires adding resonant controllers in parallel to the positive-sequence d-axis and q-axis of the existing dq0 voltage loop, without modifying the inverter main circuit topology or reconstructing the original fundamental positive-sequence PI control and existing resonant control loop. The implementation of the newly added resonant controller is completely consistent with the existing controller, and it can meet the stringent off-grid requirements of industrial and commercial applications.

[0057] It is understandable that the value of the natural number k can be an integer greater than or equal to 1. For example, the value of k can be 1, 2, 3, ..., corresponding to the 3rd, 6th, 9th, ..., 3kth harmonics of the inverter output voltage.

[0058] As can be seen from the aforementioned mechanism analysis, the generation of non-zero sequence 3k harmonics originates from the nonlinear coupling between the voltage ripple of the DC-side split capacitor and the asymmetric modulation wave during PWM modulation. According to Fourier analysis, the even-order harmonic coefficients of the absolute value of the modulation wave decay rapidly with increasing frequency; among them, the 3rd harmonic corresponding to k=1 is the dominant component with the largest corresponding Fourier coefficient and the most concentrated energy among all non-zero sequence 3k harmonics. When k≥2, since the even-order harmonic coefficients of the absolute value of the modulation wave and the amplitude of the second harmonic ripple decay rapidly with increasing frequency, their actual content is very low; usually, no additional resonant controller is needed to meet the THD index requirements. Therefore, in this embodiment, it is preferable to add a resonant controller with a resonant frequency of 4 times the fundamental frequency in parallel in both the positive sequence d-axis and q-axis voltage loops to suppress the negative sequence 3rd harmonic in the inverter output voltage.

[0059] It is important to know that the positive-sequence third harmonic in the inverter output voltage is mapped to a harmonic component at twice the fundamental frequency in the positive-sequence dq rotating coordinate system. Since the existing positive-sequence dq axis voltage loop already has a resonant controller for second-order suppression, this resonant controller can suppress the positive-sequence third harmonic mapped to twice the fundamental frequency while suppressing the pulsation at twice the fundamental frequency caused by unbalanced load; therefore, there is no need to add a corresponding resonant controller.

[0060] In a specific embodiment, for special application scenarios with extremely stringent power quality requirements, such as power supply for medical equipment, precision instruments, and uninterruptible power supply for data centers, or under specific operating conditions where the inverter switching frequency is low and high-order harmonic attenuation is insufficient, high-order non-zero sequence harmonics with k≥2 may still contribute to excessive THD. Based on an additional resonant controller with a resonant frequency of (3k+1) times the fundamental frequency, the negative-sequence 3k harmonic in the inverter output voltage can be suppressed; while the positive-sequence 3k harmonic in the inverter output voltage can be suppressed by further adding a resonant controller with a resonant frequency of (3k-1) times the fundamental frequency. For ease of understanding, a detailed description will follow.

[0061] In a specific example, such as Figure 3 As shown, resonant controllers with a resonant frequency of (3k-1) times the fundamental frequency are added in parallel to both the positive-sequence d-axis voltage loop and the positive-sequence q-axis voltage loop. The outputs of all the newly added resonant controllers in the positive-sequence d-axis voltage loop and the existing controllers are superimposed to generate the second d-axis drive command; similarly, the outputs of all the newly added resonant controllers in the positive-sequence q-axis voltage loop and the existing controllers are superimposed to generate the second q-axis drive command. Based on the second d-axis drive command and the second q-axis drive command, a second drive signal is generated to suppress the positive and negative 3kth harmonics in the inverter output voltage.

[0062] In one specific embodiment, when suppressing the non-zero sequence 3k harmonic in the inverter output voltage, the added resonant controller can be an ideal resonant controller or a quasi-resonant controller. The ideal resonant controller has a gain approaching infinity at the resonant frequency, theoretically achieving complete zero steady-state error tracking of the resonant frequency; the quasi-resonant controller approximates zero steady-state error tracking of the resonant frequency by providing high gain at the resonant frequency. The specific transfer functions of the ideal resonant controller and the quasi-resonant controller are common knowledge to those skilled in the art and will not be described in detail here. Both the ideal resonant controller and the quasi-resonant controller can meet the requirements of this application, and the appropriate controller can be selected according to the actual needs of those skilled in the art.

[0063] It is important to understand that in the aforementioned embodiments, the suppression of the non-zero-sequence 3k harmonic in the inverter output voltage using a resonant controller is a passive suppression method. As the aforementioned mechanism analysis shows, the non-zero-sequence 3k harmonic in the inverter output voltage originates from the nonlinear coupling between the voltage ripple of the DC-side split capacitor and the asymmetric modulation wave during PWM modulation. Therefore, in the technical solution of this application, a feedforward compensation stage can be set in parallel to compensate for the 3k harmonic, directly suppressing it at its source. This achieves active suppression while significantly reducing the burden of passive suppression and improving dynamic response speed. For ease of understanding, the specific implementation process of the feedforward compensation stage will be described in detail below.

[0064] In a specific embodiment, the feedforward compensation stage includes the following process: real-time acquisition of the voltage signal of the split capacitor on the DC side of the inverter, extraction of the half-bus fundamental frequency ripple and the half-bus second harmonic ripple; construction of feedforward compensation components based on the extracted ripple signals combined with the ideal modulation wave signal; and superposition of the obtained feedforward compensation components onto the modulation wave commands of each phase to generate the final modulation wave after feedforward compensation. Wherein, the feedforward compensation component of phase x... The calculation expression is as follows: ; In the formula, This represents the DC component of the inverter's DC bus voltage. This indicates the fundamental frequency ripple of the half-bus. This indicates a half-bus frequency harmonic ripple. This represents the ideal modulation wave corresponding to inverter x, where phase x is any one of phases a, b, and c.

[0065] Understandable This term is used to cancel the product coupling of the modulated wave and the second harmonic ripple. The term is used to cancel the product coupling of the absolute value of the modulated wave and the fundamental frequency ripple. The feedforward compensation component can suppress the non-zero sequence 3k harmonic in advance, and the added resonant controller can suppress the residual error of the feedforward compensation and the model deviation for a second time.

[0066] It should be understood that obtaining the fundamental frequency ripple, second harmonic ripple, and DC component of the DC bus voltage are well-known techniques to those skilled in the art. For ease of understanding, a simplified description is provided below. Specifically, the upper and lower half-bus voltages corresponding to the upper and lower split capacitors on the DC side can be acquired in real time. The half-bus voltage difference is calculated based on the obtained upper and lower half-bus voltages and extracted using a fundamental frequency bandpass filter to obtain the desired half-bus fundamental frequency ripple. Simultaneously, the DC bus voltage is calculated based on the obtained upper and lower half-bus voltages, extracted using a second harmonic bandpass filter, and divided by 2 to obtain the desired half-bus second harmonic ripple. Low-pass filtering of the obtained DC bus voltage yields the desired DC component.

[0067] It is important to understand that when adding a resonant controller to the dq0 control framework, while suppressing harmonics at specific frequencies, this controller introduces additional phase lag, which may affect the system's phase margin and stability. Furthermore, as the aforementioned mechanism analysis shows, under balanced load conditions, non-zero-sequence 3k harmonics are almost nonexistent. Continuing to operate the added resonant controller under these conditions would not only waste computational resources but also potentially cause unnecessary negative impacts. Therefore, in this embodiment, a scheduling mechanism can be configured to enable the added resonant controller. For ease of understanding, this will be described in detail below.

[0068] In a specific embodiment, the scheduling mechanism for enabling the added resonant controller includes the following process: real-time detection of the three-phase load current of the inverter and calculation of the load imbalance; when the load imbalance is less than a preset imbalance threshold, disabling the added resonant controller; when the load imbalance is greater than or equal to the preset imbalance threshold, enabling the added resonant controller.

[0069] It should be understood that the specific calculation method for load unbalance is a well-known technique among those skilled in the art. For example, the three-phase load current of the inverter can be collected, and the negative-sequence current component and positive-sequence current component can be extracted using the symmetrical component method. The load unbalance can be calculated based on the ratio of the negative-sequence current component to the positive-sequence current component. Alternatively, the effective value of the inverter's neutral current can be detected, and the load unbalance can be calculated based on the ratio of the effective value of the current to the average value of the three-phase current. The specific value of the unbalance threshold for determining whether the inverter is in an unbalanced load condition can be set according to the actual needs of those skilled in the art. For example, it can be set to 0.1~0.2. Taking an unbalance threshold of 0.1 as an example, when the load unbalance is greater than or equal to 0.1, the inverter is determined to be in an unbalanced load condition. At this time, the added resonant controller can be enabled to suppress the non-zero sequence 3k harmonics; otherwise, the added resonant controller is disabled.

[0070] In a specific embodiment, as shown in the foregoing mechanism analysis, the amplitude of the non-zero sequence 3k harmonic is positively correlated with the amplitudes of the half-bus fundamental frequency ripple and the half-bus second harmonic ripple. The amplitudes of the half-bus fundamental frequency ripple and the half-bus second harmonic ripple directly depend on the load imbalance; that is, the greater the load imbalance, the greater the neutral current, the greater the capacitor voltage ripple, and the greater the amplitude of the harmonic disturbance generated by coupling. When the added resonant controller is enabled, if a fixed gain coefficient is used, the resonant controller may overcompensate under mild load imbalance, and excessively high gain may lead to a decrease in system phase margin, overshoot of the resonance peak, or even oscillation. Under severe load imbalance, the resonant controller may undercompensate, resulting in substandard harmonic suppression. Therefore, in this embodiment, when the added resonant controller is enabled, the gain coefficient of the resonant controller can be dynamically adjusted according to the load imbalance, so that the gain coefficient increases with the increase of load imbalance, thereby achieving accurate compensation for the non-zero sequence 3k harmonic.

[0071] In a specific example, the gain coefficient adjustment of a resonant controller can be achieved using either a linear adjustment method that varies with the load imbalance or a non-linear adjustment method. In this example, to improve response speed and simplify the calculation process, the linear adjustment method that varies with the load imbalance is preferred for the gain coefficient adjustment of the resonant controller. There are several specific methods for calculating the gain coefficient adjustment; for ease of understanding, one particular adjustment calculation formula will be described below.

[0072] Specifically, the adjustment expression for the gain coefficient is as follows: .

[0073] In the formula, Indicates the gain coefficient. and These represent the preset minimum and maximum gain, respectively, and E represents the load imbalance. This indicates the preset imbalance threshold. This indicates the preset maximum load imbalance.

[0074] It should be known that minimum gain The minimum gain that the added resonant controller should have when first enabled, to ensure basic harmonic suppression capability when the imbalance just exceeds the threshold; minimum gain The value of needs to ensure sufficient gain at the resonant frequency to produce a identifiable suppression effect under slightly unbalanced operating conditions; the preferred value range is 20~80. Maximum gain This represents the upper limit of gain that the resonant controller can achieve under extreme unbalanced conditions. Its value is constrained by system stability limitations and must ensure that the phase margin of the system still meets design requirements at maximum gain. The preferred value range is 150~300. Maximum load unbalance. The upper limit of the imbalance degree is the most severe imbalance condition considered in the system design. It usually corresponds to the extreme condition of one phase being fully loaded and the other two phases being unloaded. The typical value is 1.

[0075] Another aspect of this application provides a computer-readable storage medium, in a preferred embodiment of which a computer program is stored on the storage medium; when the computer program is executed by a processor, it implements the above-described method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter.

[0076] Another aspect of this application provides an electronic device, in one preferred embodiment of which includes a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the above-described method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter.

[0077] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. A method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter, applied to a dq0 control framework, characterized in that, The steps include the following: A resonant controller with a resonant frequency of (3k+1) times the fundamental frequency is added in parallel to both the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop. The outputs of the newly added resonant controller in the positive sequence d-axis voltage loop and the existing controller are superimposed to generate the first d-axis drive command; the outputs of the newly added resonant controller in the positive sequence q-axis voltage loop and the existing controller are superimposed to generate the first q-axis drive command. Based on the first d-axis drive command and the first q-axis drive command, a first drive signal is generated to suppress the negative sequence 3k harmonics in the inverter output voltage; where k represents a natural number and takes the value of an integer greater than or equal to 1.

2. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 1, characterized in that, The existing controllers in the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop include a proportional-integral controller, a resonant controller with a resonant frequency of twice the fundamental frequency, and a resonant controller with a resonant frequency of six times the fundamental frequency.

3. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 2, characterized in that, When the value of k is an integer greater than or equal to 2, a resonant controller with a resonant frequency of (3k-1) times the fundamental frequency is added in parallel in both the positive sequence d-axis voltage loop and the positive sequence q-axis voltage loop. The outputs of all newly added resonant controllers in the positive sequence d-axis voltage loop and the outputs of existing controllers are superimposed to generate the second d-axis drive command; the outputs of all newly added resonant controllers in the positive sequence q-axis voltage loop and the outputs of existing controllers are superimposed to generate the second q-axis drive command. Based on the second d-axis drive command and the second q-axis drive command, a second drive signal is generated to suppress the positive and negative 3k harmonics in the inverter output voltage.

4. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 1, characterized in that, The value of k is 1, so that a resonant controller with a resonant frequency of 4 times the fundamental frequency is added in parallel in both the positive sequence d-axis and q-axis voltage loops.

5. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 1, characterized in that, The resonant controller uses an ideal resonant controller or a quasi-resonant controller.

6. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in any one of claims 1-5, characterized in that, While suppressing the 3kth harmonic through the added resonant controller, a feedforward compensation stage is also set up in parallel to compensate for the 3kth harmonic. The specific process includes the following: The voltage signal of the split capacitor on the DC side of the inverter is acquired in real time, and the fundamental frequency ripple and second harmonic ripple of the half bus are extracted. Based on the extracted ripple signal and the ideal modulation wave signal, a feedforward compensation component is constructed. The obtained feedforward compensation components are superimposed on the modulation wave commands of each phase to generate the final modulation wave after feedforward compensation. Among them, the feedforward compensation component of phase x The calculation expression is as follows: ； In the formula, This represents the DC component of the inverter's DC bus voltage. This indicates the fundamental frequency ripple of the half-bus. This indicates a half-bus frequency harmonic ripple. This represents the ideal modulation wave corresponding to inverter x, where phase x is any one of phases a, b, and c.

7. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 6, characterized in that, The activation and scheduling mechanism for the newly added resonant controller includes the following process: Real-time monitoring of the three-phase load current of the inverter and calculation of load imbalance; When the load imbalance is less than the preset imbalance threshold, the added resonant controller is disabled. When the load imbalance is greater than or equal to the preset imbalance threshold, the added resonant controller is enabled.

8. The method for suppressing non-zero sequence third harmonics in a three-phase four-wire inverter as described in claim 7, characterized in that, When the added resonant controller is enabled, the gain coefficient of the resonant controller is dynamically adjusted according to the load imbalance, so that the gain coefficient increases with the increase of the load imbalance. The adjustment expression for the gain coefficient is as follows: ； In the formula, Indicates the gain coefficient. and These represent the preset minimum and maximum gain, respectively, and E represents the load imbalance. This indicates the preset imbalance threshold. This indicates the preset maximum load imbalance.

9. An electronic device, characterized in that, It includes a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program to implement the non-zero sequence third harmonic suppression method for a three-phase four-wire inverter as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program; when the computer program is executed by a processor, it implements the non-zero sequence third harmonic suppression method for a three-phase four-wire inverter as described in any one of claims 1-8.

Images