A multi-functional integrated power supply technology circuit for a civil aircraft

Abstract

The application discloses a kind of civil aircraft multifunctional integrated power supply technology circuit, it is related to multifunctional integrated circuit technical field, circuit includes: input anti-reverse connection circuit, voltage spike processing circuit, surge current protection circuit, EMC filter circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power-down signal circuit, power-down switching circuit and BOOST boost circuit, can simultaneously satisfy DO-160G power input test in about input anti-reverse connection, voltage spike suppression, surge current limitation, electromagnetic compatibility filtering, surge voltage clamping, input undervoltage protection and transient power interruption and so on Multiple strict requirements of many aspects, without multiple independent protection modules, reduce the number of cascade and interconnection loss of circuit, to improve overall power conversion efficiency. To comprehensively guarantee the continuous stable operation of airborne power supply equipment under various power supply abnormal conditions.

Description

Technical Field

[0001] This invention relates to the field of multifunctional integrated circuit technology, and in particular to a multifunctional integrated power supply technology circuit for civil aircraft. Background Technology

[0002] With the increasing number and complexity of civil avionics equipment, the quality requirements for power supplies are constantly rising. Aircraft power supply systems experience various power disturbances during engine startup, power switching, and sudden load changes, including transient undervoltage, voltage spikes, inrush currents, and momentary power interruptions. The internationally recognized environmental testing standard for airborne equipment, RTCA / DO-160G, clearly stipulates the requirements for power input testing, demanding that equipment maintain normal operation under various power disturbance conditions. Designing an airborne power input circuit capable of simultaneously handling multiple abnormal power conditions has become a critical technical problem urgently needing to be solved in the development of civil avionics equipment.

[0003] Currently, power input protection circuits for avionics equipment typically employ integrated power management chips in conjunction with peripheral circuits. Designers select dedicated power management chips with functions such as overvoltage protection, undervoltage protection, and surge suppression. They then construct power input protection schemes using the chip's integrated control logic and externally configured resistors, capacitors, and power switches. Some schemes also utilize digital control chips in conjunction with software algorithms to monitor and control the power supply status. This type of integrated chip-based power input circuit solution has been widely used in aerospace power supply design.

[0004] However, the aforementioned power input protection solutions based on integrated chips have significant limitations. Integrated power management chips encapsulate multiple functional modules within a single chip, with parameters that are interconnected and inseparable. Designers cannot independently optimize device selection and parameter matching for each functional requirement, such as undervoltage protection, surge suppression, and power-down retention. Even if some modules within the chip are not required to operate under specific conditions, their static power consumption and switching losses still exist, making it difficult to further improve overall power efficiency. Furthermore, integrated chips have low fault tolerance; if a functional module within the chip fails, it often leads to the paralysis of the entire power input protection system, and chip-level repairs are costly and time-consuming. For airborne equipment, space and heat dissipation conditions are strictly limited, making the shortcomings of integrated chip solutions in terms of size, efficiency, and reliability increasingly apparent. Summary of the Invention

[0005] This invention aims to address the shortcomings of existing technologies by providing a multi-functional integrated power supply circuit for civil aircraft. The specific technical solution is as follows: The circuit includes an input reverse connection protection circuit, a voltage spike processing circuit, a surge current protection circuit, an EMC filter circuit, a surge voltage protection circuit, a DC / DC power conversion circuit, an input undervoltage protection circuit, an input power-down signal circuit, a power-down switching circuit, and a BOOST boost circuit. The input terminal of the input reverse connection protection circuit serves as the power input terminal. The output terminal of the input reverse connection protection circuit, the voltage spike processing circuit, the surge current protection circuit, the EMC filter circuit, the surge voltage protection circuit, and the first input terminal of the DC / DC power conversion circuit are connected in series. The input terminal of the input undervoltage protection circuit is connected to the power input terminal. The output of the protection circuit is connected to the second input of the DC / DC power conversion circuit; the input of the power-down signal circuit is connected to the power input, and the output of the power-down signal circuit is connected to the control terminal of the power-down switching circuit; the input of the BOOST boost circuit is connected to the power input, the output of the BOOST boost circuit is connected to the power input of the power-down switching circuit, and the output of the power-down switching circuit is connected to the third input of the DC / DC power conversion circuit. The power-down switching circuit controls whether the electrical energy output by the BOOST boost circuit is transferred to the DC / DC power conversion circuit according to the output signal of the power-down signal circuit.

[0006] The beneficial effects of the multi-functional integrated power supply technology circuit for civil aircraft provided by this invention are as follows: The integrated power supply system comprises an input reverse connection protection circuit, a voltage spike processing circuit, a surge current protection circuit, an EMC filtering circuit, a surge voltage protection circuit, a DC / DC power conversion circuit, an input undervoltage protection circuit, an input power failure signal circuit, a power failure switching circuit, and a BOOST boost circuit. These functional circuits are connected in series or parallel between the power input terminal and the DC / DC power conversion circuit, forming a complete processing link from power input to power conversion. This system simultaneously meets the stringent requirements of the DO-160G power input test regarding input reverse connection protection, voltage spike suppression, surge current limiting, electromagnetic compatibility filtering, surge voltage clamping, input undervoltage protection, and instantaneous power interruption. It eliminates the need for multiple external independent protection modules, reducing the number of cascaded circuits and interconnection losses, thereby improving the overall power conversion efficiency. The output of the input undervoltage protection circuit is connected to the second input of the DC / DC power conversion circuit. The undervoltage protection point is set below 10V for both instantaneous undervoltage and engine start-stop voltages. This ensures that instantaneous voltage fluctuations of 10.0V to 20.5V during engine start-up will not trigger the undervoltage protection, allowing the DC / DC power conversion circuit to continue operating without power loss under instantaneous undervoltage conditions. The surge current protection circuit is located between the voltage spike processing circuit and the EMC filter circuit. By limiting the magnitude of the surge current at power-on, it ensures that the input current meets the peak surge current limit requirements specified in DO-160G for all time periods, protecting downstream circuit components from excessive surge current. The surge voltage protection circuit is located between the EMC filter circuit and the first input of the DC / DC power conversion circuit. It clamps the voltage at the first input of the DC / DC power conversion circuit to a preset safe voltage value, ensuring that downstream circuits are not damaged by input overvoltage. The input terminal of the power-down signal circuit is connected to the power input terminal, and the output terminal is connected to the control terminal of the power-down switching circuit. When a momentary power interruption occurs at the power input terminal, a power-down signal is quickly generated, triggering the power-down switching circuit to transfer the energy stored in the energy storage capacitor in the BOOST boost circuit to the third input terminal of the DC / DC power conversion circuit. This maintains the normal operation of the DC / DC power conversion circuit during the input power interruption, thereby comprehensively ensuring the continuous and stable operation of the airborne power supply equipment under various abnormal power supply conditions.

[0007] Based on the above solution, the integrated power supply technology circuit for multi-functional civil aircraft of the present invention can be further improved as follows.

[0008] Furthermore, the input reverse connection protection circuit includes a first diode and a second diode. The anode of the first diode is connected to the positive line of the first input power supply, and the anode of the second diode is connected to the positive line of the second input power supply. The cathodes of the first diode and the second diode are connected together to serve as the output terminal of the input reverse connection protection circuit.

[0009] The beneficial effects of adopting the above-mentioned further solution are as follows: When the polarity of the first input power positive line or the second input power positive line is reversed, the corresponding diode is cut off due to reverse bias. The input voltage cannot be transmitted to the subsequent circuit through the input reverse connection protection circuit. The subsequent circuit stops working because it does not receive power. The reverse voltage is blocked by the diode and will not be applied to the subsequent circuit components, thus protecting the subsequent circuit components from damage by reverse voltage. Reliable reverse connection protection can be achieved without adding an additional reverse connection control chip or detection circuit. When the first input power positive line and the second input power positive line provide input voltage simultaneously, the two input voltages are combined to the output terminal of the input reverse connection protection circuit after passing through their respective corresponding diodes, jointly powering the subsequent circuit. The first diode prevents current from flowing from the second input power positive line to the first input power positive line, and the second diode prevents current from flowing from the first input power positive line to the second input power positive line, effectively solving the problem of mutual backflow between the two input power supplies. The circuit structure is simple and highly reliable.

[0010] Furthermore, the input undervoltage protection circuit includes a first sampling resistor, a second sampling resistor, a third sampling resistor, a fourth sampling resistor, a sixth sampling resistor, a seventh sampling resistor, a first operational amplifier, and a first MOSFET. The first and second sampling resistors are connected in series between the power input terminal and ground. The common connection point of the first and second sampling resistors is connected to the non-inverting input terminal of the first operational amplifier. The third and fourth sampling resistors are connected in series between the reference voltage and ground. The common connection point of the third and fourth sampling resistors is connected to the inverting input terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the gate of the first MOSFET after being divided by the sixth and seventh sampling resistors. The drain of the first MOSFET outputs an undervoltage protection signal to the second input terminal of the DC / DC power conversion circuit.

[0011] The beneficial effects of adopting the above-mentioned further scheme are as follows: The input undervoltage protection circuit samples the voltage at the power input terminal by dividing it using the first and second sampling resistors. The sampled signal is then sent to the non-inverting input of the first operational amplifier. Simultaneously, the reference voltage is divided using the third and fourth sampling resistors and sent to the inverting input of the first operational amplifier. The first operational amplifier compares the sampled voltage at the non-inverting input with the reference voltage at the inverting input. When the input voltage is lower than the set undervoltage protection point, the first operational amplifier outputs a high-level signal. After being divided by the sixth and seventh sampling resistors, this signal drives the first MOSFET to conduct. The drain of the first MOSFET outputs an undervoltage protection signal to the second input of the DC / DC power conversion circuit. By adjusting the resistance ratios of the first, second, third, and fourth sampling resistors, the undervoltage protection threshold can be flexibly configured, enabling accurate monitoring of the input voltage. This eliminates the need to rely on a fixed threshold within the integrated chip, offering advantages such as flexible protection point setting, fast response speed, and a simple and reliable circuit structure.

[0012] Furthermore, the surge current protection circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first Zener diode, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first transistor, and a second MOSFET. The first and second resistors are connected in series between the power input terminal and ground. The common connection point of the first and second resistors is connected to ground through the first Zener diode. The positive terminal of the first Zener diode is grounded, and the negative terminal of the first Zener diode is connected to the common connection point of the first and second resistors. The third resistor and the sixth capacitor are connected in series between the power input terminal and ground. The common connection point of the third resistor and the sixth capacitor is connected to the base of the first transistor. The emitter of the first transistor is grounded. The collector of the first transistor is connected to the power input terminal through the fourth resistor. The collector of the first transistor is also connected to the gate of the second MOSFET. The source of the second MOSFET is grounded through the fifth resistor. The drain of the second MOSFET serves as the output terminal of the surge current protection circuit. The seventh capacitor is connected between the power input terminal and ground.

[0013] The beneficial effects of adopting the above-mentioned further scheme are as follows: The surge current protection circuit divides the voltage at the power input terminal through the first and second resistors. The first Zener diode clamps the voltage at the voltage divider node to a stable value, providing a stable reference potential for the subsequent stage. The third resistor and the sixth capacitor are connected in series to form an RC network. The common connection point of the third resistor and the sixth capacitor is connected to the base of the first transistor. When the input surge current exceeds the set value, the voltage drop across the fifth resistor is coupled to the base of the first transistor through the third resistor and the sixth capacitor, turning on the first transistor. After the first transistor turns on, it pulls down the gate voltage of the second MOSFET, turning off the second MOSFET, thereby limiting the magnitude of the surge current flowing through the second MOSFET. By matching and adjusting the parameter values ​​of the fourth, third, fifth resistors, and sixth capacitor, the surge current protection threshold value can be accurately set, ensuring that the input surge current meets the peak surge current limit requirements in all time periods specified by DO-160G. Fast and accurate surge current limiting can be achieved without using a complex digital control scheme.

[0014] Furthermore, the surge voltage protection circuit includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth resistor, a seventh resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second Zener diode, a third diode, an eighth capacitor, a ninth capacitor, a tenth capacitor, and a second operational amplifier. The drain of the third MOSFET is connected to the power input terminal, and the source of the third MOSFET serves as the output terminal of the surge voltage protection circuit. The fourth and fifth MOSFETs form a mirror current source. The tenth, eleventh, and twelfth resistors, the second operational amplifier, the thirteenth resistor, the third diode, and the eighth capacitor form a self-oscillating circuit and a bootstrap circuit. The gate voltage of the third MOSFET is the voltage at the power input terminal plus the bootstrap voltage, and the source voltage of the third MOSFET is clamped at a set reference voltage value.

[0015] The advantages of adopting the above-mentioned further scheme are as follows: the drain of the third MOSFET in the surge voltage protection circuit is connected to the power input terminal, and the source of the third MOSFET serves as the output terminal of the surge voltage protection circuit. The fourth and fifth MOSFETs form a mirror current source to provide a stable bias current for the circuit. The tenth, eleventh, and twelfth resistors, the second operational amplifier, the thirteenth resistor, the third diode, and the eighth capacitor constitute a self-oscillating circuit and a bootstrap circuit, ensuring that the gate voltage of the third MOSFET is the voltage at the power input terminal plus the bootstrap voltage, thus ensuring that the third MOSFET obtains a sufficiently high gate drive voltage and operates in the linear region. When the external surge voltage exceeds the set clamping voltage threshold, the second operational amplifier adjusts the gate voltage of the third MOSFET through the self-oscillating circuit and the bootstrap circuit, precisely clamping the source voltage of the third MOSFET at the set reference voltage value, so that the output voltage does not increase with the increase of the input surge voltage. By adjusting the resistance ratio of the sixth and eighth resistors, the clamping voltage threshold can be flexibly set, adapting to the voltage tolerance requirements of different subsequent circuits without replacing the main power devices, and achieving fast and accurate suppression of the input surge voltage.

[0016] Furthermore, the power-down switching circuit includes a third operational amplifier, a sixth MOSFET, a seventh MOSFET, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twentieth resistor. The sixteenth and seventeenth resistors are connected in series between the power input terminal and ground. The common connection point of the sixteenth and seventeenth resistors is connected to the inverting input terminal of the third operational amplifier. The non-inverting input terminal of the third operational amplifier is connected to the reference voltage. The output terminal of the third operational amplifier is connected to the gate of the sixth MOSFET after voltage division by the nineteenth and twentieth resistors. The source of the sixth MOSFET is grounded. The drain of the sixth MOSFET is connected to the gate of the seventh MOSFET. The source of the seventh MOSFET is connected to the output terminal of the BOOST boost circuit. The drain of the seventh MOSFET is connected to the third input terminal of the DC / DC power conversion circuit.

[0017] The beneficial effects of adopting the above-mentioned further scheme are as follows: The sixteenth and seventeenth resistors of the power-down switching circuit are connected in series between the power input terminal and ground to perform voltage division sampling on the power input terminal. The divided voltage signal is sent to the inverting input terminal of the third operational amplifier, and the non-inverting input terminal of the third operational amplifier is connected to the reference voltage. The third operational amplifier compares the divided voltage signal with the reference voltage. When a power failure occurs at the power input terminal, the divided voltage signal is lower than the reference voltage, and the output terminal of the third operational amplifier outputs a high-level signal. After being divided by the nineteenth and twentieth resistors, this signal drives the sixth MOSFET to conduct. The drain of the sixth MOSFET pulls down the gate potential of the seventh MOSFET, causing the seventh MOSFET to conduct. The source of the seventh MOSFET is connected to the output terminal of the BOOST boost circuit, and the drain of the seventh MOSFET is connected to the third input terminal of the DC / DC power conversion circuit. This transfers the power output from the BOOST boost circuit to the third input terminal of the DC / DC power conversion circuit, realizing automatic and seamless switching of the backup power supply when the input power fails. The entire switching process requires no external control signal intervention, has a fast response speed, and high switching reliability.

[0018] Furthermore, the BOOST boost circuit includes a first inductor, a boost control chip, a fourth diode, and an eleventh capacitor. One end of the first inductor is connected to the power input terminal, and the other end of the first inductor is connected to the drain of the switching transistor of the boost control chip and the positive terminal of the fourth diode. The negative terminal of the fourth diode is grounded through the eleventh capacitor, and the positive terminal of the eleventh capacitor is connected to the negative terminal of the fourth diode. The positive terminal of the eleventh capacitor serves as the output terminal of the BOOST boost circuit.

[0019] The beneficial effects of adopting the above-mentioned further scheme are as follows: one end of the first inductor of the BOOST boost circuit is connected to the power input terminal, and the other end of the first inductor is connected to the drain of the switching transistor of the boost control chip and the positive terminal of the fourth diode. The boost control chip drives the internal switching transistor to periodically turn on and off. When the switching transistor is on, the first inductor stores energy, and when the switching transistor is off, the first inductor releases energy. The induced electromotive force generated by the first inductor is superimposed with the voltage of the power input terminal and charges the eleventh capacitor through the fourth diode, so that the voltage across the eleventh capacitor rises to a value higher than the set value of the power input terminal voltage. The positive terminal of the eleventh capacitor serves as the output terminal of the BOOST boost circuit, and the negative terminal of the fourth diode is grounded through the eleventh capacitor. The fourth diode prevents the charge on the eleventh capacitor from flowing back to the first inductor and the boost control chip. When the BOOST boost circuit is working normally at the power input terminal, it continuously maintains the voltage of the eleventh capacitor at a high level, so that the eleventh capacitor stores sufficient electrical energy. When a momentary interruption occurs at the power input terminal, the electrical energy stored in the eleventh capacitor can be output as a backup power supply to the power-down switching circuit, thereby providing freewheeling energy for the DC / DC power conversion circuit during the momentary interruption.

[0020] Furthermore, the EMC filter circuit includes a first common-mode inductor, a second common-mode inductor, a first Y capacitor, a second Y capacitor, a third Y capacitor, a fourth Y capacitor, a sixteenth capacitor, a seventeenth capacitor, and a twenty-second capacitor. The first input terminal of the first common-mode inductor is connected to the output terminal of the surge current protection circuit, and the second input terminal of the first common-mode inductor is grounded. The first output terminal of the first common-mode inductor is connected to the first input terminal of the second common-mode inductor, and the second output terminal of the first common-mode inductor is connected to the second input terminal of the second common-mode inductor. The first output terminal of the second common-mode inductor is connected to the input terminal of the surge voltage protection circuit, and the second output terminal of the second common-mode inductor is grounded. The first Y capacitor, the second Y capacitor, the third Y capacitor, and the fourth Y capacitor are respectively connected between the first output terminal of the first common-mode inductor, the second output terminal of the first common-mode inductor, the first output terminal of the second common-mode inductor, the second output terminal of the second common-mode inductor, and the casing ground.

[0021] The beneficial effects of adopting the above-mentioned further scheme are as follows: the first input terminal of the first common-mode inductor of the EMC filter circuit is connected to the output terminal of the surge current protection circuit, the second input terminal of the first common-mode inductor is grounded, the first output terminal of the first common-mode inductor is connected to the first input terminal of the second common-mode inductor, the second output terminal of the first common-mode inductor is connected to the second input terminal of the second common-mode inductor, the first output terminal of the second common-mode inductor is connected to the input terminal of the surge voltage protection circuit, and the second output terminal of the second common-mode inductor is grounded. The input current passes through the first common-mode inductor and the second common-mode inductor in sequence. The two stages of common-mode inductors are used in series to present a high impedance to the common-mode interference current, which significantly enhances the ability to suppress common-mode interference. The first Y capacitor, the second Y capacitor, the third Y capacitor, and the fourth Y capacitor are respectively connected between the first output terminal of the first common-mode inductor, the second output terminal of the first common-mode inductor, the first output terminal of the second common-mode inductor, the second output terminal of the second common-mode inductor, and the ground of the casing. They provide a low-impedance discharge path for high-frequency common-mode interference current, allowing the common-mode interference current to bypass to the ground of the casing through the Y capacitors. This effectively prevents common-mode interference from propagating along the power line to the subsequent circuits, ensuring that the subsequent circuits receive clean power that has undergone electromagnetic compatibility filtering.

[0022] Furthermore, the input reverse connection protection circuit, voltage spike processing circuit, surge current protection circuit, EMC filter circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power failure signal circuit, power failure switching circuit, and BOOST boost circuit are all independently set up using discrete analog components.

[0023] The beneficial effects of adopting the above-mentioned further solutions are as follows: the input reverse connection protection circuit, voltage spike processing circuit, surge current protection circuit, EMC filtering circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power-down signal circuit, power-down switching circuit, and BOOST boost circuit are all independently set up using discrete analog components, eliminating the need for integrated control chips. This avoids the space occupied by redundant functional modules and package pins within integrated chips, further reducing the overall size of the power supply system and making it easier to install in space-constrained airborne equipment. When using discrete analog components, the model and parameters of each resistor, capacitor, and semiconductor device in each functional circuit can be independently selected and accurately calculated according to specific performance requirements, ensuring that each circuit operates at its optimal efficiency point. This avoids unnecessary static power consumption and switching losses within integrated chips, improving overall power conversion efficiency. The reduction in power loss directly leads to a reduction in heat generation. When a component in a functional circuit fails, the fault can be confined to a local area because the circuits are connected through clear interfaces. This prevents the fault from spreading and causing the entire power supply system to fail. Furthermore, individual components can be replaced during maintenance, improving the system's reliability and maintainability.

[0024] Furthermore, the input power-down signal circuit includes a sampling resistor voltage divider network and a comparator. The sampling resistor voltage divider network divides the voltage at the power input terminal and outputs a divided voltage signal to the input terminal of the comparator. The comparator compares the divided voltage signal with the reference voltage and outputs a power-down signal to the control terminal of the power-down switching circuit.

[0025] The advantages of adopting the above-mentioned further scheme are as follows: The input power-down signal circuit includes a sampling resistor voltage divider network and a comparator. The sampling resistor voltage divider network divides the voltage at the power input terminal and outputs a divided voltage signal to the input terminal of the comparator. The comparator compares the divided voltage signal with a reference voltage and outputs a power-down signal to the control terminal of the power-down switching circuit. The sampling resistor voltage divider network uses a series resistor voltage divider method, which can achieve real-time sampling of the input voltage without complex active components, and the circuit structure is simple and reliable. By adjusting the resistance ratio of the resistors in the sampling resistor voltage divider network, the input voltage detection threshold can be flexibly set to adapt to the power-down detection requirements of different power supply systems. The comparator compares the divided voltage signal with the reference voltage. When the input voltage is normal, the divided voltage signal is higher than the reference voltage, and the power-down signal output by the comparator remains in the first level state; when the input voltage drops below the detection threshold, the divided voltage signal is lower than the reference voltage, the comparator output state flips, and the power-down signal switches to the second level state, realizing rapid detection of power-down events. The entire testing process does not involve software control or digital processing, has a fast response speed, and eliminates the risk of testing failure due to software malfunction or crash. The test results are accurate and reliable. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a multi-functional integrated power supply technology circuit for civil aircraft according to an embodiment of the present invention; Figure 2 This is a schematic diagram of an input reverse connection protection circuit; Figure 3 This is a schematic diagram of an input undervoltage protection circuit. Figure 4 This is a schematic diagram of a surge current protection circuit; Figure 5 This is a simulation circuit diagram for surge current protection. Figure 6 for Figure 5 The transient simulation waveform of the simulation circuit shown is shown. Figure 7 This is a schematic diagram of a surge voltage protection circuit; Figure 8 This is a simulation circuit diagram for surge voltage protection. Figure 9 for Figure 8 The waveform diagram of the simulation results obtained after transient analysis of the simulated circuit is shown. Figure 10 Block diagram of the principle of instantaneous power interruption conversion technology for power input; Figure 11 This is an EMC filter circuit composed of inductors and capacitors, used for electromagnetic compatibility conversion technology. Detailed Implementation

[0027] like Figure 1As shown in the figure, an integrated power supply circuit for a civil aircraft according to an embodiment of the present invention includes an input reverse connection protection circuit, a voltage spike processing circuit, a surge current protection circuit, an EMC filter circuit, a surge voltage protection circuit, a DC / DC power conversion circuit, an input undervoltage protection circuit, an input power failure signal circuit, a power failure switching circuit, and a BOOST boost circuit. The input terminal of the input reverse connection protection circuit serves as the power input terminal. The output terminal of the input reverse connection protection circuit, the voltage spike processing circuit, the surge current protection circuit, the EMC filter circuit, the surge voltage protection circuit, and the first input terminal of the DC / DC power conversion circuit are connected in series. The input undervoltage protection circuit... The input terminal is connected to the power input terminal, and the output terminal of the input undervoltage protection circuit is connected to the second input terminal of the DC / DC power conversion circuit. The input terminal of the input power-down signal circuit is connected to the power input terminal, and the output terminal of the input power-down signal circuit is connected to the control terminal of the power-down switching circuit. The input terminal of the BOOST boost circuit is connected to the power input terminal, and the output terminal of the BOOST boost circuit is connected to the power input terminal of the power-down switching circuit. The output terminal of the power-down switching circuit is connected to the third input terminal of the DC / DC power conversion circuit. The power-down switching circuit controls whether the electrical energy output by the BOOST boost circuit is transferred to the DC / DC power conversion circuit according to the output signal of the input power-down signal circuit.

[0028] Optionally, in the above technical solutions, such as Figure 2 As shown, the input reverse connection protection circuit includes a first diode D1-2 and a second diode D2-2. The anode of the first diode D1-2 is connected to the first input power supply positive line VIN1+, and the anode of the second diode D2-2 is connected to the second input power supply positive line VIN2+. The cathodes of the first diode D1-2 and the second diode D2-2 are connected together to form the output terminal of the input reverse connection protection circuit, which is connected to the input terminal of the voltage spike processing circuit. The cathode connection node of the first diode D1-2 and the second diode D2-2 is also grounded to GND through capacitor C1-2.

[0029] The input reverse connection protection circuit utilizes the forward conduction characteristic of diodes to achieve reverse connection protection of the input power supply and mutual isolation between multiple input power supplies. Under normal operating conditions, when only the first input power supply positive line VIN1+ provides input voltage, the first diode D1-2 is forward biased and conducts. The input voltage is transmitted through the first diode D1-2 to the output terminal of the input reverse connection protection circuit, providing the voltage required for the normal operation of subsequent circuits. Simultaneously, since the anode of the second diode D2-2 is connected to the second input power supply positive line VIN2+, and the second input power supply positive line VIN2+ has no voltage input at this time, the anode potential of the second diode D2-2 is lower than its cathode potential, and it is reverse biased and cut off. This prevents current from flowing backward from the first input power supply positive line VIN1+ through the first diode D1-2 and the output terminal of the input reverse connection protection circuit to the second input power supply positive line VIN2+.

[0030] When only the second input power positive line VIN2+ provides input voltage, the second diode D2-2 is forward biased and conducts. The input voltage is transmitted through the second diode D2-2 to the output of the input reverse connection protection circuit, providing the voltage required for the normal operation of the subsequent circuits. The first diode D1-2 is reverse biased and cut off because its anode is connected to the first input power positive line VIN1+, which has no voltage input, preventing current from flowing back from the second input power positive line VIN2+ to the first input power positive line VIN1+.

[0031] When the first input power positive line VIN1+ and the second input power positive line VIN2+ simultaneously provide input voltage, both the first diode D1-2 and the second diode D2-2 are forward biased and conduct. The two input voltages converge at the output of the input reverse connection protection circuit after passing through their respective diodes, jointly powering the subsequent circuits. Due to the unidirectional conductivity of diodes, the first diode D1-2 prevents current from flowing from the second input power positive line VIN2+ to the first input power positive line VIN1+, and the second diode D2-2 prevents current from flowing from the first input power positive line VIN1+ to the second input power positive line VIN2+, thus effectively solving the problem of reverse current flow between the two input power supplies.

[0032] When the polarity of the first input power positive line VIN1+ or the second input power positive line VIN2+ is reversed, the corresponding diode is reverse biased and cut off. The input voltage cannot be transmitted to the subsequent circuit through the input reverse connection protection circuit, and the subsequent circuit stops working due to lack of power. Because the diode is in the cutoff state, the reverse voltage is blocked by the diode and will not be applied to the subsequent circuit components, thus protecting them from damage by reverse voltage. Capacitor C1-2 is connected between the output terminal of the input reverse connection protection circuit and ground GND to filter and smooth the output voltage, removing high-frequency noise components from the input voltage and providing a more stable input voltage for the subsequent circuit.

[0033] The input reverse connection protection circuit is designed independently using discrete analog components, eliminating the need for integrated control chips. The circuit structure is simple and highly reliable. It can promptly cut off the power supply path when the input power is reversed, protecting the power supply product and preventing it from working when the input is reversed, thus avoiding damage.

[0034] Optionally, in the above technical solutions, such as Figure 3As shown, the input undervoltage protection circuit includes a first sampling resistor R1-3, a second sampling resistor R2-3, a third sampling resistor R3-3, a fourth sampling resistor R4-3, a sixth sampling resistor R6-3, a seventh sampling resistor R7-3, a first operational amplifier U1-3, and a first MOSFET Q1-3. The first sampling resistor R1-3 and the second sampling resistor R2-3 are connected in series between the power input terminal DC+ and ground GND. One end of the first sampling resistor R1-3 is connected to the power input terminal DC+, and the other end is connected to one end of the second sampling resistor R2-3. The other end of the second sampling resistor R2-3 is grounded GND. The common connection point of the first sampling resistor R1-3 and the second sampling resistor R2-3 is connected to the non-inverting input terminal of the first operational amplifier U1-3, i.e., the third pin of the first operational amplifier U1-3. The third sampling resistor R3-3 and the fourth sampling resistor R4-3 are connected in series between the reference voltage VREF and ground GND. One end of the third sampling resistor R3-3 is connected to the reference voltage VREF, and the other end is connected to one end of the fourth sampling resistor R4-3. The other end of the fourth sampling resistor R4-3 is grounded to GND. The common connection point of the third and fourth sampling resistors R3-3 is connected to the inverting input terminal of the first operational amplifier U1-3, i.e., the second pin of the first operational amplifier U1-3. The fourth pin of the first operational amplifier U1-3 is grounded to GND, and the eighth pin of the first operational amplifier U1-3 is connected to the power supply voltage VCC. The output terminal of the first operational amplifier U1-3, i.e., the first pin of the first operational amplifier U1-3, is connected to the gate G of the first MOSFET Q1-3 after being divided by the sixth sampling resistor R6-3 and the seventh sampling resistor R7-3. One end of the sixth sampling resistor R6-3 is connected to the first pin of the first operational amplifier U1-3, and the other end of the sixth sampling resistor R6-3 is connected to one end of the seventh sampling resistor R7-3. The other end of the seventh sampling resistor R7-3 is grounded (GND). The common connection point of the sixth sampling resistor R6-3 and the seventh sampling resistor R7-3 is connected to the gate (G) of the first MOSFET Q1-3. The source (S) of the first MOSFET Q1-3 is grounded (GND), and the drain (D) of the first MOSFET Q1-3 outputs an undervoltage protection signal UVLO to the second input terminal of the DC / DC power conversion circuit. The input undervoltage protection circuit also includes a first capacitor C1-3, a second capacitor C2-3, a third capacitor C3-3, and a fourth capacitor C4-3. The first capacitor C1-3 is connected between the eighth pin of the first operational amplifier U1-3 and ground GND. The second capacitor C2-3 is connected between the third pin of the first operational amplifier U1-3 and ground GND. The third capacitor C3-3 is connected between the second pin and the first pin of the first operational amplifier U1-3. The fourth capacitor C4-3 is connected between the power input terminal DC+ and ground GND.The input undervoltage protection circuit also includes a fifth sampling resistor R5-3. One end of the fifth sampling resistor R5-3 is connected to the power input terminal DC+, and the other end of the fifth sampling resistor R5-3 is connected to the drain D of the first MOSFET Q1-3. The fifth sampling resistor R5-3 serves as a pull-up resistor for the undervoltage protection signal UVLO.

[0035] The input undervoltage protection circuit is used to meet the requirements of the transient undervoltage and engine start-stop transition tests in DO-160G. During engine startup, a transient voltage of 10.0V to 20.5V may occur at the DC+ power input, lasting up to 35 seconds or the time specified in the equipment specification. The transient undervoltage test requires the equipment operating at its rated voltage to reduce the DC input voltage to 12.0V ± 0.24V for 7 seconds. To ensure that the power supply product can continue to operate without power loss under these harsh conditions, the input undervoltage protection circuit achieves a balance between protection and non-false protection by appropriately setting the undervoltage protection point.

[0036] The input undervoltage protection circuit detects undervoltage by using resistor-based voltage division sampling and voltage comparison. The first sampling resistor R1-3 and the second sampling resistor R2-3 form an input voltage divider network, which divides and samples the input voltage at the DC+ power input terminal. The divided signal is then sent to the non-inverting input (pin 3) of the first operational amplifier U1-3. The third sampling resistor R3-3 and the fourth sampling resistor R4-3 form a reference voltage divider network, which divides the reference voltage VREF to generate a fixed reference voltage divider signal. This signal is then sent to the inverting input (pin 2) of the first operational amplifier U1-3. The first operational amplifier U1-3 acts as a comparator, comparing the sampled voltage at the non-inverting input with the reference voltage divider at the inverting input. By selecting the resistance values ​​of the first sampling resistor R1-3, the second sampling resistor R2-3, the third sampling resistor R3-3, and the fourth sampling resistor R4-3, the input undervoltage protection point can be set below 10V for instantaneous undervoltage and engine start-stop voltage. In other words, the protection circuit will only activate when the input voltage is below 10V, and all instantaneous undervoltage conditions above 10V will not trigger the protection, thereby ensuring that the power supply product continues to work during transient processes such as engine start-up.

[0037] When the input voltage at the power input terminal DC+ is normal and higher than the set undervoltage protection point (e.g., higher than 10V), the voltage at the common connection point of the first sampling resistor R1-3 and the second sampling resistor R2-3 is higher than the reference voltage divider at the common connection point of the third sampling resistor R3-3 and the fourth sampling resistor R4-3. The voltage at the non-inverting input terminal of the first operational amplifier U1-3 is higher than the voltage at the inverting input terminal, and the output terminal (first pin) of the first operational amplifier U1-3 outputs a low-level signal. This low-level signal is applied to the gate G of the first MOSFET Q1-3 after being divided by the sixth sampling resistor R6-3 and the seventh sampling resistor R7-3. Since the voltage at the gate G is lower than the turn-on threshold voltage of the first MOSFET Q1-3, the first MOSFET Q1-3 is in the off state, and its drain D is pulled up to the high level of the power input terminal DC+ through the fifth sampling resistor R5-3. Therefore, the undervoltage protection signal UVLO remains high, and the DC / DC power conversion circuit operates normally after receiving the high-level undervoltage protection signal.

[0038] When the input voltage at the DC+ power input terminal drops below the set undervoltage protection point (e.g., below 10V), the sampling voltage at the common connection point of the first sampling resistor R1-3 and the second sampling resistor R2-3 decreases accordingly. When this voltage is lower than the reference voltage divider at the common connection point of the third sampling resistor R3-3 and the fourth sampling resistor R4-3, the voltage at the non-inverting input terminal of the first operational amplifier U1-3 is lower than the voltage at the inverting input terminal, and the output terminal (first pin) of the first operational amplifier U1-3 outputs a high-level signal. This high-level signal is applied to the gate G of the first MOSFET Q1-3 after being divided by the sixth sampling resistor R6-3 and the seventh sampling resistor R7-3, causing the voltage between the gate G and the source S of the first MOSFET Q1-3 to reach and exceed the turn-on threshold voltage, and the first MOSFET Q1-3 turns on. After the first MOSFET Q1-3 is turned on, its drain D is pulled low to ground GND potential, and the undervoltage protection signal UVLO is pulled low. This low-level signal is transmitted to the second input terminal of the DC / DC power conversion circuit. The DC / DC power conversion circuit performs undervoltage protection action according to the received low-level undervoltage protection signal, stopping power conversion or entering safe mode.

[0039] The second capacitor C2-3 is connected between the non-inverting input of the first operational amplifier U1-3 and ground GND to filter out high-frequency noise in the sampled signal and prevent comparator malfunction. The third capacitor C3-3 is connected between the inverting input and output of the first operational amplifier U1-3 as a feedback capacitor to improve the frequency characteristics and stability of the comparator. The fourth capacitor C4-3 is connected between the power input DC+ and ground GND to filter the input voltage and reduce the impact of input ripple on sampling accuracy. The first capacitor C1-3 is connected between the power supply pin (pin 8) of the first operational amplifier U1-3 and ground GND to provide power decoupling for the first operational amplifier U1-3 and ensure stable operation of its internal circuitry. Through the above circuit structure and parameter configuration, the input undervoltage protection circuit can meet the stringent instantaneous undervoltage and engine start-stop switching test requirements of the DO-160G standard, and can reliably provide a protection signal in the event of a real undervoltage fault, ensuring the safe operation of the entire power system.

[0040] Optionally, in the above technical solutions, such as Figure 4 As shown, the surge current protection circuit includes a first resistor R1-4, a second resistor R2-4, a third resistor R3-4, a fourth resistor R4-4, a fifth resistor R5-4, a first Zener diode Z1-4, a fifth capacitor C1-4, a sixth capacitor C2-4, a seventh capacitor C3-4, a first transistor Q1-4, and a second MOSFET Q2-4. The first resistor R1-4 and the second resistor R2-4 are connected in series between the power input terminal VIN+ and ground GND. One end of the first resistor R1-4 is connected to the power input terminal VIN+, and the other end is connected to one end of the second resistor R2-4, which is grounded to GND. The common connection point of the first resistor R1-4 and the second resistor R2-4 is connected to ground GND through the first Zener diode Z1-4. The positive terminal of the first Zener diode Z1-4 is grounded to GND, and the negative terminal of the first Zener diode Z1-4 is connected to the common connection point of the first resistor R1-4 and the second resistor R2-4. The fifth capacitor C1-4 is connected in parallel with the first Zener diode Z1-4. One end of the fifth capacitor C1-4 is connected to the common connection point of the first resistor R1-4 and the second resistor R2-4, and the other end of the fifth capacitor C1-4 is grounded to GND.

[0041] The third resistor R3-4 and the sixth capacitor C2-4 are connected in series between the power input terminal VIN+ and ground GND. One end of the third resistor R3-4 is connected to the power input terminal VIN+, and the other end of the third resistor R3-4 is connected to one end of the sixth capacitor C2-4, which is grounded to GND. The common connection point of the third resistor R3-4 and the sixth capacitor C2-4 is connected to the base B of the first transistor Q1-4. The emitter E of the first transistor Q1-4 is grounded to GND. The collector C of the first transistor Q1-4 is connected to the power input terminal VIN+ through the fourth resistor R4-4. One end of the fourth resistor R4-4 is connected to the power input terminal VIN+, and the other end of the fourth resistor R4-4 is connected to the collector C of the first transistor Q1-4. The collector C of the first transistor Q1-4 is also connected to the gate G of the second MOSFET Q2-4, and the gate G of the second MOSFET Q2-4 is a GS network node. The source (S) of the second MOSFET Q2-4 is grounded to GND through the fifth resistor R5-4. The drain (D) of the second MOSFET Q2-4 serves as the output terminal IFLD of the surge current protection circuit, which is connected to the input terminal of the EMC filter circuit. The seventh capacitor C3-4 is connected between the power input terminal VIN+ and ground GND. One end of the seventh capacitor C3-4 is connected to the power input terminal VIN+, and the other end is grounded to GND.

[0042] The surge current protection circuit is used to meet the input inrush current limitation requirements of the DO-160G standard. According to DO-160G, within the first 3.0 milliseconds of power input, the peak inrush current should be less than 9 times the maximum steady-state load current; between 3.0 milliseconds and 500 milliseconds, the peak inrush current should be less than 4 times the maximum steady-state load current; between 500 milliseconds and 2 seconds, the peak inrush current should be less than 2 times the maximum steady-state load current; after 2 seconds, the inrush current returns to its rated value. The surge current protection circuit limits the magnitude of the inrush current at the moment of power-on, ensuring that the input current meets the above standard requirements throughout the various time periods.

[0043] The first resistor R1-4 and the second resistor R2-4 form an input power supply voltage divider network to divide the voltage at the power input terminal VIN+. The first Zener diode Z1-4 is connected between the common connection point of the first resistor R1-4 and the second resistor R2-4 and ground GND. Utilizing the voltage clamping characteristic of the first Zener diode Z1-4, the voltage at the common connection point of the first resistor R1-4 and the second resistor R2-4 is clamped to a stable voltage value, preventing excessive voltage at this node from damaging subsequent circuits. The fifth capacitor C1-4 is connected in parallel with the first Zener diode Z1-4 to filter the voltage across the first Zener diode Z1-4, eliminating voltage fluctuations and ensuring the stability of the clamped voltage.

[0044] When an input voltage is applied to the power input terminal VIN+, the initial voltage across the seventh capacitor C3-4 is zero, and C3-4 is short-circuited. The input current is approximately equal to the voltage at the power input terminal VIN+ divided by the resistance of the fourth resistor R4-4, i.e., I = VIN+ / R4-4. The input current charges the seventh capacitor C3-4 through the fourth resistor R4-4. At this time, the gate (G) voltage of the second MOSFET Q2-4 is determined by the collector (C) potential of the first transistor Q1-4, while the base (B) voltage of the first transistor Q1-4 is determined by the voltage at the common connection point of the third resistor R3-4 and the sixth capacitor C2-4.

[0045] During the initial power-on phase, the voltage at the power input terminal VIN+ charges the sixth capacitor C2-4 through the third resistor R3-4, gradually increasing the voltage across C2-4. When the surge current flowing through the second MOSFET Q2-4 has not yet exceeded the set value, the base voltage (B) of the first transistor Q1-4 is lower than its turn-on threshold voltage (approximately 0.7 volts), and Q1-4 is in the off state. At this time, the collector (C) of the first transistor Q1-4 is pulled up to the high level of the power input terminal VIN+ through the fourth resistor R4-4, and the gate (G) of the second MOSFET Q2-4 becomes high and turns on. The input current flows through the drain (D) and source (S) of the second MOSFET Q2-4 to the fifth resistor R5-4 and then to ground (GND). The output terminal IFLD of the surge current protection circuit normally outputs current to the subsequent circuit.

[0046] When the input surge current exceeds the set value, the voltage drop across the fifth resistor R5-4 increases, and the voltage generated across the fifth resistor R5-4 by the source current flowing through the second MOSFET Q2-4 rises. This voltage is coupled to the base B of the first transistor Q1-4 through the RC network formed by the third resistor R3-4 and the sixth capacitor C2-4, causing the base B voltage of the first transistor Q1-4 to reach the turn-on threshold voltage of approximately 0.7 volts, and the first transistor Q1-4 turns on. After the first transistor Q1-4 turns on, its collector C potential is pulled down to ground GND potential, and the gate G voltage of the second MOSFET Q2-4 is subsequently pulled down. The voltage between the gate G and source S of the second MOSFET Q2-4 drops below the turn-on threshold voltage of the second MOSFET Q2-4, and the second MOSFET Q2-4 turns off. After the second MOSFET Q2-4 is turned off, the current flowing through the fifth resistor R5-4 decreases, the voltage drop across the fifth resistor R5-4 decreases, and the base voltage B of the first transistor Q1-4 decreases accordingly. When the base voltage B is lower than the turn-on threshold voltage, the first transistor Q1-4 is turned off, and the gate G of the second MOSFET Q2-4 is pulled up to a high level again, and the second MOSFET Q2-4 is turned on again.

[0047] The above process constitutes a dynamic feedback control loop. By switching the on and off states of the first transistor Q1-4, the gate voltage (G) of the second MOSFET Q2-4 is controlled, thereby limiting the magnitude of the inrush current flowing through the second MOSFET Q2-4. By matching and adjusting the parameter values ​​of the fourth resistor R4-4, the third resistor R3-4, the fifth resistor R5-4, and the sixth capacitor C2-4, the protection threshold value of the inrush current can be precisely set, ensuring that the input inrush current meets the peak current limit requirements within each time period specified in DO-160G. The time constant network formed by the sixth capacitor C2-4 and the third resistor R3-4 determines the response speed of the base voltage (B) of the first transistor Q1-4, thus affecting the response time and protection characteristics of the inrush current protection. By properly configuring these parameters, the inrush current protection circuit can reliably limit the inrush current at the moment of power-on, protecting downstream circuit devices from damage caused by excessive inrush current.

[0048] Figure 5 This is a simulation circuit diagram of a surge current protection circuit, that is, for Figure 4 The simulation model shown is the one built for circuit simulation verification of the surge current protection circuit. Figure 5 According to Figure 4 The circuit connection relationship was determined by importing each discrete analog component, including the first resistor R1-4, the second resistor R2-4, the first Zener diode Z1-4, the fifth capacitor C1-4, the first transistor Q1-4, the third resistor R3-4, the sixth capacitor C2-4, the second MOSFET Q2-4, the fourth resistor R4-4, the fifth resistor R5-4, and the seventh capacitor C3-4, into the simulation platform one by one, and completing the circuit connection according to the actual electrical connection relationship. Figure 5 The simulation circuit is configured with an input voltage source at the power input terminal VIN+, which is set according to the power-on transient conditions specified in the DO-160G standard. An equivalent model of the subsequent load is also set to simulate the input characteristics of the EMC filter circuit and the subsequent power conversion circuit connected to the output terminal IFLD of the surge current protection circuit in actual operation. Figure 5 The simulation circuit also includes voltage and current probes for observing waveforms at key nodes. These include a current probe for monitoring the input current, a voltage probe for monitoring the base (B) voltage of the first transistor Q1-4, a voltage probe for monitoring the gate (G) voltage (i.e., the GS network node voltage) of the second MOSFET Q2-4, and a voltage probe for monitoring the power input VIN+ voltage. These probes correspond to... Figure 6 Waveform acquisition across four channels. (Through...) Figure 5 The simulation circuit shown can simulate the dynamic response process of the surge current protection circuit at the moment of power-on in a computer-aided design environment, thereby verifying whether its surge current limiting function meets the time limit requirements for peak surge current in the DO-160G standard.

[0049] Figure 6 yes Figure 5 The transient simulation waveform of the circuit shown is as follows. Figure 6 The waveform curves of the four channels are presented sequentially from top to bottom, corresponding to... Figure 5 The measurement results of the four monitoring probes set up in the middle. Figure 6 The first channel in the diagram is a green waveform, which represents the curve of the input current at the power input terminal VIN+ changing over time, i.e., the current waveform flowing through the input terminal of the surge current protection circuit. Figure 6 The second channel is a red waveform, which represents the curve of the base B voltage of the first transistor Q1-4 changing over time, and is used to reflect the conduction state of the first transistor Q1-4. Figure 6 The third channel is a pink waveform, which represents the curve of the gate G voltage (i.e., GS network node voltage) of the second MOSFET Q2-4 changing over time, and is used to reflect the change of the gate drive voltage of the second MOSFET Q2-4. Figure 6 The fourth channel is also a red waveform, which represents the curve of the input voltage at the power input terminal VIN+ changing over time, i.e., the voltage waveform applied to the input terminal of the surge current protection circuit.

[0050] from Figure 6 As shown in the simulation waveforms, when the input voltage at the power input terminal VIN+ begins to rise in a step at time zero, the gate voltage (pink waveform) of the second MOSFET Q2-4 rises accordingly, turning on the second MOSFET Q2-4 and causing the input current (green waveform) to increase. As the input current increases, the voltage drop across the fifth resistor R5-4 increases. This voltage is coupled to the base (B) of the first transistor Q1-4 through the third resistor R3-4 and the sixth capacitor C2-4, causing the base voltage (second channel of the red waveform) of the first transistor Q1-4 to gradually increase. When the base voltage of the first transistor Q1-4 reaches the turn-on threshold of approximately 0.7 volts, the first transistor Q1-4 turns on, its collector (C) potential is pulled low, which in turn pulls down the gate voltage (pink waveform) of the second MOSFET Q2-4, causing the second MOSFET Q2-4 to turn off. After the second MOSFET Q2-4 is turned off, the input current (green waveform) drops rapidly, the voltage drop across the fifth resistor R5-4 decreases, and the base voltage (B) of the first transistor Q1-4 (red waveform, second channel) also decreases. When this voltage falls below the turn-on threshold, the first transistor Q1-4 turns off, and the gate voltage (G) of the second MOSFET Q2-4 (pink waveform) is pulled up again, turning the second MOSFET Q2-4 on again, and the input current (green waveform) rises again. This process repeats, limiting the input current (green waveform) to a set peak range and preventing it from rising indefinitely.

[0051] Figure 6 The red waveform in the fourth channel represents the input voltage waveform. It can be seen that the input voltage maintains a stable step state throughout the simulation, while the input current (green waveform) is effectively limited to a low peak level in the initial stage and then gradually stabilizes. By comparison... Figure 6 The amplitude of the current waveform at various time intervals verifies that within the first 3.0 milliseconds, the peak value of the input current is less than 9 times the maximum steady-state load current; within the time interval from 3.0 milliseconds to 500 milliseconds, the peak value of the input current is less than 4 times the maximum steady-state load current; and within the time interval from 500 milliseconds to 2 seconds, the peak value of the input current is less than 2 times the maximum steady-state load current. Figure 6 The alternating changes in the base B voltage waveform of the first transistor Q1-4 (red waveform, second channel) and the gate G voltage waveform of the second MOSFET Q2-4 (pink waveform) clearly demonstrate the dynamic process by which the surge current protection circuit limits surge current through feedback control. Figure 6 The simulation results fully demonstrate that by reasonably matching the parameters of the fourth resistor R4-4, the third resistor R3-4, the fifth resistor R5-4, and the sixth capacitor C2-4, the surge current protection circuit can strictly limit the inrush current at the moment of power-on to within the range specified by the DO-160G standard, thereby ensuring that the downstream circuit devices are not impacted by excessive surge current during power-on, verifying the correctness and effectiveness of the surge current protection circuit design.

[0052] Optionally, in the above technical solutions, such as Figure 7As shown, the surge voltage protection circuit includes a third MOSFET Q1-7, a fourth MOSFET Q2-7, a fifth MOSFET Q3-7, a sixth resistor R1-7, a seventh resistor R2-7, an eighth resistor R3-7, a ninth resistor R4-7, a tenth resistor R5-7, an eleventh resistor R6-7, a twelfth resistor R7-7, a thirteenth resistor R8-7, a second Zener diode Z1-7, a third diode D1-7, an eighth capacitor C1-7, a ninth capacitor C2-7, a tenth capacitor C3-7, and a second operational amplifier U6-7. The drain (D) of the third MOSFET Q1-7 is connected to the power input terminal VIN+, and the source (S) of the third MOSFET Q1-7 serves as the output terminal DC+ of the surge voltage protection circuit. The output terminal DC+ of the surge voltage protection circuit is connected to the first input terminal of the DC / DC power conversion circuit. The fourth MOSFET Q2-7 and the fifth MOSFET Q3-7 form a current mirror. The emitter E of the fourth MOSFET Q2-7 is connected to the emitter E of the fifth MOSFET Q3-7 and then grounded through the ninth resistor R4-7. The base B of the fourth MOSFET Q2-7 and the base B of the fifth MOSFET Q3-7 are interconnected. The collector C of the fourth MOSFET Q2-7 is connected to the gate G of the third MOSFET Q1-7, and the collector C of the fifth MOSFET Q3-7 is connected to the power supply voltage VCC. One end of the sixth resistor R1-7 is connected to the source S of the third MOSFET Q1-7, and the other end of the sixth resistor R1-7 is connected to the common connection point of the base B of the fourth MOSFET Q2-7 and the base B of the fifth MOSFET Q3-7. One end of the seventh resistor R2-7 is connected to the gate G of the third MOSFET Q1-7, and the other end of the seventh resistor R2-7 is grounded. One end of the eighth resistor R3-7 is connected to the gate G of the third MOSFET Q1-7, and the other end is connected to the negative terminal of the second Zener diode Z1-7. The positive terminal of the second Zener diode Z1-7 is connected to the common connection point of the base B of the fourth MOSFET Q2-7 and the base B of the fifth MOSFET Q3-7. The tenth resistor R5-7, the eleventh resistor R6-7, the twelfth resistor R7-7, the second operational amplifier U6-7, the thirteenth resistor R8-7, the third diode D1-7, and the eighth capacitor C1-7 constitute a self-excited oscillation circuit and a bootstrap circuit. One end of the tenth resistor R5-7 is connected to the power supply voltage VCC, and the other end is connected to one end of the eleventh resistor R6-7. The other end of the eleventh resistor R6-7 is connected to the non-inverting input terminal of the second operational amplifier U6-7, i.e., the third pin of the second operational amplifier U6-7. One end of the twelfth resistor R7-7 is connected to the reference voltage VREF, and the other end of the twelfth resistor R7-7 is connected to the non-inverting input of the second operational amplifier U6-7. The inverting input of the second operational amplifier U6-7, i.e., the second pin of the second operational amplifier U6-7, is connected to the source S of the third MOSFET Q1-7.The output terminal of the second operational amplifier U6-7, i.e., its first pin, is connected to the anode of the third diode D1-7 via the thirteenth resistor R8-7. The cathode of the third diode D1-7 is connected to one end of the eighth capacitor C1-7, and the other end of the eighth capacitor C1-7 is connected to the gate G of the third MOSFET Q1-7. The ninth capacitor C2-7 is connected between the non-inverting input terminal of the second operational amplifier U6-7 and ground. The tenth capacitor C3-7 is connected between the output terminal and the inverting input terminal of the second operational amplifier U6-7. The fourth pin of the second operational amplifier U6-7 is grounded, and the eighth pin is connected to the power supply voltage VCC.

[0053] The surge voltage protection circuit is used to suppress transient high-voltage surges on the external power line, clamping the voltage output to the subsequent DC / DC power conversion circuit within a safe range, thereby protecting the downstream circuit components from damage by high-voltage surges. The surge voltage protection circuit provides a stable bias through a mirrored current source and provides a drive voltage higher than the input voltage to the gate G of the third MOSFET Q1-7 through a self-oscillating circuit and a bootstrap circuit, enabling the third MOSFET Q1-7 to operate in the linear region to achieve voltage clamping.

[0054] The fourth MOSFET Q2-7 and the fifth MOSFET Q3-7 form a current mirror. The collector C of the fifth MOSFET Q3-7 is connected to the power supply voltage VCC, and its base B is connected to the base B of the fourth MOSFET Q2-7. The emitters E of the fourth MOSFET Q2-7 and the fifth MOSFET Q3-7 are grounded through the ninth resistor R4-7. The sixth resistor R1-7 is connected between the source S of the third MOSFET Q1-7 and the base B of the fourth MOSFET Q2-7. The second Zener diode Z1-7 is connected between the gate G of the third MOSFET Q1-7 and the base B of the fourth MOSFET Q2-7. The voltage drop across the sixth resistor R1-7 determines the potential of the base B of the fourth MOSFET Q2-7. The voltage of the sixth resistor R1-7 relative to ground is the reference voltage VREF multiplied by the resistance of the sixth resistor R1-7 divided by the resistance of the eighth resistor R3-7, plus the reference voltage VREF, i.e., the voltage value is equal to VREF × R1-7 / R3-7 + VREF. This voltage value is the clamping voltage threshold set by the surge voltage protection circuit.

[0055] The self-excited oscillation circuit and bootstrap circuit consist of resistors R5-7 (10th), R6-7 (11th), R7-7 (12th), operational amplifier U6-7 (2nd), resistor R8-7 (13th), diode D1-7 (3rd), and capacitor C1-7 (8th). The non-inverting input of operational amplifier U6-7 is connected to the power supply voltage VCC through resistors R5-7 and R6-7, and to the reference voltage VREF through resistor R7-7. The voltage at the non-inverting input of operational amplifier U6-7 is determined by both VCC and VREF. The inverting input of operational amplifier U6-7 is connected to the source S of MOSFET Q1-7, which is the output DC+ of the surge voltage protection circuit. The output of operational amplifier U6-7 charges and discharges capacitor C1-7 through resistor R8-7 and diode D1-7. The other end of capacitor C1-7 is connected to the gate G of MOSFET Q1-7. When the output of the second operational amplifier U6-7 is high, the third diode D1-7 conducts, and current flows through the thirteenth resistor R8-7 and the third diode D1-7 to charge the eighth capacitor C1-7, increasing the voltage across the eighth capacitor C1-7. When the output of the second operational amplifier U6-7 is low, the third diode D1-7 is cut off, and the eighth capacitor C1-7 discharges through other paths. The self-excited oscillation circuit creates a continuous driving voltage between the gate G and source S of the third MOSFET Q1-7 due to the voltage across the eighth capacitor C1-7. This driving voltage is superimposed on the voltage at the power input terminal VIN+, making the gate G voltage of the third MOSFET Q1-7 equal to the voltage at the power input terminal VIN+ plus the bootstrap voltage. This ensures that the voltage difference between the gate G and source S of the third MOSFET Q1-7 is large enough to allow the third MOSFET Q1-7 to operate in the linear region.

[0056] Under normal operating conditions, when the input voltage at the power input terminal VIN+ is lower than the set clamping voltage threshold, the source S voltage of the third MOSFET Q1-7 is equal to the input voltage minus the on-state voltage drop of the third MOSFET Q1-7. The voltage at the inverting input terminal of the second operational amplifier U6-7 is lower than the voltage at the non-inverting input terminal. The output terminal of the second operational amplifier U6-7 remains at a high level. The gate G of the third MOSFET Q1-7 receives sufficient driving voltage and is fully turned on. The input voltage is transmitted to the output terminal DC+ of the surge voltage protection circuit with almost no attenuation, and the subsequent circuits operate normally.

[0057] When an external surge voltage occurs at the power input terminal VIN+, causing the input voltage to rise instantaneously and exceed the set clamping voltage threshold VREF×R1-7 / R3-7+VREF, the source voltage (S) of the third MOSFET Q1-7 increases accordingly. This causes the voltage at the inverting input of the second operational amplifier U6-7 to rise and exceed the voltage at the non-inverting input, resulting in a decrease in the output voltage of the second operational amplifier U6-7. The charge on the eighth capacitor C1-7 is adjusted through the thirteenth resistor R8-7 and the third diode D1-7, thus correspondingly regulating the gate voltage (G) of the third MOSFET Q1-7. At this time, the voltage difference between the gate (G) and source (S) of the third MOSFET Q1-7 decreases, the channel resistance of the third MOSFET Q1-7 increases, and the third MOSFET Q1-7 enters the linear region. The voltage drop between its drain (D) and source (S) increases, thereby clamping the source voltage (S) of the third MOSFET Q1-7, i.e., the voltage at the output DC+ of the surge voltage protection circuit, to the set clamping voltage value VREF×R1-7 / R3-7+VREF. Regardless of the input surge voltage, the output DC+ voltage remains stable near the clamping voltage value, never exceeding the safe range. This ensures that subsequent DC / DC power conversion circuits and other components are not damaged by overvoltage. When the external surge voltage disappears and the input voltage returns to normal, the voltage at the inverting input of the second operational amplifier U6-7 decreases, the output voltage of U6-7 increases, the gate G drive voltage of the third MOSFET Q1-7 recovers, and Q1-7 returns to full conduction, allowing the input voltage to be transmitted normally to the output. The ninth capacitor C2-7 and the tenth capacitor C3-7 are used to filter noise interference at the input and output of the operational amplifier, improving circuit stability and anti-interference capabilities. By appropriately selecting the values ​​of the sixth resistor R1-7 and the eighth resistor R3-7, the clamping voltage value can be precisely set to meet the input voltage upper limit requirements of different subsequent circuits, ensuring the power supply system operates safely and reliably under the surge voltage conditions specified in DO-160G.

[0058] Figure 8 This is a simulation circuit diagram of a surge voltage protection circuit, that is, a circuit designed for use in a computer simulation environment. Figure 7 The simulation verification model of the complete topology of the surge voltage protection circuit shown is constructed. Figure 8 The simulation circuit includes all discrete analog components such as the third MOSFET Q1-7 (labeled M1 in the simulation model), the fourth MOSFET Q2-7, the fifth MOSFET Q3-7, the sixth resistor R1-7 to the thirteenth resistor R8-7, the second Zener diode Z1-7, the third diode D1-7, the eighth capacitor C1-7, the ninth capacitor C2-7, the tenth capacitor C3-7, and the second operational amplifier U6-7, and is arranged according to... Figure 7 The electrical connection relationships determined in the diagram complete the wiring connections between the various components. Figure 8The simulation circuit in the simulation circuit has a transient pulse voltage source set at the power input terminal VIN+. This pulse voltage source is used to simulate the instantaneous overvoltage surge conditions that occur on the power line as specified in the DO-160G standard. The pulse voltage source is set to jump instantaneously from the normal 28-volt DC voltage to a high voltage of 100 volts and maintain it for a duration of 100 milliseconds to simulate the voltage spikes and surges that may occur in the actual aircraft power supply system. Figure 8 The simulation circuit in the simulation has an appropriate equivalent load resistor connected at the DC+ output terminal of the surge voltage protection circuit to simulate the input impedance characteristics of the subsequent DC / DC power conversion circuit, making the simulation conditions closer to the actual working conditions. Figure 8 The simulation circuit also includes multiple voltage monitoring probes. The first probe is connected to the drain D of the third MOSFET Q1-7 to acquire the voltage waveform at the drain D of the third MOSFET Q1-7. This probe corresponds to... Figure 9 The first channel shows the green waveform; the second probe is connected to the source S of the third MOSFET Q1-7 to acquire the voltage waveform at the source S of the third MOSFET Q1-7. This probe corresponds to... Figure 9 The second channel red waveform. (Through...) Figure 8 The simulation circuit shown can be used to run transient analysis in simulation software to observe the dynamic response characteristics of the surge voltage protection circuit when a transient surge occurs in the input voltage, thereby verifying whether the clamping function of the surge voltage protection circuit meets the design requirements.

[0059] Figure 9 yes Figure 8 The waveform diagram of the simulation results obtained after transient analysis of the simulated circuit is shown. Figure 9 The voltage waveform curves of the two channels are presented from top to bottom, respectively corresponding to... Figure 8 The measurement results of the two voltage monitoring probes set in the middle. Figure 9 The first channel in the diagram is a green waveform, which represents the curve of the voltage change of the drain D of the third MOSFET Q1-7 over time. Since the drain D of the third MOSFET Q1-7 is directly connected to the power input terminal VIN+, the green waveform actually reflects the voltage change applied to the input terminal of the surge voltage protection circuit. Figure 9 The second channel is a red waveform, which represents the curve of the voltage change of the source S of the third MOSFET Q1-7 over time. Since the source S of the third MOSFET Q1-7 is the output terminal DC+ of the surge voltage protection circuit, the red waveform actually reflects the voltage change output to the subsequent DC / DC power conversion circuit after being clamped by the surge voltage protection circuit.

[0060] from Figure 9The simulation waveforms shown clearly demonstrate the surge voltage protection circuit's effect on suppressing input surge voltage. In the initial stage of the simulation, Figure 9 The green waveform in the image, representing the drain voltage (D) of the third MOSFET Q1-7, is stable at the normal 28-volt DC voltage level. Figure 9 The red waveform in the simulation, representing the source voltage (S) of the third MOSFET Q1-7, also stabilizes at a value close to 28 volts. This indicates that under normal operating voltage, the third MOSFET Q1-7 is fully conducting, and the input voltage is transmitted to the surge voltage protection circuit's output DC+ with almost no loss, allowing the subsequent circuit to operate normally. When the simulation reaches a specific point... Figure 9 The green waveform in the image, representing the drain voltage (D) of the third MOSFET Q1-7, jumps instantaneously from 28 volts to a high voltage of 100 volts. This high-voltage state lasts for 100 milliseconds to simulate a transient surge voltage on the external power line. At the same moment the green waveform jumps to 100 volts... Figure 9 The red waveform, representing the source voltage (S) of the third MOSFET Q1-7, did not jump to 100 volts along with the green waveform. Instead, it was stably clamped at a voltage level of approximately 36 volts. This phenomenon indicates that when the external surge voltage exceeds the clamping voltage threshold set by the surge voltage protection circuit, the third MOSFET Q1-7 transitions from a fully conducting state to the linear operating region. The voltage drop between the drain (D) and source (S) of the third MOSFET Q1-7 increases, absorbing excess voltage energy. This ensures that the source voltage (S) of the third MOSFET Q1-7 is strictly limited to a safe range of 36 volts and does not increase with the increase of the input surge voltage.

[0061] During the entire 100-millisecond surge duration, Figure 9 The red waveform in the image maintains a stable 36-volt clamping voltage, demonstrating that the self-oscillating circuit and bootstrap circuit in the surge voltage protection circuit continuously provide a stable drive voltage to the gate G of the third MOSFET Q1-7, ensuring that the third MOSFET Q1-7 operates stably in the linear region and thus guaranteeing that the output voltage does not change with the surge fluctuations at the input. When the 100-millisecond surge duration ends... Figure 9 The green waveform in the image, representing the drain voltage (D) of the third MOSFET Q1-7, rapidly drops from 100 volts to the normal value of 28 volts. Figure 9 The red waveform in the image, which is the source voltage (S) of the third MOSFET Q1-7, also smoothly transitions from 36 volts back to the normal operating voltage of close to 28 volts. The third MOSFET Q1-7 returns to the fully conducting state from the linear region, and the input voltage is transmitted normally to the subsequent circuit. Throughout the process, there are no spikes or drops in the output voltage. Figure 9The simulation results fully verify that the surge voltage protection circuit can effectively clamp the high voltage surge at the input terminal to the preset safe voltage value, keeping the voltage at the output terminal DC+ of the surge voltage protection circuit at around 36 volts. This ensures that the subsequent DC / DC power conversion circuit and other devices connected to the output terminal DC+ of the surge voltage protection circuit will not be subjected to overvoltage stress due to the sudden increase in input voltage, effectively protecting the safe operation of the subsequent circuit devices and proving the correctness of the surge voltage protection circuit design and the reliability of the clamping function.

[0062] like Figure 10As shown, the power-down switching circuit includes a third operational amplifier U1-10, a sixth MOSFET Q2-10, a seventh MOSFET Q3-10, a fourteenth resistor R1-10, a fifteenth resistor R2-10, a sixteenth resistor R3-10, a seventeenth resistor R4-10, an eighteenth resistor R5-10, a nineteenth resistor R6-10, and a twentieth resistor R7-10. The sixteenth resistor R3-10 and the seventeenth resistor R4-10 are connected in series between the power input terminal VIN+ and ground GND. One end of the sixteenth resistor R3-10 is connected to the power input terminal VIN+, and the other end is connected to one end of the seventeenth resistor R4-10. The other end of the seventeenth resistor R4-10 is ground GND. The common connection point of the sixteenth resistor R3-10 and the seventeenth resistor R4-10 is connected to the inverting input terminal of the third operational amplifier U1-10, i.e., the fourth pin of the third operational amplifier U1-10. The non-inverting input of the third operational amplifier U1-10, i.e., pin 3, is connected to the reference voltage VREF. Pin 8 of the third operational amplifier U1-10 is connected to the power supply voltage VCC, and pin 4 is grounded (GND). The output of the third operational amplifier U1-10, i.e., pin 1, is connected to the gate G of the sixth MOSFET Q2-10 through a voltage divider formed by resistors R6-10 (nineteenth) and R7-10 (twentieth). One end of resistor R6-10 is connected to pin 1 of the third operational amplifier U1-10, and the other end is connected to one end of resistor R7-10, which is grounded (GND). The common connection point of resistors R6-10 and R7-10 is connected to the gate G of the sixth MOSFET Q2-10. The source (S) of the sixth MOSFET Q2-10 is grounded to GND, and its drain (D) is connected to the gate (G) of the seventh MOSFET Q3-10. The source (S) of the seventh MOSFET Q3-10 is connected to the output of the BOOST boost circuit, and its drain (D) is connected to the third input terminal of the DC / DC power converter circuit, i.e., the positive input terminal VO+. The eighteenth resistor R5-10 is connected between the power input terminal VIN+ and the non-inverting input terminal of the third operational amplifier U1-10. The fourteenth resistor R1-10 is connected between the gate (G) and source (S) of the seventh MOSFET Q3-10, and the fifteenth resistor R2-10 is connected between the gate (G) of the seventh MOSFET Q3-10 and ground (GND). The power-down switching circuit also includes a twelfth capacitor C2-10, which is connected between the gate (G) of the seventh MOSFET Q3-10 and ground (GND).

[0063] The BOOST boost circuit includes a first inductor L1-10, a boost control chip U2-10, a fourth diode D2-10, and an eleventh capacitor C1-10. One end of the first inductor L1-10 is connected to the power input terminal VIN+, and the other end is connected to the drain of the switching transistor in the boost control chip U2-10 and the anode of the fourth diode D2-10. The boost control chip U2-10 is packaged in an SOIC-8 package. Its pin 1 is COMP, pin 2 is FB, pin 3 is CS, pin 4 is RC, pin 5 is GND, pin 6 is OUT (i.e., the drain of the internal switching transistor), pin 7 is VCC, and pin 8 is REF. Pin 5 of the boost control chip U2-10 is grounded (GND), pin 7 is connected to the power supply voltage VCC, and pin 6 is connected to the other end of the first inductor L1-10 and the anode of the fourth diode D2-10. The cathode of the fourth diode D2-10 is connected to the anode of the eleventh capacitor C1-10. The cathode of the eleventh capacitor C1-10 is grounded to GND, and the anode of the eleventh capacitor C1-10 is simultaneously connected to the source (S) of the seventh MOSFET Q3-10. The anode of the eleventh capacitor C1-10 serves as the output terminal of the BOOST boost circuit. The BOOST boost circuit also includes a thirteenth capacitor C3-10, a fourteenth capacitor C4-10, and a fifteenth capacitor C5-10. The thirteenth capacitor C3-10 is connected between the fourth pin of the boost control chip U2-10 and ground (GND). The fourteenth capacitor C4-10 is connected between the power input terminal VIN+ and ground (GND). The fifteenth capacitor C5-10 is connected between the anode of the eleventh capacitor C1-10 and ground (GND). The fourteenth resistor R1-10, the fifteenth resistor R2-10, and the twelfth capacitor C2-10 constitute the gate drive network of the seventh MOSFET Q3-10.

[0064] The power-down switching circuit and the BOOST boost circuit together constitute the power input instantaneous power interruption conversion function, used to meet the requirement that the load equipment continues to operate normally when the power input of the aircraft power supply system is momentarily interrupted. Under normal operating conditions, the power input terminal VIN+ provides a stable input voltage. Resistors 16-10 and 17-10 form a voltage divider sampling network to sample the voltage at the power input terminal VIN+. The sampled signal is sent to the inverting input terminal (pin 4) of the third operational amplifier U1-10. The non-inverting input terminal (pin 3) of the third operational amplifier U1-10 is connected to the reference voltage VREF. The third operational amplifier U1-10 acts as a comparator, comparing the sampled voltage at the inverting input terminal with the reference voltage VREF at the non-inverting input terminal. When the input voltage is normal, the sampled voltage at the common connection point of resistors 16-10 and 17-10 is higher than the reference voltage VREF, and the output terminal (pin 1) of the third operational amplifier U1-10 outputs a low-level signal. The low-level signal, after being divided by resistors R6-10 (19th resistor) and R7-10 (20th resistor), is applied to the gate G of the sixth MOSFET Q2-10. Since the gate G voltage of the sixth MOSFET Q2-10 is lower than its turn-on threshold voltage, Q2-10 is in the off state. At this time, the gate G of the seventh MOSFET Q3-10 is pulled up to the output voltage of the BOOST boost circuit through resistor R1-10 (14th resistor). Because the seventh MOSFET Q3-10 is a P-channel MOSFET, the voltage between its gate G and source S is greater than zero (i.e., the gate G potential is higher than the source S potential), which does not meet the turn-on condition for a P-channel MOSFET (gate G voltage lower than source S voltage). Therefore, the seventh MOSFET Q3-10 is in the off state, and the power output from the BOOST boost circuit is not transferred to the DC / DC power conversion circuit. The DC / DC power conversion circuit is directly powered from the power input VIN+ through the output DC+ of the surge voltage protection circuit and operates normally.

[0065] When a momentary power interruption occurs at the power input terminal VIN+, the input voltage drops rapidly, and the sampling voltage at the common connection point of the sixteenth resistor R3-10 and the seventeenth resistor R4-10 decreases accordingly. When the sampling voltage is lower than the reference voltage VREF, that is, when the voltage at the inverting input terminal of the third operational amplifier U1-10 is lower than the voltage at the non-inverting input terminal, the output terminal (pin 1) of the third operational amplifier U1-10 outputs a high-level signal. This high-level signal is applied to the gate G of the sixth MOSFET Q2-10 after being divided by the nineteenth resistor R6-10 and the twentieth resistor R7-10, causing the voltage between the gate G and the source S of the sixth MOSFET Q2-10 to reach the turn-on threshold voltage, and the sixth MOSFET Q2-10 turns on. After the sixth MOSFET Q2-10 turns on, its drain D is pulled low to ground GND potential, and the gate G potential of the seventh MOSFET Q3-10 is pulled low to near ground GND. Since the source (S) of the seventh MOSFET Q3-10 is connected to the output of the BOOST boost circuit, and the voltage at this output is the voltage across the eleventh capacitor C1-10 (higher than ground potential), the gate (G) voltage of the seventh MOSFET Q3-10 is lower than its source (S) voltage, satisfying the conduction condition of a P-channel MOSFET (the voltage between the gate (G) and the source (S) is less than zero), and the seventh MOSFET Q3-10 is turned on. After the seventh MOSFET Q3-10 is turned on, the output of the BOOST boost circuit is connected to the third input of the DC / DC power conversion circuit through the source (S) and drain (D) of the seventh MOSFET Q3-10. The electrical energy stored in the eleventh capacitor C1-10 is transferred to the DC / DC power conversion circuit via the seventh MOSFET Q3-10, maintaining the normal operation of the DC / DC power conversion circuit during input power interruption.

[0066] The BOOST boost circuit operates continuously during normal operation. The voltage at the power input terminal VIN+ is applied to one end of the first inductor L1-10. The integrated switch inside the boost control chip U2-10 periodically turns on and off. When the internal switch of the boost control chip U2-10 is on, the voltage across the first inductor L1-10 equals the input voltage. Current flows through the first inductor L1-10, storing energy in the form of magnetic field energy. At this time, the fourth diode D2-10 is reverse-biased and the eleventh capacitor C1-10 discharges to the load to maintain the output voltage. When the internal switch of the boost control chip U2-10 is off, the current in the first inductor L1-10 cannot change abruptly. The first inductor L1-10 generates a reverse induced electromotive force (EMF). This EMF, superimposed on the input voltage, charges the eleventh capacitor C1-10 through the fourth diode D2-10, causing the voltage across the eleventh capacitor C1-10 to rise above the set value of the input voltage. By adjusting the duty cycle of the boost control chip U2-10, the voltage of the eleventh capacitor C1-10 can be stabilized at the set high voltage value. When the input power supply is momentarily interrupted, the energy stored in the eleventh capacitor C1-10 is released and supplied to the DC / DC power conversion circuit through the seventh MOSFET Q3-10, ensuring that the DC / DC power conversion circuit does not lose power during the interruption.

[0067] The capacitance value of the eleventh capacitor C1-10 is designed according to the requirements of instantaneous power input interruption, and its calculation formula is as follows: Where P is the power required by the DC / DC power conversion circuit, and T is the duration of the instantaneous interruption requirement. The rated voltage that needs to be set for the eleventh capacitor C1-10 (i.e., the output voltage when the BOOST boost circuit is working normally). This is the minimum operating voltage at which the BOOST boost circuit stops working (i.e., the minimum input voltage at which the DC / DC power conversion circuit can operate normally). The required capacitor value is calculated using this formula to ensure that the voltage across the eleventh capacitor C1-10 remains constant during the duration of the input power interruption. Discharge to During the process, the released energy is sufficient to maintain the normal operation of the DC / DC power conversion circuit. The fourteenth capacitor C4-10 and the fifteenth capacitor C5-10 are used to filter the input and output voltages, respectively, reducing voltage ripple. The thirteenth capacitor C3-10 is connected between the RC pin of the boost control chip U2-10 and ground (GND) to set the oscillation frequency. The fourteenth resistor R1-10 and the fifteenth resistor R2-10 provide bias voltage to the gate of the seventh MOSFET Q3-10, ensuring that the seventh MOSFET Q3-10 is reliably turned off when the sixth MOSFET Q2-10 is turned off, and reliably turned on when the sixth MOSFET Q2-10 is turned on. The twelfth capacitor C2-10 is used to filter out noise interference on the gate drive signal. Through the above circuit structure and control logic, the power-down switching circuit and the BOOST boost circuit work together to seamlessly switch to energy storage power supply when the power input is momentarily interrupted, ensuring that the DC / DC power conversion circuit continuously outputs stable power, thereby meeting the test requirements for momentary interruption of power input in the DO-160G standard.

[0068] Optionally, in the above technical solutions, such as Figure 11 As shown, the EMC filter circuit includes a first common-mode inductor L1, a second common-mode inductor L2, a first Y capacitor C3-11, a second Y capacitor C4-11, a third Y capacitor C5-11, a fourth Y capacitor C6-11, a sixteenth capacitor C1-11, a seventeenth capacitor C2-11, and a twenty-second capacitor C7-11. The first input terminal of the first common-mode inductor L1 (i.e., pin 2 of the first common-mode inductor L1) is connected to the output terminal IFLD of the surge current protection circuit, and the second input terminal of the first common-mode inductor L1 (i.e., pin 3 of the first common-mode inductor L1) is connected to ground GND. The first output terminal of the first common-mode inductor L1 (i.e., pin 1 of the first common-mode inductor L1) is connected to the first input terminal of the second common-mode inductor L2 (i.e., pin 2 of the second common-mode inductor L2), and the second output terminal of the first common-mode inductor L1 (i.e., pin 4 of the first common-mode inductor L1) is connected to the second input terminal of the second common-mode inductor L2 (i.e., pin 3 of the second common-mode inductor L2). The first output terminal of the second common-mode inductor L2 (i.e., pin 1 of the second common-mode inductor L2) is connected to the input terminal VIN+ of the surge voltage protection circuit, and the second output terminal of the second common-mode inductor L2 (i.e., pin 4 of the second common-mode inductor L2) is connected to ground GND.

[0069] One end of the first Y capacitor C3-11 is connected to the common connection point of the first output terminal (i.e., pin 1 of the first common mode inductor L1) and the first input terminal (i.e., pin 2 of the second common mode inductor L2), and the other end of the first Y capacitor C3-11 is connected to the housing ground PGND. One end of the second Y capacitor C4-11 is connected to the common connection point of the second output terminal (i.e., pin 4 of the first common mode inductor L1) and the second input terminal (i.e., pin 3 of the second common mode inductor L2), and the other end of the second Y capacitor C4-11 is connected to the housing ground PGND. One end of the third Y capacitor C5-11 is connected to the common connection point of the first output terminal (i.e., pin 1 of the second common mode inductor L2) and the input terminal VIN+ of the surge voltage protection circuit, and the other end of the third Y capacitor C5-11 is connected to the housing ground PGND. One end of the fourth Y capacitor C6-11 is connected to the common connection point between the second output terminal of the second common mode inductor L2 (i.e., pin 4 of the second common mode inductor L2) and ground GND, and the other end of the fourth Y capacitor C6-11 is connected to the casing ground PGND.

[0070] The sixteenth capacitor, C1-11, is connected between the output terminal IFLD of the surge current protection circuit and ground (GND). One end of the sixteenth capacitor, C1-11, is connected to the output terminal IFLD of the surge current protection circuit, and the other end is grounded (GND). The seventeenth capacitor, C2-11, is connected between the first output terminal of the first common-mode inductor L1 and ground (GND). One end of the seventeenth capacitor, C2-11, is connected to the first output terminal of the first common-mode inductor L1, and the other end is grounded (GND). The twenty-second capacitor, C7-11, is connected between the first output terminal of the second common-mode inductor L2 and ground (GND). One end of the twenty-second capacitor, C7-11, is connected to the first output terminal of the second common-mode inductor L2, and the other end is grounded (GND). The first common-mode inductor L1 internally includes a first winding L1-A and a second winding L1-B. The first winding L1-A is connected between pin 2 and pin 1 of the first common-mode inductor L1, and the second winding L1-B is connected between pin 3 and pin 4 of the first common-mode inductor L1. The second common-mode inductor L2 internally includes a third winding L2-A and a fourth winding L2-B. The third winding L2-A is connected between pin 2 and pin 1 of the second common-mode inductor L2, and the fourth winding L2-B is connected between pin 3 and pin 4 of the second common-mode inductor L2.

[0071] EMC filter circuits are used to suppress conducted electromagnetic interference on power lines, ensuring that power supply products meet the electromagnetic compatibility requirements of the DO-160G standard. EMC filter circuits allow useful low-frequency signals to pass through smoothly while significantly suppressing high-frequency interference signals. The EMC filter circuit employs a filter network structure combining a two-stage common-mode inductor and a Y-capacitor to effectively suppress common-mode interference on power lines.

[0072] Under normal operating conditions, the input current flows from the output terminal IFLD of the surge current protection circuit into the EMC filter circuit. The current first passes through the first common-mode inductor L1. Inside the first common-mode inductor L1, the first winding L1-A and the second winding L1-B are wound in the same direction on the same magnetic core. For normally transmitted differential-mode current, the current flowing through the first winding L1-A is in the opposite direction to the current flowing through the second winding L1-B. The magnetic flux generated in the core is in opposite directions and cancels each other out. Therefore, the first common-mode inductor L1 presents a very low impedance to differential-mode current, allowing useful DC or low-frequency power signals to pass through the first common-mode inductor L1 with almost no attenuation. For common-mode interference current, the current flowing through the first winding L1-A and the second winding L1-B is in the same direction, and the magnetic flux generated in the core is in the same direction and superimposed on each other. This results in the first common-mode inductor L1 presenting a very high impedance to common-mode interference current, effectively suppressing common-mode interference signals.

[0073] The current filtered by the first common-mode inductor L1 enters the second common-mode inductor L2. The second common-mode inductor L2 operates on the same principle as the first common-mode inductor L1. Its internal third winding L2-A and fourth winding L2-B present low impedance to differential-mode current and high impedance to common-mode interference current, providing a second stage of common-mode noise suppression. By using the two stages of common-mode inductors in series, the EMC filter circuit's ability to suppress common-mode interference is significantly enhanced.

[0074] In the EMC filter circuit, the first Y capacitor C3-11, the second Y capacitor C4-11, the third Y capacitor C5-11, and the fourth Y capacitor C6-11 are connected between the positive or negative power supply line and the PGND ground, respectively. When a common-mode interference signal appears on the power supply line, the first Y capacitor C3-11, the second Y capacitor C4-11, the third Y capacitor C5-11, and the fourth Y capacitor C6-11 provide a low-impedance discharge path for the high-frequency common-mode interference current, allowing the common-mode interference current to bypass to the PGND ground through the Y capacitors, instead of continuing to propagate to subsequent circuits along the power supply line. The first Y capacitor C3-11 and the second Y capacitor C4-11 are connected between the first and second output terminals of the first common-mode inductor L1 and the PGND ground, respectively, forming the first-stage common-mode suppression filter network together with the first common-mode inductor L1. The third Y capacitor C5-11 and the fourth Y capacitor C6-11 are connected between the first and second output terminals of the second common-mode inductor L2 and the casing ground PGND, respectively, forming a second-stage common-mode rejection filter network together with the second common-mode inductor L2. The two-stage common-mode rejection filter network operates in series, achieving multi-stage attenuation of common-mode interference, ensuring that common-mode noise on the power line is sufficiently suppressed before reaching the surge voltage protection circuit.

[0075] The sixteenth capacitor, C1-11, is connected between the input terminal of the EMC filter circuit and ground (GND) to filter out differential-mode high-frequency noise on the input power line. The seventeenth capacitor, C2-11, is connected between the output terminal of the first common-mode inductor L1 and ground (GND), forming the first-stage differential-mode filter network together with the first winding L1-A of the first common-mode inductor L1, further attenuating differential-mode interference signals. The twenty-second capacitor, C7-11, is connected between the output terminal of the second common-mode inductor L2 and ground (GND), forming the second-stage differential-mode filter network together with the third winding L2-A of the second common-mode inductor L2, further attenuating residual differential-mode interference after the previous stage of filtering. Through the series connection of the two-stage differential-mode filter network, the EMC filter circuit also has a good suppression effect on differential-mode interference.

[0076] The first Y capacitor C3-11, the second Y capacitor C4-11, the third Y capacitor C5-11, and the fourth Y capacitor C6-11 are connected to the casing ground PGND via screws. This ensures a reliable and low-impedance connection between the Y capacitors and the casing ground, guaranteeing that high-frequency common-mode interference current can be effectively discharged to the casing ground and preventing common-mode interference from forming a propagation path on the power line. The power signal processed by the EMC filter circuit is output from the first output terminal of the second common-mode inductor L2 to the input terminal VIN+ of the surge voltage protection circuit, providing clean power that has undergone electromagnetic compatibility filtering to the subsequent circuits. Through the above-mentioned filter network structure combining two stages of common-mode inductors and Y capacitors, the EMC filter circuit can effectively suppress common-mode and differential-mode interference on the power line, ensuring that the power supply product meets the electromagnetic compatibility test requirements specified in the DO-160G standard, while ensuring low-loss transmission of low-frequency useful power signals.

[0077] Optionally, in the above technical solution, the input reverse connection protection circuit, voltage spike processing circuit, surge current protection circuit, EMC filtering circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power-down signal circuit, power-down switching circuit, and BOOST boost circuit are all independently set up using discrete analog components. This means that when designing and implementing the above functional circuits, no integrated dedicated control chip or digital processor is used. Instead, independent basic analog electronic components such as resistors, capacitors, diodes, transistors, MOSFETs, operational amplifiers, Zener diodes, inductors, and transformers are selected and independently connected and configured according to their respective circuit topologies. Each functional circuit is an independent analog subsystem with complete electrical functions and input / output interfaces. The circuits are cascaded and interact with each other through power lines and signal lines, together forming a complete multi-functional integrated power supply system.

[0078] The implementation method using discrete analog devices differs fundamentally from that using integrated power management chips or digital control schemes. When using integrated chips, multiple functional modules are often encapsulated within a single chip, with parameters interrelated and inseparable. Designers cannot independently optimize device selection and parameter matching for each functional requirement. However, when using discrete analog devices, the model and parameters of each resistor, capacitor, and semiconductor device in each functional circuit can be independently selected and precisely calculated based on specific performance requirements. The mutual influence between circuits can be effectively controlled through reasonable impedance matching and isolation design, significantly increasing design freedom.

[0079] The advantages of using discrete analog components and setting them up independently are specifically reflected in the following aspects: 1) While integrated power management chips are relatively small, they often require large-capacity electrolytic capacitors, large inductors, and complex heat dissipation devices, resulting in a significant footprint on the printed circuit board. In contrast, by using discrete analog components with a well-planned and compact design, multiple functional circuits can be optimally arranged according to power flow, eliminating unnecessary redundant functions and the space occupied by package pins in integrated chips. This makes the overall power system smaller than that using integrated chips, facilitating installation and integration in space-constrained environments such as aircraft.

[0080] 2) Integrated circuits typically contain multiple operating modules. Even if some modules are not needed in a specific operating state, their static power consumption and switching losses still exist, leading to a decrease in overall efficiency. Discrete analog devices, on the other hand, allow designers to independently configure the optimal on-resistance, switching frequency, and drive voltage for each functional circuit according to actual operating conditions. This ensures that each circuit operates at its optimal efficiency point, avoiding unnecessary power consumption within the integrated circuit. Furthermore, the independent circuits can be directly coupled or connected with low impedance, reducing additional losses during signal transmission and processing, thereby significantly improving the overall power system conversion efficiency.

[0081] 3) Improved power efficiency directly leads to reduced power loss, which in turn means less heat generation. Independent configuration of discrete analog components allows power devices (such as MOSFETs and diodes) to be selected independently based on actual current and voltage stresses. This enables the use of devices with lower on-resistance, faster switching speeds, and better recovery characteristics, reducing conduction and switching losses at the source. Simultaneously, the independently configured circuits can be zoned according to power density and heat distribution, ensuring even heat distribution on the printed circuit board. This prevents heat from concentrating in a particular area and forming localized hotspots, facilitating natural or conductive heat dissipation and thus reducing the overall temperature rise and heat generation of the device.

[0082] 4) The independent configuration of discrete analog components allows each functional circuit to have independent fault isolation characteristics. When a component in a circuit fails, because the circuits are connected through clear interfaces, the fault can be confined to a local area, unlike integrated chips where internal fault propagation can cause the entire power system to fail. Furthermore, discrete analog components are mature, standardized parts with long service lives and stable performance. They can be replaced individually during maintenance without replacing the entire integrated module, improving system maintainability and availability.

[0083] 5) The independent configuration of discrete analog components allows for rapid parameter adjustments and circuit optimization of the power supply system based on different aircraft models or power supply requirements. When the specific parameters of a test item in the DO-160G standard change, only the values ​​of individual resistors and capacitors in the corresponding circuit or the replacement of semiconductor devices of different specifications are needed to meet the new requirements, without having to redesign the entire power supply system, thus shortening the development cycle and reducing R&D costs.

[0084] In summary, the input reverse connection protection circuit, voltage spike processing circuit, surge current protection circuit, EMC filtering circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power failure signal circuit, power failure switching circuit, and BOOST boost circuit are all independently set up using discrete analog components. This not only achieves multi-functional integration of the power supply system, but also has significant advantages in terms of size, power efficiency, heat generation, reliability, and adaptability. It fully meets the stringent requirements of civil aircraft for miniaturized, high-efficiency, and high-reliability power supply equipment, while also providing convenient conditions for subsequent maintenance, upgrades, and adaptive improvements.

[0085] Optionally, in the above technical solution, the input power-down signal circuit includes a sampling resistor voltage divider network and a comparator. The sampling resistor voltage divider network consists of at least two resistors connected in series. One end of the sampling resistor voltage divider network is connected to the power input terminal, and the other end is grounded. The sampling resistor voltage divider network divides the voltage at the power input terminal, and outputs a voltage-divided signal with a fixed proportional relationship to the power input terminal voltage at the common connection point of the two series resistors in the sampling resistor voltage divider network. The voltage-divided signal output by the sampling resistor voltage divider network is transmitted to the input terminal of the comparator, and the other input terminal of the comparator receives a fixed reference voltage. The comparator internally compares the voltage amplitude of the voltage-divided signal with the reference voltage, and outputs a corresponding level signal based on the comparison result. This level signal is the power-down signal. The port of the comparator outputting the power-down signal is connected to the control terminal of the power-down switching circuit. The power-down signal is transmitted to the power-down switching circuit to control the power-down switching circuit to perform a switching action.

[0086] The specific process of the input power-down signal circuit in actual operation is as follows: The sampling resistor voltage divider network continuously samples and divides the voltage at the power input terminal, and its output voltage divider signal tracks the changes in the power input terminal voltage in real time. When the voltage at the power input terminal is within the normal range, the amplitude of the voltage divider signal output by the sampling resistor voltage divider network is higher than the reference voltage. After the comparator compares the voltage divider signal with the reference voltage, it outputs a fixed-level power-down signal. This power-down signal is maintained in the first level state, such as high level or low level. At this time, after the control terminal of the power-down switching circuit receives the power-down signal in the first level state, it maintains the current working state of the power-down switching circuit. The power output of the BOOST boost circuit is not transmitted to the DC / DC power conversion circuit through the power-down switching circuit, and the system is directly powered by the power input terminal.

[0087] When a momentary power interruption or voltage drop occurs at the power input terminal, the voltage at the power input terminal drops rapidly, and the amplitude of the voltage divider signal output by the sampling resistor voltage divider network also decreases proportionally. When the amplitude of the voltage divider signal drops below the reference voltage, the comparator's output state flips, and the power-down signal switches from the first level state to the second level state. The comparator outputs the switched power-down signal to the control terminal of the power-down switching circuit. Upon receiving the power-down signal in the second level state, the control terminal of the power-down switching circuit triggers the power-down switching circuit to perform a switching action, transferring the power output from the BOOST boost circuit to the DC / DC power conversion circuit. The energy stored in the energy storage capacitor in the BOOST boost circuit maintains the normal operation of the DC / DC power conversion circuit, thereby achieving seamless switching when the power input voltage drops.

[0088] The resistance ratio of the two series resistors in the sampling resistor voltage divider network can be set according to actual needs, with different resistance ratios corresponding to different input voltage detection thresholds. By reasonably selecting the specific resistance values ​​of the two series resistors in the sampling resistor voltage divider network, the voltage detection point of the input power-down signal circuit can be precisely set, enabling the input power-down signal circuit to output a power-down signal in a timely manner when the voltage at the power input terminal drops to a predetermined threshold. The reference voltage is provided by a high-precision reference voltage source, ensuring that the comparator's comparison reference is stable and unaffected by temperature changes and power supply voltage fluctuations, ensuring that the input power-down signal circuit can accurately and reliably detect input voltage drop events under various operating conditions.

[0089] The comparator can be either an open-drain output comparator or a push-pull output comparator. When using an open-drain output comparator, the output terminal needs to be connected to the power supply voltage via a pull-up resistor to ensure sufficient drive capability when the output is high. When using a push-pull output comparator, the output terminal can directly drive the control terminal of the power-down switching circuit without the need for an external pull-up resistor. Regardless of the type of comparator used, the power-down signal output from the input power-down signal circuit is a voltage level signal. The amplitude of this signal meets the input level requirements of the power-down switching circuit control terminal and can reliably drive the switching devices in the power-down switching circuit.

[0090] The input power-down signal circuit can also include a filter capacitor between the output of the sampling resistor voltage divider network and the input of the comparator. One end of the filter capacitor is connected to both the output of the sampling resistor voltage divider network and the input of the comparator, while the other end is grounded. The filter capacitor removes high-frequency noise components that may be mixed into the voltage divider signal, preventing the comparator from malfunctioning due to noise glitches in the input signal. This ensures that the power-down signal only flips when a real power failure occurs at the power input, improving the system's anti-interference capability and operational reliability.

[0091] Through the above circuit structure and signal processing, the input power failure signal circuit can quickly and accurately generate a power failure signal and transmit it to the control terminal of the power failure switching circuit at the moment when the power input is momentarily interrupted or the voltage drops. This triggers the power failure switching circuit to perform the switching operation from the main power supply to the energy storage power supply, ensuring that the DC / DC power conversion circuit receives uninterrupted input power supply. This meets the test requirements for momentary interruption of power input in the DO-160G standard, ensuring that the power supply product can continue to work stably without affecting the normal operation of downstream loads when the aircraft power supply system experiences a momentary power failure.

[0092] Combination Figure 1 The integrated power supply technology circuit for multi-functional civil aircraft of the present invention is described as follows: The integrated power supply technology circuit for civil aircraft includes an input reverse connection protection circuit, a voltage spike processing circuit, a surge current protection circuit, an EMC filtering circuit, a surge voltage protection circuit, a DC / DC power conversion circuit, an input undervoltage protection circuit, an input power-down signal circuit, a power-down switching circuit, and a BOOST boost circuit. The input terminal of the input reverse connection protection circuit serves as the power input terminal, and external DC power enters the entire power system from this terminal. The input voltage signal at the power input terminal is denoted as signal 1. The output terminal of the input reverse connection protection circuit outputs a voltage signal after reverse connection protection processing, denoted as signal 2. The output terminal of the input reverse connection protection circuit is connected to the input terminal of the voltage spike processing circuit, and signal 2 is transmitted to the voltage spike processing circuit. The output terminal of the voltage spike processing circuit outputs a voltage signal after voltage spike suppression processing, denoted as signal 3. The output terminal of the voltage spike processing circuit is connected to the input terminal of the surge current protection circuit, and signal 3 is transmitted to the surge current protection circuit. The output terminal of the surge current protection circuit outputs a voltage signal after surge current limiting processing, denoted as signal 4. The output of the surge current protection circuit is connected to the input of the EMC filter circuit, and signal 4 is transmitted to the EMC filter circuit. The output of the EMC filter circuit outputs a voltage signal after electromagnetic compatibility filtering, denoted as signal 5. The output of the EMC filter circuit is connected to the input of the surge voltage protection circuit, and signal 5 is transmitted to the surge voltage protection circuit. The output of the surge voltage protection circuit outputs a voltage signal after surge voltage clamping, denoted as signal 6. The output of the surge voltage protection circuit is connected to the first input of the DC / DC power conversion circuit, and signal 6 is transmitted to the first input of the DC / DC power conversion circuit.

[0093] The input terminal of the input undervoltage protection circuit is connected to the power input terminal, and the first signal 1 of the input voltage at the power input terminal is transmitted to the input undervoltage protection circuit. The output terminal of the input undervoltage protection circuit outputs an undervoltage protection signal generated after undervoltage detection and comparison, denoted as the eighth signal 8. The output terminal of the input undervoltage protection circuit is connected to the second input terminal of the DC / DC power conversion circuit, and the eighth signal 8 is transmitted to the second input terminal of the DC / DC power conversion circuit.

[0094] The input terminal of the input power-down signal circuit is connected to the power input terminal, and the first input voltage signal 1 from the power input terminal is transmitted to the input power-down signal circuit. The output terminal of the input power-down signal circuit outputs a power-down signal generated after voltage detection and comparison, denoted as the tenth signal 10. The output terminal of the input power-down signal circuit is connected to the control terminal of the power-down switching circuit, and the tenth signal 10 is transmitted to the control terminal of the power-down switching circuit.

[0095] The input terminal of the BOOST boost circuit is connected to the power input terminal. The first input voltage signal 1 from the power input terminal is transmitted to the BOOST boost circuit via path 11. The output terminal of the BOOST boost circuit outputs a boosted energy storage voltage signal, denoted as the twelfth signal 12. The output terminal of the BOOST boost circuit is connected to the power input terminal of the power-down switching circuit, and the twelfth signal 12 is transmitted to the power input terminal of the power-down switching circuit. The output terminal of the power-down switching circuit outputs a backup power supply voltage signal after switching control, denoted as the thirteenth signal 13. The output terminal of the power-down switching circuit is connected to the third input terminal of the DC / DC power conversion circuit, and the thirteenth signal 13 is transmitted to the third input terminal of the DC / DC power conversion circuit. Based on the tenth signal 10 sent by the output terminal of the input power-down signal circuit, the power-down switching circuit controls whether the twelfth signal 12 is converted into the thirteenth signal 13 and transmitted to the third input terminal of the DC / DC power conversion circuit.

[0096] When the multi-functional integrated power supply circuit for civil aircraft is in operation, external DC power enters the entire power system from the power input terminal, where the first input voltage signal 1 is obtained. The input power first passes through the input reverse connection protection circuit. This circuit utilizes the forward conduction characteristic of a diode, connecting it in series on the positive line of the input power supply. When the input voltage polarity is reversed, the diode is reverse-biased and cuts off the power supply path in time, protecting the power system from operation and preventing damage to components. When multiple input power supplies are supplied simultaneously, the input reverse connection protection circuit can also prevent backflow between the different input power supplies. After processing by the input reverse connection protection circuit, a second signal 2 is obtained at the output terminal of the circuit, and this second signal 2 is transmitted to the voltage spike processing circuit.

[0097] The voltage spike processing circuit absorbs and suppresses any transient high-voltage spikes that may exist in the second signal 2, limiting the amplitude of the voltage spikes to a range that the subsequent circuits can safely withstand, thus preventing overvoltage damage to the components in the subsequent circuits. After processing by the voltage spike processing circuit, the third signal 3 is obtained at the output of the voltage spike processing circuit, and the third signal 3 is transmitted to the surge current protection circuit.

[0098] The surge current protection circuit is used to limit the magnitude of the surge current generated at the moment of power-on. In the initial stage of power input, the surge current protection circuit, through its internal current-limiting resistor and switching transistor control circuit, limits the peak value of the input surge current to within the range specified in the DO-160G standard. Specifically, within the first 3.0 milliseconds, the peak surge current is less than 9 times the maximum steady-state load current; within 3.0 milliseconds to 500 milliseconds, the peak surge current is less than 4 times the maximum steady-state load current; and within 500 milliseconds to 2 seconds, the peak surge current is less than 2 times the maximum steady-state load current. This protects downstream circuit components from excessive surge current. After processing by the surge current protection circuit, a fourth signal (signal 4) is obtained at the output of the surge current protection circuit, and this fourth signal (signal 4) is transmitted to the EMC filter circuit.

[0099] The EMC filter circuit employs a two-stage common-mode inductor and Y-capacitor combination filter network structure to suppress common-mode and differential-mode interference on the fourth signal 4 power line. The common-mode inductor presents high impedance to common-mode interference current, effectively suppressing common-mode noise. The Y-capacitor provides a low-impedance discharge path for high-frequency common-mode interference current, allowing it to bypass to the casing ground. The differential-mode filter capacitor filters out differential-mode high-frequency noise. After processing by the EMC filter circuit, the fifth signal 5 is obtained at the output of the EMC filter circuit, and the fifth signal 5 is transmitted to the surge voltage protection circuit.

[0100] The surge voltage protection circuit suppresses and clamps transient high-voltage surges occurring on the external power line. An internal mirror current source provides a stable bias, while a self-oscillating circuit and a bootstrap circuit provide a drive voltage higher than the input voltage to the gate G of the third MOSFET Q1-7, ensuring that Q1-7 operates in the linear region. When the input surge voltage exceeds the set clamping voltage threshold, the surge voltage protection circuit clamps the voltage carried in the fifth signal 5 to a preset safe voltage value, ensuring that the subsequent DC / DC power conversion circuit is not damaged due to input overvoltage. After processing by the surge voltage protection circuit, a sixth signal 6 is obtained at the output of the surge voltage protection circuit. The sixth signal 6 is transmitted to the first input of the DC / DC power conversion circuit as the main power input power supply for the DC / DC power conversion circuit.

[0101] While the main power transmission link is operating, the input undervoltage protection circuit continuously monitors the first signal 1 at the power input terminal. The input undervoltage protection circuit samples the voltage of the first signal 1 by dividing it using the first sampling resistor R1-3 and the second sampling resistor R2-3. The sampled signal is then sent to the non-inverting input of the first operational amplifier U1-3 and compared with the reference voltage VREF, which is divided by the third sampling resistor R3-3 and the fourth sampling resistor R4-3 and sent to the inverting input. When the voltage of the first signal 1 drops below the set undervoltage protection point, the output of the first operational amplifier U1-3 outputs a high level. After being divided by the sixth sampling resistor R6-3 and the seventh sampling resistor R7-3, this high level drives the first MOSFET Q1-3 to conduct, pulling the eighth signal 8 low. The eighth signal 8 is then transmitted to the second input of the DC / DC power conversion circuit, which performs undervoltage protection based on the received low-level eighth signal 8. The undervoltage protection point of the input undervoltage protection circuit is set below 10V for instantaneous undervoltage and engine start-stop voltage, ensuring that the instantaneous voltage of 10.0V to 20.5V that occurs during engine start-up will not trigger the undervoltage protection, and the power supply product can continue to work without losing power.

[0102] Meanwhile, the input power-down signal circuit continuously detects the first signal 1 at the power input terminal. The sampling resistor voltage divider network in the input power-down signal circuit samples the voltage of the first signal 1 and outputs the divided voltage signal to the input terminal of the comparator. The comparator compares the divided voltage signal with a reference voltage. When the voltage of the first signal 1 is normal, the tenth signal 10 output by the comparator remains at the first level. The tenth signal 10 is transmitted to the control terminal of the power-down switching circuit. Upon receiving the tenth signal 10 at the first level, the power-down switching circuit maintains its current state. The twelfth signal 12 output by the BOOST boost circuit is not transmitted to the DC / DC power conversion circuit through the power-down switching circuit. When the first signal 1 experiences a momentary power interruption or voltage drop, the amplitude of the divided voltage signal output by the sampling resistor voltage divider network decreases accordingly. When the divided voltage signal is lower than the reference voltage, the comparator's output state flips, and the tenth signal 10 switches from the first level state to the second level state. The tenth signal 10 is then transmitted to the control terminal of the power-down switching circuit.

[0103] During normal operation, the BOOST boost circuit continuously receives the first signal 1 from the power input terminal. The first signal 1 is transmitted to the BOOST boost circuit through path 11. The boost control chip U2-10 inside the BOOST boost circuit drives the internal switching transistor to periodically turn on and off. When the switching transistor is on, the first inductor L1-10 stores energy. When the switching transistor is off, the reverse induced electromotive force generated by the first inductor L1-10 is superimposed with the voltage of the first signal 1 and then charges the eleventh capacitor C1-10 through the fourth diode D2-10, raising the voltage of the eleventh capacitor C1-10 to the set value. The twelfth signal 12 is obtained at the output terminal of the BOOST boost circuit. When the control terminal of the power-down switching circuit receives the tenth signal 10 in the second level state, the third operational amplifier U1-10 in the power-down switching circuit outputs a high level. After being divided by the nineteenth resistor R6-10 and the twentieth resistor R7-10, it drives the sixth MOSFET Q2-10 to conduct. After the sixth MOSFET Q2-10 conducts, it pulls down the gate G potential of the seventh MOSFET Q3-10, making the P-channel seventh MOSFET Q3-10 conduct. The twelfth signal 12 is converted into the thirteenth signal 13 through the power-down switching circuit. The thirteenth signal 13 is transmitted to the third input terminal of the DC / DC power conversion circuit, maintaining the normal operation of the DC / DC power conversion circuit during the interruption of the input power supply.

[0104] Through the coordinated operation of the aforementioned functional circuits, the multi-functional integrated power supply technology circuit for civil aircraft can ensure a continuous, stable, and clean power input to the DC / DC power conversion circuit under various complex power supply conditions, including normal power supply, instantaneous undervoltage, surge current, surge voltage, and instantaneous power interruption, thereby meeting the various requirements of the DO-160G power input test. The input reverse connection protection circuit, voltage spike processing circuit, surge current protection circuit, EMC filtering circuit, surge voltage protection circuit, DC / DC power conversion circuit, input undervoltage protection circuit, input power-down signal circuit, power-down switching circuit, and BOOST boost circuit all use discrete analog components independently. Clear interface definitions and functional divisions are achieved between each circuit through signals 1 to 13, realizing a high degree of integration of the power system while ensuring the independence and maintainability of each functional module. It also boasts advantages such as small size, high power efficiency, and low heat generation.

[0105] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0106] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0107] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A multi-functional integrated power supply technology circuit for civil aircraft, characterized in that, include: The circuit includes an input reverse connection protection circuit, a voltage spike processing circuit, a surge current protection circuit, an EMC filter circuit, a surge voltage protection circuit, a DC / DC power conversion circuit, an input undervoltage protection circuit, an input power-down signal circuit, a power-down switching circuit, and a BOOST boost circuit. The input terminal of the input reverse connection protection circuit serves as the power input terminal. The output terminal of the input reverse connection protection circuit, the voltage spike processing circuit, the surge current protection circuit, the EMC filter circuit, the surge voltage protection circuit, and the first input terminal of the DC / DC power conversion circuit are connected in series. The input terminal of the input undervoltage protection circuit is connected to the power input terminal. The output terminal is connected to the second input terminal of the DC / DC power conversion circuit; the input terminal of the input power-down signal circuit is connected to the power input terminal, and the output terminal of the input power-down signal circuit is connected to the control terminal of the power-down switching circuit; the input terminal of the BOOST boost circuit is connected to the power input terminal, the output terminal of the BOOST boost circuit is connected to the power input terminal of the power-down switching circuit, and the output terminal of the power-down switching circuit is connected to the third input terminal of the DC / DC power conversion circuit. The power-down switching circuit controls whether the electrical energy output by the BOOST boost circuit is transferred to the DC / DC power conversion circuit according to the output signal of the input power-down signal circuit.

2. The integrated power supply technology circuit for multi-functional civil aircraft according to claim 1, characterized in that, The input reverse connection protection circuit includes a first diode and a second diode. The anode of the first diode is connected to the positive line of the first input power supply, and the anode of the second diode is connected to the positive line of the second input power supply. The cathodes of the first diode and the second diode are connected to serve as the output terminal of the input reverse connection protection circuit.

3. The integrated power supply circuit for multi-functional civil aircraft according to claim 1, characterized in that, The input undervoltage protection circuit includes a first sampling resistor, a second sampling resistor, a third sampling resistor, a fourth sampling resistor, a sixth sampling resistor, a seventh sampling resistor, a first operational amplifier, and a first MOSFET. The first and second sampling resistors are connected in series between the power input terminal and ground. The common connection point of the first and second sampling resistors is connected to the non-inverting input terminal of the first operational amplifier. The third and fourth sampling resistors are connected in series between the reference voltage and ground. The common connection point of the third and fourth sampling resistors is connected to the inverting input terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the gate of the first MOSFET after being divided by the sixth and seventh sampling resistors. The drain of the first MOSFET outputs an undervoltage protection signal to the second input terminal of the DC / DC power conversion circuit.

4. The integrated power supply technology circuit for multi-functional civil aircraft according to claim 1, characterized in that, The surge current protection circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first Zener diode, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first transistor, and a second MOSFET. The first resistor and the second resistor are connected in series between the power input terminal and ground. The common connection point of the first resistor and the second resistor is connected to ground through the first Zener diode. The positive terminal of the first Zener diode is grounded, and the negative terminal of the first Zener diode is connected to the common connection point of the first resistor and the second resistor. The third resistor and the sixth capacitor are connected in series between the power input terminal and ground. The common connection point of the third resistor and the sixth capacitor is connected to the base of the first transistor. The emitter of the first transistor is grounded. The collector of the first transistor is connected to the power input terminal through the fourth resistor. The collector of the first transistor is also connected to the gate of the second MOSFET. The source of the second MOSFET is grounded through the fifth resistor. The drain of the second MOSFET serves as the output terminal of the surge current protection circuit. The seventh capacitor is connected between the power input terminal and ground.

5. The integrated power supply technology circuit for multi-functional civil aircraft according to claim 1, characterized in that, The surge voltage protection circuit includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second Zener diode, a third diode, an eighth capacitor, a ninth capacitor, a tenth capacitor, and a second operational amplifier. The drain of the third MOSFET is connected to the power input terminal, and the source of the third MOSFET serves as the output terminal of the surge voltage protection circuit. The fourth MOSFET and the fifth MOSFET form a mirror current source. The tenth resistor, the eleventh resistor, the twelfth resistor, the second operational amplifier, the thirteenth resistor, the third diode, and the eighth capacitor form a self-oscillating circuit and a bootstrap circuit. The gate voltage of the third MOSFET is the voltage at the power input terminal plus the bootstrap voltage, and the source voltage of the third MOSFET is clamped at a set reference voltage value.

6. The integrated power supply technology circuit for multi-functional civil aircraft according to claim 1, characterized in that, The power-down switching circuit includes a third operational amplifier, a sixth MOSFET, a seventh MOSFET, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, and a twentieth resistor. The sixteenth and seventeenth resistors are connected in series between the power input terminal and ground. The common connection point of the sixteenth and seventeenth resistors is connected to the inverting input terminal of the third operational amplifier. The non-inverting input terminal of the third operational amplifier is connected to a reference voltage. The output terminal of the third operational amplifier is connected to the gate of the sixth MOSFET after voltage division by the nineteenth and twentieth resistors. The source of the sixth MOSFET is grounded, and the drain of the sixth MOSFET is connected to the gate of the seventh MOSFET. The source of the seventh MOSFET is connected to the output terminal of the BOOST boost circuit, and the drain of the seventh MOSFET is connected to the third input terminal of the DC / DC power conversion circuit.

7. The integrated power supply circuit for multi-functional civil aircraft according to claim 1, characterized in that, The BOOST boost circuit includes a first inductor, a boost control chip, a fourth diode, and an eleventh capacitor. One end of the first inductor is connected to the power input terminal, and the other end of the first inductor is connected to the drain of the switching transistor of the boost control chip and the anode of the fourth diode. The cathode of the fourth diode is grounded through the eleventh capacitor, and the anode of the eleventh capacitor is connected to the cathode of the fourth diode. The anode of the eleventh capacitor serves as the output terminal of the BOOST boost circuit.

8. The integrated power supply circuit for multi-functional civil aircraft according to claim 1, characterized in that, The EMC filtering circuit includes a first common-mode inductor, a second common-mode inductor, a first Y capacitor, a second Y capacitor, a third Y capacitor, a fourth Y capacitor, a sixteenth capacitor, a seventeenth capacitor, and a twenty-second capacitor. The first input terminal of the first common-mode inductor is connected to the output terminal of the surge current protection circuit, and the second input terminal of the first common-mode inductor is grounded. The first output terminal of the first common-mode inductor is connected to the first input terminal of the second common-mode inductor, and the second output terminal of the first common-mode inductor is connected to the second input terminal of the second common-mode inductor. The first output terminal of the second common-mode inductor is connected to the input terminal of the surge voltage protection circuit, and the second output terminal of the second common-mode inductor is grounded. The first Y capacitor, the second Y capacitor, the third Y capacitor, and the fourth Y capacitor are respectively connected between the first output terminal of the first common-mode inductor, the second output terminal of the first common-mode inductor, the first output terminal of the second common-mode inductor, the second output terminal of the second common-mode inductor, and the casing ground.

9. The integrated power supply circuit for multi-functional civil aircraft according to claim 1, characterized in that, The input reverse connection protection circuit, the voltage spike processing circuit, the surge current protection circuit, the EMC filtering circuit, the surge voltage protection circuit, the DC / DC power conversion circuit, the input undervoltage protection circuit, the input power failure signal circuit, the power failure switching circuit, and the BOOST boost circuit are all independently set up using discrete analog components.

10. The integrated power supply technology circuit for multi-functional civil aircraft according to claim 1, characterized in that, The input power-down signal circuit includes a sampling resistor voltage divider network and a comparator. The sampling resistor voltage divider network divides the voltage at the power input terminal and outputs a divided voltage signal to the input terminal of the comparator. The comparator compares the divided voltage signal with a reference voltage and outputs a power-down signal to the control terminal of the power-down switching circuit.

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