Memory device and method of manufacturing the same

Abstract

A memory device includes an array of transistors. Each transistor includes a semiconductor layer extending along a first direction, a source region and a drain region at two opposite ends of the semiconductor layer, and a gate stack structure coupled with the semiconductor layer and covering an intermediate region of the semiconductor layer between the source region and the drain region. The gate stack structure includes a first conductive layer coupled with the semiconductor layer, a second conductive layer coupled with the semiconductor layer and located above the first conductive layer along the first direction, and a first dielectric layer located between the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and in particular to memory devices and methods of manufacturing thereof. Background Technology

[0002] Planar memory cells have been scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and expensive. As a result, the memory density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0004] Some aspects of this disclosure provide a memory device including an array of transistors, each transistor including a semiconductor layer extending along a first direction, a source region and a drain region located at two opposite ends of the semiconductor layer, and a gate stack structure coupled to the semiconductor layer and covering an intermediate region of the semiconductor layer between the source region and the drain region. The gate stack structure includes a first conductive layer coupled to the semiconductor layer, a second conductive layer coupled to the semiconductor layer and located above the first conductive layer along the first direction, and a first dielectric layer located between the first conductive layer and the second conductive layer.

[0005] In some embodiments, the first conductive layer is coupled to a first power source, and the second conductive layer is coupled to a second power source having a different voltage level than the first power source.

[0006] In some embodiments, the memory device further includes: a third conductive layer formed over a first side of the second conductive layer, the first side being away from the first conductive layer; and a second dielectric layer located between the second conductive layer and the third conductive layer.

[0007] In some embodiments, the first conductive layer is coupled to a first power source; the second conductive layer is coupled to a second power source; and the third conductive layer is coupled to a third power source. The second power source has a different voltage level than either the first or the third power source.

[0008] In some embodiments, the memory device includes a bit line coupled to the source region or the drain region of the transistor and extending along a second direction, wherein the second direction is perpendicular to the first direction.

[0009] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The bit line is located on a first side of the transistor, and the memory components are located on a second side of the transistor opposite to the first side along the first direction.

[0010] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The bit lines and the memory components are located on a first side and a second side of the transistor, the second side being opposite to the first side along the first direction, and the bit lines and the memory components are arranged in an alternating pattern on each side.

[0011] In some embodiments, the memory device includes a gate dielectric layer located between the semiconductor layer and the gate stack; and an isolation wall disposed in a second direction between two adjacent rows of vertical transistors, wherein the second direction is perpendicular to the first direction.

[0012] In some implementations, the first distance between the gate dielectric layer of the first row of transistors and the isolation wall configured to be adjacent to the first side of the first row of transistors is greater than 5 nm.

[0013] In some embodiments, the second distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the second side of the first row of transistors is greater than 0 nm, the second side being opposite to the first side in the second direction.

[0014] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The memory components arranged on opposite sides of the isolation wall are not aligned with each other.

[0015] In some embodiments, the first conductive layer, the second conductive layer, and the third conductive layer have equal thicknesses along the first direction.

[0016] In some embodiments, along the first direction, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the thickness of the third conductive layer.

[0017] In some embodiments, the thickness of the second conductive layer is greater than or equal to the thickness of the first conductive layer along the first direction.

[0018] Some aspects of this disclosure provide a memory device comprising: an array of transistors connected in parallel and extending along a first direction; word lines, each word line coupled to a row of the transistors arranged along a third direction; and a first isolation wall arranged in an alternating pattern with the word lines along a second direction. The first direction, the third direction, and the second direction are perpendicular to each other. The word lines include a first conductive layer coupled to the transistors and a second conductive layer coupled to the transistors and isolated from the first conductive layer along the first direction by a first dielectric layer.

[0019] In some embodiments, the first conductive layer is coupled to a first power source; and the second conductive layer is coupled to a second power source having a different voltage level than the first power source.

[0020] In some embodiments, the memory device includes: a third conductive layer formed over a first side of the second conductive layer, the first side being away from the first conductive layer; and a second dielectric layer located between the second conductive layer and the third conductive layer.

[0021] In some embodiments, the first conductive layer is coupled to a first power source; the second conductive layer is coupled to a second power source; and the third conductive layer is coupled to a third power source. The second power source has a different voltage level than either the first or the third power source.

[0022] In some embodiments, the memory device includes bit lines coupled to the source or drain region of the transistor and extending along a second direction perpendicular to the first direction and the third direction.

[0023] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The bit line is located on a first side of the transistor, and the memory components are located on a second side of the transistor opposite to the first side along the first direction.

[0024] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The bit lines and the memory components are located on a first side and a second side of the transistor, the second side being opposite to the first side along the first direction; and the bit lines and the memory components are arranged in an alternating pattern on each side.

[0025] In some embodiments, the transistor includes a semiconductor layer extending along the first direction and a gate dielectric layer located between the semiconductor layer and the word line coupled to the transistor; and the memory device further includes an isolation wall disposed in a second direction between two adjacent rows of vertical transistors, wherein the second direction is perpendicular to the first direction and the third direction.

[0026] In some embodiments, the first distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the first side of the first row of transistors is greater than 5 nm.

[0027] In some embodiments, the second distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the second side of the first row of transistors is greater than 0 nm, the second side being opposite to the first side in the second direction.

[0028] In some embodiments, the memory device includes an array of memory components each coupled to the transistor. The memory components arranged on opposite sides of the isolation wall are not aligned with each other.

[0029] In some embodiments, the first conductive layer, the second conductive layer, and the third conductive layer have equal thicknesses along the first direction.

[0030] In some embodiments, along the first direction, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the thickness of the third conductive layer.

[0031] In some embodiments, the thickness of the second conductive layer is greater than or equal to the thickness of the first conductive layer along the first direction.

[0032] Some aspects of this disclosure provide a method for manufacturing a memory device, comprising: forming an array of transistors extending along a first direction, each transistor including a semiconductor layer and a source region and a drain region located at two opposite ends of the semiconductor layer; and forming a gate stack structure coupled to the semiconductor layer and covering an intermediate region of the semiconductor layer between the source region and the drain region. The gate stack structure includes: a first conductive layer coupled to the transistors; a second conductive layer coupled to the transistors and located above the first conductive layer along the first direction; and a first dielectric layer located between the first conductive layer and the second conductive layer.

[0033] In some embodiments, the gate stack structure includes: a third conductive layer formed over a first side of the second conductive layer, the first side being away from the first conductive layer; and a second dielectric layer located between the second conductive layer and the third conductive layer.

[0034] In some embodiments, forming the gate stack structure includes: forming a stack structure including a first sacrificial layer, a second sacrificial layer, and a first dielectric layer located between the first sacrificial layer and the second sacrificial layer; and replacing the first sacrificial layer and the second sacrificial layer with a conductive material to form the first conductive layer and the second conductive layer.

[0035] In some embodiments, forming the array of transistors includes: forming a hole through the stacked structure along the first direction; and filling the hole with the semiconductor layer and a gate dielectric layer located between the semiconductor layer and the stacked structure.

[0036] In some embodiments, the method further includes forming a bit line coupled to the source or drain region of the transistor and extending along a second direction perpendicular to the first direction.

[0037] In some embodiments, the method further includes forming an array of memory components respectively coupled to the transistor. The bit line is located on a first side of the transistor; and the memory component is located on a second side of the transistor opposite to the first side along the first direction.

[0038] In some embodiments, the method further includes forming an array of memory components respectively coupled to the transistor. The bit lines and the memory components are located on a first side and a second side of the transistor, the second side being opposite to the first side along the first direction, and the bit lines and the memory components are arranged in an alternating pattern on each side.

[0039] In some embodiments, the method further includes forming a first isolation wall disposed in a second direction between two adjacent rows of vertical transistors, wherein the second direction is perpendicular to the first direction.

[0040] In some embodiments, the first distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the first side of the first row of transistors is greater than 5 nm.

[0041] In some embodiments, the second distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the second side of the first row of transistors is greater than 0 nm, the second side being opposite to the first side in the second direction. Attached Figure Description

[0042] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0043] Figure 1A A schematic circuit diagram of a semiconductor device including a memory cell array according to some embodiments of the present disclosure is shown.

[0044] Figure 1B A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0045] Figure 1C Some embodiments according to this disclosure are shown. Figure 1B A top view of a semiconductor device.

[0046] Figure 1D Some embodiments according to this disclosure are shown. Figure 1B A partial cross-sectional view of a semiconductor device.

[0047] Figure 1E A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0048] Figure 1F A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0049] Figure 2 A top view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0050] Figure 3 A top view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0051] Figure 4 A top view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0052] Figure 5 A top view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0053] Figure 6A A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0054] Figure 6B Some embodiments according to this disclosure are shown. Figure 6A A top view of a semiconductor device.

[0055] Figure 7A flowchart of a manufacturing method for forming a semiconductor device according to some embodiments of the present disclosure is shown.

[0056] Figure 8A-8I Each illustrates various embodiments according to this disclosure. Figure 7 A schematic diagram of a semiconductor device at a certain manufacturing stage of the method shown.

[0057] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0058] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically described in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0059] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0060] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” in the case of a layer with an intermediate feature or in between; and “above” or “above” means not only “on” or “above” but also “on” or “above” in the case of a layer without an intermediate feature or in between (i.e., directly on).

[0061] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0062] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0063] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0064] Drain-induced barrier reduction (DIBL) is a common short-channel effect in field-effect transistors (FETs), especially in nanoscale transistors. DIBL occurs when a high drain voltage reduces the barrier between the source and drain. This reduction in the barrier leads to a decrease in the transistor's threshold voltage and an increase in subthreshold leakage current. As a result, power consumption increases, potentially impairing reliability. In 3D memory devices where memory cells (or memory layers) are vertically stacked in multiple layers to achieve higher memory density, improved performance, and a reduced footprint, the performance of the transistors within the corresponding memory cells is significantly affected by DIBL.

[0065] For example, in a vertical dynamic random access memory (DRAM) cell, a precise threshold voltage is crucial for the correct switching and retention of data. If the DIBL (Distributed Isolation Blocking) reduces the threshold voltage of the transistor too much, it can cause unexpected leakage current when the transistor should be off, leading to data corruption or unwanted conduction between the access transistor and the storage node (capacitor). This can result in incorrect charge retention and data loss. Furthermore, increased leakage current can cause increased noise in the bit lines and interfere with data sensing, especially in charge-sensitive read operations stored on the capacitor. Additionally, excessive leakage can cause faster charge loss from the storage capacitor, reducing the retention time of the DRAM cell, which can lower the overall refresh rate and affect cell stability. DRAM cells rely on accurate reading of the charge stored in the capacitor. If the access transistor is not turned on correctly (due to DIBL), it can lead to incorrect readings or data degradation of the stored data. For example, if the access transistor leaks too much, it may allow charge to flow out of the capacitor during reads, interfering with the charge and potentially flipping bits or causing errors in the data.

[0066] To address one or more of the aforementioned problems, this disclosure describes a memory device including an array of transistors. The transistors include a gate stack structure comprising at least a first conductive layer and a second conductive layer isolated by a first dielectric layer. The first conductive layer, the first dielectric layer, and the second conductive layer are stacked along a first direction and coupled to a semiconductor layer of the transistor (i.e., a channel region of the transistor). For example, the first conductive layer is adjacent to an end of the channel region, while the second conductive layer covers the middle of the channel region. Because the first and second conductive layers are isolated by the first dielectric layer, they can be independently coupled to different voltage sources, such that the voltage applied to the middle of the channel region can differ from the voltage applied to the ends of the channel region. For example, the voltage applied to the ends of the channel region can be higher than the voltage applied to the middle of the channel region. Therefore, barrier reduction at the ends of the channel region is greatly limited, while gate control capability remains unaffected. Compared to a gate structure formed from a single conductive material, the negative effects of DIBL are well suppressed, while the gate control capability of the vertical transistor remains unaffected.

[0067] Consistent with the scope of this disclosure, according to some embodiments of this disclosure, the gate stack structure in the disclosed memory device further includes: a third conductive layer coupled to the channel region and located above the second conductive layer along a first direction; and a second dielectric layer located between the second conductive layer and the third conductive layer.

[0068] A first conductive layer, a second conductive layer, and a third conductive layer are stacked along a first direction and coupled to the channel region of the transistor, respectively. For example, the first conductive layer is adjacent to a first end of the channel region, the third conductive layer is adjacent to a second end of the channel region, and the second conductive layer covers the middle of the channel region. Since the first, second, and third conductive layers are isolated by a first and a second dielectric layer, they can be independently coupled to different voltage sources, allowing the voltage applied to the middle of the channel region to differ from the voltage applied to the ends of the channel region. For example, the voltage applied to the ends of the channel region can be higher than the voltage applied to the middle of the channel region. The negative effects of DIBL are effectively suppressed, while the gate control capability of the vertical transistor remains unaffected.

[0069] Figure 1A A schematic diagram of a semiconductor device 100, including peripheral circuitry and a memory cell array, is shown according to some aspects of this disclosure, with each memory cell having a vertical transistor. The semiconductor device 100 may include a memory cell array 110 and peripheral circuitry 120 coupled to the memory cell array 110. The memory cell array 110 may be any suitable memory cell array, wherein each memory cell 130 includes a vertical transistor 132 and a storage component 134 coupled to the vertical transistor 132. In some embodiments, the memory cell array 110 is a DRAM cell array, and the storage component 134 is a capacitor for storing charge as binary information stored by the respective DRAM cell. Figure 1AAs shown, memory cells 130 can be arranged as a two-dimensional (2D) array with rows and columns. Peripheral circuitry 120 can include any suitable digital, analog, and / or mixed-signal circuitry to facilitate the operation of the memory cell array. For example, peripheral circuitry can include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the functional circuitry mentioned above, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). According to some embodiments, peripheral circuitry 120 uses complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). Semiconductor device 100 may include: word lines 140 coupled to peripheral circuitry 120 and memory cell array 110 for controlling the switching of vertical transistors 132 in memory cells 130 located in rows; and bit lines 150 coupled to peripheral circuitry 120 and memory cell array 110 for sending data to and / or receiving data from memory cells 130 located in columns. That is, each word line 140 is coupled to a corresponding row of memory cells 130, and each bit line 150 is coupled to a corresponding column of memory cells 130.

[0070] like Figure 1A As shown, storage component 134 can be coupled to the source or drain of vertical transistor 132. Storage component 134 may include any means capable of storing binary data (e.g., 0 and 1), including but not limited to capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. Peripheral circuit structure 120 may be coupled to memory cell array 110 via bit line 150, word line 140, and any other suitable metal wiring. As described above, peripheral circuit structure 120 may include any suitable circuitry for facilitating the operation of memory cell array 110 by applying voltage and / or current signals to each memory cell 130 via word line 140 and bit line 150, and by sensing voltage and / or current signals from each memory cell 130. Peripheral circuit structure 120 may include various types of peripheral circuit structures formed using CMOS technology.

[0071] In some embodiments, each memory cell 130 includes a storage component 134 for storing data bits as positive or negative charges and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selecting) access to the storage component. In some embodiments, each memory cell is a single-transistor single-capacitor (1T1C) cell. Since transistors always leak a small amount of charge, capacitors will discharge slowly, causing the information stored therein to be depleted. Therefore, according to some embodiments, the memory cell must be refreshed, for example, by a peripheral circuit structure 120 coupled to the memory cell array 110 to retain the data. In some embodiments, the storage component 134 may be a columnar capacitor formed after the vertical transistor 132 is formed. In some embodiments, a columnar capacitor refers to a capacitor having a vertical orientation structure similar to pillars or columns. Typically, a columnar capacitor is formed by etching deep trenches into a substrate and then filling these trenches with conductive and dielectric materials to create a capacitor. Both the outer and inner surfaces of the columnar capacitor can be used as effective capacitor regions. This structure can be used to achieve greater packaging density in semiconductor devices. In some other embodiments, the storage component 134 may be a cup-shaped capacitor formed before the vertical transistor 132 is formed. In some embodiments, a cup-shaped capacitor refers to a capacitor having a cup-shaped or bowl-shaped form, which is formed by creating a recessed region in a substrate (and then lining the recessed region with a conductive and dielectric material to form a capacitor). In such embodiments, the high-temperature process for forming the cup-shaped capacitor does not affect the formation of the vertical transistor 132. Therefore, a metal-oxide-semiconductor can be used as the channel structure of the vertical transistor 132.

[0072] Figure 1B A schematic diagram of a memory cell array 110, in which storage components are omitted, is shown according to some embodiments of the present disclosure. For example... Figure 1B As shown, the memory cell array 110 includes a plurality of vertical patterns 131 and a gate stack structure 135 including a plurality of conductive layers. The vertical patterns 131 extend along a first direction (z-direction). A first end of the vertical pattern 131 is coupled to a bit line 150, and a second end of the vertical pattern 131 is coupled to a corresponding memory unit (…). Figure 1B (Not shown in the image). Depending on the implementation, the storage component may be a cylindrical capacitor or a cup-shaped capacitor. The storage component can be coupled to the corresponding vertical pattern 131 via contact 137, such as... Figure 1B As shown. In some embodiments, contact 137 may include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof.

[0073] The memory cell array 110 may include multiple word lines, each extending in a third direction (x direction) perpendicular to a first lateral direction (y direction). The word lines are coupled to corresponding rows of vertical transistors 132 and extend along the third direction (i.e., the x direction). It should be understood that in some examples, the gate stack body structure 135 of the vertical transistors 132 and the corresponding word lines may be continuous conductive structures. In other words, the gate stack body structure 135 of the vertical transistors 132 may be part of a word line, and the word line may be an extension of the corresponding gate stack body structure 135. That is, the gate stack body structures 135 of adjacent vertical transistors 132 are continuous in the third direction. Therefore, the gate stack body structure 135 can be considered as part of a continuous structure extending in the third direction, wherein the continuous structure is adjacent to the vertical transistors 132 in the same row on the same side.

[0074] In some embodiments, the word lines of the memory cell array 110 have a similar structure to the gate electrode of the gate stack body structure 135. That is, the word lines include a first word line layer, a second word line layer, and a third word line layer extending in a third direction, respectively. In some embodiments, the first word line layer includes a first conductive layer 135A of a vertical transistor 132 coupled to the word line, and the first conductive layer 135A of each vertical transistor 132 may be a portion of the corresponding first word line layer. That is, the first word line layer may be an extension of the corresponding first conductive layer 135A. In some embodiments, the second word line layer includes a second conductive layer 135B of a vertical transistor 132 coupled to the word line, and the second conductive layer 135B of each vertical transistor 132 may be a portion of the corresponding second word line layer. That is, the second word line layer may be an extension of the corresponding second conductive layer 135B. In some embodiments, the third word line layer includes a third conductive layer 135C of a vertical transistor 132 coupled to the word line. The third conductive layer 135C of each vertical transistor 132 may be a portion of the corresponding third word line layer. In other words, the third word line layer can be an extension of the corresponding third conductive layer 135C.

[0075] The memory cell array 110 may also include multiple bit lines 150, each extending in a second direction (y direction) perpendicular to the third third direction (x direction). It should be understood that, for ease of wiring, the gate stack body structure 135 and the bit lines 150 may be formed in different lateral planes. In some embodiments, the bit lines 150 and the memory components are disposed on opposite sides of the vertical transistor 132 in the first direction, which simplifies the wiring of the bit lines 150 and reduces the coupling capacitance between the bit lines 150 and the memory components.

[0076] like Figure 1BAs shown, the vertical transistor 132 includes a vertical pattern 131 having a semiconductor layer 131A and a gate dielectric layer 131B sandwiched between a gate stack structure and the semiconductor layer 131A. The gate dielectric layer 131B may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 131B may include silicon oxide, i.e., a gate oxide. In some embodiments, the gate dielectric layer 131B includes a high-k dielectric. In some embodiments, such as... Figure 1B As shown, the vertical pattern 131 also includes an insulating core 131C surrounded by a gate dielectric layer 131B. The insulating core 131C can comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. By applying the insulating core 131C, leakage current of the vertical transistor 132 can be significantly suppressed.

[0077] Semiconductor layer 131A may comprise silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, semiconductor layer 131A may comprise metal oxides and semiconductor materials, such as low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide (InGaZn). In some embodiments, semiconductor layer 131A may comprise indium gallium zinc oxide (In... x Ga y Zn z O), Indium gallium silicon oxide (In) x Ga y Si z O), Indium tin zinc oxide (In x Sn y Zn z O), Indium zinc oxide (In) x Zn y O), zinc oxide (Zn) x O), zinc tin oxide (Zn) x Sn y O), zinc oxide (Zn) x O y N), Zirconium zinc tin oxide (Zr) x Zn y Sn z O), tin oxide (Sn) x O), hafnium indium zinc oxide (Hf) x In y Zn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), aluminum zinc tin oxide (Al) x Zn y Snz O), ytterbium gallium zinc oxide (Yb x Ga y Zn z O), Indium gallium oxide (In) x Ga y One or more of the following: O).

[0078] like Figure 1B As shown, the vertical transistor 132 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed at both ends of the semiconductor layer 131A in a first direction (z-direction). The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the first direction (z-direction) by a gate structure.

[0079] In some embodiments, the gate stack structure 135 of the vertical transistor 132 may include any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. In some embodiments, the gate stack structure 135 of the vertical transistor 132 may include a first conductive layer 135A coupled to the semiconductor layer 131A, a second conductive layer 135B coupled to the semiconductor layer 131A and located above the first conductive layer 135A along a first direction, and a third conductive layer 135C formed above a first side of the second conductive layer 135B, the first side being away from the first conductive layer 135A. That is, the first conductive layer 135A and the third conductive layer 135C are located at opposite ends of the channel region on the semiconductor layer 131A, and close to the source and drain of the vertical transistor 132. The second conductive layer 135B is located between the first conductive layer 135A and the third conductive layer 135C along a first direction, and is coupled in the middle to the channel region of the semiconductor layer 131A. In some embodiments, the gate stack structure 135 further includes a first dielectric layer located between the first conductive layer 135A and the second conductive layer 135B. Figure 1B (not shown in the image) and the second dielectric layer located between the second conductive layer 135B and the third conductive layer 135C. Figure 1B (Not shown in the diagram). The first and second dielectric layers are configured as conductive layers of the gate stack body structure 135 to isolate each other, so that they can be independently coupled to different voltages.

[0080] In some embodiments, a first conductive layer 135A is coupled to a first power supply, a second conductive layer 135B is coupled to a second power supply, and a third conductive layer 135C is coupled to a third power supply. The second power supply has a different voltage level than the first or third power supply. In some embodiments, the second power supply has a lower voltage level than both the first and third power supplies. In this way, the first conductive layer 135A and the third conductive layer 135C will be coupled to a higher voltage level, while the second conductive layer 135B will be coupled to a lower voltage level. The effect caused by the lower barrier due to the voltage difference between the source and drain of the vertical transistor 132 can be canceled out by the voltage difference between the first conductive layer 135A and the second conductive layer 135B or the voltage difference between the third conductive layer 135C and the second conductive layer 135B.

[0081] In some embodiments, for example, during a write operation, the voltage applied to the drain of the vertical transistor 132 is higher than the voltage applied to the source of the vertical transistor 132, and due to the voltage difference, the barrier near the drain in the channel region decreases. In this case, the voltage level applied to the first conductive layer 135A is higher than the voltage level applied to the second conductive layer 135B and the third conductive layer 135C. Therefore, the barrier reduction is offset, and leakage caused by barrier losses is suppressed. In some embodiments, for example, during a read operation, the voltage applied to the source of the vertical transistor 132 is higher than the voltage applied to the drain of the vertical transistor 132, and due to the voltage difference, the barrier near the source in the channel region decreases. In this case, the voltage level applied to the third conductive layer 135C is higher than the voltage level applied to the second conductive layer 135B and the first conductive layer 135A. Therefore, the barrier reduction is offset, and leakage caused by barrier losses is suppressed.

[0082] In some implementations, reference Figure 1B and Figure 1C The memory cell array 110 also includes a plurality of isolation walls 133 arranged in a second direction between two adjacent rows of vertical transistors 132. Figure 1C A schematic diagram of a semiconductor device in the xy-plane is shown. (Reference) Figure 1C The isolation wall 133 extends along a vertical plane perpendicular to the second direction. For example... Figure 1B and 1C As shown, two adjacent rows of vertically aligned transistors 132 facing upwards are isolated by an isolation wall 133. In some embodiments, reference... Figure 1CThe first distance D1 between the gate dielectric layer 131B of the first row of vertical transistors 132 and the isolation wall 133, which is disposed adjacent to the first side of the first row of transistors 132, is greater than 5 nm, such that the gate stack structure 135 of the first row of vertical transistors 132 will not be cut off by the isolation wall 133 and can be coupled to the same word line signal. In some embodiments, refer to Figure 1C The second distance D2 between the gate dielectric layer 131B of the first row of vertical transistors 132 and the isolation wall 133, which is disposed adjacent to the second side of the first row of transistors, is greater than 0 nm. Figure 1C As shown, the second side is opposite to the first side in the second direction. Because the gate stack structure 135 of the first row of vertical transistors 132 is not cut off by the isolation wall 133 due to the existence of the first distance D1, the second distance D2 can be minimized to increase the density of the memory cell array 110.

[0083] In some embodiments, the first conductive layer 135A, the second conductive layer 135B, and the third conductive layer 135C have equal thicknesses along the first direction, such as... Figure 1D As shown in the diagram. In some embodiments, the first conductive layer 135A, the second conductive layer 135B, and the third conductive layer 135C have different thicknesses along a first direction. For example, along the first direction, the thickness of the first conductive layer 135A is less than the thickness of the second conductive layer 135B, and along the first direction, the thickness of the third conductive layer 135C is less than the thickness of the second conductive layer 135B. In some embodiments, the thickness of the first conductive layer 135A is equal to the thickness of the third conductive layer 135C, and the thickness of the third conductive layer 135C is less than the thickness of the second conductive layer 135B, such as... Figure 1E As shown in the diagram, the thicknesses of the first conductive layer 135A, the second conductive layer 135B, and the third conductive layer 135C can be designed based on the length of the channel region of the vertical transistor 132 and the need for different gate control capabilities. The embodiments in this disclosure are illustrative and should not be construed as limiting the scope of this disclosure.

[0084] In some implementations, such as Figure 1B and 1C As shown, for example, the vertical pattern 131 may have a semi-circular or semi-elliptical shape, with an arcuate side facing the isolation wall 133 on the first side and a linear side facing the isolation wall 133 on the second side. In some embodiments, the arcuate side contacts the gate stack body structure 135 to obtain a larger contact area compared to the linear side. It should be understood that the vertical pattern 131 may have any suitable shape, such as a rectangular shape, as shown in the figure. Figure 2 As shown, Figure 2A schematic diagram of a memory cell array 210 according to some embodiments of the present disclosure is shown. In some embodiments, the vertical pattern 231 includes a semiconductor layer 231A, a gate dielectric layer 231B, and an insulating core 231C. That is, the cross-section of the vertical pattern 231 in a planar view (e.g., in the xy plane) may have a square or rectangular shape. It should be noted that the vertical pattern 231 may have any other suitable shape. The embodiments in this disclosure are illustrative and should not be construed as limiting the scope of this disclosure.

[0085] Figure 1F A cross-sectional view of a memory cell array 110 according to some embodiments of the present disclosure is shown, illustrating memory components coupled to vertical patterns 131 via contacts. The memory cell array 110 may include a plurality of vertical transistors and memory components correspondingly coupled to the vertical transistors. In some embodiments, the vertical transistors include a plurality of vertical patterns 131 and a gate stack body structure 135 including a plurality of conductive layers. In some embodiments, the memory components may include vertical capacitors 122, such as… Figure 1F As shown in the diagram. The vertical capacitor 122 can be a cylindrical capacitor, which can be formed after the vertical transistor 132 is formed. Alternatively, the vertical capacitor 122 can be a cup-shaped capacitor, which is formed before the vertical transistor 132 is formed. In such an embodiment, the high-temperature process for forming the cup-shaped capacitor does not affect the formation of the vertical transistor 132. Therefore, a metal-oxide-semiconductor can be used as the channel structure of the vertical transistor 132.

[0086] The vertical capacitor 122 may include a first electrode 125 coupled to a corresponding vertical pattern 131, a capacitor dielectric 121 coupled to the first electrode 125, and a second electrode 123 coupled to the capacitor dielectric 121. That is, the storage component may be a vertical capacitor in which the first and second electrodes and the capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric may be sandwiched between the first and second electrodes. In some embodiments, each first electrode is coupled to the source or drain of a corresponding vertical transistor 132 in the same memory cell, while all second electrodes are portions coupled to a grounded common plate (e.g., common ground).

[0087] It should be understood that the structure and configuration of capacitor 122 are not limited to Figure 1FExamples are provided, and any suitable structure and configuration may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate capacitors. In some embodiments, the capacitor dielectric 121 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, the capacitor 122 may be a ferroelectric capacitor used in an FRAM cell, and the capacitor dielectric 121 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the first electrode 125 and the second electrode 123 comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0088] like Figure 1F As shown, according to some embodiments, the vertical pattern 131 extends vertically through and contacts the gate stack structure. The lower end of the vertical pattern 131 contacts the bit line 150, and the upper end of the vertical pattern 131 contacts the contact 137, which couples with the vertical capacitor 122. That is, due to the vertical arrangement of the memory cells 130, the bit line 150 and the vertical capacitor 122 can be arranged in different planes in the vertical direction and coupled to opposite ends of the vertical pattern 131 in the vertical direction. In some embodiments, the bit line 150 and the vertical capacitor 122 are arranged on opposite sides of the vertical pattern 131 in the vertical direction, which simplifies the wiring of the bit line 150 and reduces the coupling capacitance between the bit line 150 and the vertical capacitor 122.

[0089] In some implementations, such as Figure 3 and 4 As shown, the vertical transistor 132 can be a gate-all-around (GAA) vertical transistor, wherein the gate structure can surround the corresponding vertical pattern. Figure 3 A schematic diagram of a memory cell array 310 according to some embodiments of the present disclosure is shown. Figure 4 A schematic diagram of a memory cell array 410 according to some embodiments of the present disclosure is shown.

[0090] refer to Figure 3The memory cell array 310 differs from the memory cell array 110 in the structure of the vertical patterns 231 and 331. In some embodiments, the vertical pattern 331 includes a semiconductor layer 331A, a gate dielectric layer 331B, and an insulating core 331C. The vertical pattern 331 differs from the vertical pattern 131 in that the vertical pattern 131 is partially surrounded by the gate stack structure 135, while the vertical pattern 331 is completely surrounded by the gate stack structure 135. The memory cell array 310 also includes a plurality of isolation walls 133 arranged in a second direction between adjacent rows of vertical transistors 132. Figure 3 A schematic diagram of a semiconductor device in the xy-plane is shown. (Reference) Figure 3 The isolation wall 133 extends along a vertical plane perpendicular to the second direction. Two adjacent rows of vertical transistors 132 in the third direction are isolated by the isolation wall 133. In some embodiments, the first distance D1 between the gate dielectric layer 331B of the first row of vertical transistors 132 and the isolation wall 133, which is positioned adjacent to a first side of the first row of transistors 132, is greater than 5 nm, such that the gate stack structure 135 of the first row of vertical transistors 132 will not be interrupted by the isolation wall 133 and can be coupled to the same word line signal. In some embodiments, refer to... Figure 3 The second distance D2 between the gate dielectric layer 331B of the first row of vertical transistors 132 and the isolation wall 133, which is disposed adjacent to the second side of the first row of transistors, is greater than 5 nm. The second side is opposite to the first side in the second direction.

[0091] It should be understood that the vertical pattern 331 can have any suitable shape, such as a rectangular shape, like... Figure 4 As shown in the image. Figure 4 A schematic diagram of a memory cell array 410 according to some embodiments of the present disclosure is shown. In some embodiments, the vertical pattern 431 includes a semiconductor layer 431A, a gate dielectric layer 431B, and an insulating core 431C. That is, the cross-section of the vertical pattern 431 in a planar view (e.g., in the xy plane) may have a square or rectangular shape. It should be noted that the vertical pattern 431 may have any other suitable shape. The embodiments in this disclosure are illustrative and should not be construed as limiting the scope of this disclosure.

[0092] Figure 5 A schematic diagram of a memory cell array 510 of a semiconductor device 100 according to some embodiments of the present disclosure is shown. In some embodiments, such as Figure 1B and Figure 5As shown, the difference between memory cell array 510 and memory cell array 110 lies in the structure of gate stack body structure 135 and gate stack body structure 535. The memory components and bit lines in memory cell array 510 are the same as or similar to those found in memory cell array 110. Therefore, from... Figure 5 These components have been omitted to avoid redundancy.

[0093] refer to Figure 5 The gate stack structure 535 of the memory cell array 510 includes a second conductive layer 535B coupled to the semiconductor layer 131A and a third conductive layer 535C formed above a first side of the second conductive layer 535B, the first side being away from the first conductive layer 535A. In some embodiments, the gate stack structure 535 further includes a second dielectric layer located between the second conductive layer 535B and the third conductive layer 535C. Figure 5 (Not shown in the diagram). The second dielectric layer is configured as a conductive layer of the gate stack body structure 535, allowing them to be independently coupled to different voltages. (e.g.) Figure 5 As shown, the third conductive layer 535C is located at the first end of the channel region on the semiconductor layer 131A and is close to one of the source and drain of the vertical transistor 132. The second conductive layer 535B is located below the third conductive layer 535C along a first direction and is coupled to the middle of the channel region and the second end of the semiconductor layer 131A close to the other of the source and drain of the vertical transistor 132.

[0094] In some embodiments, the second conductive layer 535B is coupled to a second power supply, and the third conductive layer 535C is coupled to a third power supply. The second power supply has a different voltage level than the third power supply. In some embodiments, the second power supply has a lower voltage level than the third power supply. In this way, the third conductive layer 535C will be coupled to the higher voltage level, while the second conductive layer 535B will be coupled to the lower voltage level. The effect caused by the lower barrier due to the voltage difference between the source and drain of the vertical transistor 132 can be canceled out by the voltage difference between the third conductive layer 535C and the second conductive layer 535B.

[0095] In some embodiments, the second conductive layer 535B and the third conductive layer 535C have different thicknesses along the first direction. For example, along the first direction, the thickness of the third conductive layer 535C is less than the thickness of the second conductive layer 535B, such as... Figure 5 As shown in the diagram. The thicknesses of the second conductive layer 535B and the third conductive layer 535C can be designed based on the length of the channel region of the vertical transistor 132 and the need for different gate control capabilities. The embodiments in this disclosure are illustrative and should not be construed as limiting the scope of this disclosure.

[0096] According to some implementations of this disclosure Figure 6A A schematic diagram of a memory cell array 610 of a semiconductor device 100, in which the storage components are omitted, is shown. Figure 6B A top view of memory cell array 610 is shown. The difference between memory cell array 610 and memory cell array 110 lies in the arrangement of the storage components 634 and bit lines 650, such as... Figure 6A As shown, for ease of description, the storage component is not shown. Figure 6A As shown in the diagram. It should be understood that the storage component can be coupled to the vertical pattern 131 via contact 637, as... Figure 6A As shown in the diagram. In some embodiments, the storage components and bit lines 150 are located on either side of the vertical transistor 132 in a first direction, as shown in the diagram. Figure 1F As shown in the diagram. In some embodiments, bit line 650 and storage components are located on a first side and a second side of transistor 132. The second side is opposite to the first side along a first direction. Figure 6A and Figure 6B As shown, bit lines 650 and contacts 637 are arranged in an alternating pattern on each of the first and second sides, such that bit lines 650 and storage components are arranged in an alternating pattern on each of the first and second sides.

[0097] To avoid interference between two adjacent memory units in the memory cell array 110, the memory units are isolated by a dielectric layer. Furthermore, a minimum distance must be maintained between adjacent memory units to mitigate the risk of parasitic effects. Therefore, the cross-sectional area of ​​the memory units cannot be maximized, which limits the storage capacity of the memory device. To address this problem, such as... Figure 6A and Figure 6B As shown, bit line 650 and memory components are arranged in a mixed pattern on both sides of vertical transistor 132 in a first direction. There is no specific requirement for the size of bit line 650, and the width of bit line 650 in the third direction can be minimized to reserve more space for contact 637 and the corresponding memory components. Therefore, compared with... Figure 1B Compared to the cross-sectional area of ​​the storage component shown, the cross-sectional area of ​​the storage component can be greatly increased.

[0098] In some implementations, reference Figure 6A and Figure 6B The memory cell array 610 also includes a plurality of isolation walls 133 arranged in a second direction between two adjacent rows of vertical transistors 132. (Reference) Figure 6BThe isolation wall 133 extends along a vertical plane perpendicular to the second direction. Two adjacent rows of vertical transistors 132 in the third direction are isolated by the isolation wall 133. In some embodiments, the contacts 637 arranged on both sides of the isolation wall 133 and the corresponding memory components are misaligned with each other, as shown in FIG6. This misalignment of the contacts 637 can further increase the cross-sectional area of ​​the memory components without reducing the minimum distance between two adjacent memory components.

[0099] This disclosure also provides a method for manufacturing a memory device. The method includes: forming an array of transistors extending along a first direction, each transistor including a semiconductor layer and a source region and a drain region located at two opposite ends of the semiconductor layer. The method further includes: forming a gate stack structure coupled to the semiconductor layer and covering an intermediate region of the semiconductor layer between the source and drain regions. The gate stack structure includes: a first conductive layer coupled to the transistors, a second conductive layer coupled to the transistors and located above the first conductive layer along the first direction, and a third conductive layer formed above a first side of the second conductive layer, the first side being remote from the first conductive layer. The gate stack structure also includes a first dielectric layer located between the first conductive layer and the second conductive layer, and a second dielectric layer located between the second conductive layer and the third conductive layer.

[0100] Figure 7 A flowchart of a manufacturing method 700 for forming a storage structure according to some embodiments of the present disclosure is shown. Figure 8A-8I Various embodiments according to this disclosure are shown in Figure 7 The diagram illustrates certain manufacturing stages of a semiconductor device according to method 700. It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 7 The different execution sequences are shown.

[0101] like Figure 7 and Figure 8A As shown, method 700 may begin with operation 702, in which a stacked structure 810 is formed on substrate 801. In some embodiments, substrate 801 may be a semiconductor substrate, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0102] In some embodiments, the stacked structure 810 forms a gate stack structure of the vertical transistor 132 and includes a stack of conductive and dielectric layers alternately arranged along a first direction. The dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. The conductive layer may include any suitable conductive material, such as polysilicon, metal (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. For example, the conductive layer may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode includes multiple conductive layers, such as a W layer on a TiN layer.

[0103] In some embodiments, the stacked structure 810 includes a stack of sacrificial layers and dielectric layers alternately arranged along a first direction. After the semiconductor layer is formed, the sacrificial layer is replaced by a conductive layer. (See reference...) Figure 8A , Figure 8A A schematic diagram of a semiconductor device after the formation of a stacked structure 810 is shown. The stacked structure 810 includes a first sacrificial layer 813A, a second sacrificial layer 813B, and a third sacrificial layer 813C disposed along a first direction. The stacked structure 810 also includes a first dielectric layer 811A, a second dielectric layer 811B, a third dielectric layer 811C, and a fourth dielectric layer 811D disposed alternately with the sacrificial layers along the first direction. The sacrificial layers comprise any suitable dielectric material having an etch ratio different from that of the dielectric layers. For example, the first dielectric layer 811A, the second dielectric layer 811B, the third dielectric layer 811C, and the fourth dielectric layer 811D comprise silicon oxide, while the first sacrificial layer 813A, the second sacrificial layer 813B, and the third sacrificial layer 813C are made of silicon nitride.

[0104] In some embodiments, the stacked structure 810 can be formed by a series of manufacturing processes, including thin film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) and patterning processes (e.g., photolithography, dry etching, wet etching, cleaning, chemical mechanical polishing (CMP), etc.).

[0105] like Figure 7 As shown, method 700 can proceed to operation 704, in which a plurality of holes 821 are formed along a first direction through the stacked structure 810. The plurality of holes 821 are configured to form a vertical pattern therein. Figure 8B A schematic diagram of a semiconductor device after multiple holes 821 have been formed is shown.

[0106] In some embodiments, the stacked structure 810 includes multiple layers made of different materials, such as Figure 8A and Figure 8BAs shown in the diagram. Therefore, a selective method will be needed to create the hole 821. For example, wet etching (e.g., buffered oxide etching (BOE)) or dry etching (e.g., reactive ion etching (RIE)) can be applied to selectively etch the fourth dielectric layer 811D (made of silicon oxide). Silicon oxide can be etched relatively easily with a buffered HF solution or specific gaseous chemicals in the RIE. After etching the fourth dielectric layer 811D, the third sacrificial layer 813C (made of silicon nitride) is then selectively etched. Silicon nitride is more difficult to etch than silicon oxide due to its hardness and chemical resistance, and can be etched using a RIE with a suitable gas mixture (e.g., chemicals based on CF4, SF6, or Cl2). The RIE can selectively etch the nitride material without significantly affecting the underlying oxide. The sacrificial and dielectric layers of the stacked structure 810 can be etched alternately until the substrate 801 is exposed from the hole 821, as shown in the diagram. Figure 8B As shown in the image.

[0107] like Figure 7 As shown, method 700 can proceed to operation 704, in which a vertical pattern 820 is correspondingly formed in hole 821. Figure 8C A schematic diagram of the semiconductor device after the vertical pattern 820 has been formed is shown.

[0108] In some embodiments, the vertical pattern 820 includes a semiconductor layer 820A and a gate dielectric layer 820B sandwiched between the gate stack structure and the semiconductor layer 820A. The gate dielectric layer 820B may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 820B may include silicon oxide, i.e., a gate oxide. In some embodiments, the gate dielectric layer 820B includes a high-k dielectric. In some embodiments, the vertical pattern 820 also includes an insulating core 820C surrounded by the gate dielectric layer 820B, such as… Figure 8C As shown in the diagram. The insulating core 820C can comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. By applying the insulating core 820C, leakage current of the vertical transistor 132 can be significantly suppressed.

[0109] Semiconductor layer 820A may include silicon (e.g., single-crystal silicon, c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, semiconductor layer 131A may include metal oxides and semiconductor materials, such as low-temperature polycrystalline silicon (LTPS) and indium gallium zinc oxide. In some embodiments, semiconductor layer 820A may include indium gallium zinc oxide (In... x Ga y Zn zO), Indium gallium silicon oxide (In) x Ga y Si z O), Indium tin zinc oxide (In x Sn y Zn z O), Indium zinc oxide (In) x Zn y O), zinc oxide (Zn) x O), zinc tin oxide (Zn) x Sn y O), zinc oxide (Zn) x O y N), Zirconium zinc tin oxide (Zr) x Zn y Sn z O), tin oxide (Sn) x O), hafnium indium zinc oxide (Hf) x In y Zn z O), gallium zinc tin oxide (Ga) x Zn y Sn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), ytterbium gallium zinc oxide (Yb x Ga y Zn z O), Indium gallium oxide (In) x Ga y One or more of the following: O).

[0110] like Figure 8C As shown, the vertical transistor 132 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed at both ends of the semiconductor layer 820A in a first direction (z-direction). For example, the source region may be formed by a region of the semiconductor layer 820A covered by the fourth dielectric layer 811D, and the drain region may be formed by a region of the semiconductor layer 820A covered by the first dielectric layer 811A. The source and drain electrodes may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain electrodes may be separated in the first direction (z-direction) by a gate structure.

[0111] like Figure 7 As shown, method 700 can proceed to operation 706, in which the sacrificial layer is replaced by a conductive layer. Figure 8D A schematic diagram of the semiconductor device after the sacrificial layer has been replaced is shown.

[0112] like Figure 8C As shown, the first sacrificial layer 813A, the second sacrificial layer 813B, and the third sacrificial layer 813C are first removed. In some embodiments, the sacrificial layers can be removed by a suitable etching process (typically wet etching using hydrofluoric acid (HF) or BOE). In some embodiments, dry etching (RIE) with a suitable gas mixture can be used to remove the silicon oxide or other materials of the sacrificial layers. Conductive layers can then be formed in the spaces occupied by the sacrificial layers, respectively. For example, chemical vapor deposition (CVD) or physical vapor deposition (PVD) is typically used to deposit conductive materials such as tungsten (W), copper (Cu), aluminum (Al), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN)) or silicides. In some embodiments, for the tungsten to be formed, tungsten CVD (using a precursor similar to WF6) is typically used. Figure 8D As shown, a first conductive layer 815A is formed between the first dielectric layer 811A and the second dielectric layer 811B, a second conductive layer 815B is formed between the second dielectric layer 811B and the third dielectric layer 811C, and a third conductive layer 815C is formed between the third dielectric layer 811C and the fourth dielectric layer 811D. The conductive layers can be formed of the same material or different materials.

[0113] like Figure 7 As shown, method 700 can proceed to operation 708, wherein an isolation wall 830 is formed in the second direction between two adjacent rows of vertical transistors to prevent electrical interference or crosstalk between adjacent transistors. Figure 8E and 8F A schematic diagram of a semiconductor device during the fabrication of isolation wall 830 is shown.

[0114] In some embodiments, multiple isolation trenches 831 are formed in a semiconductor device along a third direction using photolithography and etching processes. For example, a photoresist layer is applied to the surface of the semiconductor device and exposed to UV light through a photomask with a desired trench pattern. The exposed photoresist will harden, and the unexposed areas will be washed away in a development process. The photoresist pattern acts as a mask for subsequent etching steps. After photolithography, the semiconductor device undergoes etching to create the isolation trenches 831 using either dry etching (reactive ion etching (RIE)) or wet etching. RIE is typically used because it offers good selectivity, vertical trench profile, and accuracy. The depth of the isolation trenches 831 depends on the depth of the stacked structure 810 and the isolation requirements. In some embodiments, the isolation trenches 831 extend through the stacked structure 810, such as... Figure 8E As shown in the diagram. In some embodiments, the isolation trench 831 may extend into the substrate 801.

[0115] Then, an isolation wall 830 is formed in the isolation trench 831, such as Figure 8F As shown, after etching the isolation trench 831, the isolation trench 831 is typically filled with an insulating material such as silicon oxide, silicon nitride, or other dielectrics. This filling can be performed using CVD, PVD, ALD, or any other suitable process. After forming the isolation wall 830, CMP can be used to polish the surface of the semiconductor device to remove any excess material from the top surface and ensure that the isolation wall 830 is filled flush with the semiconductor device. Reference Figure 8F The isolation wall 830 extends along a vertical plane perpendicular to the second direction. Two adjacent rows of vertical transistors in the third direction are isolated by the isolation wall 830. In some embodiments, reference... Figure 8E A first distance D1 between the gate dielectric layer 820B of the first row of vertical transistors 132 and the isolation wall 830 adjacent to the first side of the first row of transistors 132 is greater than 5 nm, such that the gate stack structure of the first row of vertical transistors 132 will not be interrupted by the isolation wall 830 and can be coupled to the same word line signal. In some embodiments, a second distance D2 between the gate dielectric layer 820B of the first row of vertical transistors 132 and the isolation wall 830 adjacent to the second side of the first row of transistors is greater than 0 nm. The second side is opposite to the first side in a second direction. Because the gate stack structure of the first row of vertical transistors 132 is not interrupted by the isolation wall 830 due to the presence of the first distance D1, the second distance D2 can be minimized to increase the density of the memory cell array 110.

[0116] like Figure 7 As shown, method 700 can proceed to operation 710, in which a plurality of storage components (not shown) are formed to be coupled to a vertical transistor in a first direction, respectively. Figure 8G A schematic diagram of the semiconductor device after the formation of the memory component 834 is shown.

[0117] like Figure 8GAs shown, the storage component can be coupled to the source or drain of the vertical transistor 132 via a corresponding contact 837. In some embodiments, each memory cell 130 includes a storage component for storing data bits as positive or negative charges and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selecting) access to it. In some embodiments, each memory cell is a single-transistor single-capacitor (1T1C) cell. In some embodiments, the storage component can be a cylindrical capacitor, which can be formed after the vertical pattern is formed. The storage component can be a cup-shaped capacitor, which is formed before the vertical transistor is formed. In such embodiments, the high-temperature process of forming the cup-shaped capacitor does not affect the formation of the vertical pattern. Therefore, metal-oxide-semiconductor can be used as the channel structure for the vertical pattern. The storage component can include a vertical capacitor comprising a first electrode coupled to a corresponding vertical pattern, a capacitor dielectric coupled to the first electrode, and a second electrode coupled to the capacitor dielectric. That is, the storage component can be a vertical capacitor in which the first electrode and the second electrode and the capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the first electrode and the second electrode. In some embodiments, each first electrode is coupled to the source or drain of a corresponding vertical transistor in the same memory cell, while all second electrodes are portions coupled to a grounded common plate (e.g., common ground). In some embodiments, the capacitor dielectric comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, TiO₂, or any combination thereof. It should be understood that in some examples, the vertical capacitor may be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the first and second electrodes comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0118] like Figure 7 As shown, method 700 can proceed to operation 712, in which multiple bit lines 850 are formed to be coupled to vertical transistors in a first direction, respectively. Figure 8H A schematic diagram of a semiconductor device after the formation of memory components is shown. In some embodiments, substrate 801 is removed to expose the second side of the stacked structure 810 and the vertical pattern 820. (See reference...) Figure 8H Bit line 850 extends along the second direction and is coupled to one side of semiconductor layer 820A.

[0119] In some embodiments, the storage components and bit lines 850 are located on either side of the vertical transistor 132 in a first direction, such as... Figure 8HAs shown in the diagram. In some embodiments, bit line 850 and storage components are located on a first side and a second side of transistor 132. The second side is opposite to the first side along a first direction. Figure 8I As shown, bit lines 850 and memory components (not shown) are arranged in an alternating pattern on each of the first and second sides. The memory components are coupled to corresponding vertical patterns via contacts 837, as... Figure 8I As shown in the figure. In some embodiments, the bit line 850 and the storage component are arranged in a mixed pattern on both sides of the vertical transistor along the first direction, and the cross-sectional area of ​​the storage component 834 can be increased to suppress parasitic effects.

[0120] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance given herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0121] The breadth and scope of this disclosure should not be limited by any of the embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device comprising an array of transistors, each transistor comprising: A semiconductor layer extending along a first direction; The source and drain regions are located at two opposite ends of the semiconductor layer; as well as A gate stack structure coupled to and covering the semiconductor layer in the intermediate region between the source region and the drain region; wherein... The gate stack body structure includes: A first conductive layer coupled to the semiconductor layer; A second conductive layer coupled to the semiconductor layer and located above the first conductive layer along the first direction; and A first dielectric layer located between the first conductive layer and the second conductive layer.

2. The memory device according to claim 1, wherein, The first conductive layer is coupled to the first power source; and The second conductive layer is coupled to a second power supply having a different voltage level than the first power supply.

3. The memory device according to claim 1, further comprising: A third conductive layer is formed above a first side of the second conductive layer, wherein the first side is away from the first conductive layer; as well as A second dielectric layer located between the second conductive layer and the third conductive layer.

4. The memory device according to claim 3, wherein, The first conductive layer is coupled to the first power source; The second conductive layer is coupled to the second power source; and The third conductive layer is coupled to the third power source; The second power supply has a different voltage level than the first power supply or the third power supply.

5. The memory device according to claim 1, further comprising: A bit line coupled to the source region or the drain region of the transistor and extending along a second direction, wherein the second direction is perpendicular to the first direction.

6. The memory device according to claim 5, further comprising: An array of memory components, each coupled to the transistor; wherein, The bit line is located on the first side of the transistor; and The storage component is located on the second side of the transistor, which is opposite to the first side along the first direction.

7. The memory device according to claim 5, further comprising: An array of memory components, each coupled to the transistor; wherein, The bit line and the storage component are located on a first side and a second side of the transistor, with the second side opposite to the first side along the first direction; and The bit lines and the storage components are arranged in an alternating pattern on each side.

8. The memory device according to claim 1, further comprising: A gate dielectric layer located between the semiconductor layer and the gate stack; as well as An isolation wall is arranged between two adjacent rows of vertical transistors in a second direction, wherein the second direction is perpendicular to the first direction.

9. The memory device according to claim 8, wherein, The first distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the first side of the first row of transistors is greater than 5 nm.

10. The memory device according to claim 9, wherein, The second distance between the gate dielectric layer of the first row transistor and the isolation wall disposed adjacent to the second side of the first row transistor is greater than 0 nm, the second side being opposite to the first side in the second direction.

11. The memory device of claim 10, further comprising: An array of memory components, each coupled to the transistor; The storage components located on both sides of the isolation wall are not aligned with each other.

12. The memory device according to claim 3, wherein, The first conductive layer, the second conductive layer, and the third conductive layer have equal thicknesses along the first direction.

13. The memory device according to claim 3, wherein, Along the first direction, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the thickness of the third conductive layer.

14. The memory device according to claim 1, wherein, Along the first direction, the thickness of the second conductive layer is greater than or equal to the thickness of the first conductive layer.

15. A memory device, comprising: An array of transistors, wherein the transistors are connected in parallel and extend along a first direction; Word lines, each word line being coupled to a row of transistors arranged along a third direction; as well as A first isolation wall, arranged in an alternating pattern with the letter lines along a second direction, wherein the first direction, the third direction, and the second direction are perpendicular to each other; wherein... The word lines include: The first conductive layer coupled to the transistor; and A second conductive layer coupled to the transistor and isolated from the first conductive layer along the first direction by a first dielectric layer.

16. The memory device according to claim 15, wherein, The first conductive layer is coupled to the first power source; and The second conductive layer is coupled to a second power source, which has a different voltage level than the first power source.

17. The memory device of claim 15, further comprising: A third conductive layer is formed above a first side of the second conductive layer, wherein the first side is away from the first conductive layer; as well as A second dielectric layer located between the second conductive layer and the third conductive layer.

18. The memory device according to claim 17, wherein, The first conductive layer is coupled to the first power source; The second conductive layer is coupled to the second power source; and The third conductive layer is coupled to the third power source; The second power supply has a different voltage level than the first power supply or the third power supply.

19. The memory device of claim 15, further comprising: A bit line coupled to the source or drain region of the transistor and extending along a second direction perpendicular to the first direction and the third direction.

20. The memory device of claim 19, further comprising: An array of memory components, each coupled to the transistor; wherein, The bit line is located on the first side of the transistor; and The storage component is located on the second side of the transistor, which is opposite to the first side along the first direction.

21. The memory device of claim 19, further comprising: An array of memory components, each coupled to the transistor; wherein, The bit line and the storage component are located on a first side and a second side of the transistor, with the second side opposite to the first side along the first direction; and The bit lines and the storage components are arranged in an alternating pattern on each side.

22. The memory device according to claim 15, wherein, The transistor includes a semiconductor layer extending along the first direction and a gate dielectric layer located between the semiconductor layer and the word line coupled to the transistor; and The memory device further includes an isolation wall disposed in a second direction between two adjacent rows of vertical transistors, wherein the second direction is perpendicular to the first direction and the third direction.

23. The memory device according to claim 22, wherein, The first distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the first side of the first row of transistors is greater than 5 nm.

24. The memory device according to claim 23, wherein, The second distance between the gate dielectric layer of the first row transistor and the isolation wall disposed adjacent to the second side of the first row transistor is greater than 0 nm, the second side being opposite to the first side in the second direction.

25. The memory device of claim 24, further comprising: An array of memory components, each coupled to the transistor; The storage components located on both sides of the isolation wall are not aligned with each other.

26. The memory device according to claim 17, wherein, The first conductive layer, the second conductive layer, and the third conductive layer have equal thicknesses along the first direction.

27. The memory device according to claim 17, wherein, Along the first direction, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the thickness of the third conductive layer.

28. The memory device according to claim 17, wherein, Along the first direction, the thickness of the second conductive layer is greater than or equal to the thickness of the first conductive layer.

29. A method for manufacturing a memory device, comprising: An array of transistors extending along a first direction is formed, each transistor including a semiconductor layer and a source region and a drain region located at two opposite ends of the semiconductor layer; A gate stack structure is formed that is coupled to the semiconductor layer and covers the intermediate region of the semiconductor layer between the source region and the drain region; wherein... The gate stack body structure includes: The first conductive layer coupled to the transistor; A second conductive layer coupled to the transistor and located above the first conductive layer along the first direction; and A first dielectric layer located between the first conductive layer and the second conductive layer.

30. The method according to claim 29, wherein, The gate stack body structure includes: A third conductive layer is formed above a first side of the second conductive layer, the first side being away from the first conductive layer; and A second dielectric layer located between the second conductive layer and the third conductive layer.

31. The method according to claim 29, wherein, Forming the gate stack body structure includes: A stacked structure is formed, the stacked structure including a first sacrificial layer, a second sacrificial layer, and a first dielectric layer located between the first sacrificial layer and the second sacrificial layer; and The first and second sacrificial layers are formed by replacing the first and second sacrificial layers with conductive materials.

32. The method according to claim 31, wherein, The array forming the transistors includes: Forming a hole through the stacked structure along the first direction; and The hole is filled using the semiconductor layer and a gate dielectric layer located between the semiconductor layer and the stacked structure.

33. The method of claim 32, further comprising: A bit line is formed that is coupled to the source or drain region of the transistor and extends along a second direction, wherein the second direction is perpendicular to the first direction.

34. The method of claim 33, further comprising: An array of memory components, each coupled to the transistor, is formed; wherein, The bit line is located on the first side of the transistor; and The storage component is located on the second side of the transistor, which is opposite to the first side along the first direction.

35. The method of claim 33, further comprising: An array of memory components, each coupled to the transistor, is formed; wherein, The bit line and the storage component are located on a first side and a second side of the transistor, with the second side opposite to the first side along the first direction; and The bit lines and the storage components are arranged in an alternating pattern on each side.

36. The method of claim 32, further comprising: A first isolation wall is formed between two adjacent rows of vertical transistors arranged in a second direction, wherein the second direction is perpendicular to the first direction.

37. The method according to claim 36, wherein, The first distance between the gate dielectric layer of the first row of transistors and the isolation wall disposed adjacent to the first side of the first row of transistors is greater than 5 nm.

38. The method according to claim 37, wherein, The second distance between the gate dielectric layer of the first row transistor and the isolation wall disposed adjacent to the second side of the first row transistor is greater than 0 nm, the second side being opposite to the first side in the second direction.

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