Method of forming a semiconductor structure
By employing chemical mechanical polishing and dry etching processes during the formation of the SGT semiconductor structure, the position and end face of the polysilicon layer are adjusted to achieve flush alignment, thus solving the problem of reduced electrical performance in existing processes, improving alignment accuracy and electrical performance uniformity, and enhancing the electrical performance of the semiconductor structure.
Patent Information
- Application Number
- CN202610914001.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-23
- Publication Date
- 2026-08-25
AI Technical Summary
The existing SGT semiconductor structure fabrication process leads to reduced electrical performance, especially in high-frequency power conversion, server power supplies, communication base station power supplies, electric vehicle on-board chargers and battery management systems, where the electrical performance is not good enough.
By employing chemical mechanical polishing and a first dry etching process during the formation of the semiconductor structure, the end faces of the polysilicon layer in the alignment mark groove and the gate groove are made flush, thereby improving alignment accuracy and electrical performance uniformity. This includes forming a first epitaxial layer, alignment mark groove and gate groove, filling polysilicon layer and isolation layer, and adjusting the position of the polysilicon layer through precise polishing and etching processes.
This improved the electrical performance of the semiconductor structure, reduced the unevenness of the top end face of the alignment mark, enhanced the recognition accuracy and electrical performance uniformity of the alignment machine, and improved the overall electrical performance of the SGT semiconductor structure.
Smart Images
Figure CN122641035A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device fabrication technology, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] Shielded Gate Trench (SGT) semiconductor devices (SGT semiconductor structures for short) are widely used in high-frequency power conversion (DC-DC converters, AC-DC adapters), server power supplies, communication base station power supplies, electric vehicle on-board chargers and battery management systems, and are especially suitable for medium and low voltage power systems with stringent requirements for efficiency, power density and heat dissipation.
[0003] However, the existing SGT semiconductor structure formation process has the problem of reduced electrical performance of the semiconductor structure. Therefore, how to improve the electrical performance of SGT semiconductor structure (hereinafter referred to as: electrical performance of semiconductor structure) has become a challenge. Summary of the Invention
[0004] The technical problem solved by the present invention is to improve the electrical performance of semiconductor structures by providing a method for forming semiconductor structures.
[0005] This invention provides a method for forming a semiconductor structure, including: forming a first epitaxial layer; Alignment mark grooves and gate grooves are formed within the first epitaxial layer, neither of which penetrates the first epitaxial layer; an alignment polysilicon layer is formed to fill the alignment mark grooves, and a shielding polysilicon layer is formed to fill the lower part of the gate grooves; an isolation layer is formed to fill the middle part of the gate grooves, the isolation layer being located on the shielding polysilicon layer, and the top surface of the isolation layer being lower than the top surface of the first epitaxial layer; a polysilicon material layer is formed to cover the first epitaxial layer, the polysilicon material layer filling the upper part of the gate grooves and covering the isolation layer; a portion of the polysilicon material layer is removed using a chemical mechanical polishing process; the remaining polysilicon material layer on the surface of the first epitaxial layer is removed using a first dry etching process; wherein, after the first dry etching process, the polysilicon material layer within the gate grooves forms a gate polysilicon layer, and the top end face of the alignment polysilicon layer within the alignment mark grooves and the top end face of the gate polysilicon layer above the gate grooves are flush with the upper surface of the first epitaxial layer.
[0006] Optionally, the grinding time of the chemical mechanical polishing process is selected from [70s, 90s]; the process parameters of the first dry etching process include: etching time selected from [15s, 30s], etching chamber pressure selected from [5mTorr, 9mTorr], etching power selected from [330W, 380W], O2 flow rate selected from [3sccm, 6sccm], SF6 flow rate selected from [18sccm, 22sccm], CF4 flow rate selected from [9sccm, 11sccm], and He flow rate selected from [140sccm, 160sccm].
[0007] Optionally, before forming the alignment mark groove and the gate groove, the forming method further includes: forming a stacked layer on the first epitaxial layer, the stacked layer including a stress buffer layer, a first etch barrier layer and a second etch barrier layer stacked sequentially; the alignment mark groove and the gate groove both penetrate the stacked layer.
[0008] Optionally, before forming the shielding polysilicon layer, and after forming the alignment mark groove and the gate groove, the forming method further includes: forming a gate dielectric layer covering the sidewall of the first epitaxial layer in the gate groove; the isolation layer, the shielding polysilicon layer, and the gate polysilicon layer all cover the sidewall of the gate dielectric layer.
[0009] Optionally, the thickness of the gate dielectric layer is selected from [400 angstroms, 600 angstroms]; the material of the gate dielectric layer is silicon oxide; the process for forming the gate dielectric layer includes: chemical vapor deposition process; the film formation process temperature for forming the gate dielectric layer is selected from [700°C, 900°C].
[0010] Optionally, the steps of forming an alignment polysilicon layer filling the alignment mark groove and forming a shielding polysilicon layer filling the lower part of the gate groove include: forming a polysilicon initial material layer covering the gate dielectric layer, the polysilicon initial material layer filling the alignment mark groove and the gate groove; using a second dry etching process to remove the polysilicon initial material layer on the surface of the gate dielectric layer and a portion of the polysilicon initial material layer in the gate groove, so as to correspondingly form the alignment polysilicon layer located in the alignment mark groove and the shielding polysilicon layer located in the lower part of the gate groove.
[0011] Optionally, the stress buffer layer is made of silicon oxide, and the thickness of the stress buffer layer is selected from [200 angstroms, 300 angstroms]; the first etch barrier layer is made of silicon nitride, and the thickness of the first etch barrier layer is selected from [1000 angstroms, 2000 angstroms]; the second etch barrier layer is made of silicon oxide, and the thickness of the second etch barrier layer is selected from [2000 angstroms, 4000 angstroms].
[0012] Optionally, the depth of the alignment mark groove is selected from [10000 angstroms, 60000 angstroms]; the depth of the gate groove is selected from [10000 angstroms, 60000 angstroms].
[0013] Optionally, the thickness of the polycrystalline silicon material layer covering the first epitaxial layer is selected from [7000 angstroms, 9000 angstroms].
[0014] Optionally, before forming the first epitaxial layer, the method further includes: providing a substrate; forming a second epitaxial layer on the substrate, wherein the first epitaxial layer covers the second epitaxial layer.
[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The method for forming a semiconductor structure provided in this invention includes: forming a first epitaxial layer; forming an alignment mark groove and a gate groove in the first epitaxial layer; forming an alignment polysilicon layer filling the alignment mark groove, and forming a shielding polysilicon layer filling the lower part of the gate groove; forming an isolation layer filling the middle part of the gate groove; forming a polysilicon material layer covering the first epitaxial layer, the polysilicon material layer filling the upper part of the gate groove and covering the isolation layer; removing a portion of the polysilicon material layer using a chemical mechanical polishing process; removing the remaining polysilicon material layer on the surface of the first epitaxial layer using a first dry etching process; after the first dry etching process, the polysilicon material layer in the gate groove forms a gate polysilicon layer; the process is first performed by chemical mechanical polishing. The process involves removing a portion of the polysilicon material layer on the upper surface of the first epitaxial layer, followed by a first dry etching process to remove the remaining polysilicon material layer on the surface of the first epitaxial layer. This allows the top end face of the alignment polysilicon layer within the alignment mark groove and the top end face of the gate polysilicon layer above the gate groove to be flush with the upper surface of the first epitaxial layer. This reduces the risk of unevenness between the top surfaces of the alignment polysilicon layers, improves the identification accuracy of the alignment machine for the alignment polysilicon layers, i.e., improves alignment accuracy, thereby improving the electrical performance of the semiconductor structure. Furthermore, reducing the unevenness of the top end face of the gate polysilicon layer improves the uniformity of electrical performance between SGT semiconductor structures, further enhancing the electrical performance of the semiconductor structure. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained as provided without creative effort.
[0017] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming alignment marks in a semiconductor structure.
[0018] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of this application. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] As can be seen from the background technology, the existing SGT semiconductor structure formation process has the problem of reduced electrical performance of the semiconductor structure. The reasons are analyzed below.
[0021] refer to Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming alignment marks in a semiconductor structure. Figure 1 This is a top view schematic diagram of the alignment mark 100 in a semiconductor structure. Figures 2 to 4 yes Figure 1 A schematic diagram of the structure corresponding to each step in the method for forming the alignment mark 100 of the semiconductor structure along the dashed line AA1.
[0022] refer to Figure 2 Provides substrate 102.
[0023] An epitaxial layer 104 is formed on the substrate 102.
[0024] The epitaxial layer 104 is formed with grooves 106 by processes such as exposure, development and etching.
[0025] refer to Figure 3 A polycrystalline silicon initial layer 108 is formed by chemical vapor deposition to cover the surface of the epitaxial layer 104, and the polycrystalline silicon initial layer 108 fills the groove 106.
[0026] refer to Figure 4 , combined Figure 1 and Figure 3 The polysilicon initial layer 108 is removed by chemical mechanical polishing process. The polysilicon initial layer 108 covering the surface of the epitaxial layer 104 is removed. The remaining polysilicon initial layer 108 in the groove 106 constitutes the alignment mark 100 of the semiconductor structure.
[0027] Continue to refer to Figure 4 In the step of removing the polysilicon initial layer 108 covering the surface of the epitaxial layer 104, the poor stability of the chemical mechanical polishing process damages the alignment marks 100 of the semiconductor structure, resulting in uneven top end faces of the alignment marks 100 (i.e., the alignment polysilicon layer). This reduces the accuracy of the alignment machine (exposure machine) in picking up the alignment marks 100 (alignment is performed using reflected light, such as infrared emission light), that is, it reduces the alignment accuracy when fabricating the semiconductor structure (alignment accuracy reflects the fitting accuracy after interlayer alignment), thereby reducing the electrical performance of the semiconductor structure.
[0028] The alignment mark 100 is used for interlayer alignment between semiconductor film layers. For example, if the control gate is made of polysilicon, alignment marks 100 made of polysilicon are formed simultaneously when the control gate (used to control the opening and closing of the semiconductor structure) is formed. This alignment is used to align the alignment marks (not shown) on the source / drain doped layer mask with the alignment mark 100 to form the source / drain doped layer.
[0029] In summary, existing semiconductor structure fabrication processes suffer from reduced electrical performance of the semiconductor structure.
[0030] This invention provides a method for forming a semiconductor structure, comprising: forming a first epitaxial layer; forming an alignment mark groove and a gate groove within the first epitaxial layer, wherein neither the alignment mark groove nor the gate groove penetrates the first epitaxial layer; forming an alignment polysilicon layer filling the alignment mark groove, and forming a shielding polysilicon layer filling the lower portion of the gate groove; forming an isolation layer filling the middle portion of the gate groove, wherein the isolation layer is located on the shielding polysilicon layer, and the top surface of the isolation layer is lower than the top surface of the first epitaxial layer; and forming a structure covering the first epitaxial layer. A polysilicon material layer is formed in the gate trench, which fills the upper part of the gate trench and covers the isolation layer. A portion of the polysilicon material layer is removed by chemical mechanical polishing. The remaining polysilicon material layer on the surface of the first epitaxial layer is removed by a first dry etching process. After the first dry etching process, the polysilicon material layer in the gate trench forms a gate polysilicon layer, and the top end face of the alignment polysilicon layer in the alignment mark trench and the top end face of the gate polysilicon layer on the upper part of the gate trench are flush with the upper surface of the first epitaxial layer.
[0031] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0032] refer to Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of this application.
[0033] refer to Figure 5 Provides a base of 200.
[0034] The substrate 200 is used to provide a process platform for the formation of the semiconductor structure and also serves as the drain doping layer of the SGT semiconductor structure.
[0035] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is monocrystalline silicon.
[0036] It should be noted that the doping type of the substrate 200 is determined based on the conductivity type of the charge carriers in the SGT semiconductor structure.
[0037] For ease of description, in this embodiment, the SGT semiconductor structure is an N-channel type, i.e., an N-type SGT semiconductor structure. Those skilled in the art can deduce the formation method of the P-type SGT semiconductor structure based on the embodiments of this application, but this does not limit this application.
[0038] In this embodiment, before forming the first epitaxial layer 204, the substrate 200 is provided, and the substrate 200 is heavily N-type doped to form the drain doped layer of the SGT semiconductor structure.
[0039] The substrate 200 is subjected to an annealing process.
[0040] Continue to refer to Figure 5 A second epitaxial layer 202 is formed on the substrate 200.
[0041] The second epitaxial layer 202 is used to prevent impurities in the substrate 200 from entering the first epitaxial layer 204, so as to improve the fabrication yield of the SGT semiconductor structure and improve the electrical performance of the SGT semiconductor structure.
[0042] In this embodiment, the doping type of the second epitaxial layer 202 is N-type doping, the doping concentration of the second epitaxial layer 202 is less than the doping concentration of the substrate 200, and the doping concentration of the second epitaxial layer 202 is greater than the doping concentration of the first epitaxial layer 204, so as to reduce the entry of doped ions or impurity ions in the substrate 200 into the first epitaxial layer 204.
[0043] In this embodiment, a second epitaxial layer 202 is formed on the substrate 200 through epitaxial and doping processes.
[0044] The second epitaxial layer 202 is subjected to an annealing process.
[0045] Continue to refer to Figure 5 This forms the first epitaxial layer 204.
[0046] The first epitaxial layer 204 is used as a drift region of the SGT semiconductor structure.
[0047] In this embodiment, the first epitaxial layer 204 is N-type doped.
[0048] In this embodiment, a first epitaxial layer 204 is formed on the second epitaxial layer 202 through epitaxial process and doping process, that is, the first epitaxial layer 204 covers the second epitaxial layer 202.
[0049] The first epitaxial layer 204 is subjected to an annealing process.
[0050] Continue to refer to Figure 5 In forming the alignment mark groove 214 (e.g. Figure 6 (as shown) and the gate recess 216 (as shown) Figure 6 As shown in the figure, the forming method further includes: forming a stacked layer 206 on the first epitaxial layer 204, the stacked layer 206 including a stress buffer layer 208, a first etch barrier layer 210 and a second etch barrier layer 212 stacked sequentially.
[0051] The stress buffer layer 208 is used to release the stress between the first etch barrier layer 210 and the first epitaxial layer 204, and to protect the surface of the first epitaxial layer 204.
[0052] The first etch barrier layer 210 is used to reduce the photolithography standing wave effect and improve the opening size (e.g., opening width) of the alignment mark groove 214 and the gate groove 216.
[0053] The second etch barrier layer 212 is used to improve the adhesion of the photoresist and to protect the first etch barrier layer 210.
[0054] In this embodiment, the stress buffer layer 208 is made of silicon oxide.
[0055] The thickness of the stress buffer layer 208 is selected from [200 angstroms, 300 angstroms]. By making the thickness of the stress buffer layer 208 greater than or equal to 200 angstroms, the stress between the first etch barrier layer 210 and the first epitaxial layer 204 can be better released, and the risk of voids in the stress buffer layer 208 can also be reduced. By making the thickness of the stress buffer layer 208 less than or equal to 300 angstroms, the manufacturing cycle can be reduced. In this embodiment, the thickness of the stress buffer layer 208 is 250 angstroms.
[0056] In this embodiment, the material of the first etching barrier layer 210 is silicon nitride.
[0057] The thickness of the first etch barrier layer 210 is selected from [1000 angstroms, 2000 angstroms]. By making the thickness of the first etch barrier layer 210 greater than or equal to 1000 angstroms, the photolithography standing wave effect can be better reduced. By making the thickness of the first etch barrier layer 210 less than or equal to 2000 angstroms, the process manufacturing cycle can be reduced. In this embodiment, the thickness of the first etch barrier layer 210 is 1500 angstroms.
[0058] In this embodiment, the material of the second etching barrier layer 212 is silicon oxide.
[0059] The thickness of the second etch barrier layer 212 is selected from [2000 angstroms, 4000 angstroms]. By making the thickness of the second etch barrier layer 212 greater than or equal to 2000 angstroms, it can be used to improve the adhesion of the photoresist and protect the first etch barrier layer 210. By making the thickness of the second etch barrier layer 212 less than or equal to 4000 angstroms, the process manufacturing cycle can be reduced. In this embodiment, the thickness of the second etch barrier layer 212 is 3000 angstroms.
[0060] refer to Figure 6 Alignment mark groove 214 and gate groove 216 are formed in the first epitaxial layer 204. Neither the alignment mark groove 214 nor the gate groove 216 penetrates the first epitaxial layer 204. Both the alignment mark groove 214 and the gate groove 216 penetrate the stacked layer 206.
[0061] The alignment mark groove 214 is used to provide a process basis for the formation process of the alignment mark, such as the interlayer alignment mark required for the alignment between the film layers of the SGT semiconductor structure.
[0062] The gate recess 216 is used for forming the gate polysilicon layer 230 (e.g., Figure 11 (as shown) and shielding polysilicon layer 224 (as shown) Figure 11 (As shown) provides the technological basis.
[0063] The depth of the alignment mark groove 214 is selected from [10,000 angstroms, 60,000 angstroms], which helps the alignment machine and testing equipment to better identify the alignment mark. In this embodiment, the depth of the alignment mark groove 214 is selected as 30,000 angstroms.
[0064] The depth of the gate recess 216 is selected from [10,000 angstroms, 60,000 angstroms]. By making the depth of the gate recess 216 greater than or equal to 10,000 angstroms, the electrical performance of the SGT semiconductor structure can be improved. If the depth of the gate recess 216 is too small, the subsequently formed gate polysilicon layer 230 will be too thin, affecting the on-state current of the SGT semiconductor structure. By making the depth of the gate recess 216 less than or equal to 60,000 angstroms, the process fabrication cycle can be reduced. In this embodiment, the depth of the gate recess 216 is 30,000 angstroms.
[0065] In this embodiment, the steps of forming the alignment mark groove 214 and the gate groove 216 include: Photoresist (not shown) is coated on the stacked layer 206, that is, photoresist covering the surface of the second etch barrier layer 212 is formed; The alignment marks (not shown) on the common mask of the gate recess 216 and the alignment mark recess 214 are aligned with the alignment marks (not shown) on the exposure machine, the photoresist is patterned, and a photoresist pattern (not shown) is formed, exposing a portion of the stacked layer 206. By using a dry etching process, the exposed stacked layer 206 is removed, that is, the second etch barrier layer 212, the first etch barrier layer 210 and the stress buffer layer 208 at the exposed locations are removed in sequence to expose a portion of the first epitaxial layer 204, that is, to expose the locations on the first epitaxial layer 204 used to form the alignment mark groove 214 and the gate groove 216.
[0066] A portion of the thickness of the first epitaxial layer 204 is exposed by a dry etching process to form an alignment mark groove 214 and a gate groove 216 within the first epitaxial layer 204. Neither the alignment mark groove 214 nor the gate groove 216 penetrates the first epitaxial layer 204.
[0067] In this embodiment, the alignment mark groove 214 and the gate groove 216 both penetrate the stacked layer 206, that is, the alignment mark groove 214 and the gate groove 216 both penetrate the stress buffer layer 208, the first etch barrier layer 210 and the second etch barrier layer 212.
[0068] In this embodiment, during the steps of forming the alignment mark groove 214 and the gate groove 216, the photoresist and the second etch barrier layer 212 are simultaneously removed by a dry etching process to expose the first etch barrier layer 210. In some embodiments, during the steps of forming the alignment mark groove 214 and the gate groove 216, neither the photoresist nor the second etch barrier layer 212 is removed. In some embodiments, after forming the alignment mark groove 214 and the gate groove 216 and before forming the gate dielectric layer, the photoresist and the second etch barrier layer 212 are removed by a stripping process and a dry etching process respectively.
[0069] refer to Figure 7 Before forming the shielding polysilicon layer 224, after forming the alignment mark groove 214 and the gate groove 216, the forming method further includes: forming a gate dielectric layer 218 covering the sidewall of the first epitaxial layer 204 in the gate groove 216.
[0070] The gate dielectric layer 218 is used to isolate the gate polysilicon layer 230 and the channel layer 232 in the SGT semiconductor structure (e.g., Figure 12 As shown, it is used to isolate and shield the polysilicon layer 224 and the first epitaxial layer 204, and also to release the stress between the polysilicon initial material layer 220 and the first etch barrier layer 210.
[0071] In this embodiment, the material of the gate dielectric layer 218 is silicon oxide.
[0072] The thickness of the gate dielectric layer 218 is selected from [400 angstroms, 600 angstroms]. By making the thickness of the gate dielectric layer 218 greater than or equal to 400 angstroms, the fabrication yield of the SGT semiconductor structure can be improved, because if the thickness of the gate dielectric layer 218 is too small, voids are easily generated in the gate dielectric layer 218. By making the thickness of the gate dielectric layer 218 less than or equal to 600 angstroms, the process fabrication cycle can be reduced. In this embodiment, the thickness of the gate dielectric layer 218 is 500 angstroms.
[0073] In this embodiment, the process for forming the gate dielectric layer 218 is chemical vapor deposition.
[0074] The film deposition process temperature for forming the gate dielectric layer 218 is selected from [700℃, 900℃] so that the formed gate dielectric layer 218 can better release the stress between the polysilicon material layer 228 and the first etch barrier layer 210, and reduce the leakage current of the SGT semiconductor structure (the formed gate dielectric layer 218 has a dense film and few defect states) to improve the electrical performance of the semiconductor structure. In this embodiment, the film deposition process temperature for forming the gate dielectric layer 218 is 800℃.
[0075] In this embodiment, the step of forming the gate dielectric layer 218 includes: A gate dielectric material layer (not shown) is formed by chemical vapor deposition, covering the surface and sidewalls of the first etch barrier layer 210. The gate dielectric material also covers the sidewalls of the stress buffer layer 208, the sidewalls of the alignment mark groove 214, and the sidewalls of the gate groove 216.
[0076] The alignment mark (not shown) on the gate dielectric layer mask is aligned with the alignment mark (not shown) on the exposure machine. Through exposure development and dry etching processes, the gate dielectric material layer on the sidewall of the alignment mark groove 214 is removed, and the remaining gate dielectric material layer forms the gate dielectric layer 218. The gate dielectric layer 218 covers the surface and sidewall of the first etch barrier layer 210 (above the gate groove 216), covers the sidewall of the stress buffer layer 208 (at the gate groove 216), and covers the sidewall of the gate groove 216.
[0077] refer to Figure 8 , combined Figure 7 An alignment polysilicon layer 222 is formed to fill the alignment mark groove 214, and a shielding polysilicon layer 224 is formed to fill the lower part of the gate groove 216.
[0078] The alignment polysilicon layer 222 is used for interlayer alignment between the various film layers of the SGT semiconductor structure.
[0079] The shielding polysilicon layer 224 is used to optimize the electric field distribution at the bottom of the gate groove 216, improve the breakdown voltage, and thus improve the electrical performance of the semiconductor structure.
[0080] In this embodiment, the steps of forming the alignment polysilicon layer 222 filling the alignment mark groove 214 and forming the shielding polysilicon layer 224 filling the lower part of the gate groove 216 include: Continue to refer to Figure 7 A polysilicon initial material layer 220 is formed by chemical vapor deposition to cover the gate dielectric layer 218. The polysilicon initial material layer 220 fills the alignment mark groove 214 and the gate groove 216.
[0081] refer to Figure 8 The second dry etching process is used to remove the polysilicon initial material layer 220 on the surface of the gate dielectric layer 218 and a portion of the polysilicon initial material layer 220 in the gate recess 216, so as to form the alignment polysilicon layer 222 located in the alignment mark recess 214 and the shielding polysilicon layer 224 located at the bottom of the gate recess 216.
[0082] In this embodiment, the second dry etching process includes a third dry etching process, a fourth dry etching process, a fifth dry etching process, and a sixth dry etching process.
[0083] The third dry etching process is used to remove the polysilicon initial material layer 220 on the surface of the gate dielectric layer 218, so that the polysilicon initial material layer 220 in the gate groove 216 and the polysilicon initial material layer 220 in the marking groove 214 are flush with the surface of the gate dielectric layer 218 on the surface of the first etch barrier layer 210.
[0084] By aligning the alignment marks (not shown) on the masking polysilicon layer with the alignment marks (not shown) on the exposure machine, and using exposure development and a fourth dry etching process, a portion of the thickness of the initial polysilicon material layer 220 located in the gate recess 216 is removed. The remaining initial polysilicon material layer 220 in the gate recess 216 constitutes the shielding polysilicon layer 224, that is, the shielding polysilicon layer 224 is formed at the lower part of the gate recess 216, and the shielding polysilicon layer 224 covers the sidewall of the gate dielectric layer 218.
[0085] Aligning the alignment marks (not shown) on the alignment polysilicon layer mask with the alignment marks (not shown) on the exposure machine, the polysilicon initial material layer 220 located at the top of the alignment mark groove 214 is removed by exposure development and the fifth dry etching process. The remaining polysilicon initial material layer 220 in the alignment mark groove 214 constitutes the alignment polysilicon layer 222, and the top surface of the alignment polysilicon layer 222 is flush with the top surface of the first epitaxial layer 204.
[0086] Align the first mask with the alignment mark (not shown) on the exposure machine, and use exposure development and the sixth dry etching process to remove the stress buffer layer 208, the first etch barrier layer 210 and the gate dielectric layer 218 on the first etch barrier layer 210 located on the upper surface of the first epitaxial layer 204, as well as the gate dielectric layer 218 covering the sidewalls of the stress buffer layer 208 and the first etch barrier layer 210.
[0087] In this embodiment, the top surface of the parallel polysilicon layer 222 and the top surface of the gate dielectric layer 218 in the gate groove 216 are flush with the upper surface (top surface) of the first epitaxial layer 204.
[0088] In this embodiment, the thickness of the polysilicon initial material layer 220 covering the surface of the gate dielectric layer 218 on the first etch barrier layer 210 is 8000 angstroms.
[0089] Continue to refer to Figure 8 An isolation layer 226 is formed to fill the middle of the gate recess 216. The isolation layer 226 is located on the shielding polysilicon layer 224, and the top surface of the isolation layer 226 is lower than the top surface of the first epitaxial layer 204.
[0090] The isolation layer 226 is used to prevent the shielding polysilicon layer 224 from short-circuiting with the gate polysilicon layer 230.
[0091] In this embodiment, the material of the isolation layer 226 is silicon oxide; in some embodiments, the material of the isolation layer 226 is silicon nitride, silicon carbide, silicon oxynitride, etc. The material of the isolation layer 226 can be selected according to actual needs, and this does not limit this application.
[0092] In this embodiment, the step of forming the isolation layer 226 includes: An isolation material layer (not shown) is formed covering the upper surface of the first epitaxial layer 204 by a chemical vapor deposition process, and the isolation material layer fills the gate recess 216; Aligning the isolation layer with the alignment marks (not shown) on the isolation layer mask and the alignment marks (not shown) on the exposure machine, the isolation material layer is formed by exposure, development, etching and other processes to form an isolation layer 226 filling the middle of the gate recess 216. The isolation layer 226 is located on the shielding polysilicon layer 224, and the top surface of the isolation layer 226 is lower than the top surface of the first epitaxial layer 204. The isolation layer 226 covers the sidewall of the gate dielectric layer 218.
[0093] In some embodiments, after the isolation layer 226 is formed, a portion of the thickness of the alignment polysilicon layer 222 is removed by a dry etching process along a direction perpendicular to the surface of the substrate 200, so that the top end face of the alignment polysilicon layer 222 is lower than the top surface of the first epitaxial layer 204, i.e., a height difference is formed, which provides alignment marks for the subsequent formation of metal films such as source metal (not shown). For example, in the step of forming source metal, visible light can be used to irradiate the alignment polysilicon layer 222, and the reflected light can be used to align the alignment marks (not shown) on the source metal mask with the alignment polysilicon layer 222 to form the source metal.
[0094] refer to Figures 9 to 11 A gate polysilicon layer 230 is formed within the gate recess 216 and located on the upper part of the gate recess 216.
[0095] The gate polysilicon layer 230 is used as a control switch for the channel layer 232 of the SGT semiconductor structure to control the opening and closing of the channel layer 232 (as shown in the figure).
[0096] In this embodiment, the step of forming the gate polysilicon layer 230 includes: refer to Figure 9 A polysilicon material layer 228 is formed by chemical vapor deposition to cover the upper surface of the first epitaxial layer 204. The polysilicon material layer 228 fills the upper part of the gate groove 216 and covers the isolation layer 226.
[0097] The thickness of the polysilicon material layer 228 covering the upper surface of the first epitaxial layer 204 is selected from [7000 angstroms, 9000 angstroms]. By making the thickness of the polysilicon material layer 228 covering the upper surface of the first epitaxial layer 204 greater than or equal to 7000 angstroms, a process basis can be provided for the top end face of the paraposition polysilicon layer 222 and the top end face of the gate polysilicon layer 230 to be flush with the upper surface of the first epitaxial layer 204, thereby improving the fabrication yield of the SGT semiconductor structure, i.e., improving the semiconductor yield. The electrical performance of the conductor structure; because the thickness of the polysilicon material layer 228 covering the first epitaxial layer 204 is too thin, during the chemical mechanical polishing process of the polysilicon material layer 228, it is easy to cause the top end face of the alignment polysilicon layer 222 and the top end face of the gate polysilicon layer 230 to be non-flush with the upper surface of the first epitaxial layer 204; by making the thickness of the polysilicon material layer 228 covering the first epitaxial layer 204 less than or equal to 9000 angstroms, the process fabrication cycle can be reduced. In this embodiment, the thickness of the polysilicon material layer 228 covering the first epitaxial layer 204 is 8000 angstroms.
[0098] refer to Figure 10 A portion of the polycrystalline silicon material layer 228 is removed using a chemical mechanical polishing process. In this embodiment, a portion of the polycrystalline silicon material layer 228 on the first epitaxial layer 204 is removed using a chemical mechanical polishing process.
[0099] The grinding time of the chemical mechanical polishing process is selected from [70s, 90s], which can better control the thickness of the polycrystalline silicon material layer 228 removed from the first epitaxial layer 204, thereby improving the fabrication yield of the SGT semiconductor structure.
[0100] In this embodiment, the grinding time of the chemical mechanical grinding process is 80 seconds.
[0101] By employing a chemical mechanical polishing (CMP) process, a portion of the polycrystalline silicon material layer 228 on the first epitaxial layer 204 is removed to a thickness greater than or equal to 1 / 2 of the thickness of the polycrystalline silicon material layer 228 covering the first epitaxial layer 204, and a portion of the polycrystalline silicon material layer 228 on the first epitaxial layer 204 is removed to a thickness less than or equal to 3 / 4 of the thickness of the polycrystalline silicon material layer 228 covering the first epitaxial layer 204. In this embodiment, the thickness of the portion of the polycrystalline silicon material layer 228 on the first epitaxial layer 204 removed by the CMP process is equal to the thickness of the polycrystalline silicon material layer 228 covering the first epitaxial layer 204. The thickness of the polysilicon material layer 228 covering the first epitaxial layer 204 is 3 / 4. In a specific embodiment, before chemical mechanical polishing, the thickness of the polysilicon material layer 228 of the first epitaxial layer 204 is 8000 angstroms (i.e., the initial thickness of the polysilicon material layer 228). After the chemical mechanical polishing process, the thickness of the remaining polysilicon material layer 228 on the surface of the first epitaxial layer 204 is 2000 angstroms. That is, through the chemical mechanical polishing process, the thickness of the polysilicon material layer 228 on the upper surface of the first epitaxial layer 204 is 6000 angstroms.
[0102] refer to Figure 11 The remaining polysilicon material layer 228 on the surface of the first epitaxial layer 204 is removed using a first dry etching process. The gate polysilicon layer 230 covers the sidewalls of the gate dielectric layer 218.
[0103] In this embodiment, the gate polysilicon layer 230 is formed by aligning the alignment mark (not shown) on the gate polysilicon layer mask with the alignment polysilicon layer 222 and then using exposure development and a first dry etching process on the remaining polysilicon material layer 228 on the surface of the first epitaxial layer 204.
[0104] In this embodiment, after the first dry etching process, the polysilicon material layer 228 in the gate groove 216 forms a gate polysilicon layer 230.
[0105] Continue to refer to Figure 11 In this embodiment, the top end face of the alignment polysilicon layer 222 in the alignment mark groove 214 and the top end face of the gate polysilicon layer 230 above the gate groove 216 are flush with the upper surface of the first epitaxial layer 204.
[0106] The top end face of the alignment polysilicon layer 222 in the alignment mark groove 214 is flush with the upper surface of the first epitaxial layer 204, which can improve the recognition ability of the alignment machine (i.e., the exposure machine) of the alignment polysilicon layer 222, thereby improving the electrical performance of the semiconductor structure.
[0107] The top end face of the gate polysilicon layer 230 above the gate recess 216 is flush with the upper surface of the first epitaxial layer 204, which can improve the uniformity of the electrical performance of the SGT semiconductor structure (e.g., reduced on-state current). The reason is as follows: If the top end faces of the gate polysilicon layer 230 above the gate recess 216 are not flush, the channel layer 232 of the SGT semiconductor structure (e.g., reduced on-state current) will be reduced. Figure 12 The uniformity of the length (as shown) reduces the fabrication yield of the SGT semiconductor structure.
[0108] The process parameters of the first dry etching process include: etching time selected from [15s, 30s], etching chamber pressure selected from [5mTorr, 9mTorr], etching power selected from [330W, 380W], O2 flow rate selected from [3sccm, 6sccm], SF6 flow rate selected from [18sccm, 22sccm], CF4 flow rate selected from [9sccm, 11sccm], and He flow rate selected from [140sccm, 160sccm].
[0109] In this embodiment, the etching time of the first dry etching process is 20s, the etching chamber pressure is 8mTorr, the etching power is 330W, the O2 flow rate is 4sccm, the SF6 flow rate is 18sccm, the CF4 flow rate is 9sccm, and the He flow rate is 140sccm.
[0110] In the first dry etching process, the roles of each gas are as follows: SF6 serves as the main etchant, dissociating a large number of fluorine radicals in the plasma, which react with polysilicon to generate volatile SiF4 to achieve efficient etching; CF4 serves as an auxiliary fluorine source, also providing fluorine radicals, mainly used to adjust the etching selectivity of polysilicon to silicon oxide and stabilize the plasma; O2 is used to oxidize byproducts, inhibit polymer redeposition, and promote the generation of fluorine radicals, thereby improving the morphology and uniformity of the gate polysilicon layer 230 after etching; He (helium) is used as a cooling gas to control the process temperature, and also plays a role in diluting and stabilizing the plasma.
[0111] The ratio of the thickness of the isolation layer 226 to the thickness of the gate dielectric layer 218 is selected from [5:1, 15:1]; the ratio of the thickness of the shielding polysilicon layer 224 to the thickness of the gate polysilicon layer 230 is selected from [0.5:1, 3:1]; the thickness ratio of the shielding polysilicon layer 224 to the thickness of the isolation layer 226 and the gate polysilicon layer 230 is (10~15):1:(5~20).
[0112] In one specific embodiment, the depth of the gate recess 216 is 60,000 angstroms, the thickness of the gate dielectric layer 218 is 500 angstroms, the thickness of the isolation layer 226 is 2,857 angstroms, the thickness of the shielding polysilicon layer 224 is 34,286 angstroms, and the thickness of the gate polysilicon layer 230 is 22,857 angstroms.
[0113] It should be noted that the thickness of the isolation layer 226, the thickness of the shielding polysilicon layer 224, and the thickness of the gate polysilicon layer 230 are all along the axial direction of the gate groove 216, and the thickness of the gate dielectric layer 218 is either along the direction perpendicular to the carrier flow direction or along the direction perpendicular to the axial direction of the gate groove 216.
[0114] refer to Figure 12 This forms channel layer 232.
[0115] In this embodiment, the first epitaxial layer 204 on both sides of the gate polysilicon layer 230 is doped and annealed to form a channel layer 232 on both sides of the gate polysilicon layer 230. The channel layer 232 is in contact with the gate dielectric layer 218 on both sides of the gate polysilicon layer 230.
[0116] In this embodiment, a doped dielectric layer (such as silicon oxide) is formed covering the surface of the first epitaxial layer 204 by chemical vapor deposition. The doped dielectric layer is aligned with the alignment polysilicon layer 222 by alignment marks (not shown) on the channel layer mask. The doped dielectric layer is exposed by exposure, development and etching process to expose the area where the channel layer 232 needs to be formed (i.e., the first epitaxial layers 204 on both sides of the gate polysilicon layer 230 are exposed). The channel layer 232 is formed on the first epitaxial layers 204 on both sides of the gate polysilicon layer 230.
[0117] Continue to refer to Figure 12 This forms a source doped layer 234 located on the channel layer 232.
[0118] In this embodiment, an initial source-doped layer covering the surface of the first epitaxial layer 204 is formed by epitaxial process, doping process and annealing process. By aligning the alignment marks (not shown) on the source doped layer mask with the alignment polysilicon layer 222, the source doped initial layer is formed by an exposure, development and etching process to form the source doped layer 234 located on the channel layer 232.
[0119] The methods for forming the source electrode and other structures of the SGT semiconductor structure can be derived by those skilled in the art based on the methods disclosed above, and will not be elaborated here.
[0120] It should be noted that for the different films forming the SGT semiconductor structure, a corresponding para-polycrystalline layer 222 will be designed on the substrate 200.
[0121] This invention also provides a semiconductor device comprising the SGT semiconductor structure described in any of the preceding embodiments.
[0122] The SGT semiconductor structure includes a logic chip and a memory chip.
[0123] It should be understood that in the embodiments of this application, the logic chip can be a central processing unit (CPU), which can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0124] It should also be understood that the memory chip in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).
[0125] This invention also provides an electronic device, including the semiconductor device described in any of the preceding embodiments. The semiconductor device can be internally or externally connected to the electronic device, which includes, but is not limited to, mobile phones, computers, tablets, servers, cloud platforms, etc.
[0126] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: Forming the first epitaxial layer; An alignment mark groove and a gate groove are formed in the first epitaxial layer, wherein neither the alignment mark groove nor the gate groove penetrates the first epitaxial layer; An alignment polysilicon layer is formed to fill the alignment mark groove, and a shielding polysilicon layer is formed to fill the lower part of the gate groove; An isolation layer is formed to fill the middle of the gate recess, the isolation layer is located on the shielding polysilicon layer, and the top surface of the isolation layer is lower than the top surface of the first epitaxial layer; A polysilicon material layer is formed covering the first epitaxial layer, the polysilicon material layer filling the upper part of the gate trench and covering the isolation layer; A portion of the polycrystalline silicon material layer is removed using a chemical mechanical polishing process; The remaining polysilicon material layer on the surface of the first epitaxial layer is removed by a first dry etching process. In this process, after the first dry etching process, the polysilicon material layer in the gate groove forms a gate polysilicon layer, and the top end face of the alignment polysilicon layer in the alignment mark groove and the top end face of the gate polysilicon layer at the top of the gate groove are flush with the upper surface of the first epitaxial layer.
2. The forming method as described in claim 1, characterized in that, The grinding time for the chemical mechanical grinding process is selected from [70s, 90s]; The process parameters for the first dry etching process include: The etching time is selected from [15s, 30s], the etching chamber pressure is selected from [5mTorr, 9mTorr], the etching power is selected from [330W, 380W], the O2 flow rate is selected from [3sccm, 6sccm], the SF6 flow rate is selected from [18sccm, 22sccm], the CF4 flow rate is selected from [9sccm, 11sccm], and the He flow rate is selected from [140sccm, 160sccm].
3. The forming method as described in claim 1, characterized in that, Before forming the alignment mark groove and the gate groove, the forming method further includes: A stacked layer is formed on the first epitaxial layer, the stacked layer comprising a stress buffer layer, a first etch barrier layer and a second etch barrier layer stacked sequentially; Both the alignment mark groove and the gate groove penetrate the stacked layer.
4. The forming method as described in claim 3, characterized in that, Before forming the shielding polysilicon layer, and after forming the alignment mark groove and the gate groove, the forming method further includes: A gate dielectric layer is formed that covers the sidewall of the first epitaxial layer in the gate recess; The isolation layer, the shielding polysilicon layer, and the gate polysilicon layer all cover the sidewalls of the gate dielectric layer.
5. The forming method as described in claim 4, characterized in that, The thickness of the gate dielectric layer is selected from [400 angstroms, 600 angstroms]; The material of the gate dielectric layer is silicon oxide; The process for forming the gate dielectric layer includes: chemical vapor deposition process; The film deposition process temperature for forming the gate dielectric layer is selected from [700℃, 900℃].
6. The forming method as described in claim 4, characterized in that, The steps of forming an alignment polysilicon layer filling the alignment mark trench and forming a shielding polysilicon layer filling the lower portion of the gate trench include: A polysilicon initial material layer is formed covering the gate dielectric layer, and the polysilicon initial material layer fills the alignment mark groove and the gate groove; A second dry etching process is used to remove the polysilicon initial material layer on the surface of the gate dielectric layer and a portion of the polysilicon initial material layer in the gate trench, so as to form the alignment polysilicon layer located in the alignment mark trench and the shielding polysilicon layer located at the bottom of the gate trench.
7. The forming method as described in claim 3, characterized in that, The stress buffer layer is made of silicon oxide, and its thickness is selected from [200 angstroms, 300 angstroms]. The material of the first etch barrier layer is silicon nitride, and the thickness of the first etch barrier layer is selected from [1000 angstroms, 2000 angstroms]; The material of the second etch barrier layer is silicon oxide, and the thickness of the second etch barrier layer is selected from [2000 angstroms, 4000 angstroms].
8. The forming method as described in claim 1, characterized in that, The depth of the alignment mark groove is selected from [10000 angstroms, 60000 angstroms]; The depth of the gate groove is selected from [10000 angstroms, 60000 angstroms].
9. The forming method as described in claim 1, characterized in that, The thickness of the polycrystalline silicon material layer covering the first epitaxial layer is selected from [7000 angstroms, 9000 angstroms].
10. The forming method according to claim 1, characterized in that, Before forming the first epitaxial layer, the method further includes: providing a substrate; A second epitaxial layer is formed on the substrate, wherein the first epitaxial layer covers the second epitaxial layer.