Array substrate, manufacturing method, display panel and display device

Abstract

The application is suitable for the technical field of display, and provides an array substrate, a manufacturing method, a display panel and a display device. The array substrate comprises a plurality of thin film transistors. The thin film transistor comprises a first gate electrode, a gate insulating layer and an active layer which are sequentially stacked. The gate insulating layer comprises a first gate insulating layer close to the active layer and a second gate insulating layer close to the first gate electrode. The surface roughness of the first gate insulating layer is small, and the thickness of the first gate insulating layer is small. The bias temperature stress effect caused by the accumulation and release of carriers in the interface charge traps is reduced. The response delay problem of the current between the source electrode and the drain electrode and the gate voltage is reduced. The manufacturing difficulty and cost of the whole gate insulating layer are reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a manufacturing method, a display panel, and a display device. Background Technology

[0002] Thin-film transistors (TFTs) used to drive pixel emission in display panels include at least amorphous silicon TFTs, low-temperature polycrystalline silicon TFTs, and metal-oxide-semiconductor TFTs. Different types of TFTs vary in electron mobility, cost, power consumption, and stability. TFTs are classified according to their function in the driving circuit.

[0003] In the existing technology, the fabrication and characteristics of thin-film transistors in display panels need to be improved. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate, which aims to provide a solution for improving the stability of thin-film transistors.

[0005] The embodiments of this application are implemented as follows: an array substrate includes:

[0006] A plurality of thin-film transistors, the thin-film transistors comprising a first gate, a gate insulating layer and an active layer stacked sequentially, the gate insulating layer comprising a first gate insulating layer disposed near the active layer and a second gate insulating layer disposed near the first gate, wherein the roughness of the first gate insulating layer is less than the roughness of the second gate insulating layer, and the thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.

[0007] In one embodiment, the roughness of the first gate insulating layer is less than or equal to 0.8 nanometers; the roughness of the second gate insulating layer is less than or equal to 3 nanometers.

[0008] Preferably, the roughness of the first gate insulating layer is less than or equal to 0.6 nanometers;

[0009] Preferably, the roughness of the second gate insulating layer is less than or equal to 2 nanometers.

[0010] In one embodiment, the ratio of the thickness of the first gate insulating layer to the thickness of the gate insulating layer is 0.05 to 0.4;

[0011] Preferably, the thickness of the gate insulating layer is 80 nanometers to 250 nanometers.

[0012] In one embodiment, the materials of the first gate insulating layer and the second gate insulating layer respectively include at least one of silicon oxide, silicon nitride, zinc oxide, and aluminum oxide;

[0013] Preferably, the first gate insulating layer and the second gate insulating layer are made of the same material;

[0014] Preferably, both the first gate insulating layer and the second gate insulating layer are made of silicon dioxide;

[0015] Preferably, the first gate insulating layer and the second gate insulating layer are made of different materials;

[0016] Preferably, the material of the first gate insulating layer is silicon dioxide, and the material of the second gate insulating layer includes at least one of silicon nitride, zirconium oxide, zinc oxide, and aluminum oxide.

[0017] In one embodiment, the array substrate further includes a substrate, and each of the thin-film transistors is disposed on one side of the substrate; the orthographic projection of the active layer on the substrate lies within the orthographic projection of the first gate insulating layer on the substrate;

[0018] Preferably, the orthographic projection of the active layer on the substrate lies within the orthographic projection of the second gate insulating layer on the substrate;

[0019] Preferably, the orthographic projection of the first gate insulating layer on the substrate coincides with the orthographic projection of the second gate insulating layer on the substrate.

[0020] In one embodiment, the first gate is disposed on the side of the active layer opposite to the substrate;

[0021] Preferably, the array substrate further includes a light-shielding layer disposed on the side of the first gate facing the substrate;

[0022] Preferably, the light-shielding layer is connected to a fixed voltage;

[0023] Alternatively, the thin-film transistor may further include an insulating layer disposed on the active layer facing the substrate, and a second gate disposed on the insulating layer facing the substrate;

[0024] Alternatively, the first gate may be disposed on the side of the active layer facing the substrate.

[0025] Another objective of this application is to provide a method for fabricating an array substrate, comprising:

[0026] Create an active layer;

[0027] The first gate insulating layer was fabricated using atomic layer deposition.

[0028] The second gate insulating layer was fabricated using chemical vapor deposition; and

[0029] Fabricate the first gate;

[0030] The first gate insulating layer is located on the side of the second gate insulating layer facing the active layer, and the thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.

[0031] In one embodiment, the second gate insulating layer is fabricated using plasma-enhanced chemical vapor deposition.

[0032] Another objective of this application is to provide a display panel comprising an array substrate as described in the above embodiments, and a plurality of light-emitting devices disposed on one side of the array substrate, each of the light-emitting devices being connected to a plurality of thin-film transistors.

[0033] Another object of the embodiments of this application is to provide a display device that includes the display panel described in the above embodiments.

[0034] The array substrate, manufacturing method, display panel, and display device provided in this application have the following advantages:

[0035] The array substrate provided in this application includes a plurality of thin-film transistors. Each thin-film transistor includes a first gate, a gate insulating layer, and an active layer stacked sequentially. The gate insulating layer includes a first gate insulating layer disposed near the active layer and a second gate insulating layer disposed near the first gate. The surface roughness of the first gate insulating layer is less than that of the second gate insulating layer, and the thickness of the first gate insulating layer is less than that of the second gate insulating layer. The first gate insulating layer has superior surface characteristics compared to the second gate insulating layer. Using the first gate insulating layer in contact with the active layer, under bias temperature stress conditions, the first gate insulating layer has fewer internal and interface defects. The reduced number of charge carriers that can be trapped and released by the charge traps reduces the bias temperature stress effect, such as threshold voltage drift, caused by the accumulation and release of charge carriers in the interface charge traps. Similarly, the reduced number of charges trapped and released by the charge traps on the surface of the first gate insulating layer also reduces the hysteresis loop area between the current and voltage, reducing the response hysteresis problem between the source and drain current and the gate voltage. The first gate insulating layer is more difficult and more expensive to manufacture. Here, the thickness of the first gate insulating layer is less than that of the second gate insulating layer, which can reduce the overall manufacturing difficulty and cost of the gate insulating layer while taking into account the interface characteristics of the gate insulating layer. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the pixel driving circuit in the display panel provided in the embodiments of this application;

[0039] Figure 3 This is a cross-sectional structural diagram of the array substrate in the display panel provided in the embodiments of this application;

[0040] Figure 4 This is another cross-sectional structural diagram of the array substrate in the display panel provided in the embodiments of this application;

[0041] Figure 5 This is another cross-sectional structural diagram of the array substrate in the display panel provided in the embodiments of this application;

[0042] Figure 6 This is a schematic diagram of the stacked structure of the gate insulating layer of the array substrate in the display panel provided in the embodiments of this application;

[0043] Figure 7 This is a cross-sectional structural diagram of the display panel provided in an embodiment of this application;

[0044] Figure 8 This is a flowchart of the fabrication method of the array substrate provided in the embodiments of this application.

[0045] The markings in the diagram mean:

[0046] 200 - Display panel, 2001 - Display area, 2002 - Non-display area;

[0047] 9-Light-emitting device, 91-First electrode, 92-Light-emitting functional layer, 93-Second electrode;

[0048] 95-pixel definition layer, 950-pixel aperture;

[0049] 100-Array substrate;

[0050] 1-Substrate;

[0051] 2-Light-shielding layer;

[0052] 3-Buffer layer;

[0053] 4-Thin film transistor, 41-First gate, 42-Second gate, 43-Gate insulating layer, 431-First gate insulating layer, 432-Second gate insulating layer, 44-Active layer, 45-Source, 46-Drain;

[0054] 5-Connecting electrodes;

[0055] 6-Interlayer insulation layer, 60-Second via;

[0056] 7 - First planarization layer; 70 - First via;

[0057] 8 - Second flat layer, 80 - Third via. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0059] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly or indirectly fixed to or set on that other component. When a component is referred to as "connected to" another component, it can be directly or indirectly connected to that other component. The terms "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the purpose of description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this patent. The terms "first" and "second" are used only for the purpose of description and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality" means two or more, unless otherwise explicitly specified.

[0060] To illustrate the technical solutions described in this application, the following detailed description is provided in conjunction with specific drawings and embodiments.

[0061] Generally, for the switching and driving thin-film transistors (TFTs) of the pixel driving circuit within the display area, greater stability (e.g., lower bias temperature stress, specifically lower threshold voltage drift) and lower leakage current are required. Therefore, metal-oxide-semiconductor (MOS) TFTs with lower mobility are typically used. These MOS TFTs offer sufficient charging and discharging speeds, low leakage current, and low hysteresis and bias temperature stress. Display screens using MOS TFT-based pixel driving circuits exhibit reduced image ghosting, blurring, and stuttering, and flicker-free low-frequency displays, providing a clear and smooth visual experience. Simultaneously, they significantly reduce screen power consumption. For the TFTs in the gate driving circuit of the non-display area, higher carrier mobility is required. Low-temperature polysilicon (LTPS) TFTs are generally preferred to reduce the TFT size, thereby minimizing bezel size.

[0062] Because of the low carrier mobility of metal-oxide-semiconductor (MOS) materials, it is difficult to reduce the area of ​​the MOS layer, resulting in larger pixel sizes and lower resolution. Furthermore, while using low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS) is more advantageous for reducing bezel width, LTPS are unsuitable for low-frequency driving and consume a lot of power, making them unsuitable for pixel driving circuits in the display area of ​​high-performance display devices.

[0063] In summary, current display panels typically use different types of thin-film transistors (TFTs) for the display area and non-display area. Manufacturing different types of TFTs separately leads to greater equipment investment, more photolithography processes and mask costs, and the more complex photolithography process also results in a decrease in product yield.

[0064] Therefore, if the metal oxide thin film transistors can be made to have higher carrier mobility while ensuring higher stability, the same metal oxide thin film transistors can be used to form the driving circuit in the display area and the non-display area, eliminating the need to manufacture two types of thin film transistors. This would help simplify the display panel process and reduce manufacturing costs.

[0065] Compared to low-mobility metal-oxide-semiconductor thin-film transistors (MOTS), high-mobility MOTS have a higher carrier concentration in the MOTS layer, such as more than three times. This requires relatively low-temperature processes during fabrication to reduce thermal stress in the film layer and reduce the diffusion of impurity atoms into the semiconductor layer. This ensures that the threshold voltage and carrier concentration of the MOTS are kept within a suitable range. In particular, low temperatures are required when forming the gate insulating layer and the interlayer insulating layer.

[0066] However, the low-temperature deposition process of the gate insulating layer and interlayer insulating layer results in a porous film structure with numerous internal and interface defects, deteriorating the bias temperature stress characteristics of the thin-film transistor and causing display defects. Furthermore, the deterioration of the film quality and bias temperature stress characteristics of the gate insulating layer and interlayer insulating layer also leads to hysteresis in the thin-film transistor, ultimately causing display problems such as image ghosting.

[0067] This application first provides an array substrate 100 for use in a display panel 200.

[0068] like Figure 3 , Figure 4 and Figure 5As shown, the array substrate 100 includes a plurality of thin-film transistors 4. Each thin-film transistor 4 includes a first gate 41, a gate insulating layer 43, and an active layer 44 stacked sequentially. The gate insulating layer 43 includes a first gate insulating layer 431 disposed near the active layer 44 and a second gate insulating layer 432 disposed near the first gate 41. The surface roughness of the first gate insulating layer 431 is less than the surface roughness of the second gate insulating layer 432, and the thickness H1 of the first gate insulating layer 431 is less than the thickness H2 of the second gate insulating layer 432. Please refer to [reference needed]. Figure 6 As shown.

[0069] In this embodiment, the surface roughness of the first gate insulating layer 431 is less than that of the second gate insulating layer 432. The first gate insulating layer 431 has better surface characteristics than the second gate insulating layer 432. When the first gate insulating layer 431 is used to contact the active layer 44, under bias temperature stress conditions, the number of carriers that can be captured and released by the fewer interface defects of the first gate insulating layer 431 is reduced, thereby reducing the bias temperature stress effect such as threshold voltage drift caused by the accumulation and release of carriers in interface charge traps. Similarly, the reduction in the number of charges captured and released by the charge traps on the surface of the first gate insulating layer 431 also improves the response hysteresis problem between the current and the gate voltage between the source 45 and the drain 46 in the thin film transistor 4.

[0070] In this embodiment, the first gate insulating layer 431 has a smaller surface roughness and better surface characteristics. During fabrication, the first gate insulating layer 431 requires better process parameter control. Therefore, the fabrication difficulty and cost of the first gate insulating layer 431 are higher. Here, the thickness H1 of the first gate insulating layer 431 is smaller than the thickness H2 of the second gate insulating layer 432. This can reduce the overall fabrication difficulty and cost of the gate insulating layer 43 while taking into account the interface characteristics of the gate insulating layer 43.

[0071] Thus, the array substrate 100 provided in this application embodiment has thin-film transistors 4 that simultaneously possess high stability and carrier mobility, which can simultaneously satisfy the display area 2001 (please refer to...). Figure 1 The diagram illustrates the operational requirements of the pixel driving circuit within the array substrate 100 and the gate driving circuit within the non-display area 2002. Furthermore, the same type of thin-film transistor 4 can be used across the entire array substrate 100. This reduces the fabrication process of the array substrate 100, lowers process costs, and improves product yield.

[0072] It should be noted that, in the embodiments of this disclosure, "roughness" represents the flatness (or undulation) of the film surface at the microscopic level, that is, the amplitude of the undulation (e.g., the distance between peaks and troughs), and therefore can be expressed in units of length (e.g., nanometers, micrometers, etc.). With high roughness, the atomic, molecular, or lattice structure on the surface of the corresponding film is loosely arranged and highly undulating; conversely, with low roughness, the atomic, molecular, or lattice structure on the surface of the corresponding film is relatively regularly arranged, densely arranged, and less undulating. Films with low roughness have a higher barrier effect against the intrusion of external substances.

[0073] Roughness can also be evaluated based on features such as the spacing of fluctuations (e.g., the spacing between crests or troughs) and microstructure. In some cases, roughness can be calculated by combining features such as amplitude (height), spacing, and shape.

[0074] In one embodiment, the roughness of the first gate insulating layer 431 is less than or equal to 0.8 nanometers. This ensures that the first gate insulating layer 431 has a low roughness.

[0075] In one alternative embodiment, the roughness of the first gate insulating layer 431 is less than or equal to 0.6 nanometers.

[0076] In one alternative embodiment, the roughness of the first gate insulating layer 431 is less than or equal to 0.5 nanometers.

[0077] In one alternative embodiment, the roughness of the first gate insulating layer 431 is less than or equal to 0.45 nanometers.

[0078] In some specific embodiments, the roughness of the first gate insulating layer 431 is 0.8 nm, 0.75 nm, 0.7 nm, 0.65 nm, 0.6 nm, 0.55 nm, 0.5 nm, 0.45 nm, 0.4 nm, 0.35 nm, 0.3 nm, 0.25 nm, 0.2 nm, 0.15 nm, etc.

[0079] In one embodiment, the roughness of the second gate insulating layer 432 is less than or equal to 3 nanometers to ensure that the second gate insulating layer 432 has a small roughness.

[0080] In one alternative embodiment, the roughness of the second gate insulating layer 432 is less than or equal to 2.5 nanometers.

[0081] In one alternative embodiment, the roughness of the second gate insulating layer 432 is less than or equal to 2 nanometers.

[0082] In some specific embodiments, the roughness of the second gate insulating layer 432 is 3 nanometers, 2.7 nanometers, 2.5 nanometers, 2.2 nanometers, 2 nanometers, 1.8 nanometers, 1.5 nanometers, 1.2 nanometers, 1 nanometer, etc.

[0083] In one embodiment, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05 to 0.4. Specifically, the ratio of the thickness H1 of the first gate insulating layer 431 to the overall thickness H of the gate insulating layer 43 can also be determined in conjunction with the roughness of the first gate insulating layer 431. For example, within the range where the roughness of the first gate insulating layer 431 is less than or equal to 0.8 nanometers, the smaller the roughness of the first gate insulating layer 431, the smaller the thickness of the first gate insulating layer 431 can be, and the smaller the proportion of thickness it occupies in the entire gate insulating layer 43. Conversely, within the range where the roughness of the first gate insulating layer 431 is less than or equal to 0.8 nanometers, the larger the roughness of the first gate insulating layer 431, the more appropriate the thickness H1 of the first gate insulating layer 431 and the proportion of thickness it occupies in the entire gate insulating layer 43 can be increased.

[0084] The gate insulating layer 43 includes a first gate insulating layer 431 and a second gate insulating layer 432. Therefore, the thickness H of the gate insulating layer 43 is at least the sum of the thickness H1 of the first gate insulating layer 431 and the thickness H2 of the second gate insulating layer 432. Please refer to [reference needed]. Figure 6 As shown. In other alternative embodiments, the gate insulating layer 43 may further include a third insulating layer (not shown), where H > H1 + H2.

[0085] In one alternative embodiment, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05 to 0.3.

[0086] In one optional embodiment, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05 to 0.2.

[0087] In one alternative embodiment, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05 to 0.1.

[0088] In some specific embodiments, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, etc.

[0089] In one embodiment, the thickness H of the gate insulating layer 43 is 70 nanometers to 250 nanometers to ensure that a suitable distance is maintained between the gate and the active layer 44, so as to avoid problems such as leakage current, breakdown of the gate insulating layer 43, increased driving power consumption, and reduced response speed.

[0090] In one alternative embodiment, the thickness H of the gate insulating layer 43 is 80 nanometers to 250 nanometers.

[0091] In one alternative embodiment, the thickness H of the gate insulating layer 43 is 80 nanometers to 200 nanometers.

[0092] In one alternative embodiment, the thickness H of the gate insulating layer 43 is 100 nanometers to 200 nanometers.

[0093] In one alternative embodiment, the thickness H of the gate insulating layer 43 is 120 nm to 200 nm.

[0094] In one embodiment, the first gate insulating layer 431 with a low roughness can be fabricated using atomic layer deposition (ALD). ALD is based on two different precursors (typically gaseous compounds) that are alternately introduced into a reaction chamber and undergo a self-limiting chemical reaction with the substrate surface. Each time a precursor is introduced, it adsorbs onto the substrate surface and forms a monolayer, which then bonds to atoms on the substrate surface or to already deposited atoms through a chemical reaction. Once this layer has reacted, a second precursor is introduced, which reacts with the product of the first layer to form a new layer. This self-limiting reaction process ensures that the thickness of each deposition is precisely controlled at the atomic layer level. The adsorption process between the precursor and the substrate surface is chemisorption, not physisorption. Chemisorption allows chemical bonds to form between the precursor and the atoms on the substrate surface, thereby ensuring the quality and adhesion of the deposited film.

[0095] In one embodiment, the second gate insulating layer 432 can be fabricated by chemical vapor deposition. In an alternative embodiment, the second gate insulating layer 432 can be fabricated by plasma-enhanced chemical vapor deposition. Plasma-enhanced chemical vapor deposition technology utilizes plasma to enhance chemical reactions, promoting chemical reactions of gaseous precursors on the substrate surface, thereby depositing a solid film. In a plasma-enhanced chemical vapor deposition system, reactive gases are introduced into a reaction chamber, and plasma is generated through radio frequency, microwave, or other means. The plasma contains a large number of high-energy electrons, ions, and free radicals, which can significantly reduce the activation energy of the reaction, allowing chemical reactions that originally required high temperatures to occur rapidly at lower temperatures, thereby forming a thin film on the substrate surface.

[0096] Furthermore, compared to chemical vapor deposition, atomic layer deposition has a lower film formation rate. Therefore, in this embodiment, the ratio of the thickness H1 of the first gate insulating layer 431 to the thickness H of the gate insulating layer 43 is 0.05 to 0.4, which is beneficial for ensuring the overall film formation time of the gate insulating layer 43 and improving the fabrication efficiency of the array substrate 100.

[0097] The materials of the first gate insulating layer 431 and the second gate insulating layer 432 include at least one of silicon oxide, silicon nitride, zinc oxide, and aluminum oxide.

[0098] In one embodiment, the first gate insulating layer 431 and the second gate insulating layer 432 are made of the same material. For example, both the first gate insulating layer 431 and the second gate insulating layer 432 may be silicon oxide, or both may be silicon nitride, or both may be a combination of silicon oxide and silicon nitride, or both may be a combination of zinc oxide and aluminum oxide, etc. The purpose of this arrangement is that, during the patterning process of the inorganic material layer, the first gate insulating layer 431 and the second gate insulating layer 432 can be obtained using the same etching process, which is beneficial for process compatibility, reducing process steps, and lowering process costs.

[0099] In one optional embodiment, both the first gate insulating layer 431 and the second gate insulating layer 432 are made of silicon dioxide. This is because silicon dioxide has more stable chemical properties and its fabrication process is mature, low-cost, and has a high yield.

[0100] In one embodiment, the first gate insulating layer 431 and the second gate insulating layer 432 are made of different materials. The purpose of this arrangement is that by combining the first gate insulating layer 431 and the second gate insulating layer 432 with different materials, the gate insulating layer 43 can achieve an optimal combination in terms of cost, stability, dielectric constant, and other aspects.

[0101] In one alternative embodiment, the first gate insulating layer 431 may be made of a chemically more stable material, while the second gate insulating layer 432 may be made of an insulating material with a higher dielectric constant. This allows the gate insulating layer 43 to simultaneously possess good chemical stability and a high dielectric constant.

[0102] In one optional embodiment, the first gate insulating layer 431 is made of silicon dioxide, and the second gate insulating layer 432 is made of at least one of silicon nitride, zirconium oxide, zinc oxide, and aluminum oxide. Silicon nitride, zirconium oxide, zinc oxide, and aluminum oxide have higher dielectric constants than silicon dioxide. Therefore, combined with the thicker second gate insulating layer 432, the gate insulating layer 43 as a whole has a higher dielectric constant, providing high capacitance at a thinner thickness. This helps to reduce the area and size of the active layer 44, and consequently, reduces the size of the thin-film transistor 4.

[0103] The active layer 44 comprises an oxide semiconductor material; therefore, the active layer 44 is an oxide semiconductor layer. Specifically, the active layer 44 comprises at least one of indium tin oxide, gallium oxide, tin oxide, and zinc oxide.

[0104] The active layer 44 may include a single layer of oxide semiconductor material or a multilayer of oxide semiconductor material. For example, the active layer 44 may include three layers of oxide semiconductor material, with the middle layer primarily used to provide charge carriers, and the two outer layers of oxide semiconductor material made of materials with good mechanical and film-forming properties, serving as support.

[0105] In one embodiment, please refer to Figures 2 to 4 As shown, the array substrate 100 also includes a substrate 1, and the aforementioned plurality of thin-film transistors 4 are disposed on one side surface of the substrate 1.

[0106] Please refer to the following: Figures 2 to 4 As shown, the orthographic projection of the active layer 44 on the substrate 1 lies within the orthographic projection of the first gate insulating layer 431 on the substrate 1. This means that the edge contour of the orthographic projection of the active layer 44 lies within the edge contour of the orthographic projection of the first gate insulating layer 431, and does not coincide with any point of the edge contour of the orthographic projection of the first gate insulating layer 431.

[0107] Please refer to the following: Figures 2 to 4 As shown, the orthographic projection of the active layer 44 onto the substrate 1 lies within the orthographic projection of the second gate insulating layer 432 onto the substrate 1. Similarly, this means that the edge contour of the orthographic projection of the active layer 44 lies within the edge contour of the orthographic projection of the second gate insulating layer 432, and does not coincide with any point of the edge contour of the orthographic projection of the second gate insulating layer 432.

[0108] In one embodiment, the orthographic projection of the first gate insulating layer 431 onto the substrate 1 coincides with the orthographic projection of the second gate insulating layer 432 onto the substrate 1. For example, the first gate insulating layer 431 and the second gate insulating layer 432 are fabricated using the same photomask process, therefore, the first gate insulating layer 431 and the second gate insulating layer 432 have a consistent shape.

[0109] In other alternative embodiments, as needed and through appropriate photomask processes, the orthographic projection of the first gate insulating layer 431 on the substrate 1 and the orthographic projection of the second gate insulating layer 432 on the substrate 1 may partially overlap.

[0110] In the aforementioned thin-film transistor 4, the first gate 41, the gate insulating layer 43, and the active layer 44, which are stacked sequentially, can be fabricated on the substrate 1 in the order of the first gate 41, the second gate insulating layer 432, the first gate insulating layer 431, and the active layer 44. That is, the thin-film transistor 4 in this case is a bottom-gate type thin-film transistor device. Please refer to [link to relevant documentation]. Figure 3 As shown. The first gate 41 is disposed on the side of the active layer 44 facing the substrate 1. In one embodiment, the thin-film transistor 4 device further includes a source 45 and a drain 46 disposed on the side of the gate insulating layer 43 away from the substrate 1 and respectively connected to the two ends of the active layer 44.

[0111] Please see Figure 3 As shown, the thin-film transistor 4 device further includes a first planarization layer 7 disposed on the side of the source electrode 45 and the drain electrode 46 facing away from the substrate 1. Optionally, the thin-film transistor 4 device further includes a connection electrode 5 disposed on the side of the first planarization layer 7 facing away from the substrate 1. The first planarization layer 7 has a through-hole 70, and the connection electrode 5 is connected to the source electrode 45 or the drain electrode 46 through the first through-hole 70. Further optionally, the thin-film transistor 4 device further includes a second planarization layer 8 disposed on the side of the connection electrode 5 facing away from the substrate 1.

[0112] In the aforementioned thin-film transistor 4, the first gate 41, gate insulating layer 43, and active layer 44, which are sequentially stacked, can be fabricated on the substrate 1 in the order of active layer 44, first gate insulating layer 431, second gate insulating layer 432, and first gate 41. That is, the thin-film transistor 4 in this case is a top-gate type thin-film transistor device, with the first gate 41 located on the side of the active layer 44 facing away from the substrate 1. Please refer to [link to relevant documentation]. Figure 4 As shown. In one example, the thin-film transistor 4 device further includes a light-shielding layer 2 disposed on one side of the substrate 1, and an active layer 44 disposed on the side of the light-shielding layer 2 facing away from the substrate 1. The orthogonal projection of the active layer 44 onto the substrate 1 lies within the orthogonal projection of the light-shielding layer 2 onto the substrate 1. That is, the edge of the light-shielding layer 2 extends outward by a certain distance relative to the edge of the active layer 44 to prevent unwanted light from illuminating the active layer 44 and generating photocurrent. The light-shielding layer 2 can be a metal material layer. In an optional embodiment, the thin-film transistor 4 device further includes a buffer layer 3 disposed on the side of the light-shielding layer 2 facing away from the substrate 1. The material of the buffer layer 3 can include an inorganic insulating material, which also serves as insulation between the metal light-shielding layer 2 and the active layer 44, specifically such as silicon dioxide. Silicon dioxide has good interface compatibility with the substrate 1 (such as a silicon-based substrate 1).

[0113] In one alternative embodiment, the light-shielding layer 2 has a fixed voltage.

[0114] Please see Figure 4As shown, in one embodiment, the thin-film transistor 4 device further includes an interlayer insulating layer 6 disposed on the side of the first gate 41 away from the substrate 1, and a source 45 and a drain 46 disposed on the side of the interlayer insulating layer 6 away from the substrate 1. The interlayer insulating layer 6 is provided with a through second via 60, and the source 45 and the drain 46 are respectively connected to both sides of the active layer 44 via the second via 60.

[0115] like Figure 5 As shown, at least one thin-film transistor 4 is a dual-gate thin-film transistor device. The first gate 41 is located on the side of the active layer 44 away from the substrate 1, and a second gate 42 is also provided on the side of the active layer 44 facing the substrate 1, and a buffer layer 3 is located between the second gate 42 and the active layer 44. The buffer layer 3 also serves as an insulating layer between the second gate 42 and the active layer 44. At the same time, the second gate 42 can shield the active layer 44, that is, the second gate 42 can also serve as a light-shielding structure.

[0116] Please see Figure 1 and Figure 7 As shown, this application embodiment also provides a display panel 200, which includes an array substrate 100 as described in the above embodiments, and a plurality of light-emitting devices 9 disposed on one side of the array substrate 100, each light-emitting device 9 being connected to a plurality of thin-film transistors 4. It is understood that one light-emitting device 9 may correspond to a plurality of thin-film transistors 4.

[0117] The array substrate 100 includes a first region and a second region located around the first region. A light-emitting device 9 is disposed within the first region and connected to a plurality of thin-film transistors 4 located within the first region. At least the plurality of thin-film transistors 4 located within the first region constitute a pixel driving circuit for driving the light-emitting device 9. A plurality of thin-film transistors 4 are also located in the second region, and at least the plurality of thin-film transistors 4 located in the second region constitute a gate driving circuit. Furthermore, an encapsulation layer (not shown) is provided on the side of the light-emitting device 9 facing away from the substrate 1, simultaneously covering both the first and second regions.

[0118] The display area 2001 of the display panel 200 is formed by at least a first region of the array substrate 100 together with a plurality of light-emitting devices 9 in the first region and a portion of the encapsulation layer. The non-display area 2002 of the display panel 200 is formed by at least a second region of the array substrate 100 together with a portion of the encapsulation layer in the second region.

[0119] The form of the pixel driving circuit is not limited; it can be a 2T1C (two thin-film transistors plus one storage capacitor) architecture, a 7T1C (seven thin-film transistors plus one storage capacitor) architecture, an 8T1C (eight thin-film transistors plus one storage capacitor) architecture, etc. The thin-film transistors in these architectures are the thin-film transistor 4 described in the embodiments of this application.

[0120] For example, please refer to the following: Figure 1 and Figure 2 As shown, taking the 2T1C architecture as an example, the gate of the switching thin-film transistor (S-TFT) is connected to the scan signal SCAN, the first terminal of the S-TFT is connected to the data signal DATA, and the second terminal of the S-TFT is connected to the first terminal of the driving thin-film transistor (D-TFT). The first terminal of the driving thin-film transistor (D-TFT) is connected to the power supply signal VDD, and the second terminal of the driving thin-film transistor (D-TFT) is connected to the sub-pixel (including a light-emitting device 9). One end of the storage capacitor Cst is connected to the power supply signal VDD, and the other end is connected to the second terminal of the switching thin-film transistor (S-TFT).

[0121] like Figure 7 As shown, the light-emitting device 9 includes a first electrode 91, a light-emitting functional layer 92, and a second electrode 93 sequentially stacked on the side of the second planarization layer 8 facing away from the substrate 1. The first electrode 91 can be an anode, and the anode is connected to the aforementioned connection electrode 5 through a third via 80 on the second planarization layer 8. Optionally, as... Figure 7 As shown, a pixel definition layer 95 may be provided on the side of the second planarization layer 8 facing away from the substrate 1. The pixel definition layer 95 defines a plurality of pixel openings 950. The first electrode 91 is disposed between the pixel definition layer 95 and the second planarization layer 8, and is at least partially exposed within the pixel openings 950. The light-emitting functional layer 92 and the second electrode 93 are stacked on the first electrode 91 on the side of the pixel definition layer 95 facing away from the substrate 1.

[0122] Please see Figure 8 As shown in the embodiments of this application, a method for fabricating an array substrate is also provided, which includes fabricating a plurality of thin-film transistors 4. Specifically, the steps for fabricating the thin-film transistors 4 include:

[0123] Step S1: Create active layer 44;

[0124] Step S2: The first gate insulating layer 431 is fabricated using atomic layer deposition.

[0125] Step S3: Fabricate the second gate insulating layer 432 using chemical vapor deposition; and

[0126] Step S4: Fabricate the first gate 41;

[0127] In this configuration, the first gate insulating layer 431 is located on the side of the second gate insulating layer 432 closest to the active layer 44, meaning that the first gate insulating layer 431 directly contacts the active layer 44. Furthermore, the thickness H1 of the first gate insulating layer 431 is less than the thickness H2 of the second gate insulating layer 432. The first gate 41 is located on the side of the second gate insulating layer 432 opposite to the first gate insulating layer 431.

[0128] The first gate insulating layer 431, fabricated by atomic layer deposition, has a smaller surface roughness compared to the second gate insulating layer 432, fabricated by chemical vapor deposition.

[0129] It should also be noted that the limitations of steps S1 to S3 described above do not imply that they must be performed in this order. Depending on the type of thin-film transistor 4, the active layer 44, the first gate insulating layer 431, and the second gate insulating layer 432 can be fabricated in different orders.

[0130] Please refer to the following: Figure 3 As shown, the fabricated thin-film transistor 4 is a bottom-gate thin-film transistor device. The fabrication method of the array substrate includes: step S4, fabricating a first gate 41 on the substrate 1; step S3, fabricating a second gate insulating layer 432 on the side of the first gate 41 away from the substrate 1 using chemical vapor deposition; step S2, fabricating a first gate insulating layer 431 on the side of the second gate insulating layer 432 away from the substrate 1 using atomic layer deposition; and step S1, fabricating an active layer 44 on the side of the first gate insulating layer 431 away from the substrate 1.

[0131] Please refer to the following: Figure 4 As shown, the fabricated thin-film transistor 4 is a top-gate thin-film transistor device. The fabrication method of the array substrate includes: step S1, fabricating an active layer 44 on one side of the substrate 1; step S2, fabricating a first gate insulating layer 431 on the side of the active layer 44 away from the substrate 1 using atomic layer deposition; step S3, fabricating a second gate insulating layer 432 on the side of the first gate insulating layer 431 away from the substrate 1 using chemical vapor deposition; and step S4, fabricating a first gate 41 on the side of the second gate insulating layer 432 away from the substrate 1.

[0132] In one embodiment, the second gate insulating layer 432 may be fabricated using plasma-enhanced chemical vapor deposition.

[0133] Finally, this application also provides a display device (not shown) that includes a display panel 200 as described in the above embodiments.

[0134] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An array substrate, characterized in that, include: A plurality of thin-film transistors, the thin-film transistors comprising a first gate, a gate insulating layer and an active layer stacked sequentially, the gate insulating layer comprising a first gate insulating layer disposed near the active layer and a second gate insulating layer disposed near the first gate, wherein the roughness of the first gate insulating layer is less than the roughness of the second gate insulating layer, and the thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.

2. The array substrate as described in claim 1, characterized in that, The roughness of the first gate insulating layer is less than or equal to 0.8 nanometers; the roughness of the second gate insulating layer is less than or equal to 3 nanometers. Preferably, the roughness of the first gate insulating layer is less than or equal to 0.6 nanometers; Preferably, the roughness of the second gate insulating layer is less than or equal to 2 nanometers.

3. The array substrate as described in claim 1, characterized in that, The ratio of the thickness of the first gate insulating layer to the thickness of the gate insulating layer is 0.05 to 0.4; Preferably, the thickness of the gate insulating layer is 70 nanometers to 250 nanometers.

4. The array substrate as described in claim 1, characterized in that, The materials of the first gate insulating layer and the second gate insulating layer respectively include at least one of silicon oxide, silicon nitride, zinc oxide, and aluminum oxide; Preferably, the first gate insulating layer and the second gate insulating layer are made of the same material; Preferably, both the first gate insulating layer and the second gate insulating layer are made of silicon dioxide; Preferably, the first gate insulating layer and the second gate insulating layer are made of different materials; Preferably, the material of the first gate insulating layer is silicon dioxide, and the material of the second gate insulating layer includes at least one of silicon nitride, zirconium oxide, zinc oxide, and aluminum oxide.

5. The array substrate as described in any one of claims 1 to 4, characterized in that, The array substrate further includes a substrate, and each of the thin-film transistors is disposed on one side of the substrate; the orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate insulating layer on the substrate; Preferably, the orthographic projection of the active layer on the substrate lies within the orthographic projection of the second gate insulating layer on the substrate; Preferably, the orthographic projection of the first gate insulating layer on the substrate coincides with the orthographic projection of the second gate insulating layer on the substrate.

6. The array substrate as described in claim 5, characterized in that, The first gate is disposed on the side of the active layer opposite to the substrate; Preferably, the array substrate further includes a light-shielding layer disposed on the side of the first gate facing the substrate; Preferably, the light-shielding layer is connected to a fixed voltage; Alternatively, the thin-film transistor may further include an insulating layer disposed on the active layer facing the substrate, and a second gate disposed on the insulating layer facing the substrate; Alternatively, the first gate may be disposed on the side of the active layer facing the substrate.

7. A method for fabricating an array substrate, characterized in that, include: Create an active layer; The first gate insulating layer was fabricated using atomic layer deposition. The second gate insulating layer was fabricated using chemical vapor deposition. as well as Fabricate the first gate; The first gate insulating layer is located on the side of the second gate insulating layer facing the active layer, and the thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.

8. The method for fabricating an array substrate as described in claim 7, characterized in that, The second gate insulating layer was fabricated using plasma-enhanced chemical vapor deposition.

9. A display panel, characterized in that, The array substrate includes any one of claims 1 to 6, and a plurality of light-emitting devices disposed on one side of the array substrate, each of the light-emitting devices being connected to a plurality of the thin-film transistors.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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